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Attach and LAW problems to fix

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Summary:
1) Attach problem - mpc85xx_probe() relies on fact that 0xfff0 mask matches all
QorIQ CPUs what is not true since e6500. This shall be reworked to match against
all supported CPUs.

2) There is no any reason for operating system to re-program or anyhow else
touch the LAWs programmed by firmware (u-boot). Right now mpc85xx_attach()
removes all LaW entries except for DRAM. This causes MCE to be generated when
later any of driver maps DTB-provided hardware addresses which do not exist
anymore because corresponding LaWs were removed.

Submitted by:	Ivan Krivonos <int0dster_AT_gmail.com>
Differential Revision: https://reviews.freebsd.org/D7663
This commit is contained in:
Justin Hibbits 2016-08-30 02:09:40 +00:00
parent e6f1b41e4e
commit adbe268544
1 changed files with 10 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
sys/powerpc/mpc85xx/platform_mpc85xx.c
View File

@ -120,11 +120,16 @@ PLATFORM_DEF(mpc85xx_platform);
static int
mpc85xx_probe(platform_t plat)
{
u_int pvr = mfpvr() >> 16;
if ((pvr & 0xfff0) == FSL_E500v1)
return (BUS_PROBE_DEFAULT);
u_int pvr = (mfpvr() >> 16) & 0xFFFF;
switch (pvr) {
case FSL_E500v1:
case FSL_E500v2:
case FSL_E500mc:
case FSL_E5500:
case FSL_E6500:
return (BUS_PROBE_DEFAULT);
}
return (ENXIO);
}
@ -135,9 +140,8 @@ mpc85xx_attach(platform_t plat)
const char *soc_name_guesses[] = {"/soc", "soc", NULL};
const char **name;
pcell_t ranges[6], acells, pacells, scells;
uint32_t sr;
uint64_t ccsrbar, ccsrsize;
int i, law_max, tgt;
int i;
if ((cpus = OF_finddevice("/cpus")) != -1) {
for (maxcpu = 0, child = OF_child(cpus); child != 0;
@ -194,23 +198,6 @@ mpc85xx_attach(platform_t plat)
mpc85xx_fix_errata(ccsrbar_va);
mpc85xx_enable_l3_cache();
/*
* Clear local access windows. Skip DRAM entries, so we don't shoot
* ourselves in the foot.
*/
law_max = law_getmax();
for (i = 0; i < law_max; i++) {
sr = ccsr_read4(OCP85XX_LAWSR(i));
if ((sr & OCP85XX_ENA_MASK) == 0)
continue;
tgt = (sr & 0x01f00000) >> 20;
if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 ||
tgt == OCP85XX_TGTIF_RAM_INTL)
continue;
ccsr_write4(OCP85XX_LAWSR(i), sr & OCP85XX_DIS_MASK);
}
return (0);
}