MFC r259728, r260752
Add Freescale i.MX515 vt(9) driver.
This commit is contained in:
ian
parent
b817c837ca
commit
adcb9fbee8
@ -50,4 +50,5 @@ dev/ofw/ofw_iicbus.c optional fsliic
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# IPU - Image Processing Unit (frame buffer also)
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arm/freescale/imx/imx51_ipuv3.c optional sc
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arm/freescale/imx/imx51_ipuv3_fbd.c optional vt
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dev/vt/hw/fb/vt_early_fb.c optional vt
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346
sys/arm/freescale/imx/imx51_ipuv3_fbd.c
Normal file
346
sys/arm/freescale/imx/imx51_ipuv3_fbd.c
Normal file
@ -0,0 +1,346 @@
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/*-
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* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* Copyright (c) 2012, 2013 The FreeBSD Foundation
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* All rights reserved.
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*
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* Portions of this software were developed by Oleksandr Rybalko
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* under sponsorship from the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bio.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/queue.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/time.h>
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#include <sys/timetc.h>
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#include <sys/fbio.h>
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#include <sys/consio.h>
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#include <sys/eventhandler.h>
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#include <sys/kdb.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/fdt.h>
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#include <machine/resource.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/vt/vt.h>
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#include <dev/vt/colors/vt_termcolors.h>
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#include <arm/freescale/imx/imx51_ccmvar.h>
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#include <arm/freescale/imx/imx51_ipuv3reg.h>
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#include "fb_if.h"
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#define IMX51_IPU_HSP_CLOCK 665000000
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struct ipu3sc_softc {
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device_t dev;
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device_t sc_fbd; /* fbd child */
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struct fb_info sc_info;
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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bus_space_handle_t cm_ioh;
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bus_space_handle_t dp_ioh;
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bus_space_handle_t di0_ioh;
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bus_space_handle_t di1_ioh;
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bus_space_handle_t dctmpl_ioh;
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bus_space_handle_t dc_ioh;
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bus_space_handle_t dmfc_ioh;
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bus_space_handle_t idmac_ioh;
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bus_space_handle_t cpmem_ioh;
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};
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static struct ipu3sc_softc *ipu3sc_softc;
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#define IPUV3_READ(ipuv3, module, reg) \
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bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg))
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#define IPUV3_WRITE(ipuv3, module, reg, val) \
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bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val))
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#define CPMEM_CHANNEL_OFFSET(_c) ((_c) * 0x40)
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#define CPMEM_WORD_OFFSET(_w) ((_w) * 0x20)
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#define CPMEM_DP_OFFSET(_d) ((_d) * 0x10000)
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#define IMX_IPU_DP0 0
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#define IMX_IPU_DP1 1
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#define CPMEM_CHANNEL(_dp, _ch, _w) \
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(CPMEM_DP_OFFSET(_dp) + CPMEM_CHANNEL_OFFSET(_ch) + \
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CPMEM_WORD_OFFSET(_w))
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#define CPMEM_OFFSET(_dp, _ch, _w, _o) \
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(CPMEM_CHANNEL((_dp), (_ch), (_w)) + (_o))
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static int ipu3_fb_probe(device_t);
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static int ipu3_fb_attach(device_t);
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static void
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ipu3_fb_init(struct ipu3sc_softc *sc)
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{
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uint64_t w0sh96;
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uint32_t w1sh96;
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/* FW W0[137:125] - 96 = [41:29] */
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/* FH W0[149:138] - 96 = [53:42] */
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w0sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 16));
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w0sh96 <<= 32;
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w0sh96 |= IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 0, 12));
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sc->sc_info.fb_width = ((w0sh96 >> 29) & 0x1fff) + 1;
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sc->sc_info.fb_height = ((w0sh96 >> 42) & 0x0fff) + 1;
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/* SLY W1[115:102] - 96 = [19:6] */
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w1sh96 = IPUV3_READ(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 12));
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sc->sc_info.fb_stride = ((w1sh96 >> 6) & 0x3fff) + 1;
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printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height,
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sc->sc_info.fb_stride);
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sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride;
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sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size,
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M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0);
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sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase);
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/* DP1 + config_ch_23 + word_2 */
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IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 0),
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(((uint32_t)sc->sc_info.fb_pbase >> 3) |
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(((uint32_t)sc->sc_info.fb_pbase >> 3) << 29)) & 0xffffffff);
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IPUV3_WRITE(sc, cpmem, CPMEM_OFFSET(IMX_IPU_DP1, 23, 1, 4),
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(((uint32_t)sc->sc_info.fb_pbase >> 3) >> 3) & 0xffffffff);
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/* XXX: fetch or set it from/to IPU. */
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sc->sc_info.fb_bpp = sc->sc_info.fb_depth = sc->sc_info.fb_stride /
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sc->sc_info.fb_width * 8;
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}
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/* Use own color map, because of different RGB offset. */
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static int
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ipu3_fb_init_cmap(uint32_t *cmap, int bytespp)
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{
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switch (bytespp) {
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case 8:
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return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB,
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0x7, 5, 0x7, 2, 0x3, 0));
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case 15:
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return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB,
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0x1f, 10, 0x1f, 5, 0x1f, 0));
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case 16:
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return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB,
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0x1f, 11, 0x3f, 5, 0x1f, 0));
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case 24:
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case 32: /* Ignore alpha. */
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return (vt_generate_vga_palette(cmap, COLOR_FORMAT_RGB,
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0xff, 16, 0xff, 8, 0xff, 0));
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default:
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return (1);
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}
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}
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static int
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ipu3_fb_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "fsl,ipu3"))
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return (ENXIO);
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device_set_desc(dev, "i.MX515 Image Processing Unit (FB)");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ipu3_fb_attach(device_t dev)
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{
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struct ipu3sc_softc *sc = device_get_softc(dev);
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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int err;
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ipu3sc_softc = sc;
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device_printf(dev, "\tclock gate status is %d\n",
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imx51_get_clk_gating(IMX51CLK_IPU_HSP_CLK_ROOT));
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sc->dev = dev;
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sc = device_get_softc(dev);
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sc->iot = iot = fdtbus_bs_tag;
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device_printf(sc->dev, ": i.MX51 IPUV3 controller\n");
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/* map controller registers */
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err = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &ioh);
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if (err)
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goto fail_retarn_cm;
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sc->cm_ioh = ioh;
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/* map Display Multi FIFO Controller registers */
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err = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &ioh);
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if (err)
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goto fail_retarn_dmfc;
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sc->dmfc_ioh = ioh;
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/* map Display Interface 0 registers */
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err = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &ioh);
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if (err)
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goto fail_retarn_di0;
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sc->di0_ioh = ioh;
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/* map Display Interface 1 registers */
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err = bus_space_map(iot, IPU_DI1_BASE, IPU_DI0_SIZE, 0, &ioh);
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if (err)
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goto fail_retarn_di1;
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sc->di1_ioh = ioh;
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/* map Display Processor registers */
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err = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &ioh);
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if (err)
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goto fail_retarn_dp;
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sc->dp_ioh = ioh;
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/* map Display Controller registers */
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err = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &ioh);
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if (err)
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goto fail_retarn_dc;
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sc->dc_ioh = ioh;
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/* map Image DMA Controller registers */
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err = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &ioh);
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if (err)
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goto fail_retarn_idmac;
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sc->idmac_ioh = ioh;
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/* map CPMEM registers */
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err = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &ioh);
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if (err)
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goto fail_retarn_cpmem;
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sc->cpmem_ioh = ioh;
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/* map DCTEMPL registers */
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err = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &ioh);
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if (err)
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goto fail_retarn_dctmpl;
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sc->dctmpl_ioh = ioh;
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#ifdef notyet
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sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO,
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ipuv3intr, sc);
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if (sc->ih == NULL) {
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device_printf(sc->dev,
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"unable to establish interrupt at irq %d\n",
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IMX51_INT_IPUV3);
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return (ENXIO);
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}
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#endif
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/*
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* We have to wait until interrupts are enabled.
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* Mailbox relies on it to get data from VideoCore
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*/
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ipu3_fb_init(sc);
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sc->sc_info.fb_name = device_get_nameunit(dev);
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ipu3_fb_init_cmap(sc->sc_info.fb_cmap, sc->sc_info.fb_depth);
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sc->sc_info.fb_cmsize = 16;
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/* Ask newbus to attach framebuffer device to me. */
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sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev));
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if (sc->sc_fbd == NULL)
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device_printf(dev, "Can't attach fbd device\n");
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return (bus_generic_attach(dev));
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fail_retarn_dctmpl:
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bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE);
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fail_retarn_cpmem:
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bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE);
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fail_retarn_idmac:
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bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE);
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fail_retarn_dp:
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bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE);
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fail_retarn_dc:
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bus_space_unmap(sc->iot, sc->di1_ioh, IPU_DI1_SIZE);
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fail_retarn_di1:
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bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE);
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fail_retarn_di0:
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bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE);
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fail_retarn_dmfc:
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bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE);
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fail_retarn_cm:
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device_printf(sc->dev,
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"failed to map registers (errno=%d)\n", err);
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return (err);
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}
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static struct fb_info *
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ipu3_fb_getinfo(device_t dev)
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{
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struct ipu3sc_softc *sc = device_get_softc(dev);
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return (&sc->sc_info);
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}
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static device_method_t ipu3_fb_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ipu3_fb_probe),
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DEVMETHOD(device_attach, ipu3_fb_attach),
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/* Framebuffer service methods */
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DEVMETHOD(fb_getinfo, ipu3_fb_getinfo),
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{ 0, 0 }
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};
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static devclass_t ipu3_fb_devclass;
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static driver_t ipu3_fb_driver = {
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"fb",
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ipu3_fb_methods,
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sizeof(struct ipu3sc_softc),
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};
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DRIVER_MODULE(fb, simplebus, ipu3_fb_driver, ipu3_fb_devclass, 0, 0);
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