From d4a0747609e71f3bc4a94b77f5b61444581f805a Mon Sep 17 00:00:00 2001
From: kib <kib@FreeBSD.org>
Date: Tue, 26 Jan 2016 07:57:44 +0000
Subject: [PATCH 001/113] Restore flushing of output for revoke(2) again. 
 Document revoke()'s intended behaviour in its man page.  Simplify tty_drain()
 to match. Don't call ttydevsw methods in tty_flush() if the device is gone
 since we now sometimes call it then.

The flushing was supposed to be implemented by passing the FNONBLOCK
flag to VOP_CLOSE() for revoke().  The tty driver is one of the few
that can block in close and was one of the fewer that knew about this.

This almost worked in FreeBSD-1 and similarly in Net/2.  These
versions only almost worked because there was and is considerable
confusion between IO_NDELAY and FNONBLOCK (aka O_NONBLOCK).  IO_NDELAY
is only valid for VOP_READ() and VOP_WRITE().  For other VOPs it has
the same value as O_SHLOCK.  But since vfs_subr.c and tty.c
consistently used the wrong flag and the O_SHLOCK flag is rarely set,
this mostly worked.  It also gave the feature than applications could
get the non-blocking close by abusing O_SHLOCK.

This was first broken then fixed in 1995.  I changed only the tty
driver to use FNONBLOCK, as a hack to get non-blocking via the normal
flag FNONBLOCK for last closes.  I didn't know about revoke()'s use
of IO_NDELAY or change it to be consistent, so revoke() was broken.
Then I changed revoke() to match.

This was next broken in 1997 then fixed in 1998.  Importing Lite2 made
the flags inconsistent again by undoing the fix only in vfs_subr.c.

This was next broken in 2008 by replacing everything in tty.c and not
checking any flags in last close.  Other bugs in draining limited the
resulting unbounded waits to drain in some cases.

It is now possible to fix this better using the new FREVOKE flag.
Just restore flushing for revoke() for now.  Don't restore or undo any
hacks for ordinary last closes yet.  But remove dead code in the
1-second relative timeout (r272789).  This did extra work to extend
the buggy draining for revoke() for as long as possible.  The 1-second
timeout made this not very long by usually flushing after 1 second.

Submitted by:	bde
MFC after:	2 weeks
---
 lib/libc/sys/revoke.2 |  8 ++++++--
 sys/kern/tty.c        | 29 ++++++++++++++---------------
 2 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/lib/libc/sys/revoke.2 b/lib/libc/sys/revoke.2
index 482cbf661ba6..3d7ad00bfe34 100644
--- a/lib/libc/sys/revoke.2
+++ b/lib/libc/sys/revoke.2
@@ -31,7 +31,7 @@
 .\"     @(#)revoke.2	8.1 (Berkeley) 6/4/93
 .\" $FreeBSD$
 .\"
-.Dd June 4, 1993
+.Dd Jan 25, 2016
 .Dt REVOKE 2
 .Os
 .Sh NAME
@@ -59,7 +59,8 @@ and a
 system call will succeed.
 If the file is a special file for a device which is open,
 the device close function
-is called as if all open references to the file had been closed.
+is called as if all open references to the file had been closed
+using a special close method which does not block.
 .Pp
 Access to a file may be revoked only by its owner or the super user.
 The
@@ -104,3 +105,6 @@ The
 .Fn revoke
 system call first appeared in
 .Bx 4.3 Reno .
+.Sh BUGS
+The non-blocking close method is only correctly implemented for
+terminal devices.
diff --git a/sys/kern/tty.c b/sys/kern/tty.c
index 2d233270dea3..04a10b38075b 100644
--- a/sys/kern/tty.c
+++ b/sys/kern/tty.c
@@ -126,7 +126,7 @@ static int
 tty_drain(struct tty *tp, int leaving)
 {
 	size_t bytesused;
-	int error, revokecnt;
+	int error;
 
 	if (ttyhook_hashook(tp, getc_inject))
 		/* buffer is inaccessible */
@@ -141,18 +141,10 @@ tty_drain(struct tty *tp, int leaving)
 
 		/* Wait for data to be drained. */
 		if (leaving) {
-			revokecnt = tp->t_revokecnt;
 			error = tty_timedwait(tp, &tp->t_outwait, hz);
-			switch (error) {
-			case ERESTART:
-				if (revokecnt != tp->t_revokecnt)
-					error = 0;
-				break;
-			case EWOULDBLOCK:
-				if (ttyoutq_bytesused(&tp->t_outq) < bytesused)
-					error = 0;
-				break;
-			}
+			if (error == EWOULDBLOCK &&
+			    ttyoutq_bytesused(&tp->t_outq) < bytesused)
+				error = 0;
 		} else
 			error = tty_wait(tp, &tp->t_outwait);
 
@@ -356,6 +348,10 @@ ttydev_close(struct cdev *dev, int fflag, int devtype __unused,
 		return (0);
 	}
 
+	/* If revoking, flush output now to avoid draining it later. */
+	if (fflag & FREVOKE)
+		tty_flush(tp, FWRITE);
+
 	/*
 	 * This can only be called once. The callin and the callout
 	 * devices cannot be opened at the same time.
@@ -1460,13 +1456,16 @@ tty_flush(struct tty *tp, int flags)
 		tp->t_flags &= ~TF_HIWAT_OUT;
 		ttyoutq_flush(&tp->t_outq);
 		tty_wakeup(tp, FWRITE);
-		ttydevsw_pktnotify(tp, TIOCPKT_FLUSHWRITE);
+		if (!tty_gone(tp))
+			ttydevsw_pktnotify(tp, TIOCPKT_FLUSHWRITE);
 	}
 	if (flags & FREAD) {
 		tty_hiwat_in_unblock(tp);
 		ttyinq_flush(&tp->t_inq);
-		ttydevsw_inwakeup(tp);
-		ttydevsw_pktnotify(tp, TIOCPKT_FLUSHREAD);
+		if (!tty_gone(tp)) {
+			ttydevsw_inwakeup(tp);
+			ttydevsw_pktnotify(tp, TIOCPKT_FLUSHREAD);
+		}
 	}
 }
 

From cb8114cddde04c71f498ec034550e219a6adac73 Mon Sep 17 00:00:00 2001
From: sephe <sephe@FreeBSD.org>
Date: Tue, 26 Jan 2016 09:42:13 +0000
Subject: [PATCH 002/113] hyperv/hn: Improve sending performance

- Avoid main lock contention by trylock for if_start, if that fails,
  schedule TX taskqueue for if_start
- Don't do direct sending if the packet to be sent is large, e.g.
  TSO packet.

This change gives me stable 9.1Gbps TCP sending performance w/ TSO
over a 10Gbe directly connected network (the performance fluctuated
between 4Gbps and 9Gbps before this commit). It also improves non-
TSO TCP sending performance a lot.

Reviewed by:		adrian, royger
Approved by:		adrian (mentor)
Sponsored by:		Microsoft OSTC
Differential Revision:	https://reviews.freebsd.org/D5074
---
 sys/dev/hyperv/netvsc/hv_net_vsc.h            |   9 +-
 sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c | 127 +++++++++++++++---
 2 files changed, 115 insertions(+), 21 deletions(-)

diff --git a/sys/dev/hyperv/netvsc/hv_net_vsc.h b/sys/dev/hyperv/netvsc/hv_net_vsc.h
index dbe546453e58..c19034043e38 100644
--- a/sys/dev/hyperv/netvsc/hv_net_vsc.h
+++ b/sys/dev/hyperv/netvsc/hv_net_vsc.h
@@ -39,9 +39,11 @@
 #define __HV_NET_VSC_H__
 
 #include <sys/param.h>
+#include <sys/kernel.h>
 #include <sys/lock.h>
 #include <sys/malloc.h>
 #include <sys/queue.h>
+#include <sys/taskqueue.h>
 #include <sys/sx.h>
 
 #include <machine/bus.h>
@@ -1008,7 +1010,6 @@ typedef struct hn_softc {
 	struct hv_device  *hn_dev_obj;
 	netvsc_dev  	*net_dev;
 
-	int		hn_txdesc_cnt;
 	struct hn_txdesc *hn_txdesc;
 	bus_dma_tag_t	hn_tx_data_dtag;
 	bus_dma_tag_t	hn_tx_rndis_dtag;
@@ -1017,9 +1018,15 @@ typedef struct hn_softc {
 
 	struct mtx	hn_txlist_spin;
 	struct hn_txdesc_list hn_txlist;
+	int		hn_txdesc_cnt;
 	int		hn_txdesc_avail;
 	int		hn_txeof;
 
+	int		hn_direct_tx_size;
+	struct taskqueue *hn_tx_taskq;
+	struct task	hn_start_task;
+	struct task	hn_txeof_task;
+
 	struct lro_ctrl	hn_lro;
 	int		hn_lro_hiwat;
 
diff --git a/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c b/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c
index 10e8adaaff96..ab88e367106d 100644
--- a/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c
+++ b/sys/dev/hyperv/netvsc/hv_netvsc_drv_freebsd.c
@@ -146,6 +146,8 @@ __FBSDID("$FreeBSD$");
 #define HN_TX_DATA_SEGCNT_MAX		\
     (NETVSC_PACKET_MAXPAGE - HV_RF_NUM_TX_RESERVED_PAGE_BUFS)
 
+#define HN_DIRECT_TX_SIZE_DEF		128
+
 struct hn_txdesc {
 	SLIST_ENTRY(hn_txdesc) link;
 	struct mbuf	*m;
@@ -194,6 +196,7 @@ struct hn_txdesc {
 #define NV_LOCK_INIT(_sc, _name) \
 	    mtx_init(&(_sc)->hn_lock, _name, MTX_NETWORK_LOCK, MTX_DEF)
 #define NV_LOCK(_sc)		mtx_lock(&(_sc)->hn_lock)
+#define NV_TRYLOCK(_sc)		mtx_trylock(&(_sc)->hn_lock)
 #define NV_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->hn_lock, MA_OWNED)
 #define NV_UNLOCK(_sc)		mtx_unlock(&(_sc)->hn_lock)
 #define NV_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->hn_lock)
@@ -219,6 +222,10 @@ TUNABLE_INT("dev.hn.tso_maxlen", &hn_tso_maxlen);
 static int hn_tx_chimney_size = 0;
 TUNABLE_INT("dev.hn.tx_chimney_size", &hn_tx_chimney_size);
 
+/* Limit the size of packet for direct transmission */
+static int hn_direct_tx_size = HN_DIRECT_TX_SIZE_DEF;
+TUNABLE_INT("dev.hn.direct_tx_size", &hn_direct_tx_size);
+
 /*
  * Forward declarations
  */
@@ -226,8 +233,9 @@ static void hn_stop(hn_softc_t *sc);
 static void hn_ifinit_locked(hn_softc_t *sc);
 static void hn_ifinit(void *xsc);
 static int  hn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
-static void hn_start_locked(struct ifnet *ifp);
+static int hn_start_locked(struct ifnet *ifp, int len);
 static void hn_start(struct ifnet *ifp);
+static void hn_start_txeof(struct ifnet *ifp);
 static int hn_ifmedia_upd(struct ifnet *ifp);
 static void hn_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr);
 #ifdef HN_LRO_HIWAT
@@ -237,6 +245,8 @@ static int hn_tx_chimney_size_sysctl(SYSCTL_HANDLER_ARGS);
 static int hn_check_iplen(const struct mbuf *, int);
 static int hn_create_tx_ring(struct hn_softc *sc);
 static void hn_destroy_tx_ring(struct hn_softc *sc);
+static void hn_start_taskfunc(void *xsc, int pending);
+static void hn_txeof_taskfunc(void *xsc, int pending);
 
 static __inline void
 hn_set_lro_hiwat(struct hn_softc *sc, int hiwat)
@@ -384,6 +394,14 @@ netvsc_attach(device_t dev)
 	sc->hn_dev = dev;
 	sc->hn_lro_hiwat = HN_LRO_HIWAT_DEF;
 	sc->hn_trust_hosttcp = hn_trust_hosttcp;
+	sc->hn_direct_tx_size = hn_direct_tx_size;
+
+	sc->hn_tx_taskq = taskqueue_create_fast("hn_tx", M_WAITOK,
+	    taskqueue_thread_enqueue, &sc->hn_tx_taskq);
+	taskqueue_start_threads(&sc->hn_tx_taskq, 1, PI_NET, "%s tx",
+	    device_get_nameunit(dev));
+	TASK_INIT(&sc->hn_start_task, 0, hn_start_taskfunc, sc);
+	TASK_INIT(&sc->hn_txeof_task, 0, hn_txeof_taskfunc, sc);
 
 	error = hn_create_tx_ring(sc);
 	if (error)
@@ -524,6 +542,9 @@ netvsc_attach(device_t dev)
 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_chimney_size",
 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, hn_tx_chimney_size_sysctl,
 	    "I", "Chimney send packet size limit");
+	SYSCTL_ADD_INT(ctx, child, OID_AUTO, "direct_tx_size",
+	    CTLFLAG_RW, &sc->hn_direct_tx_size, 0,
+	    "Size of the packet for direct transmission");
 
 	if (unit == 0) {
 		struct sysctl_ctx_list *dc_ctx;
@@ -548,6 +569,9 @@ netvsc_attach(device_t dev)
 		SYSCTL_ADD_INT(dc_ctx, dc_child, OID_AUTO, "tso_maxlen",
 		    CTLFLAG_RD, &hn_tso_maxlen, 0, "TSO burst limit");
 #endif
+		SYSCTL_ADD_INT(dc_ctx, dc_child, OID_AUTO, "direct_tx_size",
+		    CTLFLAG_RD, &hn_direct_tx_size, 0,
+		    "Size of the packet for direct transmission");
 	}
 
 	return (0);
@@ -583,6 +607,10 @@ netvsc_detach(device_t dev)
 
 	hv_rf_on_device_remove(hv_device, HV_RF_NV_DESTROY_CHANNEL);
 
+	taskqueue_drain(sc->hn_tx_taskq, &sc->hn_start_task);
+	taskqueue_drain(sc->hn_tx_taskq, &sc->hn_txeof_task);
+	taskqueue_free(sc->hn_tx_taskq);
+
 	ifmedia_removeall(&sc->hn_media);
 #if defined(INET) || defined(INET6)
 	tcp_lro_free(&sc->hn_lro);
@@ -733,24 +761,19 @@ void
 netvsc_channel_rollup(struct hv_device *device_ctx)
 {
 	struct hn_softc *sc = device_get_softc(device_ctx->device);
-	struct ifnet *ifp;
 
 	if (!sc->hn_txeof)
 		return;
 
 	sc->hn_txeof = 0;
-	ifp = sc->hn_ifp;
-	NV_LOCK(sc);
-	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
-	hn_start_locked(ifp);
-	NV_UNLOCK(sc);
+	hn_start_txeof(sc->hn_ifp);
 }
 
 /*
  * Start a transmit of one or more packets
  */
-static void
-hn_start_locked(struct ifnet *ifp)
+static int
+hn_start_locked(struct ifnet *ifp, int len)
 {
 	hn_softc_t *sc = ifp->if_softc;
 	struct hv_device *device_ctx = vmbus_get_devctx(sc->hn_dev);
@@ -768,7 +791,7 @@ hn_start_locked(struct ifnet *ifp)
 
 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
 	    IFF_DRV_RUNNING)
-		return;
+		return 0;
 
 	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
 		bus_dma_segment_t segs[HN_TX_DATA_SEGCNT_MAX];
@@ -781,11 +804,21 @@ hn_start_locked(struct ifnet *ifp)
 		if (m_head == NULL)
 			break;
 
+		if (len > 0 && m_head->m_pkthdr.len > len) {
+			/*
+			 * This sending could be time consuming; let callers
+			 * dispatch this packet sending (and sending of any
+			 * following up packets) to tx taskqueue.
+			 */
+			IF_PREPEND(&ifp->if_snd, m_head);
+			return 1;
+		}
+
 		txd = hn_txdesc_get(sc);
 		if (txd == NULL) {
 			sc->hn_no_txdescs++;
 			IF_PREPEND(&ifp->if_snd, m_head);
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+			atomic_set_int(&ifp->if_drv_flags, IFF_DRV_OACTIVE);
 			break;
 		}
 
@@ -1060,10 +1093,11 @@ hn_start_locked(struct ifnet *ifp)
 
 			sc->hn_send_failed++;
 			IF_PREPEND(&ifp->if_snd, m_head);
-			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
+			atomic_set_int(&ifp->if_drv_flags, IFF_DRV_OACTIVE);
 			break;
 		}
 	}
+	return 0;
 }
 
 /*
@@ -1555,7 +1589,8 @@ hn_stop(hn_softc_t *sc)
 	if (bootverbose)
 		printf(" Closing Device ...\n");
 
-	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
+	atomic_clear_int(&ifp->if_drv_flags,
+	    (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
 	if_link_state_change(ifp, LINK_STATE_DOWN);
 	sc->hn_initdone = 0;
 
@@ -1571,13 +1606,43 @@ hn_start(struct ifnet *ifp)
 	hn_softc_t *sc;
 
 	sc = ifp->if_softc;
-	NV_LOCK(sc);
-	if (sc->temp_unusable) {
+	if (NV_TRYLOCK(sc)) {
+		int sched;
+
+		sched = hn_start_locked(ifp, sc->hn_direct_tx_size);
 		NV_UNLOCK(sc);
-		return;
+		if (!sched)
+			return;
+	}
+	taskqueue_enqueue_fast(sc->hn_tx_taskq, &sc->hn_start_task);
+}
+
+static void
+hn_start_txeof(struct ifnet *ifp)
+{
+	hn_softc_t *sc;
+
+	sc = ifp->if_softc;
+	if (NV_TRYLOCK(sc)) {
+		int sched;
+
+		atomic_clear_int(&ifp->if_drv_flags, IFF_DRV_OACTIVE);
+		sched = hn_start_locked(ifp, sc->hn_direct_tx_size);
+		NV_UNLOCK(sc);
+		if (sched) {
+			taskqueue_enqueue_fast(sc->hn_tx_taskq,
+			    &sc->hn_start_task);
+		}
+	} else {
+		/*
+		 * Release the OACTIVE earlier, with the hope, that
+		 * others could catch up.  The task will clear the
+		 * flag again with the NV_LOCK to avoid possible
+		 * races.
+		 */
+		atomic_clear_int(&ifp->if_drv_flags, IFF_DRV_OACTIVE);
+		taskqueue_enqueue_fast(sc->hn_tx_taskq, &sc->hn_txeof_task);
 	}
-	hn_start_locked(ifp);
-	NV_UNLOCK(sc);
 }
 
 /*
@@ -1604,8 +1669,8 @@ hn_ifinit_locked(hn_softc_t *sc)
 	} else {
 		sc->hn_initdone = 1;
 	}
-	ifp->if_drv_flags |= IFF_DRV_RUNNING;
-	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+	atomic_clear_int(&ifp->if_drv_flags, IFF_DRV_OACTIVE);
+	atomic_set_int(&ifp->if_drv_flags, IFF_DRV_RUNNING);
 	if_link_state_change(ifp, LINK_STATE_UP);
 }
 
@@ -1907,6 +1972,28 @@ hn_destroy_tx_ring(struct hn_softc *sc)
 	mtx_destroy(&sc->hn_txlist_spin);
 }
 
+static void
+hn_start_taskfunc(void *xsc, int pending __unused)
+{
+	struct hn_softc *sc = xsc;
+
+	NV_LOCK(sc);
+	hn_start_locked(sc->hn_ifp, 0);
+	NV_UNLOCK(sc);
+}
+
+static void
+hn_txeof_taskfunc(void *xsc, int pending __unused)
+{
+	struct hn_softc *sc = xsc;
+	struct ifnet *ifp = sc->hn_ifp;
+
+	NV_LOCK(sc);
+	atomic_clear_int(&ifp->if_drv_flags, IFF_DRV_OACTIVE);
+	hn_start_locked(ifp, 0);
+	NV_UNLOCK(sc);
+}
+
 static device_method_t netvsc_methods[] = {
         /* Device interface */
         DEVMETHOD(device_probe,         netvsc_probe),

From 3cfb62716e7bef4bde11dcfef84d5554c0323595 Mon Sep 17 00:00:00 2001
From: skra <skra@FreeBSD.org>
Date: Tue, 26 Jan 2016 09:50:23 +0000
Subject: [PATCH 003/113] Make code more compact and readable better in
 pmap_extract() like functions. No functional change.

This is a follow up to r294722.

Suggested by:	kib
---
 sys/arm/arm/pmap-v6.c | 25 ++++++-------------------
 sys/arm/arm/pmap.c    | 41 ++++++++++++-----------------------------
 2 files changed, 18 insertions(+), 48 deletions(-)

diff --git a/sys/arm/arm/pmap-v6.c b/sys/arm/arm/pmap-v6.c
index 26a075db63df..5d7021189ed7 100644
--- a/sys/arm/arm/pmap-v6.c
+++ b/sys/arm/arm/pmap-v6.c
@@ -3446,14 +3446,10 @@ pmap_extract_locked(pmap_t pmap, vm_offset_t va)
 		pte = ptep[l2pte_index(va)];
 		if (pte == 0)
 			return (0);
-		switch (pte & L2_TYPE_MASK) {
-		case L2_TYPE_L:
+		if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
 			pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
-			break;
-		default:
+		else
 			pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
-			break;
-		}
 	}
 	return (pa);
 }
@@ -3515,20 +3511,15 @@ pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
 			PMAP_UNLOCK(pmap);
 			return (NULL);
 		} else {
-			switch (pte & L2_TYPE_MASK) {
-			case L2_TYPE_L:
+			if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
 				panic("extract and hold section mapping");
-				break;
-			default:
+			else
 				pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
-				break;
-			}
 			if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
 				goto retry;
 			m = PHYS_TO_VM_PAGE(pa);
 			vm_page_hold(m);
 		}
-
 	}
 
 	PMAP_UNLOCK(pmap);
@@ -3567,14 +3558,10 @@ pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
 			pa = 0;
 			goto out;
 		}
-		switch (pte & L2_TYPE_MASK) {
-		case L2_TYPE_L:
+		if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
 			pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
-			break;
-		default:
+		else
 			pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
-			break;
-		}
 	}
 out:
 	if (pte2p != NULL)
diff --git a/sys/arm/arm/pmap.c b/sys/arm/arm/pmap.c
index e698f0e0885e..3dd998429dfc 100644
--- a/sys/arm/arm/pmap.c
+++ b/sys/arm/arm/pmap.c
@@ -2787,18 +2787,14 @@ pmap_kremove(vm_offset_t va)
 	pte = &l2b->l2b_kva[l2pte_index(va)];
 	opte = *pte;
 	if (l2pte_valid(opte)) {
-			/* pa = vtophs(va) taken from pmap_extract() */
-		switch (opte & L2_TYPE_MASK) {
-		case L2_TYPE_L:
+		/* pa = vtophs(va) taken from pmap_extract() */
+		if ((opte & L2_TYPE_MASK) == L2_TYPE_L)
 			pa = (opte & L2_L_FRAME) | (va & L2_L_OFFSET);
-			break;
-		default:
+		else
 			pa = (opte & L2_S_FRAME) | (va & L2_S_OFFSET);
-			break;
-		}
-			/* note: should never have to remove an allocation
-			 * before the pvzone is initialized.
-			 */
+		/* note: should never have to remove an allocation
+		 * before the pvzone is initialized.
+		 */
 		rw_wlock(&pvh_global_lock);
 		PMAP_LOCK(pmap_kernel());
 		if (pvzone != NULL && (m = vm_phys_paddr_to_vm_page(pa)) &&
@@ -3645,14 +3641,10 @@ pmap_extract_locked(pmap_t pmap, vm_offset_t va)
 		pte = ptep[l2pte_index(va)];
 		if (pte == 0)
 			return (0);
-		switch (pte & L2_TYPE_MASK) {
-		case L2_TYPE_L:
+		if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
 			pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
-			break;
-		default:
+		else
 			pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
-			break;
-		}
 	}
 	return (pa);
 }
@@ -3717,15 +3709,10 @@ pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
 			return (NULL);
 		}
 		if (pte & L2_S_PROT_W || (prot & VM_PROT_WRITE) == 0) {
-			switch (pte & L2_TYPE_MASK) {
-			case L2_TYPE_L:
+			if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
 				pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
-				break;
-
-			default:
+			else
 				pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
-				break;
-			}
 			if (vm_page_pa_tryrelock(pmap, pa & PG_FRAME, &paddr))
 				goto retry;
 			m = PHYS_TO_VM_PAGE(pa);
@@ -3769,14 +3756,10 @@ pmap_dump_kextract(vm_offset_t va, pt2_entry_t *pte2p)
 			pa = 0;
 			goto out;
 		}
-		switch (pte & L2_TYPE_MASK) {
-		case L2_TYPE_L:
+		if ((pte & L2_TYPE_MASK) == L2_TYPE_L)
 			pa = (pte & L2_L_FRAME) | (va & L2_L_OFFSET);
-			break;
-		default:
+		else
 			pa = (pte & L2_S_FRAME) | (va & L2_S_OFFSET);
-			break;
-		}
 	}
 out:
 	if (pte2p != NULL)

From f628f78b7413eaed11b2da38906dd013dedf5385 Mon Sep 17 00:00:00 2001
From: skra <skra@FreeBSD.org>
Date: Tue, 26 Jan 2016 10:24:18 +0000
Subject: [PATCH 004/113] Don't do icache sync on kernel memory and keep in
 line with comment in elf_cpu_load_file(). The only time when the sync is
 needed is after kernel module is loaded and the relocation info is processed.
 And it's done in elf_cpu_load_file().

---
 sys/arm/arm/pmap-v6-new.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/sys/arm/arm/pmap-v6-new.c b/sys/arm/arm/pmap-v6-new.c
index 5c56f6c46ab4..2e4dfe26b1d9 100644
--- a/sys/arm/arm/pmap-v6-new.c
+++ b/sys/arm/arm/pmap-v6-new.c
@@ -3799,14 +3799,19 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
 		 * is set. Do it now, before the mapping is stored and made
 		 * valid for hardware table walk. If done later, there is a race
 		 * for other threads of current process in lazy loading case.
+		 * Don't do it for kernel memory which is mapped with exec
+		 * permission even if the memory isn't going to hold executable
+		 * code. The only time when icache sync is needed is after
+		 * kernel module is loaded and the relocation info is processed.
+		 * And it's done in elf_cpu_load_file().
 		 *
 		 * QQQ: (1) Does it exist any better way where
 		 *          or how to sync icache?
 		 *      (2) Now, we do it on a page basis.
 		 */
-		if ((prot & VM_PROT_EXECUTE) &&
-		    (m->md.pat_mode == PTE2_ATTR_WB_WA) &&
-		    ((opa != pa) || (opte2 & PTE2_NX)))
+		if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
+		    m->md.pat_mode == PTE2_ATTR_WB_WA &&
+		    (opa != pa || (opte2 & PTE2_NX)))
 			cache_icache_sync_fresh(va, pa, PAGE_SIZE);
 
 		npte2 |= PTE2_A;
@@ -4405,7 +4410,7 @@ pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
 		l2prot |= PTE2_U | PTE2_NG;
 	if ((prot & VM_PROT_EXECUTE) == 0)
 		l2prot |= PTE2_NX;
-	else if (m->md.pat_mode == PTE2_ATTR_WB_WA) {
+	else if (m->md.pat_mode == PTE2_ATTR_WB_WA && pmap != kernel_pmap) {
 		/*
 		 * Sync icache if exec permission and attribute PTE2_ATTR_WB_WA
 		 * is set. QQQ: For more info, see comments in pmap_enter().
@@ -4476,7 +4481,7 @@ pmap_enter_pte1(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
 		l1prot |= PTE1_U | PTE1_NG;
 	if ((prot & VM_PROT_EXECUTE) == 0)
 		l1prot |= PTE1_NX;
-	else if (m->md.pat_mode == PTE2_ATTR_WB_WA) {
+	else if (m->md.pat_mode == PTE2_ATTR_WB_WA && pmap != kernel_pmap) {
 		/*
 		 * Sync icache if exec permission and attribute PTE2_ATTR_WB_WA
 		 * is set. QQQ: For more info, see comments in pmap_enter().

From 8e0224f2c9a71228d1737b8467e708d93bbda509 Mon Sep 17 00:00:00 2001
From: trasz <trasz@FreeBSD.org>
Date: Tue, 26 Jan 2016 11:28:55 +0000
Subject: [PATCH 005/113] Fix the way RCTL handles rules' rrl_exceeded on
 credenials change. Because of what this variable does, it was probably
 harmless - but still incorrect.

MFC after:	1 month
Sponsored by:	The FreeBSD Foundation
---
 sys/kern/kern_rctl.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/sys/kern/kern_rctl.c b/sys/kern/kern_rctl.c
index ee3b385a97c1..b0d3fd62bd94 100644
--- a/sys/kern/kern_rctl.c
+++ b/sys/kern/kern_rctl.c
@@ -1745,6 +1745,7 @@ rctl_proc_ucred_changed(struct proc *p, struct ucred *newcred)
 	for (i = 0; i < rulecnt; i++) {
 		newlink = uma_zalloc(rctl_rule_link_zone, M_WAITOK);
 		newlink->rrl_rule = NULL;
+		newlink->rrl_exceeded = 0;
 		LIST_INSERT_HEAD(&newrules, newlink, rrl_next);
 	}
 
@@ -1761,6 +1762,7 @@ rctl_proc_ucred_changed(struct proc *p, struct ucred *newcred)
 				goto goaround;
 			rctl_rule_acquire(link->rrl_rule);
 			newlink->rrl_rule = link->rrl_rule;
+			newlink->rrl_exceeded = link->rrl_exceeded;
 			newlink = LIST_NEXT(newlink, rrl_next);
 			rulecnt--;
 		}
@@ -1771,6 +1773,7 @@ rctl_proc_ucred_changed(struct proc *p, struct ucred *newcred)
 			goto goaround;
 		rctl_rule_acquire(link->rrl_rule);
 		newlink->rrl_rule = link->rrl_rule;
+		newlink->rrl_exceeded = link->rrl_exceeded;
 		newlink = LIST_NEXT(newlink, rrl_next);
 		rulecnt--;
 	}
@@ -1780,6 +1783,7 @@ rctl_proc_ucred_changed(struct proc *p, struct ucred *newcred)
 			goto goaround;
 		rctl_rule_acquire(link->rrl_rule);
 		newlink->rrl_rule = link->rrl_rule;
+		newlink->rrl_exceeded = link->rrl_exceeded;
 		newlink = LIST_NEXT(newlink, rrl_next);
 		rulecnt--;
 	}
@@ -1789,6 +1793,7 @@ rctl_proc_ucred_changed(struct proc *p, struct ucred *newcred)
 			goto goaround;
 		rctl_rule_acquire(link->rrl_rule);
 		newlink->rrl_rule = link->rrl_rule;
+		newlink->rrl_exceeded = link->rrl_exceeded;
 		newlink = LIST_NEXT(newlink, rrl_next);
 		rulecnt--;
 	}

From 0631608b3c2208d619b0563a2bef9fd993be6563 Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 12:28:53 +0000
Subject: [PATCH 006/113] MFV r294793: 6367 spa_config_tryenter incorrectly
 handles the multiple-lock case

Reviewed by: Alek Pinchuk <alek.pinchuk@nexenta.com>
Reviewed by: Josef 'Jeff' Sipek <josef.sipek@nexenta.com>
Reviewed by: Prashanth Sreenivasa <prashksp@gmail.com>
Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Reviewed by: Dan McDonald <danmcd@omniti.com>
Reviewed by: Steven Hartland <steven.hartland@multiplay.co.uk>
Approved by: Matthew Ahrens <mahrens@delphix.com>

illumos/illumos-gate@e495b6e6735b803e422025a630352ef9bba788c5
---
 sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa_misc.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa_misc.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa_misc.c
index 1aa566c7d036..d5764bc96ec1 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa_misc.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa_misc.c
@@ -21,7 +21,7 @@
 /*
  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  * Copyright (c) 2011, 2015 by Delphix. All rights reserved.
- * Copyright 2011 Nexenta Systems, Inc.  All rights reserved.
+ * Copyright 2015 Nexenta Systems, Inc.  All rights reserved.
  * Copyright 2013 Martin Matuska <mm@FreeBSD.org>. All rights reserved.
  * Copyright (c) 2014 Spectra Logic Corporation, All rights reserved.
  * Copyright 2013 Saso Kiselkov. All rights reserved.
@@ -449,14 +449,16 @@ spa_config_tryenter(spa_t *spa, int locks, void *tag, krw_t rw)
 		if (rw == RW_READER) {
 			if (scl->scl_writer || scl->scl_write_wanted) {
 				mutex_exit(&scl->scl_lock);
-				spa_config_exit(spa, locks ^ (1 << i), tag);
+				spa_config_exit(spa, locks & ((1 << i) - 1),
+				    tag);
 				return (0);
 			}
 		} else {
 			ASSERT(scl->scl_writer != curthread);
 			if (!refcount_is_zero(&scl->scl_count)) {
 				mutex_exit(&scl->scl_lock);
-				spa_config_exit(spa, locks ^ (1 << i), tag);
+				spa_config_exit(spa, locks & ((1 << i) - 1),
+				    tag);
 				return (0);
 			}
 			scl->scl_writer = curthread;

From 22b46bda2f34d82190f8e8571ff9ff07f51c1e5d Mon Sep 17 00:00:00 2001
From: smh <smh@FreeBSD.org>
Date: Tue, 26 Jan 2016 12:30:17 +0000
Subject: [PATCH 007/113] ixgbe sysctl hardware defaults

Added hw.ix.flow_control which enables the default flow_control of all ix
interfaces to be set in loader.conf.

Added hw.ix.advertise_speed which enables the default advertised_speed of
all ix interfaces to be set in loader.conf.

Made enable_aim device independent based on hw.ix.enable_aim default.

Reviewed by:	erj
MFC after:	1 week
Sponsored by:	Multiplay
Differential Revision:	https://reviews.freebsd.org/D5060
---
 sys/dev/ixgbe/if_ix.c | 134 +++++++++++++++++++++++++++---------------
 sys/dev/ixgbe/ixgbe.h |   1 +
 2 files changed, 86 insertions(+), 49 deletions(-)

diff --git a/sys/dev/ixgbe/if_ix.c b/sys/dev/ixgbe/if_ix.c
index 8d96c9a40a68..168fa1310f74 100644
--- a/sys/dev/ixgbe/if_ix.c
+++ b/sys/dev/ixgbe/if_ix.c
@@ -166,12 +166,14 @@ static void	ixgbe_unregister_vlan(void *, struct ifnet *, u16);
 
 static void	ixgbe_add_device_sysctls(struct adapter *);
 static void     ixgbe_add_hw_stats(struct adapter *);
+static int	ixgbe_set_flowcntl(struct adapter *, int);
+static int	ixgbe_set_advertise(struct adapter *, int);
 
 /* Sysctl handlers */
 static void	ixgbe_set_sysctl_value(struct adapter *, const char *,
 		     const char *, int *, int);
-static int	ixgbe_set_flowcntl(SYSCTL_HANDLER_ARGS);
-static int	ixgbe_set_advertise(SYSCTL_HANDLER_ARGS);
+static int	ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS);
+static int	ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS);
 static int	ixgbe_sysctl_thermal_test(SYSCTL_HANDLER_ARGS);
 static int	ixgbe_sysctl_dmac(SYSCTL_HANDLER_ARGS);
 static int	ixgbe_sysctl_phy_temp(SYSCTL_HANDLER_ARGS);
@@ -290,6 +292,16 @@ SYSCTL_INT(_hw_ix, OID_AUTO, tx_process_limit, CTLFLAG_RDTUN,
     "Maximum number of sent packets to process at a time,"
     "-1 means unlimited");
 
+/* Flow control setting, default to full */
+static int ixgbe_flow_control = ixgbe_fc_full;
+SYSCTL_INT(_hw_ix, OID_AUTO, flow_control, CTLFLAG_RDTUN,
+    &ixgbe_flow_control, 0, "Default flow control used for all adapters");
+
+/* Advertise Speed, default to 0 (auto) */
+static int ixgbe_advertise_speed = 0;
+SYSCTL_INT(_hw_ix, OID_AUTO, advertise_speed, CTLFLAG_RDTUN,
+    &ixgbe_advertise_speed, 0, "Default advertised speed for all adapters");
+
 /*
 ** Smart speed setting, default to on
 ** this only works as a compile option
@@ -568,6 +580,11 @@ ixgbe_attach(device_t dev)
 		break;
 	}
 
+	/* hw.ix defaults init */
+	ixgbe_set_advertise(adapter, ixgbe_advertise_speed);
+	ixgbe_set_flowcntl(adapter, ixgbe_flow_control);
+	adapter->enable_aim = ixgbe_enable_aim;
+
 	if ((adapter->msix > 1) && (ixgbe_enable_msix))
 		error = ixgbe_allocate_msix(adapter); 
 	else
@@ -1553,7 +1570,7 @@ ixgbe_msix_que(void *arg)
 
 	/* Do AIM now? */
 
-	if (ixgbe_enable_aim == FALSE)
+	if (adapter->enable_aim == FALSE)
 		goto no_calc;
 	/*
 	** Do Adaptive Interrupt Moderation:
@@ -4276,7 +4293,7 @@ ixgbe_add_device_sysctls(struct adapter *adapter)
 	/* Sysctls for all devices */
 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "fc",
 			CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
-			ixgbe_set_flowcntl, "I", IXGBE_SYSCTL_DESC_SET_FC);
+			ixgbe_sysctl_flowcntl, "I", IXGBE_SYSCTL_DESC_SET_FC);
 
         SYSCTL_ADD_INT(ctx, child, OID_AUTO, "enable_aim",
 			CTLFLAG_RW,
@@ -4284,7 +4301,7 @@ ixgbe_add_device_sysctls(struct adapter *adapter)
 
 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "advertise_speed",
 			CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
-			ixgbe_set_advertise, "I", IXGBE_SYSCTL_DESC_ADV_SPEED);
+			ixgbe_sysctl_advertise, "I", IXGBE_SYSCTL_DESC_ADV_SPEED);
 
 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "thermal_test",
 			CTLTYPE_INT | CTLFLAG_RW, adapter, 0,
@@ -4649,41 +4666,51 @@ ixgbe_set_sysctl_value(struct adapter *adapter, const char *name,
 **	3 - full
 */
 static int
-ixgbe_set_flowcntl(SYSCTL_HANDLER_ARGS)
+ixgbe_sysctl_flowcntl(SYSCTL_HANDLER_ARGS)
 {
-	int error, last;
-	struct adapter *adapter = (struct adapter *) arg1;
+	int error, fc;
+	struct adapter *adapter;
 
-	last = adapter->fc;
-	error = sysctl_handle_int(oidp, &adapter->fc, 0, req);
+	adapter = (struct adapter *) arg1;
+	fc = adapter->fc;
+
+	error = sysctl_handle_int(oidp, &fc, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 
 	/* Don't bother if it's not changed */
-	if (adapter->fc == last)
+	if (adapter->fc == fc)
 		return (0);
 
-	switch (adapter->fc) {
-		case ixgbe_fc_rx_pause:
-		case ixgbe_fc_tx_pause:
-		case ixgbe_fc_full:
-			adapter->hw.fc.requested_mode = adapter->fc;
-			if (adapter->num_queues > 1)
-				ixgbe_disable_rx_drop(adapter);
-			break;
-		case ixgbe_fc_none:
-			adapter->hw.fc.requested_mode = ixgbe_fc_none;
-			if (adapter->num_queues > 1)
-				ixgbe_enable_rx_drop(adapter);
-			break;
-		default:
-			adapter->fc = last;
-			return (EINVAL);
+	return ixgbe_set_flowcntl(adapter, fc);
+}
+
+
+static int
+ixgbe_set_flowcntl(struct adapter *adapter, int fc)
+{
+
+	switch (fc) {
+	case ixgbe_fc_rx_pause:
+	case ixgbe_fc_tx_pause:
+	case ixgbe_fc_full:
+		adapter->hw.fc.requested_mode = adapter->fc;
+		if (adapter->num_queues > 1)
+			ixgbe_disable_rx_drop(adapter);
+		break;
+	case ixgbe_fc_none:
+		adapter->hw.fc.requested_mode = ixgbe_fc_none;
+		if (adapter->num_queues > 1)
+			ixgbe_enable_rx_drop(adapter);
+		break;
+	default:
+		return (EINVAL);
 	}
+	adapter->fc = fc;
 	/* Don't autoneg if forcing a value */
 	adapter->hw.fc.disable_fc_autoneg = TRUE;
 	ixgbe_fc_enable(&adapter->hw);
-	return error;
+	return (0);
 }
 
 /*
@@ -4694,31 +4721,39 @@ ixgbe_set_flowcntl(SYSCTL_HANDLER_ARGS)
 **	0x4 - advertise 10G
 */
 static int
-ixgbe_set_advertise(SYSCTL_HANDLER_ARGS)
+ixgbe_sysctl_advertise(SYSCTL_HANDLER_ARGS)
 {
-	int			error = 0, requested;
-	struct adapter		*adapter;
-	device_t		dev;
-	struct ixgbe_hw		*hw;
-	ixgbe_link_speed	speed = 0;
+	int error, advertise;
+	struct adapter *adapter;
 
 	adapter = (struct adapter *) arg1;
-	dev = adapter->dev;
-	hw = &adapter->hw;
+	advertise = adapter->advertise;
 
-	requested = adapter->advertise;
-	error = sysctl_handle_int(oidp, &requested, 0, req);
+	error = sysctl_handle_int(oidp, &advertise, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 
+	/* Checks to validate new value */
+	if (adapter->advertise == advertise) /* no change */
+		return (0);
+
+	return ixgbe_set_advertise(adapter, advertise);
+}
+
+static int
+ixgbe_set_advertise(struct adapter *adapter, int advertise)
+{
+	device_t		dev;
+	struct ixgbe_hw		*hw;
+	ixgbe_link_speed	speed;
+
+	hw = &adapter->hw;
+	dev = adapter->dev;
+
 	/* No speed changes for backplane media */
 	if (hw->phy.media_type == ixgbe_media_type_backplane)
 		return (ENODEV);
 
-	/* Checks to validate new value */
-	if (adapter->advertise == requested) /* no change */
-		return (0);
-
 	if (!((hw->phy.media_type == ixgbe_media_type_copper) ||
 	    (hw->phy.multispeed_fiber))) {
 		device_printf(dev,
@@ -4727,13 +4762,13 @@ ixgbe_set_advertise(SYSCTL_HANDLER_ARGS)
 		return (EINVAL);
 	}
 
-	if (requested < 0x1 || requested > 0x7) {
+	if (advertise < 0x1 || advertise > 0x7) {
 		device_printf(dev,
 		    "Invalid advertised speed; valid modes are 0x1 through 0x7\n");
 		return (EINVAL);
 	}
 
-	if ((requested & 0x1)
+	if ((advertise & 0x1)
 	    && (hw->mac.type != ixgbe_mac_X540)
 	    && (hw->mac.type != ixgbe_mac_X550)) {
 		device_printf(dev, "Set Advertise: 100Mb on X540/X550 only\n");
@@ -4741,18 +4776,19 @@ ixgbe_set_advertise(SYSCTL_HANDLER_ARGS)
 	}
 
 	/* Set new value and report new advertised mode */
-	if (requested & 0x1)
+	speed = 0;
+	if (advertise & 0x1)
 		speed |= IXGBE_LINK_SPEED_100_FULL;
-	if (requested & 0x2)
+	if (advertise & 0x2)
 		speed |= IXGBE_LINK_SPEED_1GB_FULL;
-	if (requested & 0x4)
+	if (advertise & 0x4)
 		speed |= IXGBE_LINK_SPEED_10GB_FULL;
+	adapter->advertise = advertise;
 
 	hw->mac.autotry_restart = TRUE;
 	hw->mac.ops.setup_link(hw, speed, TRUE);
-	adapter->advertise = requested;
 
-	return (error);
+	return (0);
 }
 
 /*
diff --git a/sys/dev/ixgbe/ixgbe.h b/sys/dev/ixgbe/ixgbe.h
index 243f37bae14b..6a1522f82564 100644
--- a/sys/dev/ixgbe/ixgbe.h
+++ b/sys/dev/ixgbe/ixgbe.h
@@ -497,6 +497,7 @@ struct adapter {
 	u32			optics;
 	u32			fc; /* local flow ctrl setting */
 	int			advertise;  /* link speeds */
+	bool			enable_aim; /* adaptive interrupt moderation */
 	bool			link_active;
 	u16			max_frame_size;
 	u16			num_segs;

From c81378ec32c559331fba0969bef5b851cf02e747 Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 12:33:58 +0000
Subject: [PATCH 008/113] MFV r294796: 6319 assertion failed in zio_ddt_write:
 bp->blk_birth == txg

Reviewed by: George Wilson <george.wilson@delphix.com>
Approved by: Dan McDonald <danmcd@omniti.com>

illumos/illumos-gate@b39b744be78c6327db43c1f69d11c2f5909f73cb

This is revert of 5693.
---
 sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c
index 896c56e04328..901e618efdcd 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c
@@ -1217,6 +1217,8 @@ zio_write_bp_init(zio_t *zio)
 			zio->io_pipeline |= ZIO_STAGE_DDT_WRITE;
 			return (ZIO_PIPELINE_CONTINUE);
 		}
+		zio->io_bp_override = NULL;
+		BP_ZERO(bp);
 	}
 
 	if (!BP_IS_HOLE(bp) && bp->blk_birth == zio->io_txg) {

From 9b06fb3e337c983bc54973e40ff3b976b1f14e6b Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 12:37:23 +0000
Subject: [PATCH 009/113] MFV r294798: 6292 exporting a pool while an async
 destroy is running can leave entries in the deferred tree

Reviewed by: Paul Dagnelie <pcd@delphix.com>
Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Reviewed by: Andriy Gapon <avg@FreeBSD.org>
Reviewed by: Fabian Keil <fk@fabiankeil.de>
Approved by: Gordon Ross <gordon.ross@nexenta.com>

illumos/illumos-gate@a443cc80c742af740aa82130db840f02b4389365
---
 .../opensolaris/uts/common/fs/zfs/dsl_scan.c    | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c
index 55229456ca34..402398572e48 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c
@@ -1440,11 +1440,24 @@ dsl_scan_sync(dsl_pool_t *dp, dmu_tx_t *tx)
 		dsl_scan_setup_sync(&func, tx);
 	}
 
+	/*
+	 * Only process scans in sync pass 1.
+	 */
+	if (spa_sync_pass(dp->dp_spa) > 1)
+		return;
+
+	/*
+	 * If the spa is shutting down, then stop scanning. This will
+	 * ensure that the scan does not dirty any new data during the
+	 * shutdown phase.
+	 */
+	if (spa_shutting_down(spa))
+		return;
+
 	/*
 	 * If the scan is inactive due to a stalled async destroy, try again.
 	 */
-	if ((!scn->scn_async_stalled && !dsl_scan_active(scn)) ||
-	    spa_sync_pass(dp->dp_spa) > 1)
+	if (!scn->scn_async_stalled && !dsl_scan_active(scn))
 		return;
 
 	scn->scn_visited_this_txg = 0;

From 39cc035b094c3947f46e395e94678da3cb4a9588 Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 12:44:49 +0000
Subject: [PATCH 010/113] MFV r294800: 6385 Fix unlocking order in zfs_zget

Reviewed by: Brian Behlendorf <behlendorf1@llnl.gov>
Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Reviewed by: Dan Kimmel <dan.kimmel@delphix.com>
Reviewed by: Andriy Gapon <avg@freebsd.org>
Approved by: Robert Mustacchi <rm@joyent.com>
Author: Richard Yao <ryao@gentoo.org>

illumos/illumos-gate@eaef6a96de3f6afbbccc69bd7a0aed4463689d0a
---
 sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_znode.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_znode.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_znode.c
index 3d30082c6b7f..0a985c3a210c 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_znode.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_znode.c
@@ -1175,13 +1175,13 @@ zfs_zget(zfsvfs_t *zfsvfs, uint64_t obj_num, znode_t **zpp)
 			*zpp = zp;
 			err = 0;
 		}
-		sa_buf_rele(db, NULL);
 
 		/* Don't let the vnode disappear after ZFS_OBJ_HOLD_EXIT. */
 		if (err == 0)
 			VN_HOLD(vp);
 
 		mutex_exit(&zp->z_lock);
+		sa_buf_rele(db, NULL);
 		ZFS_OBJ_HOLD_EXIT(zfsvfs, obj_num);
 
 		if (err == 0) {

From 291649d74a29fcc3b59ebffb992d8936cdf6df91 Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 12:48:10 +0000
Subject: [PATCH 011/113] MFV r294802: 6334 Cannot unlink files when over quota

Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Reviewed by: Toomas Soome <tsoome@me.com>
Approved by: Dan McDonald <danmcd@omniti.com>
Author: Simon Klinkert <simon.klinkert@gmail.com>

illumos/illumos-gate@6575bca01367958c7237253d88e5fa9ef0b1650a
---
 sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c
index 78f84470497a..9df85a741af1 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c
@@ -2009,12 +2009,9 @@ zfs_remove(vnode_t *dvp, char *name, cred_t *cr, caller_context_t *ct,
 	dmu_tx_hold_zap(tx, zfsvfs->z_unlinkedobj, FALSE, NULL);
 
 	/*
-	 * Mark this transaction as typically resulting in a net free of
-	 * space, unless object removal will be delayed indefinitely
-	 * (due to active holds on the vnode due to the file being open).
+	 * Mark this transaction as typically resulting in a net free of space
 	 */
-	if (may_delete_now)
-		dmu_tx_mark_netfree(tx);
+	dmu_tx_mark_netfree(tx);
 
 	error = dmu_tx_assign(tx, waited ? TXG_WAITED : TXG_NOWAIT);
 	if (error) {

From 40a0b8ba84d386690cd493a111a31c0744b733c1 Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 12:50:14 +0000
Subject: [PATCH 012/113] MFV r294804: 6386 Fix function call with
 uninitialized value in vdev_inuse

Reviewed by: Brian Behlendorf <behlendorf1@llnl.gov>
Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Reviewed by: Dan Kimmel <dan.kimmel@delphix.com>
Approved by: Robert Mustacchi <rm@joyent.com>
Author: Richard Yao <ryao@gentoo.org>

illumos/illumos-gate@5bdd995ddb777f538bfbcc5e2d5ff1bed07ae56e
---
 sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c
index 9befa75a5ee5..05dcfb4e68ed 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c
@@ -602,7 +602,8 @@ vdev_inuse(vdev_t *vd, uint64_t crtxg, vdev_labeltype_t reason,
 	 * read-only.  Instead we look to see if the pools is marked
 	 * read-only in the namespace and set the state to active.
 	 */
-	if ((spa = spa_by_guid(pool_guid, device_guid)) != NULL &&
+	if (state != POOL_STATE_SPARE && state != POOL_STATE_L2CACHE &&
+	    (spa = spa_by_guid(pool_guid, device_guid)) != NULL &&
 	    spa_mode(spa) == FREAD)
 		state = POOL_STATE_ACTIVE;
 

From 43d7dc455af608e947dce27f45f1d4d2fb22148b Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 12:52:16 +0000
Subject: [PATCH 013/113] MFV r294806: 6388 Failure of userland copy should
 return EFAULT

Reviewed by: Brian Behlendorf <behlendorf1@llnl.gov>
Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Reviewed by: Dan Kimmel <dan.kimmel@delphix.com>
Approved by: Robert Mustacchi <rm@joyent.com>
Author: Richard Yao <ryao@gentoo.org>

illumos/illumos-gate@c71c00bbe8a9cdc7e3f4048b751f48e80441d506
---
 sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c
index f12f0cd43269..25633c0c2bbe 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c
@@ -1339,7 +1339,7 @@ get_nvlist(uint64_t nvl, uint64_t size, int iflag, nvlist_t **nvp)
 	if ((error = ddi_copyin((void *)(uintptr_t)nvl, packed, size,
 	    iflag)) != 0) {
 		kmem_free(packed, size);
-		return (error);
+		return (SET_ERROR(EFAULT));
 	}
 
 	if ((error = nvlist_unpack(packed, size, &list, 0)) != 0) {

From 113741fe87b369f0d4f1d4dba4583ac4087b291b Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 12:54:03 +0000
Subject: [PATCH 014/113] MFV r294808: 6421 Add missing multilist_destroy calls
 to arc_fini

Reviewed by: Dan Kimmel <dan.kimmel@delphix.com>
Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Reviewed by: Jorgen Lundman <lundman@lundman.net>
Approved by: Robert Mustacchi <rm@joyent.com>
Author: Prakash Surya <prakash.surya@delphix.com>

illumos/illumos-gate@57deb2328260c447bf1db25fe74e0eece102733e
---
 sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c
index 0123a799eea5..fad9874d3cd2 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c
@@ -5567,10 +5567,12 @@ arc_fini(void)
 	multilist_destroy(&arc_mru_ghost->arcs_list[ARC_BUFC_METADATA]);
 	multilist_destroy(&arc_mfu->arcs_list[ARC_BUFC_METADATA]);
 	multilist_destroy(&arc_mfu_ghost->arcs_list[ARC_BUFC_METADATA]);
+	multilist_destroy(&arc_l2c_only->arcs_list[ARC_BUFC_METADATA]);
 	multilist_destroy(&arc_mru->arcs_list[ARC_BUFC_DATA]);
 	multilist_destroy(&arc_mru_ghost->arcs_list[ARC_BUFC_DATA]);
 	multilist_destroy(&arc_mfu->arcs_list[ARC_BUFC_DATA]);
 	multilist_destroy(&arc_mfu_ghost->arcs_list[ARC_BUFC_DATA]);
+	multilist_destroy(&arc_l2c_only->arcs_list[ARC_BUFC_DATA]);
 
 	buf_fini();
 

From 7a16fdf1bdbf715261321537a5b08817d6a66982 Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 12:58:58 +0000
Subject: [PATCH 015/113] MFV r294810: 6414 vdev_config_sync could be simpler

Reviewed by: George Wilson <george.wilson@delphix.com>
Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Approved by: Robert Mustacchi <rm@joyent.com>
Author: Will Andrews <will@firepipe.net>

illumos/illumos-gate@eb5bb58421f46cee79155a55688e6c675e7dd361
---
 .../contrib/opensolaris/uts/common/fs/zfs/spa.c  | 10 ++--------
 .../opensolaris/uts/common/fs/zfs/sys/vdev.h     |  3 +--
 .../opensolaris/uts/common/fs/zfs/vdev_label.c   | 16 ++++++++++------
 3 files changed, 13 insertions(+), 16 deletions(-)

diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c
index b7801acaadc5..9caed4d5c95a 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c
@@ -6768,16 +6768,10 @@ spa_sync(spa_t *spa, uint64_t txg)
 				if (svdcount == SPA_DVAS_PER_BP)
 					break;
 			}
-			error = vdev_config_sync(svd, svdcount, txg, B_FALSE);
-			if (error != 0)
-				error = vdev_config_sync(svd, svdcount, txg,
-				    B_TRUE);
+			error = vdev_config_sync(svd, svdcount, txg);
 		} else {
 			error = vdev_config_sync(rvd->vdev_child,
-			    rvd->vdev_children, txg, B_FALSE);
-			if (error != 0)
-				error = vdev_config_sync(rvd->vdev_child,
-				    rvd->vdev_children, txg, B_TRUE);
+			    rvd->vdev_children, txg);
 		}
 
 		if (error == 0)
diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev.h
index ff46ba6b513c..6312f03fa5d3 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev.h
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/vdev.h
@@ -127,8 +127,7 @@ extern void vdev_queue_register_lastoffset(vdev_t *vd, zio_t *zio);
 
 extern void vdev_config_dirty(vdev_t *vd);
 extern void vdev_config_clean(vdev_t *vd);
-extern int vdev_config_sync(vdev_t **svd, int svdcount, uint64_t txg,
-    boolean_t);
+extern int vdev_config_sync(vdev_t **svd, int svdcount, uint64_t txg);
 
 extern void vdev_state_dirty(vdev_t *vd);
 extern void vdev_state_clean(vdev_t *vd);
diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c
index 05dcfb4e68ed..77191e742ff8 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c
@@ -1194,15 +1194,16 @@ vdev_label_sync_list(spa_t *spa, int l, uint64_t txg, int flags)
  * at any time, you can just call it again, and it will resume its work.
  */
 int
-vdev_config_sync(vdev_t **svd, int svdcount, uint64_t txg, boolean_t tryhard)
+vdev_config_sync(vdev_t **svd, int svdcount, uint64_t txg)
 {
 	spa_t *spa = svd[0]->vdev_spa;
 	uberblock_t *ub = &spa->spa_uberblock;
 	vdev_t *vd;
 	zio_t *zio;
-	int error;
+	int error = 0;
 	int flags = ZIO_FLAG_CONFIG_WRITER | ZIO_FLAG_CANFAIL;
 
+retry:
 	/*
 	 * Normally, we don't want to try too hard to write every label and
 	 * uberblock.  If there is a flaky disk, we don't want the rest of the
@@ -1210,8 +1211,11 @@ vdev_config_sync(vdev_t **svd, int svdcount, uint64_t txg, boolean_t tryhard)
 	 * single label out, we should retry with ZIO_FLAG_TRYHARD before
 	 * bailing out and declaring the pool faulted.
 	 */
-	if (tryhard)
+	if (error != 0) {
+		if ((flags & ZIO_FLAG_TRYHARD) != 0)
+			return (error);
 		flags |= ZIO_FLAG_TRYHARD;
+	}
 
 	ASSERT(ub->ub_txg <= txg);
 
@@ -1255,7 +1259,7 @@ vdev_config_sync(vdev_t **svd, int svdcount, uint64_t txg, boolean_t tryhard)
 	 * are committed to stable storage before the uberblock update.
 	 */
 	if ((error = vdev_label_sync_list(spa, 0, txg, flags)) != 0)
-		return (error);
+		goto retry;
 
 	/*
 	 * Sync the uberblocks to all vdevs in svd[].
@@ -1273,7 +1277,7 @@ vdev_config_sync(vdev_t **svd, int svdcount, uint64_t txg, boolean_t tryhard)
 	 *	to the new uberblocks.
 	 */
 	if ((error = vdev_uberblock_sync_list(svd, svdcount, ub, flags)) != 0)
-		return (error);
+		goto retry;
 
 	/*
 	 * Sync out odd labels for every dirty vdev.  If the system dies
@@ -1286,7 +1290,7 @@ vdev_config_sync(vdev_t **svd, int svdcount, uint64_t txg, boolean_t tryhard)
 	 * stable storage before the next transaction group begins.
 	 */
 	if ((error = vdev_label_sync_list(spa, 1, txg, flags)) != 0)
-		return (error);
+		goto retry;;
 
 	trim_thread_wakeup(spa);
 

From 71d7abc46e4defbcf77033c417935b944c13084a Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 13:03:01 +0000
Subject: [PATCH 016/113] MFV r294812: 6434 sa_find_sizes() may compute wrong
 SA header size

Reviewed-by: Ned Bass <bass6@llnl.gov>
Reviewed-by: Brian Behlendorf <behlendorf1@llnl.gov>
Reviewed by: Andriy Gapon <avg@freebsd.org>
Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Approved by: Robert Mustacchi <rm@joyent.com>
Author: James Pan <jiaming.pan@yahoo.com>

illumos/illumos-gate@3502ed6e7cb3f3d2e781960ab8fe465fdc884834
---
 .../opensolaris/uts/common/fs/zfs/sa.c        | 46 +++++++++----------
 1 file changed, 22 insertions(+), 24 deletions(-)

diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sa.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sa.c
index 90355a9abe8a..9293e9a97e27 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sa.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sa.c
@@ -547,10 +547,9 @@ sa_find_sizes(sa_os_t *sa, sa_bulk_attr_t *attr_desc, int attr_count,
 {
 	int var_size = 0;
 	int i;
-	int j = -1;
 	int full_space;
 	int hdrsize;
-	boolean_t done = B_FALSE;
+	int extra_hdrsize;
 
 	if (buftype == SA_BONUS && sa->sa_force_spill) {
 		*total = 0;
@@ -561,10 +560,9 @@ sa_find_sizes(sa_os_t *sa, sa_bulk_attr_t *attr_desc, int attr_count,
 
 	*index = -1;
 	*total = 0;
+	*will_spill = B_FALSE;
 
-	if (buftype == SA_BONUS)
-		*will_spill = B_FALSE;
-
+	extra_hdrsize = 0;
 	hdrsize = (SA_BONUSTYPE_FROM_DB(db) == DMU_OT_ZNODE) ? 0 :
 	    sizeof (sa_hdr_phys_t);
 
@@ -576,8 +574,8 @@ sa_find_sizes(sa_os_t *sa, sa_bulk_attr_t *attr_desc, int attr_count,
 
 		*total = P2ROUNDUP(*total, 8);
 		*total += attr_desc[i].sa_length;
-		if (done)
-			goto next;
+		if (*will_spill)
+			continue;
 
 		is_var_sz = (SA_REGISTERED_LEN(sa, attr_desc[i].sa_attr) == 0);
 		if (is_var_sz) {
@@ -585,21 +583,28 @@ sa_find_sizes(sa_os_t *sa, sa_bulk_attr_t *attr_desc, int attr_count,
 		}
 
 		if (is_var_sz && var_size > 1) {
-			if (P2ROUNDUP(hdrsize + sizeof (uint16_t), 8) +
+			/*
+			 * Don't worry that the spill block might overflow.
+			 * It will be resized if needed in sa_build_layouts().
+			 */
+			if (buftype == SA_SPILL ||
+			    P2ROUNDUP(hdrsize + sizeof (uint16_t), 8) +
 			    *total < full_space) {
 				/*
 				 * Account for header space used by array of
 				 * optional sizes of variable-length attributes.
-				 * Record the index in case this increase needs
-				 * to be reversed due to spill-over.
+				 * Record the extra header size in case this
+				 * increase needs to be reversed due to
+				 * spill-over.
 				 */
 				hdrsize += sizeof (uint16_t);
-				j = i;
+				if (*index != -1)
+					extra_hdrsize += sizeof (uint16_t);
 			} else {
-				done = B_TRUE;
-				*index = i;
-				if (buftype == SA_BONUS)
-					*will_spill = B_TRUE;
+				ASSERT(buftype == SA_BONUS);
+				if (*index == -1)
+					*index = i;
+				*will_spill = B_TRUE;
 				continue;
 			}
 		}
@@ -614,22 +619,15 @@ sa_find_sizes(sa_os_t *sa, sa_bulk_attr_t *attr_desc, int attr_count,
 		    (*total + P2ROUNDUP(hdrsize, 8)) >
 		    (full_space - sizeof (blkptr_t))) {
 			*index = i;
-			done = B_TRUE;
 		}
 
-next:
 		if ((*total + P2ROUNDUP(hdrsize, 8)) > full_space &&
 		    buftype == SA_BONUS)
 			*will_spill = B_TRUE;
 	}
 
-	/*
-	 * j holds the index of the last variable-sized attribute for
-	 * which hdrsize was increased.  Reverse the increase if that
-	 * attribute will be relocated to the spill block.
-	 */
-	if (*will_spill && j == *index)
-		hdrsize -= sizeof (uint16_t);
+	if (*will_spill)
+		hdrsize -= extra_hdrsize;
 
 	hdrsize = P2ROUNDUP(hdrsize, 8);
 	return (hdrsize);

From f904c5a333da8e5dc66548da80c974216ef23c97 Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 13:14:39 +0000
Subject: [PATCH 017/113] MFV r294814: 6393 zfs receive a full send as a clone

Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Reviewed by: Prakash Surya <prakash.surya@delphix.com>
Reviewed by: Richard Elling <Richard.Elling@RichardElling.com>
Approved by: Dan McDonald <danmcd@omniti.com>
Author: Paul Dagnelie <pcd@delphix.com>

illumos/illumos-gate@68ecb2ec930c4b0f00acaf8e0abb2b19c4b8b76f

This allows to do a full (non-incremental send) and receive it as a clone
of an existing dataset. It can leverage nopwrite to share blocks with the
origin. This can be used to change the relationship of datasets on the
target. For example, maybe on the source you have:

A ---- B ---- C

And you have sent to the target a full of B, and the incremental B->C:

B ---- C

You later realize that you want to have A on the target. You will have to
do a full send of A, but nopwrite can save you space on the target if you
receive it as a clone of B, assuming that A and B have some blocks inxi
common:

B ---- C
 \
  A
---
 cddl/contrib/opensolaris/cmd/zfs/zfs.8        |   7 +-
 .../opensolaris/uts/common/fs/zfs/dmu_send.c  | 158 ++++++++++++------
 .../uts/common/fs/zfs/sys/dmu_impl.h          |   3 +-
 .../uts/common/fs/zfs/sys/zfs_ioctl.h         |  12 +-
 4 files changed, 122 insertions(+), 58 deletions(-)

diff --git a/cddl/contrib/opensolaris/cmd/zfs/zfs.8 b/cddl/contrib/opensolaris/cmd/zfs/zfs.8
index 71ac878e1cbe..dedfc0a31c03 100644
--- a/cddl/contrib/opensolaris/cmd/zfs/zfs.8
+++ b/cddl/contrib/opensolaris/cmd/zfs/zfs.8
@@ -2841,8 +2841,11 @@ Do not actually receive the stream. This can be useful in conjunction with the
 option to verify the name the receive operation would use.
 .It Fl o Sy origin Ns = Ns Ar snapshot
 Forces the stream to be received as a clone of the given snapshot.
-This is only valid if the stream is an incremental stream whose source
-is the same as the provided origin.
+If the stream is a full send stream, this will create the filesystem
+described by the stream as a clone of the specified snapshot. Which
+snapshot was specified will not affect the success or failure of the
+receive, as long as the snapshot does exist.  If the stream is an
+incremental send stream, all the normal verification will be performed.
 .It Fl F
 Force a rollback of the file system to the most recent snapshot before
 performing the receive operation. If receiving an incremental replication
diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_send.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_send.c
index ede1555b7096..00f52d6ebe38 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_send.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_send.c
@@ -158,6 +158,14 @@ dump_record(dmu_sendarg_t *dsp, void *payload, int payload_len)
 	return (0);
 }
 
+/*
+ * Fill in the drr_free struct, or perform aggregation if the previous record is
+ * also a free record, and the two are adjacent.
+ *
+ * Note that we send free records even for a full send, because we want to be
+ * able to receive a full send as a clone, which requires a list of all the free
+ * and freeobject records that were generated on the source.
+ */
 static int
 dump_free(dmu_sendarg_t *dsp, uint64_t object, uint64_t offset,
     uint64_t length)
@@ -181,15 +189,6 @@ dump_free(dmu_sendarg_t *dsp, uint64_t object, uint64_t offset,
 	    (object == dsp->dsa_last_data_object &&
 	    offset > dsp->dsa_last_data_offset));
 
-	/*
-	 * If we are doing a non-incremental send, then there can't
-	 * be any data in the dataset we're receiving into.  Therefore
-	 * a free record would simply be a no-op.  Save space by not
-	 * sending it to begin with.
-	 */
-	if (!dsp->dsa_incremental)
-		return (0);
-
 	if (length != -1ULL && offset + length < offset)
 		length = -1ULL;
 
@@ -368,10 +367,6 @@ dump_freeobjects(dmu_sendarg_t *dsp, uint64_t firstobj, uint64_t numobjs)
 {
 	struct drr_freeobjects *drrfo = &(dsp->dsa_drr->drr_u.drr_freeobjects);
 
-	/* See comment in dump_free(). */
-	if (!dsp->dsa_incremental)
-		return (0);
-
 	/*
 	 * If there is a pending op, but it's not PENDING_FREEOBJECTS,
 	 * push it out, since free block aggregation can only be done for
@@ -776,6 +771,7 @@ dmu_send_impl(void *tag, dsl_pool_t *dp, dsl_dataset_t *to_ds,
 	drr->drr_u.drr_begin.drr_toguid = dsl_dataset_phys(to_ds)->ds_guid;
 	if (dsl_dataset_phys(to_ds)->ds_flags & DS_FLAG_CI_DATASET)
 		drr->drr_u.drr_begin.drr_flags |= DRR_FLAG_CI_DATA;
+	drr->drr_u.drr_begin.drr_flags |= DRR_FLAG_FREERECORDS;
 
 	if (ancestor_zb != NULL) {
 		drr->drr_u.drr_begin.drr_fromguid =
@@ -799,7 +795,6 @@ dmu_send_impl(void *tag, dsl_pool_t *dp, dsl_dataset_t *to_ds,
 	dsp->dsa_off = off;
 	dsp->dsa_toguid = dsl_dataset_phys(to_ds)->ds_guid;
 	dsp->dsa_pending_op = PENDING_NONE;
-	dsp->dsa_incremental = (ancestor_zb != NULL);
 	dsp->dsa_featureflags = featureflags;
 	dsp->dsa_resume_object = resumeobj;
 	dsp->dsa_resume_offset = resumeoff;
@@ -1321,7 +1316,7 @@ dmu_recv_begin_check(void *arg, dmu_tx_t *tx)
 		/* target fs already exists; recv into temp clone */
 
 		/* Can't recv a clone into an existing fs */
-		if (flags & DRR_FLAG_CLONE) {
+		if (flags & DRR_FLAG_CLONE || drba->drba_origin) {
 			dsl_dataset_rele(ds, FTAG);
 			return (SET_ERROR(EINVAL));
 		}
@@ -1340,6 +1335,15 @@ dmu_recv_begin_check(void *arg, dmu_tx_t *tx)
 		    drba->drba_origin))
 			return (SET_ERROR(ENOENT));
 
+		/*
+		 * If we're receiving a full send as a clone, and it doesn't
+		 * contain all the necessary free records and freeobject
+		 * records, reject it.
+		 */
+		if (fromguid == 0 && drba->drba_origin &&
+		    !(flags & DRR_FLAG_FREERECORDS))
+			return (SET_ERROR(EINVAL));
+
 		/* Open the parent of tofs */
 		ASSERT3U(strlen(tofs), <, MAXNAMELEN);
 		(void) strlcpy(buf, tofs, strrchr(tofs, '/') - tofs + 1);
@@ -1379,7 +1383,8 @@ dmu_recv_begin_check(void *arg, dmu_tx_t *tx)
 				dsl_dataset_rele(ds, FTAG);
 				return (SET_ERROR(EINVAL));
 			}
-			if (dsl_dataset_phys(origin)->ds_guid != fromguid) {
+			if (dsl_dataset_phys(origin)->ds_guid != fromguid &&
+			    fromguid != 0) {
 				dsl_dataset_rele(origin, FTAG);
 				dsl_dataset_rele(ds, FTAG);
 				return (SET_ERROR(ENODEV));
@@ -1709,6 +1714,20 @@ struct receive_writer_arg {
 	uint64_t bytes_read; /* bytes read when current record created */
 };
 
+struct objlist {
+	list_t list; /* List of struct receive_objnode. */
+	/*
+	 * Last object looked up. Used to assert that objects are being looked
+	 * up in ascending order.
+	 */
+	uint64_t last_lookup;
+};
+
+struct receive_objnode {
+	list_node_t node;
+	uint64_t object;
+};
+
 struct receive_arg  {
 	objset_t *os;
 	kthread_t *td;
@@ -1727,12 +1746,7 @@ struct receive_arg  {
 	int err;
 	boolean_t byteswap;
 	/* Sorted list of objects not to issue prefetches for. */
-	list_t ignore_obj_list;
-};
-
-struct receive_ign_obj_node {
-	list_node_t node;
-	uint64_t object;
+	struct objlist ignore_objlist;
 };
 
 typedef struct guid_map_entry {
@@ -2068,13 +2082,14 @@ receive_freeobjects(struct receive_writer_arg *rwa,
     struct drr_freeobjects *drrfo)
 {
 	uint64_t obj;
+	int next_err = 0;
 
 	if (drrfo->drr_firstobj + drrfo->drr_numobjs < drrfo->drr_firstobj)
 		return (SET_ERROR(EINVAL));
 
 	for (obj = drrfo->drr_firstobj;
-	    obj < drrfo->drr_firstobj + drrfo->drr_numobjs;
-	    (void) dmu_object_next(rwa->os, &obj, FALSE, 0)) {
+	    obj < drrfo->drr_firstobj + drrfo->drr_numobjs && next_err == 0;
+	    next_err = dmu_object_next(rwa->os, &obj, FALSE, 0)) {
 		int err;
 
 		if (dmu_object_info(rwa->os, obj, NULL) != 0)
@@ -2084,7 +2099,8 @@ receive_freeobjects(struct receive_writer_arg *rwa,
 		if (err != 0)
 			return (err);
 	}
-
+	if (next_err != ESRCH)
+		return (next_err);
 	return (0);
 }
 
@@ -2414,6 +2430,66 @@ receive_read_payload_and_next_header(struct receive_arg *ra, int len, void *buf)
 	return (0);
 }
 
+static void
+objlist_create(struct objlist *list)
+{
+	list_create(&list->list, sizeof (struct receive_objnode),
+	    offsetof(struct receive_objnode, node));
+	list->last_lookup = 0;
+}
+
+static void
+objlist_destroy(struct objlist *list)
+{
+	for (struct receive_objnode *n = list_remove_head(&list->list);
+	    n != NULL; n = list_remove_head(&list->list)) {
+		kmem_free(n, sizeof (*n));
+	}
+	list_destroy(&list->list);
+}
+
+/*
+ * This function looks through the objlist to see if the specified object number
+ * is contained in the objlist.  In the process, it will remove all object
+ * numbers in the list that are smaller than the specified object number.  Thus,
+ * any lookup of an object number smaller than a previously looked up object
+ * number will always return false; therefore, all lookups should be done in
+ * ascending order.
+ */
+static boolean_t
+objlist_exists(struct objlist *list, uint64_t object)
+{
+	struct receive_objnode *node = list_head(&list->list);
+	ASSERT3U(object, >=, list->last_lookup);
+	list->last_lookup = object;
+	while (node != NULL && node->object < object) {
+		VERIFY3P(node, ==, list_remove_head(&list->list));
+		kmem_free(node, sizeof (*node));
+		node = list_head(&list->list);
+	}
+	return (node != NULL && node->object == object);
+}
+
+/*
+ * The objlist is a list of object numbers stored in ascending order.  However,
+ * the insertion of new object numbers does not seek out the correct location to
+ * store a new object number; instead, it appends it to the list for simplicity.
+ * Thus, any users must take care to only insert new object numbers in ascending
+ * order.
+ */
+static void
+objlist_insert(struct objlist *list, uint64_t object)
+{
+	struct receive_objnode *node = kmem_zalloc(sizeof (*node), KM_SLEEP);
+	node->object = object;
+#ifdef ZFS_DEBUG
+	struct receive_objnode *last_object = list_tail(&list->list);
+	uint64_t last_objnum = (last_object != NULL ? last_object->object : 0);
+	ASSERT3U(node->object, >, last_objnum);
+#endif
+	list_insert_tail(&list->list, node);
+}
+
 /*
  * Issue the prefetch reads for any necessary indirect blocks.
  *
@@ -2436,13 +2512,7 @@ static void
 receive_read_prefetch(struct receive_arg *ra,
     uint64_t object, uint64_t offset, uint64_t length)
 {
-	struct receive_ign_obj_node *node = list_head(&ra->ignore_obj_list);
-	while (node != NULL && node->object < object) {
-		VERIFY3P(node, ==, list_remove_head(&ra->ignore_obj_list));
-		kmem_free(node, sizeof (*node));
-		node = list_head(&ra->ignore_obj_list);
-	}
-	if (node == NULL || node->object > object) {
+	if (!objlist_exists(&ra->ignore_objlist, object)) {
 		dmu_prefetch(ra->os, object, 1, offset, length,
 		    ZIO_PRIORITY_SYNC_READ);
 	}
@@ -2475,18 +2545,7 @@ receive_read_record(struct receive_arg *ra)
 		 */
 		if (err == ENOENT ||
 		    (err == 0 && doi.doi_data_block_size != drro->drr_blksz)) {
-			struct receive_ign_obj_node *node =
-			    kmem_zalloc(sizeof (*node),
-			    KM_SLEEP);
-			node->object = drro->drr_object;
-#ifdef ZFS_DEBUG
-			struct receive_ign_obj_node *last_object =
-			    list_tail(&ra->ignore_obj_list);
-			uint64_t last_objnum = (last_object != NULL ?
-			    last_object->object : 0);
-			ASSERT3U(node->object, >, last_objnum);
-#endif
-			list_insert_tail(&ra->ignore_obj_list, node);
+			objlist_insert(&ra->ignore_objlist, drro->drr_object);
 			err = 0;
 		}
 		return (err);
@@ -2704,7 +2763,6 @@ resume_check(struct receive_arg *ra, nvlist_t *begin_nvl)
 	return (0);
 }
 
-
 /*
  * Read in the stream's records, one by one, and apply them to the pool.  There
  * are two threads involved; the thread that calls this function will spin up a
@@ -2739,8 +2797,7 @@ dmu_recv_stream(dmu_recv_cookie_t *drc, struct file *fp, offset_t *voffp,
 		    sizeof (ra.bytes_read), 1, &ra.bytes_read);
 	}
 
-	list_create(&ra.ignore_obj_list, sizeof (struct receive_ign_obj_node),
-	    offsetof(struct receive_ign_obj_node, node));
+	objlist_create(&ra.ignore_objlist);
 
 	/* these were verified in dmu_recv_begin */
 	ASSERT3U(DMU_GET_STREAM_HDRTYPE(drc->drc_drrb->drr_versioninfo), ==,
@@ -2894,12 +2951,7 @@ dmu_recv_stream(dmu_recv_cookie_t *drc, struct file *fp, offset_t *voffp,
 	}
 
 	*voffp = ra.voff;
-	for (struct receive_ign_obj_node *n =
-	    list_remove_head(&ra.ignore_obj_list); n != NULL;
-	    n = list_remove_head(&ra.ignore_obj_list)) {
-		kmem_free(n, sizeof (*n));
-	}
-	list_destroy(&ra.ignore_obj_list);
+	objlist_destroy(&ra.ignore_objlist);
 	return (err);
 }
 
diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dmu_impl.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dmu_impl.h
index e8d6294b9815..8cb63410a735 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dmu_impl.h
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/dmu_impl.h
@@ -25,7 +25,7 @@
 /*
  * Copyright (c) 2012, Joyent, Inc. All rights reserved.
  * Copyright (c) 2012, Martin Matuska <mm@FreeBSD.org>. All rights reserved.
- * Copyright (c) 2013, 2014 by Delphix. All rights reserved.
+ * Copyright (c) 2013, 2015 by Delphix. All rights reserved.
  */
 
 #ifndef _SYS_DMU_IMPL_H
@@ -296,7 +296,6 @@ typedef struct dmu_sendarg {
 	uint64_t dsa_toguid;
 	int dsa_err;
 	dmu_pendop_t dsa_pending_op;
-	boolean_t dsa_incremental;
 	uint64_t dsa_featureflags;
 	uint64_t dsa_last_data_object;
 	uint64_t dsa_last_data_offset;
diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zfs_ioctl.h b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zfs_ioctl.h
index 20bf54553329..2a50e191b01e 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zfs_ioctl.h
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/sys/zfs_ioctl.h
@@ -20,7 +20,7 @@
  */
 /*
  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2014 by Delphix. All rights reserved.
+ * Copyright (c) 2012, 2015 by Delphix. All rights reserved.
  */
 
 #ifndef	_SYS_ZFS_IOCTL_H
@@ -126,6 +126,16 @@ typedef enum dmu_send_resume_token_version {
 
 #define	DRR_FLAG_CLONE		(1<<0)
 #define	DRR_FLAG_CI_DATA	(1<<1)
+/*
+ * This send stream, if it is a full send, includes the FREE and FREEOBJECT
+ * records that are created by the sending process.  This means that the send
+ * stream can be received as a clone, even though it is not an incremental.
+ * This is not implemented as a feature flag, because the receiving side does
+ * not need to have implemented it to receive this stream; it is fully backwards
+ * compatible.  We need a flag, though, because full send streams without it
+ * cannot necessarily be received as a clone correctly.
+ */
+#define	DRR_FLAG_FREERECORDS	(1<<2)
 
 /*
  * flags in the drr_checksumflags field in the DRR_WRITE and

From 3e9d02a4043d187ef743d95070d1774c7348eea0 Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 13:37:30 +0000
Subject: [PATCH 018/113] MFV r294816: 4986 receiving replication stream fails
 if any snapshot exceeds refquota

Reviewed by: John Kennedy <john.kennedy@delphix.com>
Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Approved by: Gordon Ross <gordon.ross@nexenta.com>
Author: Dan McDonald <danmcd@omniti.com>

illumos/illumos-gate@5878fad70d76d8711f6608c1f80b0447601261c6
---
 .../lib/libzfs/common/libzfs_sendrecv.c       | 43 ++++++--
 .../opensolaris/uts/common/fs/zfs/zfs_ioctl.c | 97 +++++++++++++++++--
 2 files changed, 121 insertions(+), 19 deletions(-)

diff --git a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_sendrecv.c b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_sendrecv.c
index 3ba069e011ca..4fbab42917c0 100644
--- a/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_sendrecv.c
+++ b/cddl/contrib/opensolaris/lib/libzfs/common/libzfs_sendrecv.c
@@ -26,6 +26,7 @@
  * Copyright (c) 2012 Pawel Jakub Dawidek <pawel@dawidek.net>.
  * All rights reserved.
  * Copyright (c) 2013 Steven Hartland. All rights reserved.
+ * Copyright 2015, OmniTI Computer Consulting, Inc. All rights reserved.
  */
 
 #include <assert.h>
@@ -67,7 +68,7 @@ extern void zfs_setprop_error(libzfs_handle_t *, zfs_prop_t, int, char *);
 
 static int zfs_receive_impl(libzfs_handle_t *, const char *, const char *,
     recvflags_t *, int, const char *, nvlist_t *, avl_tree_t *, char **, int,
-    uint64_t *);
+    uint64_t *, const char *);
 static int guid_to_name(libzfs_handle_t *, const char *,
     uint64_t, boolean_t, char *);
 
@@ -2602,6 +2603,7 @@ zfs_receive_package(libzfs_handle_t *hdl, int fd, const char *destname,
 	nvlist_t *stream_nv = NULL;
 	avl_tree_t *stream_avl = NULL;
 	char *fromsnap = NULL;
+	char *sendsnap = NULL;
 	char *cp;
 	char tofs[ZFS_MAXNAMELEN];
 	char sendfs[ZFS_MAXNAMELEN];
@@ -2750,8 +2752,16 @@ zfs_receive_package(libzfs_handle_t *hdl, int fd, const char *destname,
 	 */
 	(void) strlcpy(sendfs, drr->drr_u.drr_begin.drr_toname,
 	    ZFS_MAXNAMELEN);
-	if ((cp = strchr(sendfs, '@')) != NULL)
+	if ((cp = strchr(sendfs, '@')) != NULL) {
 		*cp = '\0';
+		/*
+		 * Find the "sendsnap", the final snapshot in a replication
+		 * stream.  zfs_receive_one() handles certain errors
+		 * differently, depending on if the contained stream is the
+		 * last one or not.
+		 */
+		sendsnap = (cp + 1);
+	}
 
 	/* Finally, receive each contained stream */
 	do {
@@ -2764,7 +2774,7 @@ zfs_receive_package(libzfs_handle_t *hdl, int fd, const char *destname,
 		 */
 		error = zfs_receive_impl(hdl, destname, NULL, flags, fd,
 		    sendfs, stream_nv, stream_avl, top_zfs, cleanup_fd,
-		    action_handlep);
+		    action_handlep, sendsnap);
 		if (error == ENODATA) {
 			error = 0;
 			break;
@@ -2930,7 +2940,7 @@ zfs_receive_one(libzfs_handle_t *hdl, int infd, const char *tosnap,
     const char *originsnap, recvflags_t *flags, dmu_replay_record_t *drr,
     dmu_replay_record_t *drr_noswap, const char *sendfs, nvlist_t *stream_nv,
     avl_tree_t *stream_avl, char **top_zfs, int cleanup_fd,
-    uint64_t *action_handlep)
+    uint64_t *action_handlep, const char *finalsnap)
 {
 	zfs_cmd_t zc = { 0 };
 	time_t begin_time;
@@ -2947,6 +2957,7 @@ zfs_receive_one(libzfs_handle_t *hdl, int infd, const char *tosnap,
 	nvlist_t *snapprops_nvlist = NULL;
 	zprop_errflags_t prop_errflags;
 	boolean_t recursive;
+	char *snapname = NULL;
 
 	begin_time = time(NULL);
 
@@ -2957,7 +2968,6 @@ zfs_receive_one(libzfs_handle_t *hdl, int infd, const char *tosnap,
 	    ENOENT);
 
 	if (stream_avl != NULL) {
-		char *snapname;
 		nvlist_t *fs = fsavl_find(stream_avl, drrb->drr_toguid,
 		    &snapname);
 		nvlist_t *props;
@@ -3313,7 +3323,21 @@ zfs_receive_one(libzfs_handle_t *hdl, int infd, const char *tosnap,
 			    ZPROP_N_MORE_ERRORS) == 0) {
 				trunc_prop_errs(intval);
 				break;
-			} else {
+			} else if (snapname == NULL || finalsnap == NULL ||
+			    strcmp(finalsnap, snapname) == 0 ||
+			    strcmp(nvpair_name(prop_err),
+			    zfs_prop_to_name(ZFS_PROP_REFQUOTA)) != 0) {
+				/*
+				 * Skip the special case of, for example,
+				 * "refquota", errors on intermediate
+				 * snapshots leading up to a final one.
+				 * That's why we have all of the checks above.
+				 *
+				 * See zfs_ioctl.c's extract_delay_props() for
+				 * a list of props which can fail on
+				 * intermediate snapshots, but shouldn't
+				 * affect the overall receive.
+				 */
 				(void) snprintf(tbuf, sizeof (tbuf),
 				    dgettext(TEXT_DOMAIN,
 				    "cannot receive %s property on %s"),
@@ -3498,7 +3522,7 @@ static int
 zfs_receive_impl(libzfs_handle_t *hdl, const char *tosnap,
     const char *originsnap, recvflags_t *flags, int infd, const char *sendfs,
     nvlist_t *stream_nv, avl_tree_t *stream_avl, char **top_zfs, int cleanup_fd,
-    uint64_t *action_handlep)
+    uint64_t *action_handlep, const char *finalsnap)
 {
 	int err;
 	dmu_replay_record_t drr, drr_noswap;
@@ -3594,10 +3618,11 @@ zfs_receive_impl(libzfs_handle_t *hdl, const char *tosnap,
 			if ((cp = strchr(nonpackage_sendfs, '@')) != NULL)
 				*cp = '\0';
 			sendfs = nonpackage_sendfs;
+			VERIFY(finalsnap == NULL);
 		}
 		return (zfs_receive_one(hdl, infd, tosnap, originsnap, flags,
 		    &drr, &drr_noswap, sendfs, stream_nv, stream_avl, top_zfs,
-		    cleanup_fd, action_handlep));
+		    cleanup_fd, action_handlep, finalsnap));
 	} else {
 		assert(DMU_GET_STREAM_HDRTYPE(drrb->drr_versioninfo) ==
 		    DMU_COMPOUNDSTREAM);
@@ -3632,7 +3657,7 @@ zfs_receive(libzfs_handle_t *hdl, const char *tosnap, nvlist_t *props,
 	VERIFY(cleanup_fd >= 0);
 
 	err = zfs_receive_impl(hdl, tosnap, originsnap, flags, infd, NULL, NULL,
-	    stream_avl, &top_zfs, cleanup_fd, &action_handle);
+	    stream_avl, &top_zfs, cleanup_fd, &action_handle, NULL);
 
 	VERIFY(0 == close(cleanup_fd));
 
diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c
index 25633c0c2bbe..8c6fb974f0cc 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c
@@ -25,6 +25,7 @@
  * All rights reserved.
  * Copyright 2013 Martin Matuska <mm@FreeBSD.org>. All rights reserved.
  * Copyright 2014 Xin Li <delphij@FreeBSD.org>. All rights reserved.
+ * Copyright 2015, OmniTI Computer Consulting, Inc. All rights reserved.
  * Copyright 2015 Nexenta Systems, Inc.  All rights reserved.
  * Copyright (c) 2014, Joyent, Inc. All rights reserved.
  * Copyright (c) 2011, 2015 by Delphix. All rights reserved.
@@ -4177,6 +4178,56 @@ props_reduce(nvlist_t *props, nvlist_t *origprops)
 	}
 }
 
+/*
+ * Extract properties that cannot be set PRIOR to the receipt of a dataset.
+ * For example, refquota cannot be set until after the receipt of a dataset,
+ * because in replication streams, an older/earlier snapshot may exceed the
+ * refquota.  We want to receive the older/earlier snapshot, but setting
+ * refquota pre-receipt will set the dsl's ACTUAL quota, which will prevent
+ * the older/earlier snapshot from being received (with EDQUOT).
+ *
+ * The ZFS test "zfs_receive_011_pos" demonstrates such a scenario.
+ *
+ * libzfs will need to be judicious handling errors encountered by props
+ * extracted by this function.
+ */
+static nvlist_t *
+extract_delay_props(nvlist_t *props)
+{
+	nvlist_t *delayprops;
+	nvpair_t *nvp, *tmp;
+	static const zfs_prop_t delayable[] = { ZFS_PROP_REFQUOTA, 0 };
+	int i;
+
+	VERIFY(nvlist_alloc(&delayprops, NV_UNIQUE_NAME, KM_SLEEP) == 0);
+
+	for (nvp = nvlist_next_nvpair(props, NULL); nvp != NULL;
+	    nvp = nvlist_next_nvpair(props, nvp)) {
+		/*
+		 * strcmp() is safe because zfs_prop_to_name() always returns
+		 * a bounded string.
+		 */
+		for (i = 0; delayable[i] != 0; i++) {
+			if (strcmp(zfs_prop_to_name(delayable[i]),
+			    nvpair_name(nvp)) == 0) {
+				break;
+			}
+		}
+		if (delayable[i] != 0) {
+			tmp = nvlist_prev_nvpair(props, nvp);
+			VERIFY(nvlist_add_nvpair(delayprops, nvp) == 0);
+			VERIFY(nvlist_remove_nvpair(props, nvp) == 0);
+			nvp = tmp;
+		}
+	}
+
+	if (nvlist_empty(delayprops)) {
+		nvlist_free(delayprops);
+		delayprops = NULL;
+	}
+	return (delayprops);
+}
+
 #ifdef	DEBUG
 static boolean_t zfs_ioc_recv_inject_err;
 #endif
@@ -4213,6 +4264,7 @@ zfs_ioc_recv(zfs_cmd_t *zc)
 	offset_t off;
 	nvlist_t *props = NULL; /* sent properties */
 	nvlist_t *origprops = NULL; /* existing properties */
+	nvlist_t *delayprops = NULL; /* sent properties applied post-receive */
 	char *origin = NULL;
 	char *tosnap;
 	char tofs[ZFS_MAXNAMELEN];
@@ -4298,21 +4350,12 @@ zfs_ioc_recv(zfs_cmd_t *zc)
 		props_error = dsl_prop_set_hasrecvd(tofs);
 
 		if (props_error == 0) {
+			delayprops = extract_delay_props(props);
 			(void) zfs_set_prop_nvlist(tofs, ZPROP_SRC_RECEIVED,
 			    props, errors);
 		}
 	}
 
-	if (zc->zc_nvlist_dst_size != 0 &&
-	    (nvlist_smush(errors, zc->zc_nvlist_dst_size) != 0 ||
-	    put_nvlist(zc, errors) != 0)) {
-		/*
-		 * Caller made zc->zc_nvlist_dst less than the minimum expected
-		 * size or supplied an invalid address.
-		 */
-		props_error = SET_ERROR(EINVAL);
-	}
-
 	off = fp->f_offset;
 	error = dmu_recv_stream(&drc, fp, &off, zc->zc_cleanup_fd,
 	    &zc->zc_action_handle);
@@ -4337,6 +4380,40 @@ zfs_ioc_recv(zfs_cmd_t *zc)
 		} else {
 			error = dmu_recv_end(&drc, NULL);
 		}
+
+		/* Set delayed properties now, after we're done receiving. */
+		if (delayprops != NULL && error == 0) {
+			(void) zfs_set_prop_nvlist(tofs, ZPROP_SRC_RECEIVED,
+			    delayprops, errors);
+		}
+	}
+
+	if (delayprops != NULL) {
+		/*
+		 * Merge delayed props back in with initial props, in case
+		 * we're DEBUG and zfs_ioc_recv_inject_err is set (which means
+		 * we have to make sure clear_received_props() includes
+		 * the delayed properties).
+		 *
+		 * Since zfs_ioc_recv_inject_err is only in DEBUG kernels,
+		 * using ASSERT() will be just like a VERIFY.
+		 */
+		ASSERT(nvlist_merge(props, delayprops, 0) == 0);
+		nvlist_free(delayprops);
+	}
+
+	/*
+	 * Now that all props, initial and delayed, are set, report the prop
+	 * errors to the caller.
+	 */
+	if (zc->zc_nvlist_dst_size != 0 &&
+	    (nvlist_smush(errors, zc->zc_nvlist_dst_size) != 0 ||
+	    put_nvlist(zc, errors) != 0)) {
+		/*
+		 * Caller made zc->zc_nvlist_dst less than the minimum expected
+		 * size or supplied an invalid address.
+		 */
+		props_error = SET_ERROR(EINVAL);
 	}
 
 	zc->zc_cookie = off - fp->f_offset;

From a8467604b3539248cfcdf339b0013a7de448703c Mon Sep 17 00:00:00 2001
From: mav <mav@FreeBSD.org>
Date: Tue, 26 Jan 2016 13:45:41 +0000
Subject: [PATCH 019/113] MFV r294819: 6495 Fix mutex leak in
 dmu_objset_find_dp

Reviewed by: George Wilson <george.wilson@delphix.com>
Reviewed by: Matthew Ahrens <mahrens@delphix.com>
Approved by: Albert Lee <trisk@omniti.com>
Author: Steven Hartland <steven.hartland@multiplay.co.uk>

illumos/illumos-gate@2bad22584defe4667f99737e3158d336e4dcca11
---
 sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c
index 79de1d127d42..85465ec94334 100644
--- a/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c
+++ b/sys/cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c
@@ -1789,6 +1789,7 @@ dmu_objset_find_dp(dsl_pool_t *dp, uint64_t ddobj,
 		 * thread suffices. For now, stay single threaded.
 		 */
 		dmu_objset_find_dp_impl(dcp);
+		mutex_destroy(&err_lock);
 
 		return (error);
 	}
@@ -1800,6 +1801,8 @@ dmu_objset_find_dp(dsl_pool_t *dp, uint64_t ddobj,
 	    INT_MAX, 0);
 	if (tq == NULL) {
 		kmem_free(dcp, sizeof (*dcp));
+		mutex_destroy(&err_lock);
+
 		return (SET_ERROR(ENOMEM));
 	}
 	dcp->dc_tq = tq;

From c79983aa4ceb0c55fbc46d966688fc754aa29a17 Mon Sep 17 00:00:00 2001
From: skra <skra@FreeBSD.org>
Date: Tue, 26 Jan 2016 13:50:44 +0000
Subject: [PATCH 020/113] Make pmap_fault() return values vm subsystem
 compliant to simplify their handling in abort_handler(). While here, remove
 one extra initialization of pcb variable.

---
 sys/arm/arm/pmap-v6-new.c | 14 +++++++-------
 sys/arm/arm/trap-v6.c     | 11 +++--------
 2 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/sys/arm/arm/pmap-v6-new.c b/sys/arm/arm/pmap-v6-new.c
index 2e4dfe26b1d9..2996898a4510 100644
--- a/sys/arm/arm/pmap-v6-new.c
+++ b/sys/arm/arm/pmap-v6-new.c
@@ -6151,7 +6151,7 @@ pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
 			    __func__, pmap, pmap->pm_pt1, far);
 			panic("%s: pm_pt1 abort", __func__);
 		}
-		return (EFAULT);
+		return (KERN_INVALID_ADDRESS);
 	}
 	if (__predict_false(IN_RANGE2(far, PT2MAP, PT2MAP_SIZE))) {
 		/*
@@ -6167,7 +6167,7 @@ pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
 			    __func__, pmap, PT2MAP, far);
 			panic("%s: PT2MAP abort", __func__);
 		}
-		return (EFAULT);
+		return (KERN_INVALID_ADDRESS);
 	}
 
 	/*
@@ -6187,7 +6187,7 @@ pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
 			if (!pte2_cmpset(pte2p, pte2, pte2 | PTE2_A)) {
 				goto pte2_seta;
 			}
-			return (0);
+			return (KERN_SUCCESS);
 		}
 	}
 	if (idx == FAULT_ACCESS_L1) {
@@ -6198,7 +6198,7 @@ pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
 			if (!pte1_cmpset(pte1p, pte1, pte1 | PTE1_A)) {
 				goto pte1_seta;
 			}
-			return (0);
+			return (KERN_SUCCESS);
 		}
 	}
 
@@ -6222,7 +6222,7 @@ pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
 				goto pte2_setrw;
 			}
 			tlb_flush(trunc_page(far));
-			return (0);
+			return (KERN_SUCCESS);
 		}
 	}
 	if ((fsr & FSR_WNR) && (idx == FAULT_PERM_L1)) {
@@ -6235,7 +6235,7 @@ pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
 				goto pte1_setrw;
 			}
 			tlb_flush(pte1_trunc(far));
-			return (0);
+			return (KERN_SUCCESS);
 		}
 	}
 
@@ -6274,7 +6274,7 @@ pmap_fault(pmap_t pmap, vm_offset_t far, uint32_t fsr, int idx, bool usermode)
 		}
 	}
 #endif
-	return (EAGAIN);
+	return (KERN_FAILURE);
 }
 
 /* !!!! REMOVE !!!! */
diff --git a/sys/arm/arm/trap-v6.c b/sys/arm/arm/trap-v6.c
index 80cf793e7311..6d8015137939 100644
--- a/sys/arm/arm/trap-v6.c
+++ b/sys/arm/arm/trap-v6.c
@@ -336,14 +336,10 @@ abort_handler(struct trapframe *tf, int prefetch)
 
 #ifdef ARM_NEW_PMAP
 	rv = pmap_fault(PCPU_GET(curpmap), far, fsr, idx, usermode);
-	if (rv == 0) {
+	if (rv == KERN_SUCCESS)
 		return;
-	} else if (rv == EFAULT) {
-
-		call_trapsignal(td, SIGSEGV, SEGV_MAPERR, far);
-		userret(td, tf);
-		return;
-	}
+	if (rv == KERN_INVALID_ADDRESS)
+		goto nogo;
 #endif
 	/*
 	 * Now, when we handled imprecise and debug aborts, the rest of
@@ -452,7 +448,6 @@ abort_handler(struct trapframe *tf, int prefetch)
 	 */
 
 	/* fusubailout is used by [fs]uswintr to avoid page faulting. */
-	pcb = td->td_pcb;
 	if (__predict_false(pcb->pcb_onfault == fusubailout)) {
 		tf->tf_r0 = EFAULT;
 		tf->tf_pc = (register_t)pcb->pcb_onfault;

From ee391c56ca829f0f6aa345b3699f8df7ec252e0f Mon Sep 17 00:00:00 2001
From: br <br@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:17:39 +0000
Subject: [PATCH 021/113] Add the openssl header for RISC-V. Copied from
 aarch64 as we can't generate it yet.

---
 secure/lib/libcrypto/opensslconf-riscv.h | 254 +++++++++++++++++++++++
 1 file changed, 254 insertions(+)
 create mode 100644 secure/lib/libcrypto/opensslconf-riscv.h

diff --git a/secure/lib/libcrypto/opensslconf-riscv.h b/secure/lib/libcrypto/opensslconf-riscv.h
new file mode 100644
index 000000000000..e158f513a3f5
--- /dev/null
+++ b/secure/lib/libcrypto/opensslconf-riscv.h
@@ -0,0 +1,254 @@
+/* $FreeBSD$ */
+/* opensslconf.h */
+/* RISCVTODO: generate from opensslconf.h.in by Configure. */
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+/* OpenSSL was configured with the following options: */
+#ifndef OPENSSL_DOING_MAKEDEPEND
+
+
+#ifndef OPENSSL_NO_EC_NISTP_64_GCC_128
+# define OPENSSL_NO_EC_NISTP_64_GCC_128
+#endif
+#ifndef OPENSSL_NO_GMP
+# define OPENSSL_NO_GMP
+#endif
+#ifndef OPENSSL_NO_JPAKE
+# define OPENSSL_NO_JPAKE
+#endif
+#ifndef OPENSSL_NO_KRB5
+# define OPENSSL_NO_KRB5
+#endif
+#ifndef OPENSSL_NO_LIBUNBOUND
+# define OPENSSL_NO_LIBUNBOUND
+#endif
+#ifndef OPENSSL_NO_MD2
+# define OPENSSL_NO_MD2
+#endif
+#ifndef OPENSSL_NO_SCTP
+# define OPENSSL_NO_SCTP
+#endif
+#ifndef OPENSSL_NO_SSL_TRACE
+# define OPENSSL_NO_SSL_TRACE
+#endif
+#ifndef OPENSSL_NO_SSL2
+# define OPENSSL_NO_SSL2
+#endif
+#ifndef OPENSSL_NO_STORE
+# define OPENSSL_NO_STORE
+#endif
+#ifndef OPENSSL_NO_UNIT_TEST
+# define OPENSSL_NO_UNIT_TEST
+#endif
+
+#endif /* OPENSSL_DOING_MAKEDEPEND */
+
+#ifndef OPENSSL_THREADS
+# define OPENSSL_THREADS
+#endif
+#ifndef OPENSSL_NO_ASM
+# define OPENSSL_NO_ASM
+#endif
+#ifndef OPENSSL_NO_STATIC_ENGINE
+# define OPENSSL_NO_STATIC_ENGINE
+#endif
+
+/* The OPENSSL_NO_* macros are also defined as NO_* if the application
+   asks for it.  This is a transient feature that is provided for those
+   who haven't had the time to do the appropriate changes in their
+   applications.  */
+#ifdef OPENSSL_ALGORITHM_DEFINES
+# if defined(OPENSSL_NO_EC_NISTP_64_GCC_128) && !defined(NO_EC_NISTP_64_GCC_128)
+#  define NO_EC_NISTP_64_GCC_128
+# endif
+# if defined(OPENSSL_NO_GMP) && !defined(NO_GMP)
+#  define NO_GMP
+# endif
+# if defined(OPENSSL_NO_JPAKE) && !defined(NO_JPAKE)
+#  define NO_JPAKE
+# endif
+# if defined(OPENSSL_NO_KRB5) && !defined(NO_KRB5)
+#  define NO_KRB5
+# endif
+# if defined(OPENSSL_NO_LIBUNBOUND) && !defined(NO_LIBUNBOUND)
+#  define NO_LIBUNBOUND
+# endif
+# if defined(OPENSSL_NO_MD2) && !defined(NO_MD2)
+#  define NO_MD2
+# endif
+# if defined(OPENSSL_NO_SCTP) && !defined(NO_SCTP)
+#  define NO_SCTP
+# endif
+# if defined(OPENSSL_NO_SSL_TRACE) && !defined(NO_SSL_TRACE)
+#  define NO_SSL_TRACE
+# endif
+# if defined(OPENSSL_NO_SSL2) && !defined(NO_SSL2)
+#  define NO_SSL2
+# endif
+# if defined(OPENSSL_NO_STORE) && !defined(NO_STORE)
+#  define NO_STORE
+# endif
+# if defined(OPENSSL_NO_UNIT_TEST) && !defined(NO_UNIT_TEST)
+#  define NO_UNIT_TEST
+# endif
+#endif
+
+/* crypto/opensslconf.h.in */
+
+/* Generate 80386 code? */
+#undef I386_ONLY
+
+#if !(defined(VMS) || defined(__VMS)) /* VMS uses logical names instead */
+#if defined(HEADER_CRYPTLIB_H) && !defined(OPENSSLDIR)
+#define ENGINESDIR "/usr/lib/engines"
+#define OPENSSLDIR "/etc/ssl"
+#endif
+#endif
+
+#undef OPENSSL_UNISTD
+#define OPENSSL_UNISTD <unistd.h>
+
+#undef OPENSSL_EXPORT_VAR_AS_FUNCTION
+
+#if defined(HEADER_IDEA_H) && !defined(IDEA_INT)
+#define IDEA_INT unsigned int
+#endif
+
+#if defined(HEADER_MD2_H) && !defined(MD2_INT)
+#define MD2_INT unsigned int
+#endif
+
+#if defined(HEADER_RC2_H) && !defined(RC2_INT)
+/* I need to put in a mod for the alpha - eay */
+#define RC2_INT unsigned int
+#endif
+
+#if defined(HEADER_RC4_H)
+#if !defined(RC4_INT)
+/* using int types make the structure larger but make the code faster
+ * on most boxes I have tested - up to %20 faster. */
+/*
+ * I don't know what does "most" mean, but declaring "int" is a must on:
+ * - Intel P6 because partial register stalls are very expensive;
+ * - elder Alpha because it lacks byte load/store instructions;
+ */
+#define RC4_INT unsigned int
+#endif
+#if !defined(RC4_CHUNK)
+/*
+ * This enables code handling data aligned at natural CPU word
+ * boundary. See crypto/rc4/rc4_enc.c for further details.
+ */
+#undef RC4_CHUNK
+#endif
+#endif
+
+#if (defined(HEADER_NEW_DES_H) || defined(HEADER_DES_H)) && !defined(DES_LONG)
+/* If this is set to 'unsigned int' on a DEC Alpha, this gives about a
+ * %20 speed up (longs are 8 bytes, int's are 4). */
+#ifndef DES_LONG
+#define DES_LONG unsigned int
+#endif
+#endif
+
+#if defined(HEADER_BN_H) && !defined(CONFIG_HEADER_BN_H)
+#define CONFIG_HEADER_BN_H
+#undef BN_LLONG
+
+/* Should we define BN_DIV2W here? */
+
+/* Only one for the following should be defined */
+#define SIXTY_FOUR_BIT_LONG
+#undef SIXTY_FOUR_BIT
+#undef THIRTY_TWO_BIT
+#endif
+
+#if defined(HEADER_RC4_LOCL_H) && !defined(CONFIG_HEADER_RC4_LOCL_H)
+#define CONFIG_HEADER_RC4_LOCL_H
+/* if this is defined data[i] is used instead of *data, this is a %20
+ * speedup on x86 */
+#define RC4_INDEX
+#endif
+
+#if defined(HEADER_BF_LOCL_H) && !defined(CONFIG_HEADER_BF_LOCL_H)
+#define CONFIG_HEADER_BF_LOCL_H
+#undef BF_PTR
+#endif /* HEADER_BF_LOCL_H */
+
+#if defined(HEADER_DES_LOCL_H) && !defined(CONFIG_HEADER_DES_LOCL_H)
+#define CONFIG_HEADER_DES_LOCL_H
+#ifndef DES_DEFAULT_OPTIONS
+/* the following is tweaked from a config script, that is why it is a
+ * protected undef/define */
+#ifndef DES_PTR
+#define DES_PTR
+#endif
+
+/* This helps C compiler generate the correct code for multiple functional
+ * units.  It reduces register dependancies at the expense of 2 more
+ * registers */
+#ifndef DES_RISC1
+#define DES_RISC1
+#endif
+
+#ifndef DES_RISC2
+#undef DES_RISC2
+#endif
+
+#if defined(DES_RISC1) && defined(DES_RISC2)
+#error YOU SHOULD NOT HAVE BOTH DES_RISC1 AND DES_RISC2 DEFINED!!!!!
+#endif
+
+/* Unroll the inner loop, this sometimes helps, sometimes hinders.
+ * Very mucy CPU dependant */
+#ifndef DES_UNROLL
+#define DES_UNROLL
+#endif
+
+/* These default values were supplied by
+ * Peter Gutman <pgut001@cs.auckland.ac.nz>
+ * They are only used if nothing else has been defined */
+#if !defined(DES_PTR) && !defined(DES_RISC1) && !defined(DES_RISC2) && !defined(DES_UNROLL)
+/* Special defines which change the way the code is built depending on the
+   CPU and OS.  For SGI machines you can use _MIPS_SZLONG (32 or 64) to find
+   even newer MIPS CPU's, but at the moment one size fits all for
+   optimization options.  Older Sparc's work better with only UNROLL, but
+   there's no way to tell at compile time what it is you're running on */
+ 
+#if defined( sun )		/* Newer Sparc's */
+#  define DES_PTR
+#  define DES_RISC1
+#  define DES_UNROLL
+#elif defined( __ultrix )	/* Older MIPS */
+#  define DES_PTR
+#  define DES_RISC2
+#  define DES_UNROLL
+#elif defined( __osf1__ )	/* Alpha */
+#  define DES_PTR
+#  define DES_RISC2
+#elif defined ( _AIX )		/* RS6000 */
+  /* Unknown */
+#elif defined( __hpux )		/* HP-PA */
+  /* Unknown */
+#elif defined( __aux )		/* 68K */
+  /* Unknown */
+#elif defined( __dgux )		/* 88K (but P6 in latest boxes) */
+#  define DES_UNROLL
+#elif defined( __sgi )		/* Newer MIPS */
+#  define DES_PTR
+#  define DES_RISC2
+#  define DES_UNROLL
+#elif defined(i386) || defined(__i386__)	/* x86 boxes, should be gcc */
+#  define DES_PTR
+#  define DES_RISC1
+#  define DES_UNROLL
+#endif /* Systems-specific speed defines */
+#endif
+
+#endif /* DES_DEFAULT_OPTIONS */
+#endif /* HEADER_DES_LOCL_H */
+#ifdef  __cplusplus
+}
+#endif

From 553c3e5b93b8f8eb3af0e9dacbc97ebd2c332b62 Mon Sep 17 00:00:00 2001
From: hselasky <hselasky@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:20:25 +0000
Subject: [PATCH 022/113] Add more LinuxKPI PCI related functions and defines.
 Removed comments deriving from Linux.

MFC after:	1 week
Sponsored by:	Mellanox Technologies
---
 .../linuxkpi/common/include/linux/pci.h       | 107 +++++++++---------
 1 file changed, 51 insertions(+), 56 deletions(-)

diff --git a/sys/compat/linuxkpi/common/include/linux/pci.h b/sys/compat/linuxkpi/common/include/linux/pci.h
index 0e6dbfd0bb4e..54a9b2fd5304 100644
--- a/sys/compat/linuxkpi/common/include/linux/pci.h
+++ b/sys/compat/linuxkpi/common/include/linux/pci.h
@@ -114,14 +114,29 @@ struct pci_device_id {
 #define	PCI_EXP_TYPE_DOWNSTREAM PCIEM_TYPE_DOWNSTREAM_PORT	/* Downstream Port */
 #define	PCI_EXP_FLAGS_SLOT	PCIEM_FLAGS_SLOT		/* Slot implemented */
 #define	PCI_EXP_TYPE_RC_EC	PCIEM_TYPE_ROOT_EC		/* Root Complex Event Collector */
-
+#define	PCI_EXP_LNKCAP_SLS_2_5GB 0x01	/* Supported Link Speed 2.5GT/s */
+#define	PCI_EXP_LNKCAP_SLS_5_0GB 0x02	/* Supported Link Speed 5.0GT/s */
+#define	PCI_EXP_LNKCAP_MLW	0x03f0	/* Maximum Link Width */
+#define	PCI_EXP_LNKCAP2_SLS_2_5GB 0x02	/* Supported Link Speed 2.5GT/s */
+#define	PCI_EXP_LNKCAP2_SLS_5_0GB 0x04	/* Supported Link Speed 5.0GT/s */
+#define	PCI_EXP_LNKCAP2_SLS_8_0GB 0x08	/* Supported Link Speed 8.0GT/s */
 
 #define	IORESOURCE_MEM	SYS_RES_MEMORY
 #define	IORESOURCE_IO	SYS_RES_IOPORT
 #define	IORESOURCE_IRQ	SYS_RES_IRQ
 
-struct pci_dev;
+enum pci_bus_speed {
+	PCI_SPEED_UNKNOWN = -1,
+	PCIE_SPEED_2_5GT,
+	PCIE_SPEED_5_0GT,
+	PCIE_SPEED_8_0GT,
+};
 
+enum pcie_link_width {
+	PCIE_LNK_WIDTH_UNKNOWN = -1,
+};
+
+struct pci_dev;
 
 struct pci_driver {
 	struct list_head		links;
@@ -351,20 +366,6 @@ pci_find_capability(struct pci_dev *pdev, int capid)
 	return (reg);
 }
 
-
-
-
-/**
- * pci_pcie_cap - get the saved PCIe capability offset
- * @dev: PCI device
- *
- * PCIe capability offset is calculated at PCI device initialization
- * time and saved in the data structure. This function returns saved
- * PCIe capability offset. Using this instead of pci_find_capability()
- * reduces unnecessary search in the PCI configuration space. If you
- * need to calculate PCIe capability offset from raw device for some
- * reasons, please use pci_find_capability() instead.
- */
 static inline int pci_pcie_cap(struct pci_dev *dev)
 {
         return pci_find_capability(dev, PCI_CAP_ID_EXP);
@@ -505,13 +506,6 @@ static inline void pci_disable_sriov(struct pci_dev *dev)
 {
 }
 
-/**
- * DEFINE_PCI_DEVICE_TABLE - macro used to describe a pci device table
- * @_table: device table name
- *
- * This macro is used to create a struct pci_device_id array (a device table)
- * in a generic manner.
- */
 #define DEFINE_PCI_DEVICE_TABLE(_table) \
 	const struct pci_device_id _table[] __devinitdata
 
@@ -569,54 +563,31 @@ typedef unsigned int __bitwise pci_channel_state_t;
 typedef unsigned int __bitwise pci_ers_result_t;
 
 enum pci_channel_state {
-        /* I/O channel is in normal state */
-        pci_channel_io_normal = (__force pci_channel_state_t) 1,
-
-        /* I/O to channel is blocked */
-        pci_channel_io_frozen = (__force pci_channel_state_t) 2,
-
-        /* PCI card is dead */
-        pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
+        pci_channel_io_normal = 1,
+        pci_channel_io_frozen = 2,
+        pci_channel_io_perm_failure = 3,
 };
 
 enum pci_ers_result {
-        /* no result/none/not supported in device driver */
-        PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
-
-        /* Device driver can recover without slot reset */
-        PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
-
-        /* Device driver wants slot to be reset. */
-        PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
-
-        /* Device has completely failed, is unrecoverable */
-        PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
-
-        /* Device driver is fully recovered and operational */
-        PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
+        PCI_ERS_RESULT_NONE = 1,
+        PCI_ERS_RESULT_CAN_RECOVER = 2,
+        PCI_ERS_RESULT_NEED_RESET = 3,
+        PCI_ERS_RESULT_DISCONNECT = 4,
+        PCI_ERS_RESULT_RECOVERED = 5,
 };
 
 
 /* PCI bus error event callbacks */
 struct pci_error_handlers {
-        /* PCI bus error detected on this device */
         pci_ers_result_t (*error_detected)(struct pci_dev *dev,
                         enum pci_channel_state error);
-
-        /* MMIO has been re-enabled, but not DMA */
         pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
-
-        /* PCI Express link has been reset */
         pci_ers_result_t (*link_reset)(struct pci_dev *dev);
-
-        /* PCI slot has been reset */
         pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
-
-        /* Device driver may resume normal operations */
         void (*resume)(struct pci_dev *dev);
 };
 
-/* freeBSD does not support SRIOV - yet */
+/* FreeBSD does not support SRIOV - yet */
 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
 {
         return dev;
@@ -721,7 +692,17 @@ static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
         }
 }
 
- 
+static inline int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *dst)
+{
+        if (pos & 3)
+                return -EINVAL;
+
+        if (!pcie_capability_reg_implemented(dev, pos))
+                return -EINVAL;
+
+        return pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, dst);
+}
+
 static inline int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
 {
         if (pos & 1)
@@ -733,4 +714,18 @@ static inline int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 v
         return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
 }
 
+static inline int pcie_get_minimum_link(struct pci_dev *dev,
+    enum pci_bus_speed *speed, enum pcie_link_width *width)
+{
+	*speed = PCI_SPEED_UNKNOWN;
+	*width = PCIE_LNK_WIDTH_UNKNOWN;
+	return (0);
+}
+
+static inline int
+pci_num_vf(struct pci_dev *dev)
+{
+	return (0);
+}
+
 #endif	/* _LINUX_PCI_H_ */

From 71eec1d7860827138472dcd016ebfcf8e78dabd1 Mon Sep 17 00:00:00 2001
From: hselasky <hselasky@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:21:30 +0000
Subject: [PATCH 023/113] Define __get_user() and __put_user() for the
 LinuxKPI.

MFC after:	1 week
Sponsored by:	Mellanox Technologies
---
 sys/compat/linuxkpi/common/include/linux/uaccess.h | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/sys/compat/linuxkpi/common/include/linux/uaccess.h b/sys/compat/linuxkpi/common/include/linux/uaccess.h
index 87d1babddce2..e44024ec56df 100644
--- a/sys/compat/linuxkpi/common/include/linux/uaccess.h
+++ b/sys/compat/linuxkpi/common/include/linux/uaccess.h
@@ -2,7 +2,7 @@
  * Copyright (c) 2010 Isilon Systems, Inc.
  * Copyright (c) 2010 iX Systems, Inc.
  * Copyright (c) 2010 Panasas, Inc.
- * Copyright (c) 2013-2015 Mellanox Technologies, Ltd.
+ * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
  * Copyright (c) 2015 François Tigeot
  * All rights reserved.
  *
@@ -34,6 +34,17 @@
 
 #include <linux/compiler.h>
 
+#define	__get_user(_x, _p) ({				\
+	int __err;					\
+	__typeof(*(_p)) __x;				\
+	__err = -copyin((_p), &(__x), sizeof(*(_p)));	\
+	(_x) = __x;					\
+	__err;						\
+})
+#define	__put_user(_x, _p) ({			\
+	__typeof(*(_p)) __x = (_x);		\
+	-copyout(&(__x), (_p), sizeof(*(_p)));	\
+})
 #define	get_user(_x, _p)	-copyin((_p), &(_x), sizeof(*(_p)))
 #define	put_user(_x, _p)	-copyout(&(_x), (_p), sizeof(*(_p)))
 

From 674ad7b19270eb19f7f6a727a18de798a620270a Mon Sep 17 00:00:00 2001
From: hselasky <hselasky@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:27:00 +0000
Subject: [PATCH 024/113] Add definition for the NETDEV_CHANGE event and tidy
 up the LinuxKPI notifier header file a bit while at it.

MFC after:	1 week
Sponsored by:	Mellanox Technologies
---
 .../linuxkpi/common/include/linux/notifier.h  | 36 +++++++++----------
 1 file changed, 17 insertions(+), 19 deletions(-)

diff --git a/sys/compat/linuxkpi/common/include/linux/notifier.h b/sys/compat/linuxkpi/common/include/linux/notifier.h
index 472236853dcf..ae292439bf54 100644
--- a/sys/compat/linuxkpi/common/include/linux/notifier.h
+++ b/sys/compat/linuxkpi/common/include/linux/notifier.h
@@ -2,7 +2,7 @@
  * Copyright (c) 2010 Isilon Systems, Inc.
  * Copyright (c) 2010 iX Systems, Inc.
  * Copyright (c) 2010 Panasas, Inc.
- * Copyright (c) 2013, 2014 Mellanox Technologies, Ltd.
+ * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -34,26 +34,24 @@
 #include <sys/types.h>
 #include <sys/eventhandler.h>
 
-/*
- * Max number of FreeBSD events to map to Linux events per notify type.
- */
 #define	NOTIFY_DONE	0
-#define	_NOTIFY_COUNT	7
 
-struct notifier_block {
-	int (*notifier_call)(struct notifier_block *, unsigned long, void *);
-	struct notifier_block	*next;
-	int			priority;
-	eventhandler_tag	tags[_NOTIFY_COUNT];
+enum {
+	NETDEV_CHANGE,
+	NETDEV_UP,
+	NETDEV_DOWN,
+	NETDEV_REGISTER,
+	NETDEV_UNREGISTER,
+	NETDEV_CHANGEADDR,
+	NETDEV_CHANGEIFADDR,
+	LINUX_NOTIFY_TAGS		/* must be last */
 };
 
-/* Values must be less than NOTIFY_COUNT */
-#define	NETDEV_UP		0x0001
-#define	NETDEV_DOWN		0x0002
-#define	NETDEV_REGISTER		0x0003
-#define	NETDEV_UNREGISTER	0x0004
-#define	NETDEV_CHANGEADDR       0x0005
-#define	NETDEV_CHANGEIFADDR     0x0006
+struct notifier_block {
+	int     (*notifier_call) (struct notifier_block *, unsigned long, void *);
+	struct notifier_block *next;
+	int	priority;
+	eventhandler_tag tags[LINUX_NOTIFY_TAGS];
+};
 
-
-#endif	/* _LINUX_NOTIFIER_H_ */
+#endif					/* _LINUX_NOTIFIER_H_ */

From 821336ce2f2365f2088975b4b4d9fe1306222915 Mon Sep 17 00:00:00 2001
From: hselasky <hselasky@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:29:50 +0000
Subject: [PATCH 025/113] Add more network related macros and functions to the
 LinuxKPI.

MFC after:	1 week
Sponsored by:	Mellanox Technologies
---
 .../linuxkpi/common/include/linux/netdevice.h     | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/sys/compat/linuxkpi/common/include/linux/netdevice.h b/sys/compat/linuxkpi/common/include/linux/netdevice.h
index 1d50ac19a627..d79cdf2aa514 100644
--- a/sys/compat/linuxkpi/common/include/linux/netdevice.h
+++ b/sys/compat/linuxkpi/common/include/linux/netdevice.h
@@ -58,6 +58,9 @@ extern struct net init_net;
 #define	dev_get_by_index(n, idx)	ifnet_byindex_ref((idx))
 #define	dev_hold(d)	if_ref((d))
 #define	dev_put(d)	if_rele((d))
+#define	dev_net(d)	(&init_net)
+
+#define	net_eq(a,b)	((a) == (b))
 
 #define	netif_running(dev)	!!((dev)->if_drv_flags & IFF_DRV_RUNNING)
 #define	netif_oper_up(dev)	!!((dev)->if_flags & IFF_UP)
@@ -69,6 +72,12 @@ netdev_priv(const struct net_device *dev)
 	return (dev->if_softc);
 }
 
+static inline struct net_device *
+netdev_notifier_info_to_dev(void *ifp)
+{
+	return (ifp);
+}
+
 int	register_netdevice_notifier(struct notifier_block *);
 int	register_inetaddr_notifier(struct notifier_block *);
 int	unregister_netdevice_notifier(struct notifier_block *);
@@ -93,6 +102,12 @@ dev_mc_delete(struct net_device *dev, void *addr, int alen, int all)
 	return -if_delmulti(dev, (struct sockaddr *)&sdl);
 }
 
+static inline int
+dev_mc_del(struct net_device *dev, void *addr)
+{
+	return (dev_mc_delete(dev, addr, 6, 0));
+}
+
 static inline int
 dev_mc_add(struct net_device *dev, void *addr, int alen, int newonly)
 {

From 01e92615b0258ad313473e9a5fbbc576e25354b4 Mon Sep 17 00:00:00 2001
From: hselasky <hselasky@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:31:20 +0000
Subject: [PATCH 026/113] Implement bitmap_weight() and bitmap_equal() for the
 LinuxKPI.

MFC after:	1 week
Sponsored by:	Mellanox Technologies
---
 .../linuxkpi/common/include/linux/bitops.h    | 32 ++++++++++++++++++-
 1 file changed, 31 insertions(+), 1 deletion(-)

diff --git a/sys/compat/linuxkpi/common/include/linux/bitops.h b/sys/compat/linuxkpi/common/include/linux/bitops.h
index 2f402e86bf78..0dcdfe0f9f93 100644
--- a/sys/compat/linuxkpi/common/include/linux/bitops.h
+++ b/sys/compat/linuxkpi/common/include/linux/bitops.h
@@ -467,10 +467,40 @@ bitmap_release_region(unsigned long *bitmap, int pos, int order)
         __reg_op(bitmap, pos, order, REG_OP_RELEASE);
 }
 
-
 #define for_each_set_bit(bit, addr, size) \
 	for ((bit) = find_first_bit((addr), (size));		\
 	     (bit) < (size);					\
 	     (bit) = find_next_bit((addr), (size), (bit) + 1))
 
+static inline unsigned
+bitmap_weight(unsigned long *bitmap, unsigned nbits)
+{
+	unsigned bit;
+	unsigned retval = 0;
+
+	for_each_set_bit(bit, bitmap, nbits)
+		retval++;
+	return (retval);
+}
+
+static inline int
+bitmap_equal(const unsigned long *pa,
+    const unsigned long *pb, unsigned bits)
+{
+	unsigned x;
+	unsigned y = bits / BITS_PER_LONG;
+ 
+	for (x = 0; x != y; x++) {
+		if (pa[x] != pb[x])
+			return (0);
+	}
+
+	y = bits % BITS_PER_LONG;
+	if (y != 0) {
+		if ((pa[x] ^ pb[x]) & BITMAP_LAST_WORD_MASK(y))
+			return (0);
+	}
+	return (1);
+}
+
 #endif	/* _LINUX_BITOPS_H_ */

From 69c5dfb50414f77c66c5de329b6743d3e97880ad Mon Sep 17 00:00:00 2001
From: hselasky <hselasky@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:33:20 +0000
Subject: [PATCH 027/113] Implement is_vlan_dev() and vlan_dev_vlan_id() for
 the LinuxKPI.

MFC after:	1 week
Sponsored by:	Mellanox Technologies
---
 .../linuxkpi/common/include/linux/if_vlan.h   | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/sys/compat/linuxkpi/common/include/linux/if_vlan.h b/sys/compat/linuxkpi/common/include/linux/if_vlan.h
index cd65183250d1..59b1c7e0a8c4 100644
--- a/sys/compat/linuxkpi/common/include/linux/if_vlan.h
+++ b/sys/compat/linuxkpi/common/include/linux/if_vlan.h
@@ -2,7 +2,7 @@
  * Copyright (c) 2010 Isilon Systems, Inc.
  * Copyright (c) 2010 iX Systems, Inc.
  * Copyright (c) 2010 Panasas, Inc.
- * Copyright (c) 2013 Mellanox Technologies, Ltd.
+ * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -35,8 +35,25 @@
 #include <sys/socket.h>
 #include <net/if.h>
 #include <net/ethernet.h>
+#include <net/if_var.h>
 #include <net/if_vlan_var.h>
+#include <net/if_types.h>
 
 #define VLAN_N_VID              4096
 
+static inline int
+is_vlan_dev(struct ifnet *ifp)
+{
+	return (ifp->if_type == IFT_L2VLAN);
+}
+
+static inline uint16_t
+vlan_dev_vlan_id(struct ifnet *ifp)
+{
+	uint16_t vtag;
+	if (VLAN_TAG(ifp, &vtag) == 0)
+		return (vtag);
+	return (0);
+}
+
 #endif	/* _LINUX_IF_VLAN_H_ */

From 541ea0041eee7ac8fa1013e24135394578838685 Mon Sep 17 00:00:00 2001
From: br <br@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:34:40 +0000
Subject: [PATCH 028/113] Remove uathload from build due to issue with GCC
 5.2.0: "ld: --relax and -r may not be used together." Requires fixing ld
 command line arguments and testing.

---
 usr.sbin/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/usr.sbin/Makefile b/usr.sbin/Makefile
index 16feb68073a5..86b5247132b5 100644
--- a/usr.sbin/Makefile
+++ b/usr.sbin/Makefile
@@ -194,7 +194,9 @@ SUBDIR.${MK_TIMED}+=	timed
 SUBDIR.${MK_TOOLCHAIN}+=	config
 SUBDIR.${MK_TOOLCHAIN}+=	crunch
 SUBDIR.${MK_UNBOUND}+=	unbound
+.if !(${COMPILER_TYPE} == "gcc" && ${COMPILER_VERSION} >= 50200)
 SUBDIR.${MK_USB}+=	uathload
+.endif
 SUBDIR.${MK_USB}+=	uhsoctl
 SUBDIR.${MK_USB}+=	usbconfig
 SUBDIR.${MK_USB}+=	usbdump

From 6530ee10673a0681ec91d4fb10aaef1e12c9b3ca Mon Sep 17 00:00:00 2001
From: hselasky <hselasky@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:36:16 +0000
Subject: [PATCH 029/113] Implement ether_addr_equal(),
 ether_addr_equal_64bits() and random_ether_addr() for the LinuxKPI.

MFC after:	1 week
Sponsored by:	Mellanox Technologies
---
 .../common/include/linux/etherdevice.h        | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/sys/compat/linuxkpi/common/include/linux/etherdevice.h b/sys/compat/linuxkpi/common/include/linux/etherdevice.h
index c7a6ebead341..70e5f64581b1 100644
--- a/sys/compat/linuxkpi/common/include/linux/etherdevice.h
+++ b/sys/compat/linuxkpi/common/include/linux/etherdevice.h
@@ -29,6 +29,9 @@
 
 #include <linux/types.h>
 
+#include <sys/random.h>
+#include <sys/libkern.h>
+
 #define	ETH_MODULE_SFF_8079		1
 #define	ETH_MODULE_SFF_8079_LEN		256
 #define	ETH_MODULE_SFF_8472		2
@@ -78,4 +81,25 @@ ether_addr_copy(u8 * dst, const u8 * src)
 	memcpy(dst, src, 6);
 }
 
+static inline bool
+ether_addr_equal(const u8 *pa, const u8 *pb)
+{
+	return (memcmp(pa, pb, 6) == 0);
+}
+
+static inline bool
+ether_addr_equal_64bits(const u8 *pa, const u8 *pb)
+{
+	return (memcmp(pa, pb, 6) == 0);
+}
+
+static inline void
+random_ether_addr(u8 * dst)
+{
+	read_random(dst, 6);
+
+	dst[0] &= 0xfe;
+	dst[0] |= 0x02;
+}
+
 #endif					/* _LINUX_ETHERDEVICE */

From f3807e96bd2de9a9523a664367c1bcc891e01a4b Mon Sep 17 00:00:00 2001
From: br <br@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:40:41 +0000
Subject: [PATCH 030/113] Add fenv.c for RISC-V. Copied from MIPS.

---
 lib/msun/riscv/fenv.c | 52 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)
 create mode 100644 lib/msun/riscv/fenv.c

diff --git a/lib/msun/riscv/fenv.c b/lib/msun/riscv/fenv.c
new file mode 100644
index 000000000000..a5a5c03d3a74
--- /dev/null
+++ b/lib/msun/riscv/fenv.c
@@ -0,0 +1,52 @@
+/*-
+ * Copyright (c) 2004 David Schultz <das@FreeBSD.ORG>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#define	__fenv_static
+#include "fenv.h"
+
+#ifdef __GNUC_GNU_INLINE__
+#error "This file must be compiled with C99 'inline' semantics"
+#endif
+
+/*
+ * Hopefully the system ID byte is immutable, so it's valid to use
+ * this as a default environment.
+ */
+const fenv_t __fe_dfl_env = 0;
+
+extern inline int feclearexcept(int __excepts);
+extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
+extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
+extern inline int feraiseexcept(int __excepts);
+extern inline int fetestexcept(int __excepts);
+extern inline int fegetround(void);
+extern inline int fesetround(int __round);
+extern inline int fegetenv(fenv_t *__envp);
+extern inline int feholdexcept(fenv_t *__envp);
+extern inline int fesetenv(const fenv_t *__envp);
+extern inline int feupdateenv(const fenv_t *__envp);

From cd64a150736f4a9f271c0e345a97941128bba948 Mon Sep 17 00:00:00 2001
From: br <br@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:45:21 +0000
Subject: [PATCH 031/113] Make libgcc compilable on RISC-V.

---
 gnu/lib/libgcc/Makefile | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/gnu/lib/libgcc/Makefile b/gnu/lib/libgcc/Makefile
index f3166e78a9b5..cdf62dd3df78 100644
--- a/gnu/lib/libgcc/Makefile
+++ b/gnu/lib/libgcc/Makefile
@@ -58,8 +58,10 @@ LIB2FUNCS+= _fixuns${mode}si
 .endfor
 
 # Likewise double-word routines.
-.if ${TARGET_CPUARCH} != "aarch64" && ${TARGET_CPUARCH} != "arm"
-# These are implemented in an ARM specific file but will not be filtered out
+.if ${TARGET_CPUARCH} != "aarch64" && ${TARGET_CPUARCH} != "arm" && \
+    ${TARGET_CPUARCH} != "riscv64"
+# These are implemented in an ARM specific file but will not be filtered out.
+# RISCVTODO: can't compile
 .for mode in sf df xf tf
 LIB2FUNCS+= _fix${mode}di _fixuns${mode}di
 LIB2FUNCS+= _floatdi${mode} _floatundi${mode}
@@ -322,7 +324,10 @@ EH_OBJS_T = ${LIB2ADDEHSTATIC:R:S/$/.o/}
 EH_OBJS_P = ${LIB2ADDEHSTATIC:R:S/$/.po/}
 EH_OBJS_S = ${LIB2ADDEHSHARED:R:S/$/.So/}
 EH_CFLAGS = -fexceptions -D__GLIBC__=3 -DElfW=__ElfN
+.if ${TARGET_CPUARCH} != "riscv64"
+# RISCVTODO: unwinding support
 SOBJS    += ${EH_OBJS_S}
+.endif
 
 .for _src in ${LIB2ADDEHSTATIC:M*.c}
 ${_src:R:S/$/.o/}: ${_src} ${COMMONHDRS}

From e18e95605fb9a92882e097edc4001cf79441c2c4 Mon Sep 17 00:00:00 2001
From: kib <kib@FreeBSD.org>
Date: Tue, 26 Jan 2016 14:46:39 +0000
Subject: [PATCH 032/113] Don't clear the software flow control flag before
 draining for last close or assert the bug that it is clear when leaving.

Remove an unrelated rotted comment that was attached to the buggy
clearing.

Since draining is not done in more cases, flushing is needed in more
cases, so start fixing flushing:
- do a full flush in ttydisc_close().  State what POSIX requires more
  clearly.  This was missing ttydevsw_pktnotify() calls to tell the
  devsw layer to flush.  Hardware tty drivers don't actually flush
  since they don't understand this API.
- fix 2 missing wakeups in tty_flush().  Most of the wakeups here are
  unnecessary for last close.  But ttydisc_close() did one of the
  missing ones.

This flow control bug ameliorated the design bug of requiring
potentially unbounded waits in draining.  Software flow control is the
easiest way to get an unbounded wait, and a long wait is sometimes
actually useful.  Users can type the xoff character on the receiver
and (if ixon is set on the sender) expect the output to be held until
the user is ready for more.

Hardware flow control can also give the unbounded wait, and this bug
didn't affect hardware flow control.  Unbounded waits from hardware
flow control take a more unusual configuration.  E.g., a terminal
program that controls the modem status lines, or unplugging the cable
in a configuration where this doesn't break the connection.

The design bug is still ameliorated by a newer bug in draining for
last close -- the 1 second timeout.  E.g., if the user types the
xoff character and the sender reaches last close, then output is
not resumed and the wait times out after just 1 second.  This is
broken, but preferable to an unbounded wait.  Before this change,
the output was resumed immediately and usually completed.

Submitted by:	bde
MFC after:	2 weeks
---
 sys/kern/tty.c         | 12 +++++-------
 sys/kern/tty_ttydisc.c | 13 +++++--------
 2 files changed, 10 insertions(+), 15 deletions(-)

diff --git a/sys/kern/tty.c b/sys/kern/tty.c
index 04a10b38075b..f10b9eaba3e8 100644
--- a/sys/kern/tty.c
+++ b/sys/kern/tty.c
@@ -201,7 +201,6 @@ ttydev_leave(struct tty *tp)
 		constty_clear();
 
 	/* Drain any output. */
-	MPASS((tp->t_flags & TF_STOPPED) == 0);
 	if (!tty_gone(tp))
 		tty_drain(tp, 1);
 
@@ -352,11 +351,7 @@ ttydev_close(struct cdev *dev, int fflag, int devtype __unused,
 	if (fflag & FREVOKE)
 		tty_flush(tp, FWRITE);
 
-	/*
-	 * This can only be called once. The callin and the callout
-	 * devices cannot be opened at the same time.
-	 */
-	tp->t_flags &= ~(TF_EXCLUDE|TF_STOPPED);
+	tp->t_flags &= ~TF_EXCLUDE;
 
 	/* Properly wake up threads that are stuck - revoke(). */
 	tp->t_revokecnt++;
@@ -1456,12 +1451,15 @@ tty_flush(struct tty *tp, int flags)
 		tp->t_flags &= ~TF_HIWAT_OUT;
 		ttyoutq_flush(&tp->t_outq);
 		tty_wakeup(tp, FWRITE);
-		if (!tty_gone(tp))
+		if (!tty_gone(tp)) {
+			ttydevsw_outwakeup(tp);
 			ttydevsw_pktnotify(tp, TIOCPKT_FLUSHWRITE);
+		}
 	}
 	if (flags & FREAD) {
 		tty_hiwat_in_unblock(tp);
 		ttyinq_flush(&tp->t_inq);
+		tty_wakeup(tp, FREAD);
 		if (!tty_gone(tp)) {
 			ttydevsw_inwakeup(tp);
 			ttydevsw_pktnotify(tp, TIOCPKT_FLUSHREAD);
diff --git a/sys/kern/tty_ttydisc.c b/sys/kern/tty_ttydisc.c
index 63b144ac79d2..99fde3110705 100644
--- a/sys/kern/tty_ttydisc.c
+++ b/sys/kern/tty_ttydisc.c
@@ -94,14 +94,11 @@ ttydisc_close(struct tty *tp)
 	/* Clean up our flags when leaving the discipline. */
 	tp->t_flags &= ~(TF_STOPPED|TF_HIWAT|TF_ZOMBIE);
 
-	/* POSIX states we should flush when close() is called. */
-	ttyinq_flush(&tp->t_inq);
-	ttyoutq_flush(&tp->t_outq);
-
-	if (!tty_gone(tp)) {
-		ttydevsw_inwakeup(tp);
-		ttydevsw_outwakeup(tp);
-	}
+	/*
+	 * POSIX states that we must drain output and flush input on
+	 * last close.  Draining has already been done if possible.
+	 */
+	tty_flush(tp, FREAD | FWRITE);
 
 	if (ttyhook_hashook(tp, close))
 		ttyhook_close(tp);

From c9e96da51585a3f40cadc95224ff8c41923e9e60 Mon Sep 17 00:00:00 2001
From: hselasky <hselasky@FreeBSD.org>
Date: Tue, 26 Jan 2016 15:12:31 +0000
Subject: [PATCH 033/113] LinuxKPI list updates: - Add some new hlist macros. -
 Update existing hlist macros removing the need for a temporary   iteration
 variable. - Properly define the RCU hlist macros to be SMP safe with regard  
 to RCU. - Safe list macro arguments by adding a pair of parentheses. - Prefix
 the _list_add() and _list_splice() functions with "linux"   to reflect they
 are LinuxKPI internal functions.

Obtained from:	Linux
MFC after:	1 week
Sponsored by:	Mellanox Technologies
---
 .../linuxkpi/common/include/linux/list.h      | 77 ++++++++++---------
 .../linuxkpi/common/include/linux/rcupdate.h  | 21 +++++
 sys/ofed/drivers/net/mlx4/en_netdev.c         |  4 +-
 3 files changed, 64 insertions(+), 38 deletions(-)

diff --git a/sys/compat/linuxkpi/common/include/linux/list.h b/sys/compat/linuxkpi/common/include/linux/list.h
index 6aad25ea7b7a..f20c8632ba27 100644
--- a/sys/compat/linuxkpi/common/include/linux/list.h
+++ b/sys/compat/linuxkpi/common/include/linux/list.h
@@ -2,7 +2,7 @@
  * Copyright (c) 2010 Isilon Systems, Inc.
  * Copyright (c) 2010 iX Systems, Inc.
  * Copyright (c) 2010 Panasas, Inc.
- * Copyright (c) 2013, 2014 Mellanox Technologies, Ltd.
+ * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -109,7 +109,7 @@ list_replace(struct list_head *old, struct list_head *new)
 }
 
 static inline void
-_list_add(struct list_head *new, struct list_head *prev,
+linux_list_add(struct list_head *new, struct list_head *prev,
     struct list_head *next)
 {
 
@@ -136,47 +136,55 @@ list_del_init(struct list_head *entry)
 	list_entry(((ptr)->member.next), typeof(*(ptr)), member)
 
 #define	list_for_each(p, head)						\
-	for (p = (head)->next; p != (head); p = p->next)
+	for (p = (head)->next; p != (head); p = (p)->next)
 
 #define	list_for_each_safe(p, n, head)					\
-	for (p = (head)->next, n = p->next; p != (head); p = n, n = p->next)
+	for (p = (head)->next, n = (p)->next; p != (head); p = n, n = (p)->next)
 
 #define list_for_each_entry(p, h, field)				\
-	for (p = list_entry((h)->next, typeof(*p), field); &p->field != (h); \
-	    p = list_entry(p->field.next, typeof(*p), field))
+	for (p = list_entry((h)->next, typeof(*p), field); &(p)->field != (h); \
+	    p = list_entry((p)->field.next, typeof(*p), field))
 
 #define list_for_each_entry_safe(p, n, h, field)			\
 	for (p = list_entry((h)->next, typeof(*p), field), 		\
-	    n = list_entry(p->field.next, typeof(*p), field); &p->field != (h);\
+	    n = list_entry((p)->field.next, typeof(*p), field); &(p)->field != (h);\
 	    p = n, n = list_entry(n->field.next, typeof(*n), field))
 
+#define	list_for_each_entry_from(p, h, field) \
+	for ( ; &(p)->field != (h); \
+	    p = list_entry((p)->field.next, typeof(*p), field))
+
 #define	list_for_each_entry_continue(p, h, field)			\
-	for (p = list_next_entry((p), field); &p->field != (h);		\
+	for (p = list_next_entry((p), field); &(p)->field != (h);	\
 	    p = list_next_entry((p), field))
 
 #define	list_for_each_entry_safe_from(pos, n, head, member) 			\
-	for (n = list_entry(pos->member.next, typeof(*pos), member);		\
-	     &pos->member != (head);						\
+	for (n = list_entry((pos)->member.next, typeof(*pos), member);		\
+	     &(pos)->member != (head);						\
 	     pos = n, n = list_entry(n->member.next, typeof(*n), member))
 
 #define	list_for_each_entry_reverse(p, h, field)			\
-	for (p = list_entry((h)->prev, typeof(*p), field); &p->field != (h); \
-	    p = list_entry(p->field.prev, typeof(*p), field))
+	for (p = list_entry((h)->prev, typeof(*p), field); &(p)->field != (h); \
+	    p = list_entry((p)->field.prev, typeof(*p), field))
 
-#define	list_for_each_prev(p, h) for (p = (h)->prev; p != (h); p = p->prev)
+#define	list_for_each_entry_continue_reverse(p, h, field) \
+	for (p = list_entry((p)->field.prev, typeof(*p), field); &(p)->field != (h); \
+	    p = list_entry((p)->field.prev, typeof(*p), field))
+
+#define	list_for_each_prev(p, h) for (p = (h)->prev; p != (h); p = (p)->prev)
 
 static inline void
 list_add(struct list_head *new, struct list_head *head)
 {
 
-	_list_add(new, head, head->next);
+	linux_list_add(new, head, head->next);
 }
 
 static inline void
 list_add_tail(struct list_head *new, struct list_head *head)
 {
 
-	_list_add(new, head->prev, head);
+	linux_list_add(new, head->prev, head);
 }
 
 static inline void
@@ -196,7 +204,7 @@ list_move_tail(struct list_head *entry, struct list_head *head)
 }
 
 static inline void
-_list_splice(const struct list_head *list, struct list_head *prev,  
+linux_list_splice(const struct list_head *list, struct list_head *prev,  
     struct list_head *next)
 {
 	struct list_head *first;
@@ -216,21 +224,21 @@ static inline void
 list_splice(const struct list_head *list, struct list_head *head)
 {
 
-	_list_splice(list, head, head->next);
+	linux_list_splice(list, head, head->next);
 } 
 
 static inline void
 list_splice_tail(struct list_head *list, struct list_head *head)
 {
 
-	_list_splice(list, head->prev, head);
+	linux_list_splice(list, head->prev, head);
 }
  
 static inline void
 list_splice_init(struct list_head *list, struct list_head *head)
 {
 
-	_list_splice(list, head, head->next);
+	linux_list_splice(list, head, head->next);
 	INIT_LIST_HEAD(list);   
 }
  
@@ -238,7 +246,7 @@ static inline void
 list_splice_tail_init(struct list_head *list, struct list_head *head)
 {
 
-	_list_splice(list, head->prev, head);
+	linux_list_splice(list, head->prev, head);
 	INIT_LIST_HEAD(list);
 }
 
@@ -401,10 +409,10 @@ static inline int list_is_last(const struct list_head *list,
 #define	hlist_entry(ptr, type, field)	container_of(ptr, type, field)
 
 #define	hlist_for_each(p, head)						\
-	for (p = (head)->first; p; p = p->next)
+	for (p = (head)->first; p; p = (p)->next)
 
 #define	hlist_for_each_safe(p, n, head)					\
-	for (p = (head)->first; p && ({ n = p->next; 1; }); p = n)
+	for (p = (head)->first; p && ({ n = (p)->next; 1; }); p = n)
 
 #define	hlist_entry_safe(ptr, type, member) \
 	((ptr) ? hlist_entry(ptr, type, member) : NULL)
@@ -414,21 +422,18 @@ static inline int list_is_last(const struct list_head *list,
 	     pos;							\
 	     pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
 
-#define hlist_for_each_entry_continue(tp, p, field)			\
-	for (p = (p)->next;						\
-	    p ? (tp = hlist_entry(p, typeof(*tp), field)): NULL; p = p->next)
+#define	hlist_for_each_entry_continue(pos, member)			\
+	for (pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member); \
+	     (pos);							\
+	     pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
 
-#define	hlist_for_each_entry_from(tp, p, field)				\
-	for (; p ? (tp = hlist_entry(p, typeof(*tp), field)): NULL; p = p->next)
+#define	hlist_for_each_entry_from(pos, member)				\
+	for (; (pos);								\
+	     pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member))
 
-#define hlist_for_each_entry_safe(tpos, pos, n, head, member) 		 \
-	for (pos = (head)->first;					 \
-	     (pos) != 0 && ({ n = (pos)->next; \
-		 tpos = hlist_entry((pos), typeof(*(tpos)), member); 1;}); \
-	     pos = (n))
-
-#define	hlist_add_head_rcu(n, h)	hlist_add_head(n, h)
-
-#define	hlist_del_init_rcu(n)		hlist_del_init(n)
+#define	hlist_for_each_entry_safe(pos, n, head, member)			\
+	for (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member); \
+	     (pos) && ({ n = (pos)->member.next; 1; });			\
+	     pos = hlist_entry_safe(n, typeof(*(pos)), member))
 
 #endif /* _LINUX_LIST_H_ */
diff --git a/sys/compat/linuxkpi/common/include/linux/rcupdate.h b/sys/compat/linuxkpi/common/include/linux/rcupdate.h
index f8e2b04bc3de..12f43bb23bbb 100644
--- a/sys/compat/linuxkpi/common/include/linux/rcupdate.h
+++ b/sys/compat/linuxkpi/common/include/linux/rcupdate.h
@@ -73,4 +73,25 @@ synchronize_rcu(void)
 	sx_xunlock(&linux_global_rcu_lock);
 }
 
+#define	hlist_add_head_rcu(n, h)		\
+do {						\
+  	sx_xlock(&linux_global_rcu_lock);	\
+	hlist_add_head(n, h);			\
+	sx_xunlock(&linux_global_rcu_lock);	\
+} while (0)
+
+#define	hlist_del_init_rcu(n)			\
+do {						\
+    	sx_xlock(&linux_global_rcu_lock);	\
+	hlist_del_init(n);			\
+	sx_xunlock(&linux_global_rcu_lock);	\
+} while (0)
+
+#define	hlist_del_rcu(n)			\
+do {						\
+    	sx_xlock(&linux_global_rcu_lock);	\
+	hlist_del(n);				\
+	sx_xunlock(&linux_global_rcu_lock);	\
+} while (0)
+
 #endif					/* _LINUX_RCUPDATE_H_ */
diff --git a/sys/ofed/drivers/net/mlx4/en_netdev.c b/sys/ofed/drivers/net/mlx4/en_netdev.c
index 6fe2bded72fa..ae7f8576d76e 100644
--- a/sys/ofed/drivers/net/mlx4/en_netdev.c
+++ b/sys/ofed/drivers/net/mlx4/en_netdev.c
@@ -606,13 +606,13 @@ static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
 		mlx4_unregister_mac(dev, priv->port, mac);
 	} else {
 		struct mlx4_mac_entry *entry;
-		struct hlist_node *n, *tmp;
+		struct hlist_node *tmp;
 		struct hlist_head *bucket;
 		unsigned int i;
 
 		for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
 			bucket = &priv->mac_hash[i];
-			hlist_for_each_entry_safe(entry, n, tmp, bucket, hlist) {
+			hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
 				mac = mlx4_mac_to_u64(entry->mac);
 				en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
 				       entry->mac);

From f3d0abf0fdf238654a7b38dd0eaf59227a61ead8 Mon Sep 17 00:00:00 2001
From: zbb <zbb@FreeBSD.org>
Date: Tue, 26 Jan 2016 15:22:04 +0000
Subject: [PATCH 034/113] Import Annapurna Labs Alpine HAL for networking

Files required for the NIC driver

Import from vendor-sys/alpine-hal/2.7
SVN rev.: 294828
HAL version: 2.7

Obtained from:  Semihalf
Sponsored by:   Annapurna Labs
---
 sys/contrib/alpine-hal/al_hal_iofic.c         |  291 +
 sys/contrib/alpine-hal/al_hal_serdes.c        | 3228 ++++++++++
 sys/contrib/alpine-hal/al_hal_serdes.h        | 1125 ++++
 .../alpine-hal/al_hal_serdes_internal_regs.h  |  750 +++
 sys/contrib/alpine-hal/al_hal_serdes_regs.h   |  495 ++
 sys/contrib/alpine-hal/al_hal_udma.h          |  672 +++
 sys/contrib/alpine-hal/al_hal_udma_config.c   | 1373 +++++
 sys/contrib/alpine-hal/al_hal_udma_config.h   |  755 +++
 sys/contrib/alpine-hal/al_hal_udma_debug.c    |  497 ++
 sys/contrib/alpine-hal/al_hal_udma_debug.h    |  134 +
 sys/contrib/alpine-hal/al_hal_udma_iofic.c    |  151 +
 sys/contrib/alpine-hal/al_hal_udma_iofic.h    |  614 ++
 .../alpine-hal/al_hal_udma_iofic_regs.h       |   66 +
 sys/contrib/alpine-hal/al_hal_udma_main.c     |  618 ++
 sys/contrib/alpine-hal/al_hal_udma_regs.h     |  104 +
 sys/contrib/alpine-hal/al_hal_udma_regs_gen.h |  414 ++
 sys/contrib/alpine-hal/al_hal_udma_regs_m2s.h | 1159 ++++
 sys/contrib/alpine-hal/al_hal_udma_regs_s2m.h |  998 ++++
 .../eth/al_hal_an_lt_wrapper_regs.h           |  264 +
 sys/contrib/alpine-hal/eth/al_hal_eth.h       | 2381 ++++++++
 sys/contrib/alpine-hal/eth/al_hal_eth_alu.h   |   95 +
 .../alpine-hal/eth/al_hal_eth_ec_regs.h       | 3362 +++++++++++
 sys/contrib/alpine-hal/eth/al_hal_eth_kr.c    | 1030 ++++
 sys/contrib/alpine-hal/eth/al_hal_eth_kr.h    |  372 ++
 .../alpine-hal/eth/al_hal_eth_mac_regs.h      | 1809 ++++++
 sys/contrib/alpine-hal/eth/al_hal_eth_main.c  | 5260 +++++++++++++++++
 26 files changed, 28017 insertions(+)
 create mode 100644 sys/contrib/alpine-hal/al_hal_iofic.c
 create mode 100644 sys/contrib/alpine-hal/al_hal_serdes.c
 create mode 100644 sys/contrib/alpine-hal/al_hal_serdes.h
 create mode 100644 sys/contrib/alpine-hal/al_hal_serdes_internal_regs.h
 create mode 100644 sys/contrib/alpine-hal/al_hal_serdes_regs.h
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma.h
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_config.c
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_config.h
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_debug.c
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_debug.h
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_iofic.c
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_iofic.h
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_iofic_regs.h
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_main.c
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_regs.h
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_regs_gen.h
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_regs_m2s.h
 create mode 100644 sys/contrib/alpine-hal/al_hal_udma_regs_s2m.h
 create mode 100644 sys/contrib/alpine-hal/eth/al_hal_an_lt_wrapper_regs.h
 create mode 100644 sys/contrib/alpine-hal/eth/al_hal_eth.h
 create mode 100644 sys/contrib/alpine-hal/eth/al_hal_eth_alu.h
 create mode 100644 sys/contrib/alpine-hal/eth/al_hal_eth_ec_regs.h
 create mode 100644 sys/contrib/alpine-hal/eth/al_hal_eth_kr.c
 create mode 100644 sys/contrib/alpine-hal/eth/al_hal_eth_kr.h
 create mode 100644 sys/contrib/alpine-hal/eth/al_hal_eth_mac_regs.h
 create mode 100644 sys/contrib/alpine-hal/eth/al_hal_eth_main.c

diff --git a/sys/contrib/alpine-hal/al_hal_iofic.c b/sys/contrib/alpine-hal/al_hal_iofic.c
new file mode 100644
index 000000000000..28467f2e3b87
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_iofic.c
@@ -0,0 +1,291 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ *  @{
+ * @file   al_hal_iofic.c
+ *
+ * @brief  interrupt controller hal
+ *
+ */
+
+#include "al_hal_iofic.h"
+#include "al_hal_iofic_regs.h"
+
+/*
+ * configure the interrupt registers, interrupts will are kept masked
+ */
+int al_iofic_config(void __iomem *regs_base, int group, uint32_t flags)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	al_reg_write32(&regs->ctrl[group].int_control_grp, flags);
+
+	return 0;
+}
+
+/*
+ * configure the moderation timer resolution for a given group
+ */
+int al_iofic_moder_res_config(void __iomem *regs_base, int group,
+			     uint8_t resolution)
+
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+	uint32_t reg;
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	reg = al_reg_read32(&regs->ctrl[group].int_control_grp);
+	AL_REG_FIELD_SET(reg,
+			 INT_CONTROL_GRP_MOD_RES_MASK,
+			 INT_CONTROL_GRP_MOD_RES_SHIFT,
+			 resolution);
+	al_reg_write32(&regs->ctrl[group].int_control_grp, reg);
+
+	return 0;
+}
+
+/*
+ * configure the moderation timer interval for a given legacy interrupt group
+ */
+int al_iofic_legacy_moder_interval_config(void __iomem *regs_base, int group,
+				     uint8_t interval)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+	uint32_t reg;
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	reg = al_reg_read32(&regs->ctrl[group].int_control_grp);
+	AL_REG_FIELD_SET(reg,
+			 INT_CONTROL_GRP_MOD_INTV_MASK,
+			 INT_CONTROL_GRP_MOD_INTV_SHIFT,
+			 interval);
+	al_reg_write32(&regs->ctrl[group].int_control_grp, reg);
+
+	return 0;
+}
+
+
+/*
+ * configure the moderation timer interval for a given msix vector.
+ */
+int al_iofic_msix_moder_interval_config(void __iomem *regs_base, int group,
+				       uint8_t vector, uint8_t interval)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+	uint32_t reg;
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	reg = al_reg_read32(&regs->grp_int_mod[group][vector].grp_int_mod_reg);
+	AL_REG_FIELD_SET(reg,
+			 INT_MOD_INTV_MASK,
+			 INT_MOD_INTV_SHIFT,
+			 interval);
+	al_reg_write32(&regs->grp_int_mod[group][vector].grp_int_mod_reg, reg);
+
+	return 0;
+}
+
+/*
+ * configure the vmid attributes for a given msix vector.
+ */
+int al_iofic_msix_vmid_attributes_config(void __iomem *regs_base, int group,
+				       uint8_t vector, uint32_t vmid, uint8_t vmid_en)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+	uint32_t reg = 0;
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	AL_REG_FIELD_SET(reg,
+			 INT_MSIX_VMID_MASK,
+			 INT_MSIX_VMID_SHIFT,
+			 vmid);
+	AL_REG_BIT_VAL_SET(reg,
+			 INT_MSIX_VMID_EN_SHIFT,
+			 vmid_en);
+
+	al_reg_write32(&regs->grp_int_mod[group][vector].grp_int_vmid_reg, reg);
+
+	return 0;
+}
+
+/*
+ * return the offset of the unmask register for a given group
+ */
+uint32_t __iomem * al_iofic_unmask_offset_get(void __iomem *regs_base, int group)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	return &regs->ctrl[group].int_mask_clear_grp;
+}
+
+
+/*
+ * unmask specific interrupts for a given group
+ */
+void al_iofic_unmask(void __iomem *regs_base, int group, uint32_t mask)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	/*
+	 * use the mask clear register, no need to read the mask register
+	 * itself. write 0 to unmask, 1 has no effect
+	 */
+	al_reg_write32_relaxed(&regs->ctrl[group].int_mask_clear_grp, ~mask);
+}
+
+/*
+ * mask specific interrupts for a given group
+ */
+void al_iofic_mask(void __iomem *regs_base, int group, uint32_t mask)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+	uint32_t reg;
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	reg = al_reg_read32(&regs->ctrl[group].int_mask_grp);
+
+	al_reg_write32(&regs->ctrl[group].int_mask_grp, reg | mask);
+}
+
+/*
+ * read the mask for a given group
+ */
+uint32_t al_iofic_read_mask(void __iomem *regs_base, int group)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	return al_reg_read32(&regs->ctrl[group].int_mask_grp);
+}
+
+/*
+ * read interrupt cause register for a given group
+ */
+uint32_t al_iofic_read_cause(void __iomem *regs_base, int group)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	return al_reg_read32(&regs->ctrl[group].int_cause_grp);
+}
+
+/*
+ * clear bits in the interrupt cause register for a given group
+ */
+void al_iofic_clear_cause(void __iomem *regs_base, int group, uint32_t mask)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	/* inverse mask, writing 1 has no effect */
+	al_reg_write32(&regs->ctrl[group].int_cause_grp, ~mask);
+}
+
+/*
+ * Set the cause register for a given group
+ */
+void al_iofic_set_cause(void __iomem *regs_base, int group, uint32_t mask)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	al_reg_write32(&regs->ctrl[group].int_cause_set_grp, mask);
+}
+
+
+/*
+ * unmask specific interrupts from aborting the udma a given group
+ */
+void al_iofic_abort_mask(void __iomem *regs_base, int group, uint32_t mask)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	al_reg_write32(&regs->ctrl[group].int_abort_msk_grp, mask);
+
+}
+
+/*
+ * trigger all interrupts that are waiting for moderation timers to expire
+ */
+void al_iofic_interrupt_moderation_reset(void __iomem *regs_base, int group)
+{
+	struct al_iofic_regs __iomem *regs = (struct al_iofic_regs __iomem *)(regs_base);
+	uint32_t reg = 0;
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	al_assert(regs_base);
+	al_assert(group < AL_IOFIC_MAX_GROUPS);
+
+	reg = al_reg_read32(&regs->ctrl[group].int_control_grp);
+	reg |= INT_CONTROL_GRP_MOD_RST;
+
+	al_reg_write32(&regs->ctrl[group].int_control_grp, reg);
+}
+
+/** @} end of interrupt controller group */
diff --git a/sys/contrib/alpine-hal/al_hal_serdes.c b/sys/contrib/alpine-hal/al_hal_serdes.c
new file mode 100644
index 000000000000..bb34d13c765f
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_serdes.c
@@ -0,0 +1,3228 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#include "al_hal_serdes.h"
+#include "al_hal_serdes_regs.h"
+#include "al_hal_serdes_internal_regs.h"
+
+#define SRDS_CORE_REG_ADDR(page, type, offset)\
+	(((page) << 13) | ((type) << 12) | (offset))
+
+/* Link Training configuration */
+#define AL_SERDES_TX_DEEMPH_SUM_MAX		0x1b
+
+/* c configurations */
+#define AL_SERDES_TX_DEEMPH_C_ZERO_MAX_VAL	0x1b
+#define AL_SERDES_TX_DEEMPH_C_ZERO_MIN_VAL	0
+#define AL_SERDES_TX_DEEMPH_C_ZERO_PRESET	AL_SERDES_TX_DEEMPH_C_ZERO_MAX_VAL
+
+/* c(+1) configurations */
+#define AL_SERDES_TX_DEEMPH_C_PLUS_MAX_VAL	0x9
+#define AL_SERDES_TX_DEEMPH_C_PLUS_MIN_VAL	0
+#define AL_SERDES_TX_DEEMPH_C_PLUS_PRESET	AL_SERDES_TX_DEEMPH_C_PLUS_MIN_VAL
+
+/* c(-1) configurations */
+#define AL_SERDES_TX_DEEMPH_C_MINUS_MAX_VAL	0x6
+#define AL_SERDES_TX_DEEMPH_C_MINUS_MIN_VAL	0
+#define AL_SERDES_TX_DEEMPH_C_MINUS_PRESET	AL_SERDES_TX_DEEMPH_C_MINUS_MIN_VAL
+
+/* Rx equal total delay = MDELAY * TRIES */
+#define AL_SERDES_RX_EQUAL_MDELAY		10
+#define AL_SERDES_RX_EQUAL_TRIES		50
+
+/* Rx eye calculation delay = MDELAY * TRIES */
+#define AL_SERDES_RX_EYE_CAL_MDELAY		50
+#define AL_SERDES_RX_EYE_CAL_TRIES		70
+
+
+/**
+ * Prototypes for _lane_ compatibility
+ */
+int al_serdes_lane_read(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	enum al_serdes_reg_type	type,
+	uint16_t		offset,
+	uint8_t			*data);
+
+int al_serdes_lane_write(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	enum al_serdes_reg_type	type,
+	uint16_t		offset,
+	uint8_t			data);
+
+
+/**
+ * SERDES core reg/lane read
+ */
+static inline uint8_t al_serdes_grp_reg_read(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_reg_page		page,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset);
+
+static inline uint8_t al_serdes_grp_lane_read(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_lane		page,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset);
+
+/**
+ * SERDES core reg/lane write
+ */
+static inline void al_serdes_grp_reg_write(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_reg_page		page,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset,
+	uint8_t				data);
+
+static inline void al_serdes_grp_lane_write(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_lane		lane,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset,
+	uint8_t				data);
+
+/**
+ * SERDES core masked reg/lane write
+ */
+static inline void al_serdes_grp_reg_masked_write(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_reg_page		page,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset,
+	uint8_t				mask,
+	uint8_t				data);
+
+/**
+ * Lane Rx rate change software flow disable
+ */
+static void _al_serdes_lane_rx_rate_change_sw_flow_dis(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_lane		lane);
+
+/**
+ * Group Rx rate change software flow enable if all conditions met
+ */
+static void al_serdes_group_rx_rate_change_sw_flow_dis(
+	struct al_serdes_group_info	*grp_info);
+
+/**
+ * Lane Rx rate change software flow enable if all conditions met
+ */
+static void _al_serdes_lane_rx_rate_change_sw_flow_en_cond(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_lane		lane);
+
+/**
+ * Group Rx rate change software flow enable if all conditions met
+ */
+static void al_serdes_group_rx_rate_change_sw_flow_en_cond(
+	struct al_serdes_group_info	*grp_info);
+
+
+static inline void al_serdes_grp_lane_masked_write(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_lane		lane,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset,
+	uint8_t				mask,
+	uint8_t				data);
+
+/******************************************************************************/
+/******************************************************************************/
+int al_serdes_handle_init(
+	void __iomem			*serdes_regs_base,
+	struct al_serdes_obj		*obj)
+{
+	int i;
+
+	al_dbg(
+		"%s(%p, %p)\n",
+		__func__,
+		serdes_regs_base,
+		obj);
+
+	al_assert(serdes_regs_base);
+
+	for (i = 0; i < AL_SRDS_NUM_GROUPS; i++) {
+		obj->grp_info[i].pobj = obj;
+
+		obj->grp_info[i].regs_base =
+			&((struct al_serdes_regs *)serdes_regs_base)[i];
+	}
+
+	return 0;
+}
+
+/******************************************************************************/
+/******************************************************************************/
+int al_serdes_reg_read(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_reg_page	page,
+	enum al_serdes_reg_type	type,
+	uint16_t		offset,
+	uint8_t			*data)
+{
+	int status = 0;
+
+	al_dbg(
+		"%s(%p, %d, %d, %d, %u)\n",
+		__func__,
+		obj,
+		grp,
+		page,
+		type,
+		offset);
+
+	al_assert(obj);
+	al_assert(data);
+	al_assert(((int)grp) >= AL_SRDS_GRP_A);
+	al_assert(((int)grp) <= AL_SRDS_GRP_D);
+	al_assert(((int)page) >= AL_SRDS_REG_PAGE_0_LANE_0);
+	al_assert(((int)page) <= AL_SRDS_REG_PAGE_4_COMMON);
+	al_assert(((int)type) >= AL_SRDS_REG_TYPE_PMA);
+	al_assert(((int)type) <= AL_SRDS_REG_TYPE_PCS);
+
+	*data = al_serdes_grp_reg_read(
+		&obj->grp_info[grp],
+		page,
+		type,
+		offset);
+
+	al_dbg(
+		"%s: return(%u)\n",
+		__func__,
+		*data);
+
+	return status;
+}
+
+int al_serdes_lane_read(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	enum al_serdes_reg_type	type,
+	uint16_t		offset,
+	uint8_t			*data)
+{
+	return al_serdes_reg_read(obj, grp, (enum al_serdes_reg_page)lane, type,
+				  offset, data);
+}
+/******************************************************************************/
+/******************************************************************************/
+int al_serdes_reg_write(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_reg_page	page,
+	enum al_serdes_reg_type	type,
+	uint16_t		offset,
+	uint8_t			data)
+{
+	int status = 0;
+
+	al_dbg(
+		"%s(%p, %d, %d, %d, %u, %u)\n",
+		__func__,
+		obj,
+		grp,
+		page,
+		type,
+		offset,
+		data);
+
+	al_assert(obj);
+	al_assert(((int)grp) >= AL_SRDS_GRP_A);
+	al_assert(((int)grp) <= AL_SRDS_GRP_D);
+	al_assert(((int)page) >= AL_SRDS_REG_PAGE_0_LANE_0);
+	al_assert(((int)page) <= AL_SRDS_REG_PAGE_0123_LANES_0123);
+	al_assert(((int)type) >= AL_SRDS_REG_TYPE_PMA);
+	al_assert(((int)type) <= AL_SRDS_REG_TYPE_PCS);
+
+	al_serdes_grp_reg_write(
+		&obj->grp_info[grp],
+		page,
+		type,
+		offset,
+		data);
+
+	return status;
+}
+
+int al_serdes_lane_write(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	enum al_serdes_reg_type	type,
+	uint16_t		offset,
+	uint8_t			data)
+{
+	return al_serdes_reg_write(obj, grp, (enum al_serdes_reg_page)lane,
+				   type, offset, data);
+}
+/******************************************************************************/
+/******************************************************************************/
+#if (SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM != SERDES_IREG_FLD_PCSTX_DATAWIDTH_REG_NUM)
+#error "Wrong assumption!"
+#endif
+#if (SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM != SERDES_IREG_FLD_PCSTX_DIVRATE_REG_NUM)
+#error "Wrong assumption!"
+#endif
+#if (SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM != SERDES_IREG_FLD_CMNPCS_LOCWREN_REG_NUM)
+#error "Wrong assumption!"
+#endif
+#if (SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM != SERDES_IREG_FLD_CMNPCSBIST_LOCWREN_REG_NUM)
+#error "Wrong assumption!"
+#endif
+#if (SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM != SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN_REG_NUM)
+#error "Wrong assumption!"
+#endif
+#if (SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM != SERDES_IREG_FLD_LB_LOCWREN_REG_NUM)
+#error "Wrong assumption!"
+#endif
+#if (SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM != SERDES_IREG_FLD_PCSRX_LOCWREN_REG_NUM)
+#error "Wrong assumption!"
+#endif
+#if (SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM != SERDES_IREG_FLD_PCSRXBIST_LOCWREN_REG_NUM)
+#error "Wrong assumption!"
+#endif
+#if (SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM != SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM)
+#error "Wrong assumption!"
+#endif
+#if (SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM != SERDES_IREG_FLD_PCSTX_LOCWREN_REG_NUM)
+#error "Wrong assumption!"
+#endif
+void al_serdes_bist_overrides_enable(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_rate	rate)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+	int i;
+
+	uint8_t rx_rate_val;
+	uint8_t tx_rate_val;
+
+	switch (rate) {
+	case AL_SRDS_RATE_1_8:
+		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8;
+		tx_rate_val = SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_8;
+		break;
+	case AL_SRDS_RATE_1_4:
+		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4;
+		tx_rate_val = SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_4;
+		break;
+	case AL_SRDS_RATE_1_2:
+		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2;
+		tx_rate_val = SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_2;
+		break;
+	case AL_SRDS_RATE_FULL:
+		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1;
+		tx_rate_val = SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1;
+		break;
+	default:
+		al_err("%s: invalid rate (%d)\n",  __func__, rate);
+		al_assert(0);
+		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1;
+		tx_rate_val = SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1;
+	}
+
+	for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
+		al_serdes_grp_reg_masked_write(
+			grp_info,
+			(enum al_serdes_reg_page)i,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM,
+			SERDES_IREG_FLD_PCSRX_DATAWIDTH_MASK |
+			SERDES_IREG_FLD_PCSTX_DATAWIDTH_MASK,
+			SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_20 |
+			SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_20);
+
+		al_serdes_grp_reg_masked_write(
+			grp_info,
+			(enum al_serdes_reg_page)i,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM,
+			SERDES_IREG_FLD_PCSRX_DIVRATE_MASK |
+			SERDES_IREG_FLD_PCSTX_DIVRATE_MASK,
+			rx_rate_val | tx_rate_val);
+	}
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM,
+		SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN |
+		SERDES_IREG_FLD_CMNPCS_LOCWREN |
+		SERDES_IREG_FLD_CMNPCSBIST_LOCWREN |
+		SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN,
+		0);
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM,
+		SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN |
+		SERDES_IREG_FLD_CMNPCS_LOCWREN |
+		SERDES_IREG_FLD_CMNPCSBIST_LOCWREN |
+		SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN,
+		0);
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_PCS_LOCWREN_REG_NUM,
+		SERDES_IREG_FLD_PCS_LOCWREN,
+		0);
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_CMNPCS_TXENABLE_REG_NUM,
+		SERDES_IREG_FLD_CMNPCS_TXENABLE,
+		SERDES_IREG_FLD_CMNPCS_TXENABLE);
+
+	for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
+		al_serdes_grp_reg_masked_write(
+			grp_info,
+			(enum al_serdes_reg_page)i,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM,
+			SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN |
+			SERDES_IREG_FLD_LB_LOCWREN |
+			SERDES_IREG_FLD_PCSRX_LOCWREN |
+			SERDES_IREG_FLD_PCSRXBIST_LOCWREN |
+			SERDES_IREG_FLD_PCSRXEQ_LOCWREN |
+			SERDES_IREG_FLD_PCSTX_LOCWREN,
+			0);
+
+		al_serdes_grp_reg_masked_write(
+			grp_info,
+			(enum al_serdes_reg_page)i,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM,
+			SERDES_IREG_FLD_PCSTXBIST_LOCWREN,
+			0);
+
+		al_serdes_grp_reg_masked_write(
+			grp_info,
+			(enum al_serdes_reg_page)i,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
+			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN,
+			0);
+
+		al_serdes_grp_reg_masked_write(
+			grp_info,
+			(enum al_serdes_reg_page)i,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM,
+			SERDES_IREG_FLD_RXLOCK2REF_OVREN,
+			SERDES_IREG_FLD_RXLOCK2REF_OVREN);
+	}
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_bist_overrides_disable(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+	int i;
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM,
+		SERDES_IREG_FLD_CMNPCSBIST_LOCWREN,
+		SERDES_IREG_FLD_CMNPCSBIST_LOCWREN);
+
+	for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
+		al_serdes_grp_reg_masked_write(
+			grp_info,
+			(enum al_serdes_reg_page)i,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM,
+			SERDES_IREG_FLD_LB_LOCWREN |
+			SERDES_IREG_FLD_PCSRXBIST_LOCWREN,
+			SERDES_IREG_FLD_LB_LOCWREN |
+			SERDES_IREG_FLD_PCSRXBIST_LOCWREN);
+
+		al_serdes_grp_reg_masked_write(
+			grp_info,
+			(enum al_serdes_reg_page)i,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM,
+			SERDES_IREG_FLD_PCSTXBIST_LOCWREN,
+			SERDES_IREG_FLD_PCSTXBIST_LOCWREN);
+	}
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_rx_rate_change(
+	struct al_serdes_obj *obj,
+	enum al_serdes_group grp,
+	enum al_serdes_rate rate)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+	int i;
+
+	uint8_t rx_rate_val;
+
+	switch (rate) {
+	case AL_SRDS_RATE_1_8:
+		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8;
+		break;
+	case AL_SRDS_RATE_1_4:
+		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4;
+		break;
+	case AL_SRDS_RATE_1_2:
+		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2;
+		break;
+	case AL_SRDS_RATE_FULL:
+		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1;
+		break;
+	default:
+		al_err("%s: invalid rate (%d)\n",  __func__, rate);
+		rx_rate_val = SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1;
+		break;
+	}
+
+	for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
+		al_serdes_grp_reg_masked_write(
+				   grp_info,
+				   (enum al_serdes_reg_page)i,
+				   AL_SRDS_REG_TYPE_PMA,
+				   SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM,
+				   SERDES_IREG_FLD_PCSRX_DIVRATE_MASK,
+				   rx_rate_val);
+	}
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_group_pm_set(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_pm	pm)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	uint8_t pm_val;
+
+	switch (pm) {
+	case AL_SRDS_PM_PD:
+		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD;
+		break;
+	case AL_SRDS_PM_P2:
+		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P2;
+		break;
+	case AL_SRDS_PM_P1:
+		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P1;
+		break;
+	case AL_SRDS_PM_P0S:
+		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0S;
+		break;
+	case AL_SRDS_PM_P0:
+		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0;
+		break;
+	default:
+		al_err("%s: invalid power mode (%d)\n",  __func__, pm);
+		al_assert(0);
+		pm_val = SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0;
+	}
+
+	if (pm == AL_SRDS_PM_PD)
+		al_serdes_group_rx_rate_change_sw_flow_dis(grp_info);
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM,
+		SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK,
+		pm_val);
+
+	if (pm != AL_SRDS_PM_PD)
+		al_serdes_group_rx_rate_change_sw_flow_en_cond(grp_info);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_lane_rx_rate_change_sw_flow_en(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane)
+{
+	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 201, 0xfc);
+	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 202, 0xff);
+	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 203, 0xff);
+	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 204, 0xff);
+	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 205, 0x7f);
+	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 205, 0xff);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_lane_rx_rate_change_sw_flow_dis(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane)
+{
+	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA, 205, 0x7f);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_lane_pcie_rate_override_enable_set(
+	struct al_serdes_obj		*obj,
+	enum al_serdes_group		grp,
+	enum al_serdes_lane		lane,
+	al_bool				en)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PCS,
+		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM,
+		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA,
+		en ? SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA : 0);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+al_bool al_serdes_lane_pcie_rate_override_is_enabled(
+	struct al_serdes_obj		*obj,
+	enum al_serdes_group		grp,
+	enum al_serdes_lane		lane)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	return (al_serdes_grp_lane_read(
+		grp_info,
+		lane,
+		AL_SRDS_REG_TYPE_PCS,
+		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM) &
+		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA) ? AL_TRUE : AL_FALSE;
+}
+
+/******************************************************************************/
+/******************************************************************************/
+enum al_serdes_pcie_rate al_serdes_lane_pcie_rate_get(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	return (al_serdes_grp_reg_read(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PCS,
+		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM) &
+		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK) >>
+		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT;
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_lane_pcie_rate_set(
+	struct al_serdes_obj		*obj,
+	enum al_serdes_group		grp,
+	enum al_serdes_lane		lane,
+	enum al_serdes_pcie_rate	rate)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PCS,
+		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM,
+		SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK,
+		rate << SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_lane_pm_set(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	enum al_serdes_pm	rx_pm,
+	enum al_serdes_pm	tx_pm)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	uint8_t rx_pm_val;
+	uint8_t tx_pm_val;
+
+	switch (rx_pm) {
+	case AL_SRDS_PM_PD:
+		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD;
+		break;
+	case AL_SRDS_PM_P2:
+		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P2;
+		break;
+	case AL_SRDS_PM_P1:
+		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P1;
+		break;
+	case AL_SRDS_PM_P0S:
+		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0S;
+		break;
+	case AL_SRDS_PM_P0:
+		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0;
+		break;
+	default:
+		al_err("%s: invalid rx power mode (%d)\n",  __func__, rx_pm);
+		al_assert(0);
+		rx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0;
+	}
+
+	switch (tx_pm) {
+	case AL_SRDS_PM_PD:
+		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_PD;
+		break;
+	case AL_SRDS_PM_P2:
+		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P2;
+		break;
+	case AL_SRDS_PM_P1:
+		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P1;
+		break;
+	case AL_SRDS_PM_P0S:
+		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0S;
+		break;
+	case AL_SRDS_PM_P0:
+		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0;
+		break;
+	default:
+		al_err("%s: invalid tx power mode (%d)\n",  __func__, tx_pm);
+		al_assert(0);
+		tx_pm_val = SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0;
+	}
+
+	if (rx_pm == AL_SRDS_PM_PD)
+		_al_serdes_lane_rx_rate_change_sw_flow_dis(grp_info, lane);
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM,
+		SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK,
+		rx_pm_val);
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_LANEPCSPSTATE_TX_REG_NUM,
+		SERDES_IREG_FLD_LANEPCSPSTATE_TX_MASK,
+		tx_pm_val);
+
+	if (rx_pm != AL_SRDS_PM_PD)
+		_al_serdes_lane_rx_rate_change_sw_flow_en_cond(grp_info, lane);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_pma_hard_reset_group(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	al_bool			enable)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	if (enable)
+		al_serdes_group_rx_rate_change_sw_flow_dis(grp_info);
+
+	/* Enable Hard Reset Override */
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM,
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK,
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS);
+
+	/* Assert/Deassert Hard Reset Override */
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM,
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK,
+		enable ?
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT :
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_DEASSERT);
+
+	if (!enable)
+		al_serdes_group_rx_rate_change_sw_flow_en_cond(grp_info);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_pma_hard_reset_lane(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	al_bool			enable)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	if (enable)
+		_al_serdes_lane_rx_rate_change_sw_flow_dis(grp_info, lane);
+
+	/* Enable Hard Reset Override */
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM,
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK,
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS);
+
+	/* Assert/Deassert Hard Reset Override */
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM,
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK,
+		enable ?
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT :
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_DEASSERT);
+
+	if (!enable)
+		_al_serdes_lane_rx_rate_change_sw_flow_en_cond(grp_info, lane);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+#if	(SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM !=\
+	SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM) ||\
+	(SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM !=\
+	SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM) ||\
+	(SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM !=\
+	 SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM) ||\
+	(SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM !=\
+	 SERDES_IREG_FLD_LB_CDRCLK2TXEN_REG_NUM)
+#error Wrong assumption
+#endif
+
+void al_serdes_loopback_control(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	enum al_serdes_lb_mode	mode)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+	uint8_t val = 0;
+
+	switch (mode) {
+	case AL_SRDS_LB_MODE_OFF:
+		break;
+	case AL_SRDS_LB_MODE_PMA_IO_UN_TIMED_RX_TO_TX:
+		val = SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN;
+		break;
+	case AL_SRDS_LB_MODE_PMA_INTERNALLY_BUFFERED_SERIAL_TX_TO_RX:
+		val = SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN;
+		break;
+	case AL_SRDS_LB_MODE_PMA_SERIAL_TX_IO_TO_RX_IO:
+		val = SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN;
+		break;
+	case AL_SRDS_LB_MODE_PMA_PARALLEL_RX_TO_TX:
+		val = SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN |
+			SERDES_IREG_FLD_LB_CDRCLK2TXEN;
+		break;
+	default:
+		al_err("%s: invalid mode (%d)\n",  __func__, mode);
+		al_assert(0);
+	}
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM,
+		SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN |
+		SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN |
+		SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN |
+		SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN |
+		SERDES_IREG_FLD_LB_CDRCLK2TXEN,
+		val);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_bist_pattern_select(
+	struct al_serdes_obj		*obj,
+	enum al_serdes_group		grp,
+	enum al_serdes_bist_pattern	pattern,
+	uint8_t				*user_data)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+	uint8_t val = 0;
+
+	switch (pattern) {
+	case AL_SRDS_BIST_PATTERN_USER:
+		al_assert(user_data);
+		val = SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_USER;
+		break;
+	case AL_SRDS_BIST_PATTERN_PRBS7:
+		val = SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS7;
+		break;
+	case AL_SRDS_BIST_PATTERN_PRBS23:
+		val = SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS23;
+		break;
+	case AL_SRDS_BIST_PATTERN_PRBS31:
+		val = SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS31;
+		break;
+	case AL_SRDS_BIST_PATTERN_CLK1010:
+		val = SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_CLK1010;
+		break;
+	default:
+		al_err("%s: invalid pattern (%d)\n", __func__, pattern);
+		al_assert(0);
+	}
+
+	if (pattern == AL_SRDS_BIST_PATTERN_USER) {
+		int i;
+
+		for (i = 0; i < SERDES_IREG_FLD_TX_BIST_PAT_NUM_BYTES; i++)
+			al_serdes_grp_reg_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_TX_BIST_PAT_REG_NUM(i),
+				user_data[i]);
+	}
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_CMNPCSBIST_MODESEL_REG_NUM,
+		SERDES_IREG_FLD_CMNPCSBIST_MODESEL_MASK,
+		val);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_bist_tx_enable(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	al_bool			enable)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_PCSTXBIST_EN_REG_NUM,
+		SERDES_IREG_FLD_PCSTXBIST_EN,
+		enable ? SERDES_IREG_FLD_PCSTXBIST_EN : 0);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_bist_tx_err_inject(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM,
+		SERDES_IREG_FLD_TXBIST_BITERROR_EN,
+		SERDES_IREG_FLD_TXBIST_BITERROR_EN);
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM,
+		SERDES_IREG_FLD_TXBIST_BITERROR_EN,
+		0);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+void al_serdes_bist_rx_enable(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	al_bool			enable)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	al_serdes_grp_reg_masked_write(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_PCSRXBIST_EN_REG_NUM,
+		SERDES_IREG_FLD_PCSRXBIST_EN,
+		enable ? SERDES_IREG_FLD_PCSRXBIST_EN : 0);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+#if	(SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW_REG_NUM !=\
+	SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM)
+#error Wrong assumption
+#endif
+
+void al_serdes_bist_rx_status(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	al_bool			*is_locked,
+	al_bool			*err_cnt_overflow,
+	uint16_t		*err_cnt)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+	uint8_t status_reg_val;
+	uint16_t err_cnt_msb_reg_val;
+	uint16_t err_cnt_lsb_reg_val;
+
+	status_reg_val = al_serdes_grp_reg_read(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM);
+
+	err_cnt_msb_reg_val = al_serdes_grp_reg_read(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXBIST_ERRCOUNT_MSB_REG_NUM);
+
+	err_cnt_lsb_reg_val = al_serdes_grp_reg_read(
+		grp_info,
+		(enum al_serdes_reg_page)lane,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXBIST_ERRCOUNT_LSB_REG_NUM);
+
+	*is_locked =
+		(status_reg_val & SERDES_IREG_FLD_RXBIST_RXLOCKED) ?
+		AL_TRUE : AL_FALSE;
+
+	*err_cnt_overflow =
+		(status_reg_val & SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW) ?
+		AL_TRUE : AL_FALSE;
+
+	*err_cnt = (err_cnt_msb_reg_val << 8) + err_cnt_lsb_reg_val;
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static inline uint8_t al_serdes_grp_reg_read(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_reg_page		page,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset)
+{
+	al_reg_write32(
+		&grp_info->regs_base->gen.reg_addr,
+		SRDS_CORE_REG_ADDR(page, type, offset));
+
+	return al_reg_read32(&grp_info->regs_base->gen.reg_data);
+}
+
+static inline uint8_t al_serdes_grp_lane_read(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_lane		page,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset)
+{
+	return al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)page,
+				      type, offset);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static inline void al_serdes_grp_reg_write(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_reg_page		page,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset,
+	uint8_t				data)
+{
+	al_reg_write32(
+		&grp_info->regs_base->gen.reg_addr,
+		SRDS_CORE_REG_ADDR(page, type, offset));
+
+	al_reg_write32(&grp_info->regs_base->gen.reg_data, data);
+}
+
+
+static inline void al_serdes_grp_lane_write(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_lane		lane,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset,
+	uint8_t				data)
+{
+	al_serdes_grp_reg_write(grp_info, (enum al_serdes_reg_page)lane,
+				type, offset, data);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static inline void al_serdes_ns_delay(int cnt)
+{
+	al_udelay((cnt + 999) / 1000);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static inline void al_serdes_grp_reg_masked_write(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_reg_page		page,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset,
+	uint8_t				mask,
+	uint8_t				data)
+{
+	uint8_t val;
+	enum al_serdes_reg_page	start_page = page;
+	enum al_serdes_reg_page	end_page   = page;
+	enum al_serdes_reg_page	iter_page;
+
+	if (page == AL_SRDS_REG_PAGE_0123_LANES_0123) {
+		start_page = AL_SRDS_REG_PAGE_0_LANE_0;
+		end_page   = AL_SRDS_REG_PAGE_3_LANE_3;
+	}
+
+	for(iter_page = start_page; iter_page <= end_page; ++iter_page) {
+		val = al_serdes_grp_reg_read(grp_info, iter_page, type, offset);
+		val &= ~mask;
+		val |= data;
+		al_serdes_grp_reg_write(grp_info, iter_page, type, offset, val);
+	}
+}
+
+static inline void al_serdes_grp_lane_masked_write(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_lane		lane,
+	enum al_serdes_reg_type		type,
+	uint16_t			offset,
+	uint8_t				mask,
+	uint8_t				data)
+{
+	al_serdes_grp_reg_masked_write(grp_info, (enum al_serdes_reg_page)lane,
+				       type, offset, mask, data);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static void _al_serdes_lane_rx_rate_change_sw_flow_dis(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_lane		lane)
+{
+	al_bool lane_sw_flow_enabled;
+
+	al_assert(lane != AL_SRDS_LANES_0123);
+
+	lane_sw_flow_enabled =
+		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 201) == 0xfc) &&
+		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 202) == 0xff) &&
+		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 203) == 0xff) &&
+		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 204) == 0xff) &&
+		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 205) == 0xff);
+
+	/**
+	 * Disable the Rx rate change software flow by clearing bit 7 of lane PMA register 205
+	 * (RSTPDOVR_RX_OVREN)
+	 */
+	if (lane_sw_flow_enabled) {
+		al_dbg("%s(%d): actually disabling\n", __func__, lane);
+		al_serdes_grp_reg_masked_write(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 205, 0x80, 0x00);
+	}
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static void al_serdes_group_rx_rate_change_sw_flow_dis(
+	struct al_serdes_group_info	*grp_info)
+{
+	int lane;
+
+	for (lane = AL_SRDS_LANE_0; lane < AL_SRDS_NUM_LANES; lane++)
+		_al_serdes_lane_rx_rate_change_sw_flow_dis(grp_info, lane);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static void _al_serdes_lane_rx_rate_change_sw_flow_en_cond(
+	struct al_serdes_group_info	*grp_info,
+	enum al_serdes_lane		lane)
+{
+	al_bool lane_sw_flow_almost_enabled;
+	al_bool group_reset_enabled;
+	al_bool lane_reset_enabled;
+	al_bool group_pd_enabled;
+	al_bool lane_pd_enabled;
+
+	al_assert(lane != AL_SRDS_LANES_0123);
+
+	lane_sw_flow_almost_enabled =
+		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 201) == 0xfc) &&
+		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 202) == 0xff) &&
+		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 203) == 0xff) &&
+		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 204) == 0xff) &&
+		(al_serdes_grp_reg_read(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 205) == 0x7f);
+
+	group_reset_enabled =
+		((al_serdes_grp_reg_read(
+			grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM) &
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK) ==
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS) &&
+		((al_serdes_grp_reg_read(
+			grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM) &
+			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK) ==
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT);
+
+	lane_reset_enabled =
+		((al_serdes_grp_reg_read(
+			grp_info, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM) &
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK) ==
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS) &&
+		((al_serdes_grp_reg_read(
+			grp_info, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM) &
+			SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK) ==
+		SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT);
+
+	group_pd_enabled =
+		(al_serdes_grp_reg_read(
+			grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM) &
+		SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK) ==
+		SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD;
+
+	lane_pd_enabled =
+		(al_serdes_grp_reg_read(
+			grp_info, (enum al_serdes_reg_page)lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM) &
+		SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK) ==
+		SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD;
+
+	/**
+	 * Enable the Rx rate change software flow by setting bit 7 of lane PMA register 205
+	 * (RSTPDOVR_RX_OVREN)
+	 */
+	if (lane_sw_flow_almost_enabled && !group_reset_enabled && !lane_reset_enabled &&
+		!group_pd_enabled && !lane_pd_enabled) {
+		al_dbg("%s(%d): actually enabling\n", __func__, lane);
+
+		al_serdes_ns_delay(500);
+		al_serdes_grp_reg_masked_write(grp_info, (enum al_serdes_reg_page)lane,
+			AL_SRDS_REG_TYPE_PMA, 205, 0x80, 0x80);
+	}
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static void al_serdes_group_rx_rate_change_sw_flow_en_cond(
+	struct al_serdes_group_info	*grp_info)
+{
+	int lane;
+
+	for (lane = AL_SRDS_LANE_0; lane < AL_SRDS_NUM_LANES; lane++)
+		_al_serdes_lane_rx_rate_change_sw_flow_en_cond(grp_info, lane);
+}
+
+/******************************************************************************/
+/******************************************************************************/
+int al_serdes_eye_measure_run(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane,
+		uint32_t		timeout,
+		unsigned int		*value)
+{
+	uint32_t reg = 0;
+	uint32_t i;
+	struct serdes_lane *lane_regs;
+
+	lane_regs = &obj->grp_info[grp].regs_base->lane[lane];
+
+	al_reg_write32(&lane_regs->ictl_multi_rxeq,
+		       SERDES_LANE_ICTL_MULTI_RXEQ_START_L_A);
+
+	for (i = 0 ; i < timeout ; i++) {
+		reg = al_reg_read32(&lane_regs->octl_multi);
+
+		if (reg & SERDES_LANE_OCTL_MULTI_RXEQ_DONE_L_A)
+			break;
+
+		al_msleep(10);
+	}
+
+	if (i == timeout) {
+		al_err("%s: measure eye failed on timeout\n", __func__);
+		return -ETIMEDOUT;
+	}
+
+	*value = al_reg_read32(&lane_regs->odat_multi_rxeq);
+
+	al_reg_write32(&lane_regs->ictl_multi_rxeq, 0);
+
+	return 0;
+}
+
+/******************************************************************************/
+/******************************************************************************/
+int al_serdes_eye_diag_sample(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane,
+		unsigned int		x,
+		int			y,
+		unsigned int		timeout,
+		unsigned int		*value)
+{
+	enum al_serdes_reg_page	page = (enum al_serdes_reg_page)lane;
+	struct al_serdes_group_info *grp_info;
+	uint32_t i;
+	uint8_t sample_count_orig_msb;
+	uint8_t sample_count_orig_lsb;
+
+	al_assert(obj);
+	al_assert(((int)grp) >= AL_SRDS_GRP_A);
+	al_assert(((int)grp) <= AL_SRDS_GRP_D);
+	al_assert(((int)page) >= AL_SRDS_REG_PAGE_0_LANE_0);
+	al_assert(((int)page) <= AL_SRDS_REG_PAGE_0123_LANES_0123);
+
+	grp_info = &obj->grp_info[grp];
+
+	/* Obtain sample count by reading RXCALROAMEYEMEAS_COUNT */
+	sample_count_orig_msb = al_serdes_grp_reg_read(grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM);
+	sample_count_orig_lsb = al_serdes_grp_reg_read(grp_info,
+		AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM);
+
+	/* Set sample count to ~100000 samples */
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM, 0x13);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM, 0x88);
+
+	/* BER Contour Overwrite */
+	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM,
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN,
+		0);
+	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM,
+		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN,
+		0);
+	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
+		SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN,
+		0);
+
+	/* RXROAM_XORBITSEL = 0x1 or 0x0 */
+	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
+		SERDES_IREG_FLD_RXROAM_XORBITSEL,
+		SERDES_IREG_FLD_RXROAM_XORBITSEL_2ND);
+
+	/* Set X */
+	al_serdes_grp_reg_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMXADJUST_REG_NUM, x);
+
+	/* Set Y */
+	al_serdes_grp_reg_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMYADJUST_REG_NUM,
+		y < 32 ? 31 - y : y + 1);
+
+	/* Start Measurement by setting RXCALROAMEYEMEASIN_CYCLEEN = 0x1 */
+	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM,
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START,
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START);
+
+	/* Check RXCALROAMEYEMEASDONE Signal (Polling Until 0x1) */
+	for (i = 0 ; i < timeout ; i++) {
+		if (al_serdes_grp_reg_read(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM) &
+			SERDES_IREG_FLD_RXCALROAMEYEMEASDONE)
+			break;
+		al_udelay(1);
+	}
+	if (i == timeout) {
+		al_err("%s: eye diagram sampling timed out!\n", __func__);
+		return -ETIMEDOUT;
+	}
+
+	/* Stop Measurement by setting RXCALROAMEYEMEASIN_CYCLEEN = 0x0 */
+	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM,
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START,
+		0);
+
+	/* Obtain Error Counts by reading RXCALROAMEYEMEAS_ACC */
+	*value = ((unsigned int)al_serdes_grp_reg_read(grp_info, page,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_MSB_REG_NUM)) << 8 |
+		al_serdes_grp_reg_read(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_LSB_REG_NUM);
+
+	/* BER Contour Overwrite */
+	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM,
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN,
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN);
+	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM,
+		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN,
+		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN);
+	al_serdes_grp_reg_masked_write(grp_info, page, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
+		SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN,
+		SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN);
+
+	/* Restore sample count */
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM,
+		sample_count_orig_msb);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM,
+		sample_count_orig_lsb);
+
+	return 0;
+}
+
+/******************************************************************************/
+/******************************************************************************/
+static void al_serdes_tx_deemph_set(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane,
+		uint32_t		c_zero,
+		uint32_t		c_plus_1,
+		uint32_t		c_minus_1)
+{
+	al_serdes_grp_lane_masked_write(
+			&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_TX_DRV_1_REG_NUM,
+			SERDES_IREG_TX_DRV_1_LEVN_MASK,
+			((c_zero + c_plus_1 + c_minus_1)
+				<< SERDES_IREG_TX_DRV_1_LEVN_SHIFT));
+
+	al_serdes_grp_lane_masked_write(
+			&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_TX_DRV_2_REG_NUM,
+			SERDES_IREG_TX_DRV_2_LEVNM1_MASK,
+			(c_plus_1 << SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT));
+
+	al_serdes_grp_lane_masked_write(
+			&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_TX_DRV_3_REG_NUM,
+			SERDES_IREG_TX_DRV_3_LEVNP1_MASK,
+			(c_minus_1 << SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT));
+}
+
+static void al_serdes_tx_deemph_get(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane,
+		uint32_t		*c_zero,
+		uint32_t		*c_plus_1,
+		uint32_t		*c_minus_1)
+{
+	uint32_t reg = 0;
+
+	reg = al_serdes_grp_lane_read(
+			&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_TX_DRV_2_REG_NUM);
+
+	*c_plus_1 = ((reg & SERDES_IREG_TX_DRV_2_LEVNM1_MASK) >>
+					SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT);
+
+	reg = al_serdes_grp_lane_read(
+			&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_TX_DRV_3_REG_NUM);
+
+	*c_minus_1 = ((reg & SERDES_IREG_TX_DRV_3_LEVNP1_MASK) >>
+					SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT);
+
+	reg = al_serdes_grp_lane_read(
+			&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_TX_DRV_1_REG_NUM);
+
+	*c_zero = (((reg & SERDES_IREG_TX_DRV_1_LEVN_MASK) >>
+		SERDES_IREG_TX_DRV_1_LEVN_SHIFT) - *c_plus_1 - *c_minus_1);
+}
+
+al_bool al_serdes_tx_deemph_inc(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane,
+		enum al_serdes_tx_deemph_param param)
+{
+	al_bool ret = AL_TRUE;
+	uint32_t c0;
+	uint32_t c1;
+	uint32_t c_1;
+
+	al_serdes_tx_deemph_get(obj, grp, lane, &c0, &c1, &c_1);
+
+	al_dbg("%s: current txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
+		__func__, c0, c1, c_1);
+
+	switch (param) {
+	case AL_SERDES_TX_DEEMP_C_ZERO:
+
+		if (c0 == AL_SERDES_TX_DEEMPH_C_ZERO_MAX_VAL)
+			return AL_FALSE;
+
+		c0++;
+
+		break;
+	case AL_SERDES_TX_DEEMP_C_PLUS:
+
+		if (c1 == AL_SERDES_TX_DEEMPH_C_PLUS_MAX_VAL)
+			return AL_FALSE;
+
+		c1++;
+
+		break;
+	case AL_SERDES_TX_DEEMP_C_MINUS:
+
+		if (c_1 == AL_SERDES_TX_DEEMPH_C_MINUS_MAX_VAL)
+			return AL_FALSE;
+
+		c_1++;
+
+		break;
+	}
+
+	if ((c0 + c1 + c_1) > AL_SERDES_TX_DEEMPH_SUM_MAX) {
+		al_dbg("%s: sum of all tx de-emphasis over the max limit\n",
+			__func__);
+
+		return AL_FALSE;
+	}
+
+	al_dbg("%s: new txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
+		__func__, c0, c1, c_1);
+
+	al_serdes_tx_deemph_set(obj, grp, lane, c0, c1, c_1);
+
+	return ret;
+}
+
+al_bool al_serdes_tx_deemph_dec(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane,
+		enum al_serdes_tx_deemph_param param)
+{
+	al_bool ret = AL_TRUE;
+	uint32_t c0;
+	uint32_t c1;
+	uint32_t c_1;
+
+	al_serdes_tx_deemph_get(obj, grp, lane, &c0, &c1, &c_1);
+
+	al_dbg("%s: current txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
+		__func__, c0, c1, c_1);
+
+	switch (param) {
+	case AL_SERDES_TX_DEEMP_C_ZERO:
+
+		if (c0 == AL_SERDES_TX_DEEMPH_C_ZERO_MIN_VAL)
+			return AL_FALSE;
+
+		c0--;
+
+		break;
+	case AL_SERDES_TX_DEEMP_C_PLUS:
+
+		if (c1 == AL_SERDES_TX_DEEMPH_C_PLUS_MIN_VAL)
+			return AL_FALSE;
+
+		c1--;
+
+		break;
+	case AL_SERDES_TX_DEEMP_C_MINUS:
+
+		if (c_1 == AL_SERDES_TX_DEEMPH_C_MINUS_MIN_VAL)
+			return AL_FALSE;
+
+		c_1--;
+
+		break;
+	}
+
+	al_dbg("%s: new txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
+		__func__, c0, c1, c_1);
+
+	al_serdes_tx_deemph_set(obj, grp, lane, c0, c1, c_1);
+
+	return ret;
+}
+
+void al_serdes_tx_deemph_preset(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane)
+{
+	uint32_t c0;
+	uint32_t c1;
+	uint32_t c_1;
+
+	c0 = AL_SERDES_TX_DEEMPH_C_ZERO_PRESET;
+
+	c1 = AL_SERDES_TX_DEEMPH_C_PLUS_PRESET;
+
+	c_1 = AL_SERDES_TX_DEEMPH_C_MINUS_PRESET;
+
+	al_dbg("preset: new txdeemph: c0 = 0x%x c1 = 0x%x c-1 = 0x%x\n",
+		c0, c1, c_1);
+
+	al_serdes_tx_deemph_set(obj, grp, lane, c0, c1, c_1);
+}
+
+al_bool al_serdes_signal_is_detected(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane)
+{
+	uint32_t reg = 0;
+
+	reg = al_serdes_grp_lane_read(
+			&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXRANDET_REG_NUM);
+
+	return ((reg & SERDES_IREG_FLD_RXRANDET_STAT) ? AL_TRUE : AL_FALSE);
+}
+
+void al_serdes_tx_advanced_params_set(struct al_serdes_obj		*obj,
+				      enum al_serdes_group		grp,
+				      enum al_serdes_lane		lane,
+				      struct al_serdes_adv_tx_params	*params)
+{
+	uint8_t reg = 0;
+
+	if(!params->override) {
+		al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
+			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN,
+			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN);
+
+		return;
+	}
+
+	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
+			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN,
+			0);
+
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_TX_DRV_1_HLEV_MASK,
+			 SERDES_IREG_TX_DRV_1_HLEV_SHIFT,
+			 params->amp);
+
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_TX_DRV_1_LEVN_MASK,
+			 SERDES_IREG_TX_DRV_1_LEVN_SHIFT,
+			 params->total_driver_units);
+
+	al_serdes_grp_lane_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_TX_DRV_1_REG_NUM,
+				reg);
+
+	reg = 0;
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_TX_DRV_2_LEVNM1_MASK,
+			 SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT,
+			 params->c_plus_1);
+
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_TX_DRV_2_LEVNM2_MASK,
+			 SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT,
+			 params->c_plus_2);
+
+	al_serdes_grp_lane_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_TX_DRV_2_REG_NUM,
+				reg);
+
+	reg = 0;
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_TX_DRV_3_LEVNP1_MASK,
+			 SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT,
+			 params->c_minus_1);
+
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_TX_DRV_3_SLEW_MASK,
+			 SERDES_IREG_TX_DRV_3_SLEW_SHIFT,
+			 params->slew_rate);
+
+	al_serdes_grp_lane_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_TX_DRV_3_REG_NUM,
+				reg);
+
+}
+
+void al_serdes_tx_advanced_params_get(struct al_serdes_obj	     	*obj,
+				      enum al_serdes_group	      	grp,
+				      enum al_serdes_lane		lane,
+				      struct al_serdes_adv_tx_params *tx_params)
+{
+	uint8_t reg_val = 0;
+
+	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_TX_DRV_1_REG_NUM,
+			&reg_val);
+	tx_params->amp = (reg_val & SERDES_IREG_TX_DRV_1_HLEV_MASK) >>
+				SERDES_IREG_TX_DRV_1_HLEV_SHIFT;
+	tx_params->total_driver_units = (reg_val &
+					SERDES_IREG_TX_DRV_1_LEVN_MASK) >>
+					SERDES_IREG_TX_DRV_1_LEVN_SHIFT;
+
+	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_TX_DRV_2_REG_NUM,
+			&reg_val);
+	tx_params->c_plus_1 = (reg_val & SERDES_IREG_TX_DRV_2_LEVNM1_MASK) >>
+				SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT;
+	tx_params->c_plus_2 = (reg_val & SERDES_IREG_TX_DRV_2_LEVNM2_MASK) >>
+				SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT;
+
+	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_TX_DRV_3_REG_NUM,
+			&reg_val);
+	tx_params->c_minus_1 = (reg_val & SERDES_IREG_TX_DRV_3_LEVNP1_MASK) >>
+				SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT;
+	tx_params->slew_rate = (reg_val & SERDES_IREG_TX_DRV_3_SLEW_MASK) >>
+				SERDES_IREG_TX_DRV_3_SLEW_SHIFT;
+
+	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM,
+			&reg_val);
+	tx_params->override = ((reg_val & SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN) == 0);
+}
+
+
+void al_serdes_rx_advanced_params_set(struct al_serdes_obj	      *obj,
+				      enum al_serdes_group	      grp,
+				      enum al_serdes_lane	      lane,
+				      struct al_serdes_adv_rx_params  *params)
+{
+	uint8_t reg = 0;
+
+	if(!params->override) {
+		al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM,
+			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN,
+			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN);
+
+		return;
+	}
+
+	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM,
+			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN,
+			0);
+
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK,
+			 SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT,
+			 params->dcgain);
+
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK,
+			 SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT,
+			 params->dfe_3db_freq);
+
+	al_serdes_grp_lane_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_RX_CALEQ_1_REG_NUM,
+				reg);
+
+	reg = 0;
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK,
+			 SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT,
+			 params->dfe_gain);
+
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK,
+			 SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT,
+			 params->dfe_first_tap_ctrl);
+
+	al_serdes_grp_lane_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_RX_CALEQ_2_REG_NUM,
+				reg);
+
+	reg = 0;
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK,
+			 SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT,
+			 params->dfe_secound_tap_ctrl);
+
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK,
+			 SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT,
+			 params->dfe_third_tap_ctrl);
+
+	al_serdes_grp_lane_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_RX_CALEQ_3_REG_NUM,
+				reg);
+
+	reg = 0;
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK,
+			 SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT,
+			 params->dfe_fourth_tap_ctrl);
+
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK,
+			 SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT,
+			 params->low_freq_agc_gain);
+
+	al_serdes_grp_lane_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_RX_CALEQ_4_REG_NUM,
+				reg);
+
+	reg = 0;
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK,
+			 SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT,
+			 params->precal_code_sel);
+
+	AL_REG_FIELD_SET(reg,
+			 SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK,
+			 SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT,
+			 params->high_freq_agc_boost);
+
+	al_serdes_grp_lane_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_RX_CALEQ_5_REG_NUM,
+				reg);
+}
+
+static inline void al_serdes_common_cfg_eth(struct al_serdes_group_info *grp_info)
+{
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_REG_NUM,
+				SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_MASK,
+				(0x1 << SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_REG_NUM,
+				SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_MASK,
+				(0 << SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_REG_NUM,
+				SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_MASK,
+				(0x2 << SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_REG_NUM,
+				SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_MASK,
+				(0 << SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXEQ_COARSE_STEP_REG_NUM,
+				SERDES_IREG_FLD_RXEQ_COARSE_STEP_MASK,
+				(0x1 << SERDES_IREG_FLD_RXEQ_COARSE_STEP_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_REG_NUM,
+				SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_MASK,
+				(0x1 << SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_REG_NUM,
+				SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_MASK,
+				(0xf0 << SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_REG_NUM,
+				SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_MASK,
+				(0 << SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXEQ_FINE_STEP_REG_NUM,
+				SERDES_IREG_FLD_RXEQ_FINE_STEP_MASK,
+				(1 << SERDES_IREG_FLD_RXEQ_FINE_STEP_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_REG_NUM,
+				SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_MASK,
+				(0x8 << SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_REG_NUM,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_MASK,
+				(0 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_REG_NUM,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_MASK,
+				(0x64 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_MASK,
+				(0x3 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_MASK,
+				(0x1 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_MASK,
+				(3 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_MASK,
+				(1 << SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM,
+				SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_MASK,
+				(0xc << SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_SHIFT));
+
+	al_serdes_grp_reg_masked_write(
+				grp_info,
+				AL_SRDS_REG_PAGE_4_COMMON,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM,
+				SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_MASK,
+				(0xcc << SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_SHIFT));
+}
+
+struct al_serdes_mode_rx_tx_inv_state {
+	al_bool		restore;
+	uint32_t	pipe_rst;
+	uint32_t	ipd_multi[AL_SRDS_NUM_LANES];
+	uint8_t		inv_value[AL_SRDS_NUM_LANES];
+};
+
+static void al_serdes_mode_rx_tx_inv_state_save(
+	struct al_serdes_group_info		*grp_info,
+	struct al_serdes_mode_rx_tx_inv_state	*state)
+{
+	if (al_reg_read32(&grp_info->regs_base->gen.irst) & SERDES_GEN_IRST_POR_B_A) {
+		int i;
+
+		state->restore = AL_TRUE;
+		state->pipe_rst = al_reg_read32(&grp_info->regs_base->gen.irst);
+
+		for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
+			state->inv_value[i] = al_serdes_grp_reg_read(
+				grp_info,
+				i,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_POLARITY_RX_REG_NUM);
+			state->ipd_multi[i] =
+				al_reg_read32(&grp_info->regs_base->lane[i].ipd_multi);
+		}
+	} else {
+		state->restore = AL_FALSE;
+	}
+}
+
+static void al_serdes_mode_rx_tx_inv_state_restore(
+	struct al_serdes_group_info		*grp_info,
+	struct al_serdes_mode_rx_tx_inv_state	*state)
+{
+	if (state->restore) {
+		int i;
+
+		for (i = 0; i < AL_SRDS_NUM_LANES; i++) {
+			al_serdes_grp_reg_write(
+				grp_info,
+				i,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_POLARITY_RX_REG_NUM,
+				state->inv_value[i]);
+			al_reg_write32(
+				&grp_info->regs_base->lane[i].ipd_multi, state->ipd_multi[i]);
+			al_reg_write32_masked(
+				&grp_info->regs_base->gen.irst,
+				(SERDES_GEN_IRST_PIPE_RST_L0_B_A_SEL >> i) |
+				(SERDES_GEN_IRST_PIPE_RST_L0_B_A >> i),
+				state->pipe_rst);
+		}
+	}
+}
+
+void al_serdes_mode_set_sgmii(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp)
+{
+	struct al_serdes_group_info *grp_info;
+	struct al_serdes_mode_rx_tx_inv_state rx_tx_inv_state;
+
+	al_assert(obj);
+	al_assert(((int)grp) >= AL_SRDS_GRP_A);
+	al_assert(((int)grp) <= AL_SRDS_GRP_D);
+
+	grp_info = &obj->grp_info[grp];
+
+	al_serdes_mode_rx_tx_inv_state_save(grp_info, &rx_tx_inv_state);
+
+	al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
+	al_reg_write32(&grp_info->regs_base->lane[0].ictl_multi, 0x10110010);
+	al_reg_write32(&grp_info->regs_base->lane[1].ictl_multi, 0x10110010);
+	al_reg_write32(&grp_info->regs_base->lane[2].ictl_multi, 0x10110010);
+	al_reg_write32(&grp_info->regs_base->lane[3].ictl_multi, 0x10110010);
+	al_reg_write32(&grp_info->regs_base->gen.ipd_multi_synth , 0x0001);
+	al_reg_write32(&grp_info->regs_base->lane[0].ipd_multi, 0x0003);
+	al_reg_write32(&grp_info->regs_base->lane[1].ipd_multi, 0x0003);
+	al_reg_write32(&grp_info->regs_base->lane[2].ipd_multi, 0x0003);
+	al_reg_write32(&grp_info->regs_base->lane[3].ipd_multi, 0x0003);
+	al_reg_write32(&grp_info->regs_base->gen.ictl_pcs , 0);
+	al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
+	al_serdes_ns_delay(800);
+	al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
+	al_serdes_ns_delay(500);
+	al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
+	al_serdes_ns_delay(500);
+
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 101, 183);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 102, 183);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 103, 12);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 104, 12);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 105, 26);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 106, 26);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 107, 2);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 108, 2);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 109, 17);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 110, 13);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 101, 153);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 102, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 103, 108);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 104, 183);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 105, 183);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 106, 12);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 107, 12);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 108, 26);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 109, 26);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 110, 7);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 111, 12);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 112, 8);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 113, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 114, 8);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 115, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 116, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 117, 179);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 118, 246);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 119, 208);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 120, 239);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 121, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 122, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 123, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 124, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 125, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 126, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 127, 211);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 128, 211);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 129, 226);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 130, 239);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 131, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 132, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 133, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 134, 239);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 135, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 136, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 137, 211);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 138, 211);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 139, 226);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 140, 239);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 141, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 142, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 143, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 144, 239);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 145, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 146, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 147, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 148, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 149, 63);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 150, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 151, 100);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 152, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 153, 4);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 154, 2);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 155, 5);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 156, 5);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 157, 4);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 158, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 159, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 160, 8);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 161, 4);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 162, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 163, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 164, 4);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0_LANE_0,
+		AL_SRDS_REG_TYPE_PMA, 7, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_1_LANE_1,
+		AL_SRDS_REG_TYPE_PMA, 7, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_2_LANE_2,
+		AL_SRDS_REG_TYPE_PMA, 7, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_3_LANE_3,
+		AL_SRDS_REG_TYPE_PMA, 7, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 13, 16);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 48, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 49, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 54, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 55, 180);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 93, 2);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 165, 3);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 41, 6);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 354, 3);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 355, 58);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 356, 9);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 357, 3);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 358, 62);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 359, 12);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 701, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 87, 0x1f);
+
+	al_serdes_common_cfg_eth(grp_info);
+
+	al_serdes_mode_rx_tx_inv_state_restore(grp_info, &rx_tx_inv_state);
+
+	al_reg_write32(&grp_info->regs_base->gen.irst, 0x0011F0);
+	al_serdes_ns_delay(500);
+}
+
+void al_serdes_mode_set_kr(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp)
+{
+	struct al_serdes_group_info *grp_info;
+	struct al_serdes_mode_rx_tx_inv_state rx_tx_inv_state;
+
+	al_assert(obj);
+	al_assert(((int)grp) >= AL_SRDS_GRP_A);
+	al_assert(((int)grp) <= AL_SRDS_GRP_D);
+
+	grp_info = &obj->grp_info[grp];
+
+	al_serdes_mode_rx_tx_inv_state_save(grp_info, &rx_tx_inv_state);
+
+	al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
+	al_reg_write32(&grp_info->regs_base->lane[0].ictl_multi, 0x30330030);
+	al_reg_write32(&grp_info->regs_base->lane[1].ictl_multi, 0x30330030);
+	al_reg_write32(&grp_info->regs_base->lane[2].ictl_multi, 0x30330030);
+	al_reg_write32(&grp_info->regs_base->lane[3].ictl_multi, 0x30330030);
+	al_reg_write32(&grp_info->regs_base->gen.ipd_multi_synth , 0x0001);
+	al_reg_write32(&grp_info->regs_base->lane[0].ipd_multi, 0x0003);
+	al_reg_write32(&grp_info->regs_base->lane[1].ipd_multi, 0x0003);
+	al_reg_write32(&grp_info->regs_base->lane[2].ipd_multi, 0x0003);
+	al_reg_write32(&grp_info->regs_base->lane[3].ipd_multi, 0x0003);
+	al_reg_write32(&grp_info->regs_base->gen.ictl_pcs , 0);
+	al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
+	al_serdes_ns_delay(800);
+	al_reg_write32(&grp_info->regs_base->gen.irst, 0x000000);
+	al_serdes_ns_delay(500);
+	al_reg_write32(&grp_info->regs_base->gen.irst, 0x001000);
+	al_serdes_ns_delay(500);
+
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 101, 189);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 102, 189);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 103, 6);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 104, 6);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 105, 27);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 106, 27);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 107, 1);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 108, 1);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 109, 119);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 110, 5);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 101, 170);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 102, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 103, 108);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 104, 189);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 105, 189);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 106, 6);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 107, 6);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 108, 27);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 109, 27);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 110, 7);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 111, 12);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 112, 16);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 113, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 114, 16);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 115, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 116, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 117, 179);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 118, 246);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 119, 208);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 120, 239);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 121, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 122, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 123, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 124, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 125, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 126, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 127, 211);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 128, 211);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 129, 226);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 130, 239);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 131, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 132, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 133, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 134, 239);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 135, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 136, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 137, 211);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 138, 211);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 139, 226);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 140, 239);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 141, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 142, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 143, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 144, 239);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 145, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 146, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 147, 251);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 148, 255);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 149, 63);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 150, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 151, 50);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 152, 17);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 153, 2);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 154, 1);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 155, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 156, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 157, 4);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 158, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 159, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 160, 8);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 161, 4);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 162, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 163, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 164, 4);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0_LANE_0,
+		AL_SRDS_REG_TYPE_PMA, 7, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_1_LANE_1,
+		AL_SRDS_REG_TYPE_PMA, 7, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_2_LANE_2,
+		AL_SRDS_REG_TYPE_PMA, 7, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_3_LANE_3,
+		AL_SRDS_REG_TYPE_PMA, 7, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 13, 16);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 48, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 49, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 54, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 55, 149); /*Was 182*/
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 93, 2);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 165, 3);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 41, 6);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 354, 3);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 355, 58);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 356, 9);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 357, 3);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 358, 62);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON,
+		AL_SRDS_REG_TYPE_PMA, 359, 12);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 701, 0);
+	al_serdes_grp_reg_write(grp_info, AL_SRDS_REG_PAGE_0123_LANES_0123,
+		AL_SRDS_REG_TYPE_PMA, 87, 0x1f);
+
+	al_serdes_common_cfg_eth(grp_info);
+
+	al_serdes_mode_rx_tx_inv_state_restore(grp_info, &rx_tx_inv_state);
+
+	al_reg_write32(&grp_info->regs_base->gen.irst, 0x0011F0);
+	al_serdes_ns_delay(500);
+}
+
+void al_serdes_rx_advanced_params_get(struct al_serdes_obj           *obj,
+				      enum al_serdes_group	      grp,
+				      enum al_serdes_lane	      lane,
+				      struct al_serdes_adv_rx_params* rx_params)
+{
+	uint8_t temp_val;
+
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_RX_CALEQ_1_REG_NUM,
+			&temp_val);
+	rx_params->dcgain = (temp_val & SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK) >>
+				SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT;
+	rx_params->dfe_3db_freq = (temp_val &
+				SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK) >>
+				SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT;
+
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_RX_CALEQ_2_REG_NUM,
+			&temp_val);
+	rx_params->dfe_gain = (temp_val &
+				SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK) >>
+				SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT;
+	rx_params->dfe_first_tap_ctrl = (temp_val &
+			SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK) >>
+			SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT;
+
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_RX_CALEQ_3_REG_NUM,
+			&temp_val);
+	rx_params->dfe_secound_tap_ctrl = (temp_val &
+			SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK) >>
+			SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT;
+	rx_params->dfe_third_tap_ctrl = (temp_val &
+			SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK) >>
+			SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT;
+
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_RX_CALEQ_4_REG_NUM,
+			&temp_val);
+	rx_params->dfe_fourth_tap_ctrl = (temp_val &
+			SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK) >>
+			SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT;
+	rx_params->low_freq_agc_gain = (temp_val &
+			SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK) >>
+			SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT;
+
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_RX_CALEQ_5_REG_NUM,
+			&temp_val);
+	rx_params->precal_code_sel = (temp_val &
+			SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK) >>
+			SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT;
+	rx_params->high_freq_agc_boost = (temp_val &
+			SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK) >>
+			SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT;
+
+	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM,
+			&temp_val);
+	rx_params->override = ((temp_val & SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN) == 0);
+}
+
+#if (	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM != \
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM || \
+	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM != \
+		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM)
+#error Wrong assumption
+#endif
+int al_serdes_rx_equalization(
+		struct al_serdes_obj *obj,
+		enum al_serdes_group grp,
+		enum al_serdes_lane  lane)
+{
+	uint8_t serdes_ireg_fld_rxcalroamyadjust_locwren_val;
+	uint8_t serdes_ireg_fld_rxroam_xorbitsel_val;
+	uint8_t serdes_ireg_fld_pcsrxeq_locwren_val;
+	uint8_t serdes_ireg_fld_rxcal_locwren_val;
+	uint8_t temp_val;
+	uint8_t done;
+
+	int test_score;
+	int i;
+
+	/*
+	 * Make sure Roam Eye mechanism is not overridden
+	 * Lane SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN = 1,
+	 * 	so Rx 4-Point Eye process is not overridden
+	 * Lane SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN = 1,
+	 * 	so Eye Roam latch is not overridden
+	 * Lane SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN = 1,
+	 * 	so Eye Roam latch 'X adjust' is not overridden
+	 * Lane SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN = 1,
+	 * 	so Eye Roam latch 'Y adjust' is not overridden
+	 * Lane SERDES_IREG_FLD_RXROAM_XORBITSEL = 0/1,
+	 * 	so Eye Roamlatch works on the right Eye position (XORBITSEL)
+	 * 	For most cases 0 is needed, but sometimes 1 is needed.
+	 * 	I couldn't sort out why is this so the code uses a global
+	 *      XORBITSELmode variable, set by the user (GUI). Default is 0.
+	 * control must be internal. At the end we restore original setting
+	 */
+
+	/* save current values for restoring them later in the end */
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
+			&serdes_ireg_fld_rxcal_locwren_val);
+
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
+			&serdes_ireg_fld_rxcalroamyadjust_locwren_val );
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
+			&serdes_ireg_fld_rxroam_xorbitsel_val );
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM,
+			&serdes_ireg_fld_pcsrxeq_locwren_val );
+
+	/*
+	 * Set Bits:
+	 * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN
+	 * SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN
+	 * SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
+	 * to return 4pt-RxEye and EyeRoam Latch to internal logic
+	 *
+	 * clear bit SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN
+	 * AGC/DFE controlled via PMA registers
+	 */
+	temp_val  = serdes_ireg_fld_rxcal_locwren_val;
+	temp_val |= SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN;
+	temp_val |= SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN;
+	temp_val |= SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN;
+	temp_val |= SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN;
+
+	al_serdes_lane_write(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
+			temp_val );
+
+	/*
+	 * Set bit SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN
+	 * to return EyeRoam Latch Y to internal logic
+	 */
+	temp_val = serdes_ireg_fld_rxcalroamyadjust_locwren_val |
+			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN;
+	al_serdes_lane_write(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
+			temp_val );
+
+	/*
+	 * Clear Bit: SERDES_IREG_FLD_RXROAM_XORBITSEL
+	 * so XORBITSEL=0, needed for the Eye mapping.
+	 */
+	temp_val = serdes_ireg_fld_rxroam_xorbitsel_val &
+			~SERDES_IREG_FLD_RXROAM_XORBITSEL;
+	al_serdes_lane_write(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
+			temp_val );
+
+	/*
+	 * Take Control from int.pin over RxEQ process.
+	 * Clear Bit SERDES_IREG_FLD_PCSRXEQ_LOCWREN
+	 * to override RxEQ via PMA
+	 */
+	temp_val = serdes_ireg_fld_pcsrxeq_locwren_val &
+			~SERDES_IREG_FLD_PCSRXEQ_LOCWREN;
+	al_serdes_lane_write(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM,
+			temp_val );
+
+
+	/*
+	 * Start/Stop RxEQ Cal is via PCSRXEQ_START: 1=START. 0=STOP.
+	 * Clear Bit SERDES_IREG_FLD_PCSRXEQ_START
+	 * to start fresh from Stop
+	 */
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
+			&temp_val );
+	temp_val &= ~SERDES_IREG_FLD_PCSRXEQ_START;
+	al_serdes_lane_write(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
+			temp_val );
+
+	/* Set Bit SERDES_IREG_FLD_PCSRXEQ_START
+	 * to begin Rx Eq Cal */
+	temp_val |= SERDES_IREG_FLD_PCSRXEQ_START;
+	al_serdes_lane_write(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
+			temp_val );
+
+	/* Poll on RxEq Cal completion. SERDES_IREG_FLD_RXEQ_DONE. 1=Done. */
+	for( i = 0; i < AL_SERDES_RX_EQUAL_TRIES; ++i ) {
+		al_serdes_lane_read(
+				obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM,
+				&done );
+		done &= SERDES_IREG_FLD_RXEQ_DONE;
+
+		/* Check if RxEQ Cal is done */
+		if (done)
+			break;
+		al_msleep(AL_SERDES_RX_EQUAL_MDELAY);
+	}
+
+	if (!done) {
+		al_err("%s: Timeout!\n", __func__);
+		return -1;
+	}
+
+	/* Stop the RxEQ process. */
+	temp_val &= ~SERDES_IREG_FLD_PCSRXEQ_START;
+	al_serdes_lane_write(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM,
+			temp_val );
+	/* Get score */
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_RXEQ_BEST_EYE_MSB_VAL_REG_NUM,
+			&temp_val );
+	test_score = (int)( (temp_val & 0xFF) << 6 );
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_REG_NUM,
+			&temp_val );
+	test_score += (int)(temp_val & SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_MASK);
+
+	/* Restore start values */
+	al_serdes_lane_write(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
+			serdes_ireg_fld_rxcal_locwren_val);
+	al_serdes_lane_write(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
+			serdes_ireg_fld_rxcalroamyadjust_locwren_val );
+	al_serdes_lane_write(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
+			serdes_ireg_fld_rxroam_xorbitsel_val );
+	al_serdes_lane_write(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM,
+			serdes_ireg_fld_pcsrxeq_locwren_val );
+
+	return test_score;
+}
+
+#if (	SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM != \
+		SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM || \
+	SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM != \
+		SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM || \
+	SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM != \
+		SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM)
+#error Wrong assumption
+#endif
+int al_serdes_calc_eye_size(
+		struct al_serdes_obj *obj,
+		enum al_serdes_group grp,
+		enum al_serdes_lane  lane,
+		int*                 width,
+		int*                 height)
+{
+	uint8_t rxcaleyediagfsm_x_y_valweight_val;
+	uint8_t rxcaleyediagfsm_xvalcoarse_val;
+	uint8_t rxcaleyediagfsm_xvalfine_val;
+	uint8_t rxcaleyediagfsm_yvalcoarse_val;
+	uint8_t rxcaleyediagfsm_yvalfine_val;
+	uint8_t rxlock2ref_locwren_val;
+	uint8_t rxcal_locwren_val;
+	uint8_t rxcalroamyadjust_locwren_val;
+	uint8_t rxlock2ref_ovren_val;
+
+	int i;
+	uint8_t status;
+	uint8_t reg_value;
+
+	/* Save Registers */
+	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM,
+			&rxlock2ref_locwren_val);
+	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
+			&rxcal_locwren_val);
+	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
+			&rxcalroamyadjust_locwren_val);
+	al_serdes_lane_read(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM,
+			&rxlock2ref_ovren_val);
+
+	al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
+			&rxcaleyediagfsm_x_y_valweight_val);
+	al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
+			&rxcaleyediagfsm_xvalcoarse_val);
+	al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
+			&rxcaleyediagfsm_xvalfine_val);
+	al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
+			&rxcaleyediagfsm_yvalcoarse_val);
+	al_serdes_reg_read(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
+			&rxcaleyediagfsm_yvalfine_val);
+
+	/*
+	 * Clear Bit:
+	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN
+	 * 	to override RxEQ via PMA
+	 * Set Bits:
+	 * 	SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN,
+	 * 	SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
+	 * 	to keep Eye Diag Roam controlled internally
+	 */
+	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN  |
+			SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN |
+			SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN,
+			SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN |
+			SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN);
+	/*
+	 * Set Bit:
+	 * 	 SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN
+	 * 	 to keep Eye Diag Roam controlled internally
+	 */
+	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
+			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN,
+			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN);
+
+	/*
+	 * Clear Bit:
+	 * 	SERDES_IREG_FLD_RXROAM_XORBITSEL,
+	 * 	so XORBITSEL=0, needed for the Eye mapping
+	 *  Set Bit:
+	 *  SERDES_IREG_FLD_RXLOCK2REF_OVREN,
+	 *  so RXLOCK2REF_OVREN=1, keeping lock to data, preventing data hit
+	 */
+	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+			lane,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM,
+			SERDES_IREG_FLD_RXLOCK2REF_OVREN |
+			SERDES_IREG_FLD_RXROAM_XORBITSEL,
+			SERDES_IREG_FLD_RXLOCK2REF_OVREN);
+
+
+	/*
+	 * Clear Bit:
+	 * 	SERDES_IREG_FLD_RXLOCK2REF_LOCWREN,
+	 * 	so RXLOCK2REF_LOCWREN=0, to override control
+	 */
+	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM,
+				SERDES_IREG_FLD_RXLOCK2REF_LOCWREN,
+				0);
+
+	/* Width Calculation */
+
+	/* Return Value = 0*Y + 1*X */
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
+			0x01);
+	/* X coarse scan step = 3 */
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
+			0x03);
+	/* X fine scan step = 1   */
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
+			0x01);
+	/* Y coarse scan step = 0 */
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
+			0x00);
+	/* Y fine scan step = 0   */
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
+			0x00);
+
+	/*
+	 * Set Bit:
+	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+	 * 	to start Eye measurement
+	 */
+	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START);
+
+	for( i = 0; i < AL_SERDES_RX_EYE_CAL_TRIES; ++i ) {
+		/* Check if RxEQ Cal is done */
+		al_serdes_lane_read(
+				obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM,
+				&status );
+		if (status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE)
+			break;
+		al_msleep(AL_SERDES_RX_EYE_CAL_MDELAY);
+	}
+
+	if (status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR) {
+		al_err("%s: eye measure error!\n", __func__);
+		return -1;
+	}
+
+	if (!(status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE)) {
+		al_err("%s: eye measure timeout!\n", __func__);
+		return -1;
+	}
+
+	/*  Read Eye Opening Metrics, Bits:
+	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB,
+	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB
+	 */
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM,
+			&reg_value );
+	*width = reg_value << 6;
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM,
+			&reg_value );
+	*width =+ reg_value & SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE;
+
+	/*
+	 * Clear Bit:
+	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+	 * 	to stop Eye measurement
+	 */
+	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+				0);
+
+	/* Height Calculation */
+
+	/* Return Value = 1*Y + 0*X */
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
+			0x10);
+	/* X coarse scan step = 0 */
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
+			0x00);
+	/* X fine scan step = 0   */
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
+			0x00);
+	/* Y coarse scan step = 3 */
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
+			0x03);
+	/* Y fine scan step = 1   */
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
+			0x01);
+
+	/*
+	 * Set Bit:
+	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+	 * 	to start Eye measurement
+	 */
+	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START);
+
+	for( i = 0; i < AL_SERDES_RX_EYE_CAL_TRIES; ++i ) {
+		/* Check if RxEQ Cal is done */
+		al_serdes_lane_read(
+				obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM,
+				&status );
+		if (status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE)
+			break;
+		al_msleep(AL_SERDES_RX_EYE_CAL_MDELAY);
+	}
+
+	if (status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR) {
+		al_err("%s: eye measure error!\n", __func__);
+		return -1;
+	}
+
+	if (!(status & SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE)) {
+		al_err("%s: eye measure timeout!\n", __func__);
+		return -1;
+	}
+
+	/*  Read Eye Opening Metrics, Bits:
+	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB,
+	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB
+	 */
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM,
+			&reg_value );
+	*height = reg_value << 6;
+	al_serdes_lane_read(
+			obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM,
+			&reg_value );
+	*height =+ reg_value & SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE;
+
+	/*
+	 * Clear Bit:
+	 * 	SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+	 * 	to stop Eye measurement
+	 */
+	al_serdes_grp_lane_masked_write(&obj->grp_info[grp],
+				lane,
+				AL_SRDS_REG_TYPE_PMA,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM,
+				SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START,
+				0);
+
+	/* Restore Registers */
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM,
+			rxcaleyediagfsm_x_y_valweight_val);
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM,
+			rxcaleyediagfsm_xvalcoarse_val);
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM,
+			rxcaleyediagfsm_xvalfine_val);
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM,
+			rxcaleyediagfsm_yvalcoarse_val);
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON,
+			AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM,
+			rxcaleyediagfsm_yvalfine_val);
+
+	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM,
+			rxlock2ref_locwren_val);
+	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM,
+			rxcal_locwren_val);
+	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM,
+			rxcalroamyadjust_locwren_val);
+	al_serdes_lane_write(obj, grp, lane, AL_SRDS_REG_TYPE_PMA,
+			SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM,
+			rxlock2ref_ovren_val);
+	return 0;
+}
+
+void al_serdes_sris_config(
+	struct al_serdes_obj		*obj,
+	enum al_serdes_group		grp,
+	struct al_serdes_sris_params	*params)
+{
+	struct al_serdes_group_info *grp_info = &obj->grp_info[grp];
+
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_PPMDRIFTCOUNT1_REG_NUM,
+		(params->ppm_drift_count & AL_FIELD_MASK(7, 0)) >> 0);
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_PPMDRIFTCOUNT2_REG_NUM,
+		(params->ppm_drift_count & AL_FIELD_MASK(15, 8)) >> 8);
+
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_PPMDRIFTMAX1_REG_NUM,
+		(params->ppm_drift_max & AL_FIELD_MASK(7, 0)) >> 0);
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_PPMDRIFTMAX2_REG_NUM,
+		(params->ppm_drift_max & AL_FIELD_MASK(15, 8)) >> 8);
+
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_SYNTHPPMDRIFTMAX1_REG_NUM,
+		(params->synth_ppm_drift_max & AL_FIELD_MASK(7, 0)) >> 0);
+	al_serdes_reg_write(obj, grp, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PMA,
+		SERDES_IREG_FLD_SYNTHPPMDRIFTMAX2_REG_NUM,
+		(params->synth_ppm_drift_max & AL_FIELD_MASK(15, 8)) >> 8);
+
+	al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
+		SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_NUM,
+		SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_MASK,
+		(params->full_d2r1)
+			<< SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_SHIFT);
+
+	al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
+		SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_NUM,
+		SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_MASK,
+		(params->full_pcie_g3)
+			<< SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_SHIFT);
+
+	al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
+		SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_NUM,
+		SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_MASK,
+		(params->rd_threshold_d2r1)
+			<< SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_SHIFT);
+
+	al_serdes_grp_reg_masked_write(grp_info, AL_SRDS_REG_PAGE_4_COMMON, AL_SRDS_REG_TYPE_PCS,
+		SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_NUM,
+		SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_MASK,
+		(params->rd_threshold_pcie_g3)
+			<< SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_SHIFT);
+}
diff --git a/sys/contrib/alpine-hal/al_hal_serdes.h b/sys/contrib/alpine-hal/al_hal_serdes.h
new file mode 100644
index 000000000000..37aec839b2f2
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_serdes.h
@@ -0,0 +1,1125 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_serdes_api API
+ * SerDes HAL driver API
+ * @ingroup group_serdes SerDes
+ * @{
+ *
+ * @file   al_hal_serdes.h
+ *
+ * @brief Header file for the SerDes HAL driver
+ *
+ */
+
+#ifndef __AL_HAL_SERDES_H__
+#define __AL_HAL_SERDES_H__
+
+#include "al_hal_common.h"
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+struct al_serdes_obj;
+
+enum al_serdes_group {
+	AL_SRDS_GRP_A = 0,
+	AL_SRDS_GRP_B,
+	AL_SRDS_GRP_C,
+	AL_SRDS_GRP_D,
+
+	AL_SRDS_NUM_GROUPS,
+};
+
+struct al_serdes_group_info {
+	/*
+	 * Group parent object - filled automatically by al_serdes_handle_init
+	 */
+	struct al_serdes_obj		*pobj;
+
+	/*
+	 * Group specific register base - filled automatically by
+	 * al_sedres_handle_init
+	 */
+	struct al_serdes_regs __iomem	*regs_base;
+};
+
+struct al_serdes_obj {
+	struct al_serdes_group_info	grp_info[AL_SRDS_NUM_GROUPS];
+};
+
+enum al_serdes_reg_page {
+	AL_SRDS_REG_PAGE_0_LANE_0 = 0,
+	AL_SRDS_REG_PAGE_1_LANE_1,
+	AL_SRDS_REG_PAGE_2_LANE_2,
+	AL_SRDS_REG_PAGE_3_LANE_3,
+	AL_SRDS_REG_PAGE_4_COMMON,
+	AL_SRDS_REG_PAGE_0123_LANES_0123 = 7,
+};
+
+enum al_serdes_reg_type {
+	AL_SRDS_REG_TYPE_PMA = 0,
+	AL_SRDS_REG_TYPE_PCS,
+};
+
+enum al_serdes_lane {
+	AL_SRDS_LANE_0 = AL_SRDS_REG_PAGE_0_LANE_0,
+	AL_SRDS_LANE_1 = AL_SRDS_REG_PAGE_1_LANE_1,
+	AL_SRDS_LANE_2 = AL_SRDS_REG_PAGE_2_LANE_2,
+	AL_SRDS_LANE_3 = AL_SRDS_REG_PAGE_3_LANE_3,
+
+	AL_SRDS_NUM_LANES,
+	AL_SRDS_LANES_0123 = AL_SRDS_REG_PAGE_0123_LANES_0123,
+};
+
+/** Serdes loopback mode */
+enum al_serdes_lb_mode {
+	/** No loopback */
+	AL_SRDS_LB_MODE_OFF,
+
+	/**
+	 * Transmits the untimed, partial equalized RX signal out the transmit
+	 * IO pins.
+	 * No clock used (untimed)
+	 */
+	AL_SRDS_LB_MODE_PMA_IO_UN_TIMED_RX_TO_TX,
+
+	/**
+	 * Loops back the TX serializer output into the CDR.
+	 * CDR recovered bit clock used (without attenuation)
+	 */
+	AL_SRDS_LB_MODE_PMA_INTERNALLY_BUFFERED_SERIAL_TX_TO_RX,
+
+	/**
+	 * Loops back the TX driver IO signal to the RX IO pins
+	 * CDR recovered bit clock used (only through IO)
+	 */
+	AL_SRDS_LB_MODE_PMA_SERIAL_TX_IO_TO_RX_IO,
+
+	/**
+	 * Parallel loopback from the PMA receive lane data ports, to the
+	 * transmit lane data ports
+	 * CDR recovered bit clock used
+	 */
+	AL_SRDS_LB_MODE_PMA_PARALLEL_RX_TO_TX,
+
+	/** Loops received data after elastic buffer to transmit path */
+	AL_SRDS_LB_MODE_PCS_PIPE,
+
+	/** Loops TX data (to PMA) to RX path (instead of PMA data) */
+	AL_SRDS_LB_MODE_PCS_NEAR_END,
+
+	/** Loops receive data prior to interface block to transmit path */
+	AL_SRDS_LB_MODE_PCS_FAR_END,
+};
+
+/** Serdes BIST pattern */
+enum al_serdes_bist_pattern {
+	AL_SRDS_BIST_PATTERN_USER,
+	AL_SRDS_BIST_PATTERN_PRBS7,
+	AL_SRDS_BIST_PATTERN_PRBS23,
+	AL_SRDS_BIST_PATTERN_PRBS31,
+	AL_SRDS_BIST_PATTERN_CLK1010,
+};
+
+/** SerDes group rate */
+enum al_serdes_rate {
+	AL_SRDS_RATE_1_8,
+	AL_SRDS_RATE_1_4,
+	AL_SRDS_RATE_1_2,
+	AL_SRDS_RATE_FULL,
+};
+
+/** SerDes power mode */
+enum al_serdes_pm {
+	AL_SRDS_PM_PD,
+	AL_SRDS_PM_P2,
+	AL_SRDS_PM_P1,
+	AL_SRDS_PM_P0S,
+	AL_SRDS_PM_P0,
+};
+
+/** SerDes PCIe Rate - values are important for proper behavior */
+enum al_serdes_pcie_rate {
+	AL_SRDS_PCIE_RATE_GEN1 = 0,
+	AL_SRDS_PCIE_RATE_GEN2,
+	AL_SRDS_PCIE_RATE_GEN3,
+};
+
+/**
+ * Initializes a SERDES object
+ *
+ * @param  serdes_regs_base
+ *             The SERDES register file base pointer
+ *
+ * @param obj
+ *             An allocated, non initialized object context
+ *
+ *
+ * @return 0 if no error found.
+ *
+ */
+int al_serdes_handle_init(
+	void __iomem		*serdes_regs_base,
+	struct al_serdes_obj	*obj);
+
+/**
+ * SERDES register read
+ *
+ * Reads a SERDES register
+ *
+ * @param  obj
+ *             The object context
+ *
+ * @param  grp
+ *             The SERDES group
+ *
+ * @param  page
+ *             The SERDES register page within the group
+ *
+ * @param  type
+ *             The SERDES register type (PMA /PCS)
+ *
+ * @param  offset
+ *             The SERDES register offset (0 - 4095)
+ *
+ * @param data
+ *             The read data
+ *
+ *
+ * @return 0 if no error found.
+ *
+ */
+int al_serdes_reg_read(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_reg_page	page,
+	enum al_serdes_reg_type	type,
+	uint16_t		offset,
+	uint8_t			*data);
+
+/**
+ * SERDES register write
+ *
+ * Writes a SERDES register
+ *
+ * @param  obj
+ *             The object context
+ *
+ * @param  grp
+ *             The SERDES group
+ *
+ * @param  page
+ *             The SERDES register page within the group
+ *
+ * @param  type
+ *             The SERDES register type (PMA /PCS)
+ *
+ * @param  offset
+ *             The SERDES register offset (0 - 4095)
+ *
+ * @param  data
+ *             The data to write
+ *
+ *
+ * @return 0 if no error found.
+ *
+ */
+int al_serdes_reg_write(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_reg_page	page,
+	enum al_serdes_reg_type	type,
+	uint16_t		offset,
+	uint8_t			data);
+
+/**
+ * Enable BIST required overrides
+ *
+ * @param	obj
+ *		The object context
+ * @param	grp
+ *		The SERDES group
+ * @param	rate
+ *		The required speed rate
+ */
+void al_serdes_bist_overrides_enable(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_rate	rate);
+
+/**
+ * Disable BIST required overrides
+ *
+ * @param	obj
+ *		The object context
+ * @param	grp
+ *		The SERDES group
+ * @param	rate
+ *		The required speed rate
+ */
+void al_serdes_bist_overrides_disable(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp);
+
+/**
+ * Rx rate change
+ *
+ * @param	obj
+ *		The object context
+ * @param	grp
+ *		The SERDES group
+ * @param	rate
+ *		The Rx required rate
+ */
+void al_serdes_rx_rate_change(
+	struct al_serdes_obj *obj,
+	enum al_serdes_group grp,
+	enum al_serdes_rate rate);
+
+/**
+ * SERDES lane Rx rate change software flow enable
+ *
+ * @param	obj
+ *		The object context
+ * @param	grp
+ *		The SERDES group
+ * @param	lane
+ *		The SERDES lane within the group
+ */
+void al_serdes_lane_rx_rate_change_sw_flow_en(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane);
+
+/**
+ * SERDES lane Rx rate change software flow disable
+ *
+ * @param	obj
+ *		The object context
+ * @param	grp
+ *		The SERDES group
+ * @param	lane
+ *		The SERDES lane within the group
+ */
+void al_serdes_lane_rx_rate_change_sw_flow_dis(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane);
+
+/**
+ * PCIe lane rate override check
+ *
+ * @param	obj
+ *		The object context
+ * @param	grp
+ *		The SERDES group
+ * @param	lane
+ *		The SERDES lane within the group
+ * @returns	AL_TRUE if the override is enabled
+ */
+al_bool al_serdes_lane_pcie_rate_override_is_enabled(
+	struct al_serdes_obj		*obj,
+	enum al_serdes_group		grp,
+	enum al_serdes_lane		lane);
+
+/**
+ * PCIe lane rate override control
+ *
+ * @param	obj
+ *		The object context
+ * @param	grp
+ *		The SERDES group
+ * @param	lane
+ *		The SERDES lane within the group
+ * @param	en
+ *		Enable/disable
+ */
+void al_serdes_lane_pcie_rate_override_enable_set(
+	struct al_serdes_obj		*obj,
+	enum al_serdes_group		grp,
+	enum al_serdes_lane		lane,
+	al_bool				en);
+
+/**
+ * PCIe lane rate get
+ *
+ * @param	obj
+ *		The object context
+ * @param	grp
+ *		The SERDES group
+ * @param	lane
+ *		The SERDES lane within the group
+ */
+enum al_serdes_pcie_rate al_serdes_lane_pcie_rate_get(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane);
+
+/**
+ * PCIe lane rate set
+ *
+ * @param	obj
+ *		The object context
+ * @param	grp
+ *		The SERDES group
+ * @param	lane
+ *		The SERDES lane within the group
+ * @param	rate
+ *		The required rate
+ */
+void al_serdes_lane_pcie_rate_set(
+	struct al_serdes_obj		*obj,
+	enum al_serdes_group		grp,
+	enum al_serdes_lane		lane,
+	enum al_serdes_pcie_rate	rate);
+
+/**
+ * SERDES group power mode control
+ *
+ * @param	obj
+ *		The object context
+ * @param	grp
+ *		The SERDES group
+ * @param	pm
+ *		The required power mode
+ */
+void al_serdes_group_pm_set(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_pm	pm);
+
+/**
+ * SERDES lane power mode control
+ *
+ * @param	obj
+ *		The object context
+ * @param	grp
+ *		The SERDES group
+ * @param	lane
+ *		The SERDES lane within the group
+ * @param	rx_pm
+ *		The required RX power mode
+ * @param	tx_pm
+ *		The required TX power mode
+ */
+void al_serdes_lane_pm_set(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	enum al_serdes_pm	rx_pm,
+	enum al_serdes_pm	tx_pm);
+
+/**
+ * SERDES group PMA hard reset
+ *
+ * Controls Serdes group PMA hard reset
+ *
+ * @param  obj
+ *             The object context
+ *
+ * @param  grp
+ *             The SERDES group
+ *
+ * @param  enable
+ *             Enable/disable hard reset
+ */
+void al_serdes_pma_hard_reset_group(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	al_bool			enable);
+
+/**
+ * SERDES lane PMA hard reset
+ *
+ * Controls Serdes lane PMA hard reset
+ *
+ * @param  obj
+ *             The object context
+ *
+ * @param  grp
+ *             The SERDES group
+ *
+ * @param  lane
+ *             The SERDES lane within the group
+ *
+ * @param  enable
+ *             Enable/disable hard reset
+ */
+void al_serdes_pma_hard_reset_lane(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	al_bool			enable);
+
+/**
+ * SERDES loopback control
+ *
+ * Controls the loopback
+ *
+ * @param  obj
+ *             The object context
+ *
+ * @param  grp
+ *             The SERDES group
+ *
+ * @param  lane
+ *             The SERDES lane within the group
+ *
+ * @param  mode
+ *             The requested loopback mode
+ *
+ */
+void al_serdes_loopback_control(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	enum al_serdes_lb_mode	mode);
+
+/**
+ * SERDES BIST pattern selection
+ *
+ * Selects the BIST pattern to be used
+ *
+ * @param  obj
+ *             The object context
+ *
+ * @param  grp
+ *             The SERDES group
+ *
+ * @param  pattern
+ *             The pattern to set
+ *
+ * @param  user_data
+ *             The pattern user data (when pattern == AL_SRDS_BIST_PATTERN_USER)
+ *             80 bits (8 bytes array)
+ *
+ */
+void al_serdes_bist_pattern_select(
+	struct al_serdes_obj		*obj,
+	enum al_serdes_group		grp,
+	enum al_serdes_bist_pattern	pattern,
+	uint8_t				*user_data);
+
+/**
+ * SERDES BIST TX Enable
+ *
+ * Enables/disables TX BIST per lane
+ *
+ * @param  obj
+ *             The object context
+ *
+ * @param  grp
+ *             The SERDES group
+ *
+ * @param  lane
+ *             The SERDES lane within the group
+ *
+ * @param  enable
+ *             Enable or disable TX BIST
+ */
+void al_serdes_bist_tx_enable(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	al_bool			enable);
+
+/**
+ * SERDES BIST TX single bit error injection
+ *
+ * Injects single bit error during a TX BIST
+ *
+ * @param  obj
+ *             The object context
+ *
+ * @param  grp
+ *             The SERDES group
+ */
+void al_serdes_bist_tx_err_inject(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp);
+
+/**
+ * SERDES BIST RX Enable
+ *
+ * Enables/disables RX BIST per lane
+ *
+ * @param  obj
+ *             The object context
+ *
+ * @param  grp
+ *             The SERDES group
+ *
+ * @param  lane
+ *             The SERDES lane within the group
+ *
+ * @param  enable
+ *             Enable or disable TX BIST
+ */
+void al_serdes_bist_rx_enable(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	al_bool			enable);
+
+/**
+ * SERDES BIST RX status
+ *
+ * Checks the RX BIST status for a specific SERDES lane
+ *
+ * @param  obj
+ *             The object context
+ *
+ * @param  grp
+ *             The SERDES group
+ *
+ * @param  lane
+ *             The SERDES lane within the group
+ *
+ * @param is_locked
+ *             An indication whether RX BIST is locked
+ *
+ * @param err_cnt_overflow
+ *             An indication whether error count overflow occured
+ *
+ * @param err_cnt
+ *             Current bit error count
+ */
+void al_serdes_bist_rx_status(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	al_bool			*is_locked,
+	al_bool			*err_cnt_overflow,
+	uint16_t		*err_cnt);
+
+/**
+ * SERDES Digital Test Bus
+ *
+ * Samples the digital test bus of a specific SERDES lane
+ *
+ * @param  obj
+ *             The object context
+ *
+ * @param  grp
+ *             The SERDES group
+ *
+ * @param  lane
+ *             The SERDES lane within the group
+ *
+ * @param  sel
+ *             The selected sampling group (0 - 31)
+ *
+ * @param sampled_data
+ *             The sampled data (5 bytes array)
+ *
+ *
+ * @return 0 if no error found.
+ *
+ */
+int al_serdes_digital_test_bus(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp,
+	enum al_serdes_lane	lane,
+	uint8_t			sel,
+	uint8_t			*sampled_data);
+
+
+/* KR link training */
+/**
+ * Set the tx de-emphasis to preset values
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ *
+ */
+void al_serdes_tx_deemph_preset(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane);
+
+/**
+ * Tx de-emphasis parameters
+ */
+enum al_serdes_tx_deemph_param {
+	AL_SERDES_TX_DEEMP_C_ZERO,	/*< c(0) */
+	AL_SERDES_TX_DEEMP_C_PLUS,	/*< c(1) */
+	AL_SERDES_TX_DEEMP_C_MINUS,	/*< c(-1) */
+};
+
+/**
+ * Increase tx de-emphasis param.
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ *
+ * @param param which tx de-emphasis to change
+ *
+ * @return false in case max is reached. true otherwise.
+ */
+al_bool al_serdes_tx_deemph_inc(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane,
+		enum al_serdes_tx_deemph_param param);
+
+/**
+ * Decrease tx de-emphasis param.
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ *
+ * @param param which tx de-emphasis to change
+ *
+ * @return false in case min is reached. true otherwise.
+ */
+al_bool al_serdes_tx_deemph_dec(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane,
+		enum al_serdes_tx_deemph_param param);
+
+/**
+ * run Rx eye measurement.
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ *
+ * @param timeout timeout in uSec
+ *
+ * @param value Rx eye measurement value
+ *		(0 - completely closed eye, 0xffff - completely open eye).
+ *
+ * @return 0 if no error found.
+ */
+int al_serdes_eye_measure_run(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane,
+		uint32_t		timeout,
+		unsigned int		*value);
+
+/**
+ * Eye diagram single sampling
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ *
+ * @param x Sampling X position (0 - 63 --> -1.00 UI ... 1.00 UI)
+ *
+ * @param y Sampling Y position (0 - 62 --> 500mV ... -500mV)
+ *
+ * @param timeout timeout in uSec
+ *
+ * @param value Eye diagram sample value (BER - 0x0000 - 0xffff)
+ *
+ * @return 0 if no error found.
+ */
+int al_serdes_eye_diag_sample(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane,
+		unsigned int		x,
+		int			y,
+		unsigned int		timeout,
+		unsigned int		*value);
+
+/**
+ * Check if signal is detected
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ *
+ * @return true if signal is detected. false otherwise.
+ */
+al_bool al_serdes_signal_is_detected(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane);
+
+
+struct al_serdes_adv_tx_params {
+	/*
+	 * select the input values location.
+	 * When set to true the values will be taken from the internal registers
+	 * that will be override with the next following parameters.
+	 * When set to false the values will be taken from external pins (the
+	 * other parameters in this case is not needed)
+	 */
+	al_bool				override;
+	/*
+	 * Transmit Amplitude control signal. Used to define the full-scale
+	 * maximum swing of the driver.
+	 *	000 - Not Supported
+	 *	001 - 952mVdiff-pkpk
+	 *	010 - 1024mVdiff-pkpk
+	 *	011 - 1094mVdiff-pkpk
+	 *	100 - 1163mVdiff-pkpk
+	 *	101 - 1227mVdiff-pkpk
+	 *	110 - 1283mVdiff-pkpk
+	 *	111 - 1331mVdiff-pkpk
+	 */
+	uint8_t				amp;
+	/* Defines the total number of driver units allocated in the driver */
+	uint8_t				total_driver_units;
+	/* Defines the total number of driver units allocated to the
+	 * first post-cursor (C+1) tap. */
+	uint8_t				c_plus_1;
+	/* Defines the total number of driver units allocated to the
+	 * second post-cursor (C+2) tap. */
+	uint8_t				c_plus_2;
+	/* Defines the total number of driver units allocated to the
+	 * first pre-cursor (C-1) tap. */
+	uint8_t				c_minus_1;
+	/* TX driver Slew Rate control:
+	 *	00 - 31ps
+	 *	01 - 33ps
+	 *	10 - 68ps
+	 *	11 - 170ps
+	 */
+	uint8_t				slew_rate;
+};
+
+struct al_serdes_adv_rx_params {
+	/*
+	 * select the input values location.
+	 * When set to true the values will be taken from the internal registers
+	 * that will be override with the next following parameters.
+	 * When set to false the values will be taken based in the equalization
+	 * results (the other parameters in this case is not needed)
+	 */
+	al_bool				override;
+	/* RX agc high frequency dc gain:
+	 *	-3'b000: -3dB
+	 *	-3'b001: -2.5dB
+	 *	-3'b010: -2dB
+	 *	-3'b011: -1.5dB
+	 *	-3'b100: -1dB
+	 *	-3'b101: -0.5dB
+	 *	-3'b110: -0dB
+	 *	-3'b111: 0.5dB
+	 */
+	uint8_t				dcgain;
+	/* DFE post-shaping tap 3dB frequency
+	 *	-3'b000: 684MHz
+	 *	-3'b001: 576MHz
+	 *	-3'b010: 514MHz
+	 *	-3'b011: 435MHz
+	 *	-3'b100: 354MHz
+	 *	-3'b101: 281MHz
+	 *	-3'b110: 199MHz
+	 *	-3'b111: 125MHz
+	 */
+	uint8_t				dfe_3db_freq;
+	/* DFE post-shaping tap gain
+	 *	0: no pulse shaping tap
+	 *	1: -24mVpeak
+	 *	2: -45mVpeak
+	 *	3: -64mVpeak
+	 *	4: -80mVpeak
+	 *	5: -93mVpeak
+	 *	6: -101mVpeak
+	 *	7: -105mVpeak
+	 */
+	uint8_t				dfe_gain;
+	/* DFE first tap gain control
+	 *	-4'b0000: +1mVpeak
+	 *	-4'b0001: +10mVpeak
+	 *	....
+	 *	-4'b0110: +55mVpeak
+	 *	-4'b0111: +64mVpeak
+	 *	-4'b1000: -1mVpeak
+	 *	-4'b1001: -10mVpeak
+	 *	....
+	 *	-4'b1110: -55mVpeak
+	 *	-4'b1111: -64mVpeak
+	 */
+	uint8_t				dfe_first_tap_ctrl;
+	/* DFE second tap gain control
+	 *	-4'b0000: +0mVpeak
+	 *	-4'b0001: +9mVpeak
+	 *	....
+	 *	-4'b0110: +46mVpeak
+	 *	-4'b0111: +53mVpeak
+	 *	-4'b1000: -0mVpeak
+	 *	-4'b1001: -9mVpeak
+	 *	....
+	 *	-4'b1110: -46mVpeak
+	 *	-4'b1111: -53mVpeak
+	 */
+	uint8_t				dfe_secound_tap_ctrl;
+	/* DFE third tap gain control
+	 *	-4'b0000: +0mVpeak
+	 *	-4'b0001: +7mVpeak
+	 *	....
+	 *	-4'b0110: +38mVpeak
+	 *	-4'b0111: +44mVpeak
+	 *	-4'b1000: -0mVpeak
+	 *	-4'b1001: -7mVpeak
+	 *	....
+	 *	-4'b1110: -38mVpeak
+	 *	-4'b1111: -44mVpeak
+	 */
+	uint8_t				dfe_third_tap_ctrl;
+	/* DFE fourth tap gain control
+	 *	-4'b0000: +0mVpeak
+	 *	-4'b0001: +6mVpeak
+	 *	....
+	 *	-4'b0110: +29mVpeak
+	 *	-4'b0111: +33mVpeak
+	 *	-4'b1000: -0mVpeak
+	 *	-4'b1001: -6mVpeak
+	 *	....
+	 *	-4'b1110: -29mVpeak
+	 *	-4'b1111: -33mVpeak
+	 */
+	uint8_t				dfe_fourth_tap_ctrl;
+	/* Low frequency agc gain (att) select
+	 *	-3'b000: Disconnected
+	 *	-3'b001: -18.5dB
+	 *	-3'b010: -12.5dB
+	 *	-3'b011: -9dB
+	 *	-3'b100: -6.5dB
+	 *	-3'b101: -4.5dB
+	 *	-3'b110: -2.9dB
+	 *	-3'b111: -1.6dB
+	 */
+	uint8_t				low_freq_agc_gain;
+	/* Provides a RX Equalizer pre-hint, prior to beginning
+	 * adaptive equalization */
+	uint8_t				precal_code_sel;
+	/* High frequency agc boost control
+	 *	Min d0: Boost ~4dB
+	 *	Max d31: Boost ~20dB
+	 */
+	uint8_t				high_freq_agc_boost;
+};
+
+/**
+ * configure tx advanced parameters
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ *
+ * @param params pointer to the tx parameters
+ */
+void al_serdes_tx_advanced_params_set(struct al_serdes_obj	      	*obj,
+				      enum al_serdes_group		grp,
+				      enum al_serdes_lane		lane,
+				      struct al_serdes_adv_tx_params  *params);
+
+/**
+ * read tx advanced parameters
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ *
+ * @param params pointer to the tx parameters
+ */
+void al_serdes_tx_advanced_params_get(struct al_serdes_obj	     	*obj,
+				      enum al_serdes_group	      	grp,
+				      enum al_serdes_lane		lane,
+				      struct al_serdes_adv_tx_params *params);
+
+/**
+ * configure rx advanced parameters
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ *
+ * @param params pointer to the rx parameters
+ */
+void al_serdes_rx_advanced_params_set(struct al_serdes_obj	      *obj,
+				      enum al_serdes_group	      grp,
+				      enum al_serdes_lane	      lane,
+				      struct al_serdes_adv_rx_params  *params);
+
+/**
+ * read rx advanced parameters
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ *
+ * @param params pointer to the rx parameters
+ */
+void al_serdes_rx_advanced_params_get(struct al_serdes_obj           *obj,
+				      enum al_serdes_group	      grp,
+				      enum al_serdes_lane	      lane,
+				      struct al_serdes_adv_rx_params* params);
+
+/**
+ *  Switch entire SerDes group to SGMII mode based on 156.25 Mhz reference clock
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ */
+void al_serdes_mode_set_sgmii(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp);
+
+/**
+ *  Switch entire SerDes group to KR mode based on 156.25 Mhz reference clock
+ *
+ * @param obj The object context
+ *
+ * @param grp The SERDES group
+ */
+void al_serdes_mode_set_kr(
+	struct al_serdes_obj	*obj,
+	enum al_serdes_group	grp);
+
+/**
+ * performs SerDes HW equalization test and update equalization parameters
+ *
+ * @param obj the object context
+ *
+ * @param grp the SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ */
+int al_serdes_rx_equalization(
+		struct al_serdes_obj	*obj,
+		enum al_serdes_group	grp,
+		enum al_serdes_lane	lane);
+
+/**
+ * performs Rx equalization and compute the width and height of the eye
+ *
+ * @param obj the object context
+ *
+ * @param grp the SERDES group
+ *
+ * @param lane The SERDES lane within the group
+ *
+ * @param width the output width of the eye
+ *
+ * @param height the output height of the eye
+ */
+int al_serdes_calc_eye_size(
+		struct al_serdes_obj *obj,
+		enum al_serdes_group grp,
+		enum al_serdes_lane  lane,
+		int*                 width,
+		int*                 height);
+
+/**
+ * SRIS parameters
+ */
+struct al_serdes_sris_params {
+	/* Controls the frequency accuracy threshold (ppm) for lock detection CDR */
+	uint16_t	ppm_drift_count;
+	/* Controls the frequency accuracy threshold (ppm) for lock detection in the CDR */
+	uint16_t	ppm_drift_max;
+	/* Controls the frequency accuracy threshold (ppm) for lock detection in PLL */
+	uint16_t	synth_ppm_drift_max;
+	/* Elastic buffer full threshold for PCIE modes: GEN1/GEN2 */
+	uint8_t		full_d2r1;
+	/* Elastic buffer full threshold for PCIE modes: GEN3 */
+	uint8_t		full_pcie_g3;
+	/* Elastic buffer midpoint threshold.
+	 * Sets the depth of the buffer while in PCIE mode, GEN1/GEN2
+	 */
+	uint8_t		rd_threshold_d2r1;
+	/* Elastic buffer midpoint threshold.
+	 * Sets the depth of the buffer while in PCIE mode, GEN3
+	 */
+	uint8_t		rd_threshold_pcie_g3;
+};
+
+/**
+ * SRIS: Separate Refclk Independent SSC (Spread Spectrum Clocking)
+ * Currently available only for PCIe interfaces.
+ * When working with local Refclk, same SRIS configuration in both serdes sides
+ * (EP and RC in PCIe interface) is required.
+ *
+ * performs SRIS configuration according to params
+ *
+ * @param obj the object context
+ *
+ * @param grp the SERDES group
+ *
+ * @param params the SRIS parameters
+ */
+void al_serdes_sris_config(
+	struct al_serdes_obj		*obj,
+	enum al_serdes_group		grp,
+	struct al_serdes_sris_params	*params);
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+}
+#endif
+
+/* *INDENT-ON* */
+#endif		/* __AL_SRDS__ */
+
+/** @} end of SERDES group */
+
diff --git a/sys/contrib/alpine-hal/al_hal_serdes_internal_regs.h b/sys/contrib/alpine-hal/al_hal_serdes_internal_regs.h
new file mode 100644
index 000000000000..8f53469bc4cf
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_serdes_internal_regs.h
@@ -0,0 +1,750 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+#ifndef __AL_SERDES_INTERNAL_REGS_H__
+#define  __AL_SERDES_INTERNAL_REGS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ * Per lane register fields
+ ******************************************************************************/
+/*
+ * RX and TX lane hard reset
+ * 0 - Hard reset is asserted
+ * 1 - Hard reset is de-asserted
+ */
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_REG_NUM			2
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_MASK			0x01
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_ASSERT		0x00
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_VAL_DEASSERT		0x01
+
+/*
+ * RX and TX lane hard reset control
+ * 0 - Hard reset is taken from the interface pins
+ * 1 - Hard reset is taken from registers
+ */
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_REG_NUM		2
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_MASK			0x02
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_IFACE		0x00
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_VAL_REGS		0x02
+
+/* RX lane power state control */
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_REG_NUM			3
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_MASK				0x1f
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_PD				0x01
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P2				0x02
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P1				0x04
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0S			0x08
+#define SERDES_IREG_FLD_LANEPCSPSTATE_RX_VAL_P0				0x10
+
+/* TX lane power state control */
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_REG_NUM			4
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_MASK				0x1f
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_PD				0x01
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P2				0x02
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P1				0x04
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0S			0x08
+#define SERDES_IREG_FLD_LANEPCSPSTATE_TX_VAL_P0				0x10
+
+/* RX lane word width */
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_REG_NUM				5
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_MASK				0x07
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_8				0x00
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_10				0x01
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_16				0x02
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_20				0x03
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_32				0x04
+#define SERDES_IREG_FLD_PCSRX_DATAWIDTH_VAL_40				0x05
+
+/* TX lane word width */
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_REG_NUM				5
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_MASK				0x70
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_8				0x00
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_10				0x10
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_16				0x20
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_20				0x30
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_32				0x40
+#define SERDES_IREG_FLD_PCSTX_DATAWIDTH_VAL_40				0x50
+
+/* RX lane rate select */
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_REG_NUM				6
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_MASK				0x07
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_8				0x00
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_4				0x01
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_2				0x02
+#define SERDES_IREG_FLD_PCSRX_DIVRATE_VAL_1_1				0x03
+
+/* TX lane rate select */
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_REG_NUM				6
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_MASK				0x70
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_8				0x00
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_4				0x10
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_2				0x20
+#define SERDES_IREG_FLD_PCSTX_DIVRATE_VAL_1_1				0x30
+
+/*
+ * PMA serial RX-to-TX loop-back enable (from AGC to IO Driver). Serial receive
+ * to transmit loopback: 0 - Disables loopback 1 - Transmits the untimed,
+ * partial equalized RX signal out the transmit IO pins
+ */
+#define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN_REG_NUM			7
+#define SERDES_IREG_FLD_LB_RX2TXUNTIMEDEN				0x10
+
+/*
+ * PMA TX-to-RX buffered serial loop-back enable (bypasses IO Driver). Serial
+ * transmit to receive buffered loopback: 0 - Disables loopback 1 - Loops back
+ * the TX serializer output into the CDR
+ */
+#define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN_REG_NUM			7
+#define SERDES_IREG_FLD_LB_TX2RXBUFTIMEDEN				0x20
+
+/*
+ * PMA TX-to-RX I/O serial loop-back enable (loop back done directly from TX to
+ * RX pads). Serial IO loopback from the transmit lane IO pins to the receive
+ * lane IO pins: 0 - Disables loopback 1 - Loops back the driver IO signal to
+ * the RX IO pins
+ */
+#define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN_REG_NUM			7
+#define SERDES_IREG_FLD_LB_TX2RXIOTIMEDEN				0x40
+
+/*
+ * PMA Parallel RX-to-TX loop-back enable. Parallel loopback from the PMA
+ * receive lane 20-bit data ports, to the transmit lane 20-bit data ports 0 -
+ * Disables loopback 1 - Loops back the 20-bit receive data port to the
+ * transmitter
+ */
+#define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN_REG_NUM			7
+#define SERDES_IREG_FLD_LB_PARRX2TXTIMEDEN				0x80
+
+/*
+ * PMA CDR recovered-clock loopback enable; asserted when PARRX2TXTIMEDEN is 1.
+ * Transmit bit clock select: 0 - Selects synthesizer bit clock for transmit 1
+ * - Selects CDR clock for transmit
+ */
+#define SERDES_IREG_FLD_LB_CDRCLK2TXEN_REG_NUM				7
+#define SERDES_IREG_FLD_LB_CDRCLK2TXEN					0x01
+
+/* Receive lane BIST enable. Active High */
+#define SERDES_IREG_FLD_PCSRXBIST_EN_REG_NUM				8
+#define SERDES_IREG_FLD_PCSRXBIST_EN					0x01
+
+/* TX lane BIST enable. Active High */
+#define SERDES_IREG_FLD_PCSTXBIST_EN_REG_NUM				8
+#define SERDES_IREG_FLD_PCSTXBIST_EN					0x02
+
+/*
+ * RX BIST completion signal 0 - Indicates test is not completed 1 - Indicates
+ * the test has completed, and will remain high until a new test is initiated
+ */
+#define SERDES_IREG_FLD_RXBIST_DONE_REG_NUM				8
+#define SERDES_IREG_FLD_RXBIST_DONE					0x04
+
+/*
+ * RX BIST error count overflow indicator. Indicates an overflow in the number
+ * of byte errors identified during the course of the test. This word is stable
+ * to sample when *_DONE_* signal has asserted
+ */
+#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW_REG_NUM		8
+#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_OVERFLOW			0x08
+
+/*
+ * RX BIST locked indicator 0 - Indicates BIST is not word locked and error
+ * comparisons have not begun yet 1 - Indicates BIST is word locked and error
+ * comparisons have begun
+ */
+#define SERDES_IREG_FLD_RXBIST_RXLOCKED_REG_NUM				8
+#define SERDES_IREG_FLD_RXBIST_RXLOCKED					0x10
+
+/*
+ * RX BIST error count word. Indicates the number of byte errors identified
+ * during the course of the test. This word is stable to sample when *_DONE_*
+ * signal has asserted
+ */
+#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_MSB_REG_NUM			9
+#define SERDES_IREG_FLD_RXBIST_ERRCOUNT_LSB_REG_NUM			10
+
+/* Tx params */
+#define SERDES_IREG_TX_DRV_1_REG_NUM					21
+#define SERDES_IREG_TX_DRV_1_HLEV_MASK					0x7
+#define SERDES_IREG_TX_DRV_1_HLEV_SHIFT					0
+#define SERDES_IREG_TX_DRV_1_LEVN_MASK					0xf8
+#define SERDES_IREG_TX_DRV_1_LEVN_SHIFT					3
+
+#define SERDES_IREG_TX_DRV_2_REG_NUM					22
+#define SERDES_IREG_TX_DRV_2_LEVNM1_MASK				0xf
+#define SERDES_IREG_TX_DRV_2_LEVNM1_SHIFT				0
+#define SERDES_IREG_TX_DRV_2_LEVNM2_MASK				0x30
+#define SERDES_IREG_TX_DRV_2_LEVNM2_SHIFT				4
+
+#define SERDES_IREG_TX_DRV_3_REG_NUM					23
+#define SERDES_IREG_TX_DRV_3_LEVNP1_MASK				0x7
+#define SERDES_IREG_TX_DRV_3_LEVNP1_SHIFT				0
+#define SERDES_IREG_TX_DRV_3_SLEW_MASK					0x18
+#define SERDES_IREG_TX_DRV_3_SLEW_SHIFT					3
+
+/* Rx params */
+#define SERDES_IREG_RX_CALEQ_1_REG_NUM					24
+#define SERDES_IREG_RX_CALEQ_1_DCGAIN_MASK				0x7
+#define SERDES_IREG_RX_CALEQ_1_DCGAIN_SHIFT				0
+/* DFE post-shaping tap 3dB frequency */
+#define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_MASK				0x38
+#define SERDES_IREG_RX_CALEQ_1_DFEPSTAP3DB_SHIFT			3
+
+#define SERDES_IREG_RX_CALEQ_2_REG_NUM					25
+/* DFE post-shaping tap gain */
+#define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_MASK			0x7
+#define SERDES_IREG_RX_CALEQ_2_DFEPSTAPGAIN_SHIFT			0
+/* DFE first tap gain control */
+#define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_MASK				0x78
+#define SERDES_IREG_RX_CALEQ_2_DFETAP1GAIN_SHIFT			3
+
+#define SERDES_IREG_RX_CALEQ_3_REG_NUM					26
+#define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_MASK				0xf
+#define SERDES_IREG_RX_CALEQ_3_DFETAP2GAIN_SHIFT			0
+#define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_MASK				0xf0
+#define SERDES_IREG_RX_CALEQ_3_DFETAP3GAIN_SHIFT			4
+
+#define SERDES_IREG_RX_CALEQ_4_REG_NUM					27
+#define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_MASK				0xf
+#define SERDES_IREG_RX_CALEQ_4_DFETAP4GAIN_SHIFT			0
+#define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_MASK			0x70
+#define SERDES_IREG_RX_CALEQ_4_LOFREQAGCGAIN_SHIFT			4
+
+#define SERDES_IREG_RX_CALEQ_5_REG_NUM					28
+#define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_MASK			0x7
+#define SERDES_IREG_RX_CALEQ_5_PRECAL_CODE_SEL_SHIFT			0
+#define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_MASK			0xf8
+#define SERDES_IREG_RX_CALEQ_5_HIFREQAGCCAP_SHIFT			3
+
+/* RX lane best eye point measurement result */
+#define SERDES_IREG_RXEQ_BEST_EYE_MSB_VAL_REG_NUM			29
+#define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_REG_NUM			30
+#define SERDES_IREG_RXEQ_BEST_EYE_LSB_VAL_MASK				0x3F
+
+/*
+ * Adaptive RX Equalization enable
+ * 0 - Disables adaptive RX equalization.
+ * 1 - Enables adaptive RX equalization.
+ */
+#define SERDES_IREG_FLD_PCSRXEQ_START_REG_NUM				31
+#define SERDES_IREG_FLD_PCSRXEQ_START					(1 << 0)
+
+/*
+ * Enables an eye diagram measurement
+ * within the PHY.
+ * 0 - Disables eye diagram measurement
+ * 1 - Enables eye diagram measurement
+ */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START_REG_NUM			31
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_START				(1 << 1)
+
+
+/*
+ * RX lane single roam eye point measurement start signal.
+ * If asserted, single measurement at fix XADJUST and YADJUST is started.
+ */
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_REG_NUM		31
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_CYCLEEN_START		(1 << 2)
+
+
+/*
+ * PHY Eye diagram measurement status
+ * signal
+ * 0 - Indicates eye diagram results are not
+ * valid for sampling
+ * 1 - Indicates eye diagram is complete and
+ * results are valid for sampling
+ */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE_REG_NUM			32
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_DONE				(1 << 0)
+
+/*
+ * Eye diagram error signal. Indicates if the
+ * measurement was invalid because the eye
+ * diagram was interrupted by the link entering
+ * electrical idle.
+ * 0 - Indicates eye diagram is valid
+ * 1- Indicates an error occurred, and the eye
+ * diagram measurement should be re-run
+ */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR_REG_NUM			32
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_ERR				(1 << 1)
+
+/*
+ * PHY Adaptive Equalization status
+ * 0 - Indicates Adaptive Equalization results are not valid for sampling
+ * 1 - Indicates Adaptive Equalization is complete and results are valid for
+ *     sampling
+ */
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE_REG_NUM			32
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASDONE				(1 << 2)
+
+/*
+ *
+ * PHY Adaptive Equalization Status Signal
+ * 0 – Indicates adaptive equalization results
+ * are not valid for sampling
+ * 1 – Indicates adaptive equalization is
+ * complete and results are valid for sampling.
+ */
+#define SERDES_IREG_FLD_RXEQ_DONE_REG_NUM				32
+#define SERDES_IREG_FLD_RXEQ_DONE					(1 << 3)
+
+
+/*
+ * 7-bit eye diagram time adjust control
+ * - 6-bits per UI
+ * - spans 2 UI
+ */
+#define SERDES_IREG_FLD_RXCALROAMXADJUST_REG_NUM			33
+
+/* 6-bit eye diagram voltage adjust control - spans +/-300mVdiff */
+#define SERDES_IREG_FLD_RXCALROAMYADJUST_REG_NUM			34
+
+/*
+ * Eye diagram status signal. Safe for
+ * sampling when *DONE* signal has
+ * asserted
+ * 14'h0000 - Completely Closed Eye
+ * 14'hFFFF - Completely Open Eye
+ */
+#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_REG_NUM		35
+#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_MAKE			0xFF
+#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_MSB_SHIFT		0
+
+#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_REG_NUM		36
+#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_MAKE			0x3F
+#define	SERDES_IREG_FLD_RXCALEYEDIAGFSM_EYESUM_LSB_SHIFT		0
+
+/*
+ * RX lane single roam eye point measurement result.
+ * If 0, eye is open at current XADJUST and YADJUST settings.
+ */
+#define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_MSB_REG_NUM		37
+#define SERDES_IREG_FLD_RXCALROAMEYEMEAS_ACC_LSB_REG_NUM		38
+
+/*
+ * Override enable for CDR lock to reference clock
+ * 0 - CDR is always locked to reference
+ * 1 - CDR operation mode (Lock2Reference or Lock2data are controlled internally
+ *     depending on the incoming signal and ppm status)
+ */
+#define SERDES_IREG_FLD_RXLOCK2REF_OVREN_REG_NUM			39
+#define SERDES_IREG_FLD_RXLOCK2REF_OVREN				(1 << 1)
+
+/*
+ * Selects Eye to capture based on edge
+ * 0 - Capture 1st Eye in Eye Diagram
+ * 1 - Capture 2nd Eye in Eye Diagram measurement
+ */
+#define SERDES_IREG_FLD_RXROAM_XORBITSEL_REG_NUM			39
+#define SERDES_IREG_FLD_RXROAM_XORBITSEL				(1 << 2)
+#define SERDES_IREG_FLD_RXROAM_XORBITSEL_1ST				0
+#define SERDES_IREG_FLD_RXROAM_XORBITSEL_2ND				(1 << 2)
+
+/*
+ * RX Signal detect. 0 indicates no signal, 1 indicates signal detected.
+ */
+#define SERDES_IREG_FLD_RXRANDET_REG_NUM				41
+#define SERDES_IREG_FLD_RXRANDET_STAT					0x20
+
+/*
+ * RX data polarity inversion control:
+ * 1'b0: no inversion
+ * 1'b1: invert polarity
+ */
+#define SERDES_IREG_FLD_POLARITY_RX_REG_NUM				46
+#define SERDES_IREG_FLD_POLARITY_RX_INV					(1 << 0)
+
+/*
+ * TX data polarity inversion control:
+ * 1'b0: no inversion
+ * 1'b1: invert polarity
+ */
+#define SERDES_IREG_FLD_POLARITY_TX_REG_NUM				46
+#define SERDES_IREG_FLD_POLARITY_TX_INV					(1 << 1)
+
+/* LANEPCSPSTATE* override enable (Active low) */
+#define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN_REG_NUM			85
+#define SERDES_IREG_FLD_LANEPCSPSTATE_LOCWREN				(1 << 0)
+
+/* LB* override enable (Active low) */
+#define SERDES_IREG_FLD_LB_LOCWREN_REG_NUM				85
+#define SERDES_IREG_FLD_LB_LOCWREN					(1 << 1)
+
+/* PCSRX* override enable (Active low) */
+#define SERDES_IREG_FLD_PCSRX_LOCWREN_REG_NUM				85
+#define SERDES_IREG_FLD_PCSRX_LOCWREN					(1 << 4)
+
+/* PCSRXBIST* override enable (Active low) */
+#define SERDES_IREG_FLD_PCSRXBIST_LOCWREN_REG_NUM			85
+#define SERDES_IREG_FLD_PCSRXBIST_LOCWREN				(1 << 5)
+
+/* PCSRXEQ* override enable (Active low) */
+#define SERDES_IREG_FLD_PCSRXEQ_LOCWREN_REG_NUM				85
+#define SERDES_IREG_FLD_PCSRXEQ_LOCWREN					(1 << 6)
+
+/* PCSTX* override enable (Active low) */
+#define SERDES_IREG_FLD_PCSTX_LOCWREN_REG_NUM				85
+#define SERDES_IREG_FLD_PCSTX_LOCWREN					(1 << 7)
+
+/*
+ * group registers:
+ * SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN,
+ * SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN
+ * SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN
+ */
+#define SERDES_IREG_FLD_RXCAL_LOCWREN_REG_NUM				86
+
+/* PCSTXBIST* override enable (Active low) */
+#define SERDES_IREG_FLD_PCSTXBIST_LOCWREN_REG_NUM			86
+#define SERDES_IREG_FLD_PCSTXBIST_LOCWREN				(1 << 0)
+
+/* Override RX_CALCEQ through the internal registers (Active low) */
+#define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN_REG_NUM			86
+#define SERDES_IREG_FLD_RX_DRV_OVERRIDE_EN				(1 << 3)
+
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN_REG_NUM		86
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSMIN_LOCWREN			(1 << 4)
+
+
+/* RXCALROAMEYEMEASIN* override enable - Active Low */
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN_REG_NUM		86
+#define SERDES_IREG_FLD_RXCALROAMEYEMEASIN_LOCWREN			(1 << 6)
+
+/* RXCALROAMXADJUST* override enable - Active Low */
+#define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN_REG_NUM		86
+#define SERDES_IREG_FLD_RXCALROAMXADJUST_LOCWREN			(1 << 7)
+
+/* RXCALROAMYADJUST* override enable - Active Low */
+#define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN_REG_NUM		87
+#define SERDES_IREG_FLD_RXCALROAMYADJUST_LOCWREN			(1 << 0)
+
+/* RXCDRCALFOSC* override enable. Active Low */
+#define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN_REG_NUM			87
+#define SERDES_IREG_FLD_RXCDRCALFOSC_LOCWREN				(1 << 1)
+
+/* Over-write enable for RXEYEDIAGFSM_INITXVAL */
+#define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN_REG_NUM			87
+#define SERDES_IREG_FLD_RXEYEDIAGFSM_LOCWREN				(1 << 2)
+
+/* Over-write enable for CMNCLKGENMUXSEL_TXINTERNAL */
+#define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN_REG_NUM			87
+#define SERDES_IREG_FLD_RXTERMHIZ_LOCWREN				(1 << 3)
+
+/* TXCALTCLKDUTY* override enable. Active Low */
+#define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN_REG_NUM			87
+#define SERDES_IREG_FLD_TXCALTCLKDUTY_LOCWREN				(1 << 4)
+
+/* Override TX_DRV through the internal registers (Active low) */
+#define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN_REG_NUM			87
+#define SERDES_IREG_FLD_TX_DRV_OVERRIDE_EN				(1 << 5)
+
+/*******************************************************************************
+ * Common lane register fields - PMA
+ ******************************************************************************/
+/*
+ * Common lane hard reset control
+ * 0 - Hard reset is taken from the interface pins
+ * 1 - Hard reset is taken from registers
+ */
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_REG_NUM		2
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_MASK		0x01
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_IFACE	0x00
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASSEN_SYNTH_VAL_REGS	0x01
+
+/*
+ * Common lane hard reset
+ * 0 - Hard reset is asserted
+ * 1 - Hard reset is de-asserted
+ */
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_REG_NUM		2
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_MASK		0x02
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_ASSERT	0x00
+#define SERDES_IREG_FLD_CMNCTLPOR_HARDRSTBYPASS_SYNTH_VAL_DEASSERT	0x02
+
+/* Synth power state control */
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_REG_NUM			3
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_MASK				0x1f
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_PD			0x01
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P2			0x02
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P1			0x04
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0S			0x08
+#define SERDES_IREG_FLD_CMNPCSPSTATE_SYNTH_VAL_P0			0x10
+
+/* Transmit datapath FIFO enable (Active High) */
+#define SERDES_IREG_FLD_CMNPCS_TXENABLE_REG_NUM				8
+#define SERDES_IREG_FLD_CMNPCS_TXENABLE					(1 << 2)
+
+/*
+ * RX lost of signal detector enable
+ * - 0 - disable
+ * - 1 - enable
+ */
+#define SERDES_IREG_FLD_RXLOSDET_ENABLE_REG_NUM				13
+#define SERDES_IREG_FLD_RXLOSDET_ENABLE					AL_BIT(4)
+
+/* Signal Detect Threshold Level */
+#define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_REG_NUM			15
+#define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_MASK			AL_FIELD_MASK(2, 0)
+
+/* LOS Detect Threshold Level */
+#define SERDES_IREG_FLD_RXLOSDET_THRESH_REG_NUM				15
+#define SERDES_IREG_FLD_RXLOSDET_THRESH_MASK				AL_FIELD_MASK(4, 3)
+#define SERDES_IREG_FLD_RXLOSDET_THRESH_SHIFT				3
+
+#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_REG_NUM			30
+#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_MASK			0x7f
+#define SERDES_IREG_FLD_RXEQ_COARSE_ITER_NUM_SHIFT			0
+
+#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_REG_NUM			31
+#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_MASK				0x7f
+#define SERDES_IREG_FLD_RXEQ_FINE_ITER_NUM_SHIFT			0
+
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_REG_NUM			32
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_MASK			0xff
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN1_MASK_SHIFT			0
+
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_REG_NUM			33
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_MASK			0x1
+#define SERDES_IREG_FLD_RXEQ_COARSE_RUN2_MASK_SHIFT			0
+
+#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_REG_NUM			33
+#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_MASK				0x3e
+#define SERDES_IREG_FLD_RXEQ_COARSE_STEP_SHIFT				1
+
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_REG_NUM			34
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_MASK			0xff
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN1_MASK_SHIFT			0
+
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_REG_NUM			35
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_MASK			0x1
+#define SERDES_IREG_FLD_RXEQ_FINE_RUN2_MASK_SHIFT			0
+
+#define SERDES_IREG_FLD_RXEQ_FINE_STEP_REG_NUM				35
+#define SERDES_IREG_FLD_RXEQ_FINE_STEP_MASK				0x3e
+#define SERDES_IREG_FLD_RXEQ_FINE_STEP_SHIFT				1
+
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_REG_NUM			36
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_MASK			0xff
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_CODE_EN_SHIFT			0
+
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_REG_NUM			37
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_MASK			0x7
+#define SERDES_IREG_FLD_RXEQ_LOOKUP_LASTCODE_SHIFT			0
+
+#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_REG_NUM			43
+#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_MASK				0x7
+#define SERDES_IREG_FLD_RXEQ_DCGAIN_LUP0_SHIFT				0
+
+#define SERDES_IREG_FLD_TX_BIST_PAT_REG_NUM(byte_num)			(56 + (byte_num))
+#define SERDES_IREG_FLD_TX_BIST_PAT_NUM_BYTES				10
+
+/*
+ * Selects the transmit BIST mode:
+ * 0 - Uses the 80-bit internal memory pattern (w/ OOB)
+ * 1 - Uses a 27 PRBS pattern
+ * 2 - Uses a 223 PRBS pattern
+ * 3 - Uses a 231 PRBS pattern
+ * 4 - Uses a 1010 clock pattern
+ * 5 and above - Reserved
+ */
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_REG_NUM			80
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_MASK				0x07
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_USER			0x00
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS7			0x01
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS23			0x02
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_PRBS31			0x03
+#define SERDES_IREG_FLD_CMNPCSBIST_MODESEL_VAL_CLK1010			0x04
+
+/* Single-Bit error injection enable (on posedge) */
+#define SERDES_IREG_FLD_TXBIST_BITERROR_EN_REG_NUM			80
+#define SERDES_IREG_FLD_TXBIST_BITERROR_EN				0x20
+
+/* CMNPCIEGEN3* override enable (Active Low) */
+#define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN_REG_NUM			95
+#define SERDES_IREG_FLD_CMNPCIEGEN3_LOCWREN				(1 << 2)
+
+/* CMNPCS* override enable (Active Low) */
+#define SERDES_IREG_FLD_CMNPCS_LOCWREN_REG_NUM				95
+#define SERDES_IREG_FLD_CMNPCS_LOCWREN					(1 << 3)
+
+/* CMNPCSBIST* override enable (Active Low) */
+#define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN_REG_NUM			95
+#define SERDES_IREG_FLD_CMNPCSBIST_LOCWREN				(1 << 4)
+
+/* CMNPCSPSTATE* override enable (Active Low) */
+#define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN_REG_NUM			95
+#define SERDES_IREG_FLD_CMNPCSPSTATE_LOCWREN				(1 << 5)
+
+/*  PCS_EN* override enable (Active Low) */
+#define SERDES_IREG_FLD_PCS_LOCWREN_REG_NUM				96
+#define SERDES_IREG_FLD_PCS_LOCWREN					(1 << 3)
+
+/* Eye diagram sample count */
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_REG_NUM			150
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_MASK			0xff
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_MSB_SHIFT			0
+
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_REG_NUM			151
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_MASK			0xff
+#define SERDES_IREG_FLD_EYE_DIAG_SAMPLE_CNT_LSB_SHIFT			0
+
+/* override control */
+#define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN_REG_NUM			230
+#define SERDES_IREG_FLD_RXLOCK2REF_LOCWREN				1 << 0
+
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_REG_NUM		623
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_MASK		0xff
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD1_SHIFT		0
+
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_REG_NUM		624
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_MASK		0xff
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_BERTHRESHOLD2_SHIFT		0
+
+/* X and Y coefficient return value */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_X_Y_VALWEIGHT_REG_NUM		626
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_MASK			0x0F
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALWEIGHT_SHIFT		0
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_MASK			0xF0
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALWEIGHT_SHIFT		4
+
+/* X coarse scan step */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_REG_NUM		627
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_MASK			0x7F
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALCOARSE_SHIFT		0
+
+/* X fine scan step */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_REG_NUM		628
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_MASK			0x7F
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_XVALFINE_SHIFT			0
+
+/* Y coarse scan step */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_REG_NUM		629
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_MASK			0x0F
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALCOARSE_SHIFT		0
+
+/* Y fine scan step */
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_REG_NUM		630
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_MASK			0x0F
+#define SERDES_IREG_FLD_RXCALEYEDIAGFSM_YVALFINE_SHIFT			0
+
+#define SERDES_IREG_FLD_PPMDRIFTCOUNT1_REG_NUM				157
+
+#define SERDES_IREG_FLD_PPMDRIFTCOUNT2_REG_NUM				158
+
+#define SERDES_IREG_FLD_PPMDRIFTMAX1_REG_NUM				159
+
+#define SERDES_IREG_FLD_PPMDRIFTMAX2_REG_NUM				160
+
+#define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX1_REG_NUM			163
+
+#define SERDES_IREG_FLD_SYNTHPPMDRIFTMAX2_REG_NUM			164
+
+/*******************************************************************************
+ * Common lane register fields - PCS
+ ******************************************************************************/
+#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_REG_NUM			3
+#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK			AL_FIELD_MASK(5, 4)
+#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_SHIFT			4
+
+#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA_REG_NUM			6
+#define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_ENA				AL_BIT(2)
+
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_NUM			18
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_MASK			0x1F
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_D2R1_REG_SHIFT			0
+
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_NUM			19
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_MASK			0x7C
+#define SERDES_IREG_FLD_PCS_EBUF_FULL_PCIE_G3_REG_SHIFT			2
+
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_NUM		20
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_MASK		0x1F
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_D2R1_REG_SHIFT		0
+
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_NUM		21
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_MASK		0x7C
+#define SERDES_IREG_FLD_PCS_EBUF_RD_THRESHOLD_PCIE_G3_REG_SHIFT		2
+
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_REG_NUM		22
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_MASK			0x7f
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_ITER_NUM_SHIFT			0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_REG_NUM			34
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_MASK			0x7f
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_ITER_NUM_SHIFT			0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_REG_NUM		23
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_MASK			0xff
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN1_MASK_SHIFT			0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_REG_NUM		22
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_MASK			0x80
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_RUN2_MASK_SHIFT			7
+
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_REG_NUM			24
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_MASK			0x3e
+#define SERDES_IREG_FLD_PCS_RXEQ_COARSE_STEP_SHIFT			1
+
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_REG_NUM			35
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_MASK			0xff
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN1_MASK_SHIFT			0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_REG_NUM			34
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_MASK			0x80
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_RUN2_MASK_SHIFT			7
+
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_REG_NUM			36
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_MASK				0x1f
+#define SERDES_IREG_FLD_PCS_RXEQ_FINE_STEP_SHIFT			0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_REG_NUM			37
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_MASK			0xff
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_CODE_EN_SHIFT			0
+
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_REG_NUM		36
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_MASK			0xe0
+#define SERDES_IREG_FLD_PCS_RXEQ_LOOKUP_LASTCODE_SHIFT			5
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_serdes_REG_H */
+
diff --git a/sys/contrib/alpine-hal/al_hal_serdes_regs.h b/sys/contrib/alpine-hal/al_hal_serdes_regs.h
new file mode 100644
index 000000000000..1af7a918e215
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_serdes_regs.h
@@ -0,0 +1,495 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ *  @{
+ * @file   al_hal_serdes_regs.h
+ *
+ * @brief ... registers
+ *
+ */
+
+#ifndef __AL_HAL_SERDES_REGS_H__
+#define __AL_HAL_SERDES_REGS_H__
+
+#include "al_hal_plat_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+struct serdes_gen {
+	/* [0x0] SerDes Registers Version */
+	uint32_t version;
+	uint32_t rsrvd_0[3];
+	/* [0x10] SerDes register file address */
+	uint32_t reg_addr;
+	/* [0x14] SerDes register file data */
+	uint32_t reg_data;
+	uint32_t rsrvd_1[2];
+	/* [0x20] SerDes control */
+	uint32_t ictl_multi_bist;
+	/* [0x24] SerDes control */
+	uint32_t ictl_pcs;
+	/* [0x28] SerDes control */
+	uint32_t ictl_pma;
+	uint32_t rsrvd_2;
+	/* [0x30] SerDes control */
+	uint32_t ipd_multi_synth;
+	/* [0x34] SerDes control */
+	uint32_t irst;
+	/* [0x38] SerDes control */
+	uint32_t octl_multi_synthready;
+	/* [0x3c] SerDes control */
+	uint32_t octl_multi_synthstatus;
+	/* [0x40] SerDes control */
+	uint32_t clk_out;
+	uint32_t rsrvd[47];
+};
+struct serdes_lane {
+	uint32_t rsrvd1[4];
+	/* [0x10] SerDes status */
+	uint32_t octl_pma;
+	/* [0x14] SerDes control */
+	uint32_t ictl_multi_andme;
+	/* [0x18] SerDes control */
+	uint32_t ictl_multi_lb;
+	/* [0x1c] SerDes control */
+	uint32_t ictl_multi_rxbist;
+	/* [0x20] SerDes control */
+	uint32_t ictl_multi_txbist;
+	/* [0x24] SerDes control */
+	uint32_t ictl_multi;
+	/* [0x28] SerDes control */
+	uint32_t ictl_multi_rxeq;
+	/* [0x2c] SerDes control */
+	uint32_t ictl_multi_rxeq_l_low;
+	/* [0x30] SerDes control */
+	uint32_t ictl_multi_rxeq_l_high;
+	/* [0x34] SerDes control */
+	uint32_t ictl_multi_rxeyediag;
+	/* [0x38] SerDes control */
+	uint32_t ictl_multi_txdeemph;
+	/* [0x3c] SerDes control */
+	uint32_t ictl_multi_txmargin;
+	/* [0x40] SerDes control */
+	uint32_t ictl_multi_txswing;
+	/* [0x44] SerDes control */
+	uint32_t idat_multi;
+	/* [0x48] SerDes control */
+	uint32_t ipd_multi;
+	/* [0x4c] SerDes control */
+	uint32_t octl_multi_rxbist;
+	/* [0x50] SerDes control */
+	uint32_t octl_multi;
+	/* [0x54] SerDes control */
+	uint32_t octl_multi_rxeyediag;
+	/* [0x58] SerDes control */
+	uint32_t odat_multi_rxbist;
+	/* [0x5c] SerDes control */
+	uint32_t odat_multi_rxeq;
+	/* [0x60] SerDes control */
+	uint32_t multi_rx_dvalid;
+	/* [0x64] SerDes control */
+	uint32_t reserved;
+	uint32_t rsrvd[6];
+};
+
+struct al_serdes_regs {
+	uint32_t rsrvd_0[64];
+	struct serdes_gen gen;                               /* [0x100] */
+	struct serdes_lane lane[4];                          /* [0x200] */
+};
+
+
+/*
+* Registers Fields
+*/
+
+
+/**** version register ****/
+/*  Revision number (Minor) */
+#define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
+#define SERDES_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
+/*  Revision number (Major) */
+#define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
+#define SERDES_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
+/*  Date of release */
+#define SERDES_GEN_VERSION_DATE_DAY_MASK 0x001F0000
+#define SERDES_GEN_VERSION_DATE_DAY_SHIFT 16
+/*  Month of release */
+#define SERDES_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
+#define SERDES_GEN_VERSION_DATA_MONTH_SHIFT 21
+/* Year of release (starting from 2000) */
+#define SERDES_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
+#define SERDES_GEN_VERSION_DATE_YEAR_SHIFT 25
+/*  Reserved */
+#define SERDES_GEN_VERSION_RESERVED_MASK 0xC0000000
+#define SERDES_GEN_VERSION_RESERVED_SHIFT 30
+
+/**** reg_addr register ****/
+/* Address value */
+#define SERDES_GEN_REG_ADDR_VAL_MASK     0x0000FFFF
+#define SERDES_GEN_REG_ADDR_VAL_SHIFT    0
+
+/**** reg_data register ****/
+/* Data value */
+#define SERDES_GEN_REG_DATA_VAL_MASK     0x000000FF
+#define SERDES_GEN_REG_DATA_VAL_SHIFT    0
+
+/**** ICTL_MULTI_BIST register ****/
+
+#define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_MASK 0x00000007
+#define SERDES_GEN_ICTL_MULTI_BIST_MODESEL_NT_SHIFT 0
+
+/**** ICTL_PCS register ****/
+
+#define SERDES_GEN_ICTL_PCS_EN_NT        (1 << 0)
+
+/**** ICTL_PMA register ****/
+
+#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_MASK 0x00000007
+#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT 0
+
+#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_REF \
+	(0 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_R2L \
+	(3 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REF_SEL_NT_L2R \
+	(4 << (SERDES_GEN_ICTL_PMA_REF_SEL_NT_SHIFT))
+
+#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_MASK 0x00000070
+#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT 4
+
+#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_0 \
+	(0 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_REF \
+	(2 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_R2L \
+	(3 << (SERDES_GEN_ICTL_PMA_REFBUSRIGHT2LEFT_MODE_NT_SHIFT))
+
+#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_MASK 0x00000700
+#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT 8
+
+#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_0 \
+	(0 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_REF \
+	(2 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
+#define SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_L2R \
+	(3 << (SERDES_GEN_ICTL_PMA_REFBUSLEFT2RIGHT_MODE_NT_SHIFT))
+
+#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC		(1 << 11)
+#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_THIS		(0 << 11)
+#define SERDES_GEN_ICTL_PMA_TXENABLE_A_SRC_MASTER	(1 << 11)
+
+#define SERDES_GEN_ICTL_PMA_TXENABLE_A   (1 << 12)
+
+#define SERDES_GEN_ICTL_PMA_SYNTHCKBYPASSEN_NT (1 << 13)
+
+/**** IPD_MULTI_SYNTH register ****/
+
+#define SERDES_GEN_IPD_MULTI_SYNTH_B     (1 << 0)
+
+/**** IRST register ****/
+
+#define SERDES_GEN_IRST_PIPE_RST_L3_B_A  (1 << 0)
+
+#define SERDES_GEN_IRST_PIPE_RST_L2_B_A  (1 << 1)
+
+#define SERDES_GEN_IRST_PIPE_RST_L1_B_A  (1 << 2)
+
+#define SERDES_GEN_IRST_PIPE_RST_L0_B_A  (1 << 3)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A (1 << 4)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A (1 << 5)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A (1 << 6)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A (1 << 7)
+
+#define SERDES_GEN_IRST_MULTI_HARD_SYNTH_B_A (1 << 8)
+
+#define SERDES_GEN_IRST_POR_B_A          (1 << 12)
+
+#define SERDES_GEN_IRST_PIPE_RST_L3_B_A_SEL (1 << 16)
+
+#define SERDES_GEN_IRST_PIPE_RST_L2_B_A_SEL (1 << 17)
+
+#define SERDES_GEN_IRST_PIPE_RST_L1_B_A_SEL (1 << 18)
+
+#define SERDES_GEN_IRST_PIPE_RST_L0_B_A_SEL (1 << 19)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L3_B_A_SEL (1 << 20)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L2_B_A_SEL (1 << 21)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L1_B_A_SEL (1 << 22)
+
+#define SERDES_GEN_IRST_MULTI_HARD_TXRX_L0_B_A_SEL (1 << 23)
+
+/**** OCTL_MULTI_SYNTHREADY register ****/
+
+#define SERDES_GEN_OCTL_MULTI_SYNTHREADY_A (1 << 0)
+
+/**** OCTL_MULTI_SYNTHSTATUS register ****/
+
+#define SERDES_GEN_OCTL_MULTI_SYNTHSTATUS_A (1 << 0)
+
+/**** clk_out register ****/
+
+#define SERDES_GEN_CLK_OUT_SEL_MASK      0x0000003F
+#define SERDES_GEN_CLK_OUT_SEL_SHIFT     0
+
+/**** OCTL_PMA register ****/
+
+#define SERDES_LANE_OCTL_PMA_TXSTATUS_L_A (1 << 0)
+
+/**** ICTL_MULTI_ANDME register ****/
+
+#define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A (1 << 0)
+
+#define SERDES_LANE_ICTL_MULTI_ANDME_EN_L_A_SEL (1 << 1)
+
+/**** ICTL_MULTI_LB register ****/
+
+#define SERDES_LANE_ICTL_MULTI_LB_TX2RXIOTIMEDEN_L_NT (1 << 0)
+
+#define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT (1 << 1)
+
+#define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT (1 << 2)
+
+#define SERDES_LANE_ICTL_MULTI_LB_PARRX2TXTIMEDEN_L_NT (1 << 3)
+
+#define SERDES_LANE_ICTL_MULTI_LB_CDRCLK2TXEN_L_NT (1 << 4)
+
+#define SERDES_LANE_ICTL_MULTI_LB_TX2RXBUFTIMEDEN_L_NT_SEL (1 << 8)
+
+#define SERDES_LANE_ICTL_MULTI_LB_RX2TXUNTIMEDEN_L_NT_SEL (1 << 9)
+
+/**** ICTL_MULTI_RXBIST register ****/
+
+#define SERDES_LANE_ICTL_MULTI_RXBIST_EN_L_A (1 << 0)
+
+/**** ICTL_MULTI_TXBIST register ****/
+
+#define SERDES_LANE_ICTL_MULTI_TXBIST_EN_L_A (1 << 0)
+
+/**** ICTL_MULTI register ****/
+
+#define SERDES_LANE_ICTL_MULTI_PSTATE_L_MASK 0x00000003
+#define SERDES_LANE_ICTL_MULTI_PSTATE_L_SHIFT 0
+
+#define SERDES_LANE_ICTL_MULTI_PSTATE_L_SEL (1 << 2)
+
+#define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_MASK 0x00000070
+#define SERDES_LANE_ICTL_MULTI_RXDATAWIDTH_L_SHIFT 4
+
+#define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATAEN_L_A (1 << 8)
+
+#define SERDES_LANE_ICTL_MULTI_RXOVRCDRLOCK2DATA_L_A (1 << 9)
+
+#define SERDES_LANE_ICTL_MULTI_TXBEACON_L_A (1 << 12)
+
+#define SERDES_LANE_ICTL_MULTI_TXDETECTRXREQ_L_A (1 << 13)
+
+#define SERDES_LANE_ICTL_MULTI_RXRATE_L_MASK 0x00070000
+#define SERDES_LANE_ICTL_MULTI_RXRATE_L_SHIFT 16
+
+#define SERDES_LANE_ICTL_MULTI_RXRATE_L_SEL (1 << 19)
+
+#define SERDES_LANE_ICTL_MULTI_TXRATE_L_MASK 0x00700000
+#define SERDES_LANE_ICTL_MULTI_TXRATE_L_SHIFT 20
+
+#define SERDES_LANE_ICTL_MULTI_TXRATE_L_SEL (1 << 23)
+
+#define SERDES_LANE_ICTL_MULTI_TXAMP_L_MASK 0x07000000
+#define SERDES_LANE_ICTL_MULTI_TXAMP_L_SHIFT 24
+
+#define SERDES_LANE_ICTL_MULTI_TXAMP_EN_L (1 << 27)
+
+#define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_MASK 0x70000000
+#define SERDES_LANE_ICTL_MULTI_TXDATAWIDTH_L_SHIFT 28
+
+/**** ICTL_MULTI_RXEQ register ****/
+
+#define SERDES_LANE_ICTL_MULTI_RXEQ_EN_L (1 << 0)
+
+#define SERDES_LANE_ICTL_MULTI_RXEQ_START_L_A (1 << 1)
+
+#define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_MASK 0x00000070
+#define SERDES_LANE_ICTL_MULTI_RXEQ_PRECAL_CODE_SEL_SHIFT 4
+
+/**** ICTL_MULTI_RXEQ_L_high register ****/
+
+#define SERDES_LANE_ICTL_MULTI_RXEQ_L_HIGH_VAL (1 << 0)
+
+/**** ICTL_MULTI_RXEYEDIAG register ****/
+
+#define SERDES_LANE_ICTL_MULTI_RXEYEDIAG_START_L_A (1 << 0)
+
+/**** ICTL_MULTI_TXDEEMPH register ****/
+
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_MASK 0x0003FFFF
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_L_SHIFT 0
+
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_MASK	0x7c0
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_ZERO_SHIFT	6
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_MASK	0xf000
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_PLUS_SHIFT	12
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_MASK	0x7
+#define SERDES_LANE_ICTL_MULTI_TXDEEMPH_C_MINUS_SHIFT	0
+
+/**** ICTL_MULTI_TXMARGIN register ****/
+
+#define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_MASK 0x00000007
+#define SERDES_LANE_ICTL_MULTI_TXMARGIN_L_SHIFT 0
+
+/**** ICTL_MULTI_TXSWING register ****/
+
+#define SERDES_LANE_ICTL_MULTI_TXSWING_L (1 << 0)
+
+/**** IDAT_MULTI register ****/
+
+#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_MASK 0x0000000F
+#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SHIFT 0
+
+#define SERDES_LANE_IDAT_MULTI_TXELECIDLE_L_SEL (1 << 4)
+
+/**** IPD_MULTI register ****/
+
+#define SERDES_LANE_IPD_MULTI_TX_L_B     (1 << 0)
+
+#define SERDES_LANE_IPD_MULTI_RX_L_B     (1 << 1)
+
+/**** OCTL_MULTI_RXBIST register ****/
+
+#define SERDES_LANE_OCTL_MULTI_RXBIST_DONE_L_A (1 << 0)
+
+#define SERDES_LANE_OCTL_MULTI_RXBIST_RXLOCKED_L_A (1 << 1)
+
+/**** OCTL_MULTI register ****/
+
+#define SERDES_LANE_OCTL_MULTI_RXCDRLOCK2DATA_L_A (1 << 0)
+
+#define SERDES_LANE_OCTL_MULTI_RXEQ_DONE_L_A (1 << 1)
+
+#define SERDES_LANE_OCTL_MULTI_RXREADY_L_A (1 << 2)
+
+#define SERDES_LANE_OCTL_MULTI_RXSTATUS_L_A (1 << 3)
+
+#define SERDES_LANE_OCTL_MULTI_TXREADY_L_A (1 << 4)
+
+#define SERDES_LANE_OCTL_MULTI_TXDETECTRXSTAT_L_A (1 << 5)
+
+#define SERDES_LANE_OCTL_MULTI_TXDETECTRXACK_L_A (1 << 6)
+
+#define SERDES_LANE_OCTL_MULTI_RXSIGNALDETECT_L_A (1 << 7)
+
+/**** OCTL_MULTI_RXEYEDIAG register ****/
+
+#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_MASK 0x00003FFF
+#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_STAT_L_A_SHIFT 0
+
+#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_DONE_L_A (1 << 16)
+
+#define SERDES_LANE_OCTL_MULTI_RXEYEDIAG_ERR_L_A (1 << 17)
+
+/**** ODAT_MULTI_RXBIST register ****/
+
+#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_MASK 0x0000FFFF
+#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_L_A_SHIFT 0
+
+#define SERDES_LANE_ODAT_MULTI_RXBIST_ERRCOUNT_OVERFLOW_L_A (1 << 16)
+
+/**** ODAT_MULTI_RXEQ register ****/
+
+#define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_MASK 0x00003FFF
+#define SERDES_LANE_ODAT_MULTI_RXEQ_BEST_EYE_VAL_L_A_SHIFT 0
+
+/**** MULTI_RX_DVALID register ****/
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_CDR_LOCK (1 << 0)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_SIGNALDETECT (1 << 1)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_TX_READY (1 << 2)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_READY (1 << 3)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_SYNT_READY (1 << 4)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MASK_RX_ELECIDLE (1 << 5)
+
+#define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_MASK 0x00FF0000
+#define SERDES_LANE_MULTI_RX_DVALID_MUX_SEL_SHIFT 16
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_00_SEL (1 << 24)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_00_VAL (1 << 25)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_01_SEL (1 << 26)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_01_VAL (1 << 27)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_10_SEL (1 << 28)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_10_VAL (1 << 29)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_11_SEL (1 << 30)
+
+#define SERDES_LANE_MULTI_RX_DVALID_PS_11_VAL (1 << 31)
+
+/**** reserved register ****/
+
+#define SERDES_LANE_RESERVED_OUT_MASK    0x000000FF
+#define SERDES_LANE_RESERVED_OUT_SHIFT   0
+
+#define SERDES_LANE_RESERVED_IN_MASK     0x00FF0000
+#define SERDES_LANE_RESERVED_IN_SHIFT    16
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_serdes_REGS_H__ */
+
+/** @} end of ... group */
+
+
diff --git a/sys/contrib/alpine-hal/al_hal_udma.h b/sys/contrib/alpine-hal/al_hal_udma.h
new file mode 100644
index 000000000000..a1bdb4fe8dbb
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma.h
@@ -0,0 +1,672 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_udma_api API
+ * @ingroup group_udma
+ * UDMA API
+ * @{
+ * @}
+ *
+ * @defgroup group_udma_main UDMA Main
+ * @ingroup group_udma_api
+ * UDMA main API
+ * @{
+ * @file   al_hal_udma.h
+ *
+ * @brief C Header file for the Universal DMA HAL driver
+ *
+ */
+
+#ifndef __AL_HAL_UDMA_H__
+#define __AL_HAL_UDMA_H__
+
+#include "al_hal_common.h"
+#include "al_hal_udma_regs.h"
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#define DMA_MAX_Q 	4
+#define AL_UDMA_MIN_Q_SIZE 	4
+#define AL_UDMA_MAX_Q_SIZE 	(1 << 16) /* hw can do more, but we limit it */
+
+/* Default Max number of descriptors supported per action */
+#define AL_UDMA_DEFAULT_MAX_ACTN_DESCS	16
+
+#define AL_UDMA_REV_ID_0	0
+#define AL_UDMA_REV_ID_1	1
+#define AL_UDMA_REV_ID_2	2
+
+#define DMA_RING_ID_MASK	0x3
+/* New registers ?? */
+/* Statistics - TBD */
+
+/** UDMA submission descriptor */
+union al_udma_desc {
+	/* TX */
+	struct {
+		uint32_t len_ctrl;
+		uint32_t meta_ctrl;
+		uint64_t buf_ptr;
+	} tx;
+	/* TX Meta, used by upper layer */
+	struct {
+		uint32_t len_ctrl;
+		uint32_t meta_ctrl;
+		uint32_t meta1;
+		uint32_t meta2;
+	} tx_meta;
+	/* RX */
+	struct {
+		uint32_t len_ctrl;
+		uint32_t buf2_ptr_lo;
+		uint64_t buf1_ptr;
+	} rx;
+} __packed_a16;
+
+/* TX desc length and control fields */
+
+#define AL_M2S_DESC_CONCAT			AL_BIT(31)	/* concatenate */
+#define AL_M2S_DESC_DMB				AL_BIT(30)
+						/** Data Memory Barrier */
+#define AL_M2S_DESC_NO_SNOOP_H			AL_BIT(29)
+#define AL_M2S_DESC_INT_EN			AL_BIT(28)	/** enable interrupt */
+#define AL_M2S_DESC_LAST			AL_BIT(27)
+#define AL_M2S_DESC_FIRST			AL_BIT(26)
+#define AL_M2S_DESC_RING_ID_SHIFT		24
+#define AL_M2S_DESC_RING_ID_MASK		(0x3 << AL_M2S_DESC_RING_ID_SHIFT)
+#define AL_M2S_DESC_META_DATA			AL_BIT(23)
+#define AL_M2S_DESC_DUMMY			AL_BIT(22) /* for Metdata only */
+#define AL_M2S_DESC_LEN_ADJ_SHIFT		20
+#define AL_M2S_DESC_LEN_ADJ_MASK		(0x7 << AL_M2S_DESC_LEN_ADJ_SHIFT)
+#define AL_M2S_DESC_LEN_SHIFT			0
+#define AL_M2S_DESC_LEN_MASK			(0xfffff << AL_M2S_DESC_LEN_SHIFT)
+
+#define AL_S2M_DESC_DUAL_BUF			AL_BIT(31)
+#define AL_S2M_DESC_NO_SNOOP_H			AL_BIT(29)
+#define AL_S2M_DESC_INT_EN			AL_BIT(28)	/** enable interrupt */
+#define AL_S2M_DESC_RING_ID_SHIFT		24
+#define AL_S2M_DESC_RING_ID_MASK		(0x3 << AL_S2M_DESC_RING_ID_SHIFT)
+#define AL_S2M_DESC_LEN_SHIFT			0
+#define AL_S2M_DESC_LEN_MASK			(0xffff << AL_S2M_DESC_LEN_SHIFT)
+#define AL_S2M_DESC_LEN2_SHIFT			16
+#define AL_S2M_DESC_LEN2_MASK			(0x3fff << AL_S2M_DESC_LEN2_SHIFT)
+#define AL_S2M_DESC_LEN2_GRANULARITY_SHIFT	6
+
+/* TX/RX descriptor VMID field (in the buffer address 64 bit field) */
+#define AL_UDMA_DESC_VMID_SHIFT		48
+
+/** UDMA completion descriptor */
+union al_udma_cdesc {
+	/* TX completion */
+	struct {
+		uint32_t ctrl_meta;
+	} al_desc_comp_tx;
+	/* RX completion */
+	struct {
+		/* TBD */
+		uint32_t ctrl_meta;
+	} al_desc_comp_rx;
+} __packed_a4;
+
+/* TX/RX common completion desc ctrl_meta feilds */
+#define AL_UDMA_CDESC_ERROR		AL_BIT(31)
+#define AL_UDMA_CDESC_BUF1_USED		AL_BIT(30)
+#define AL_UDMA_CDESC_DDP		AL_BIT(29)
+#define AL_UDMA_CDESC_LAST		AL_BIT(27)
+#define AL_UDMA_CDESC_FIRST		AL_BIT(26)
+/* word 2 */
+#define AL_UDMA_CDESC_BUF2_USED			AL_BIT(31)
+#define AL_UDMA_CDESC_BUF2_LEN_SHIFT	16
+#define AL_UDMA_CDESC_BUF2_LEN_MASK		AL_FIELD_MASK(29, 16)
+/** Basic Buffer structure */
+struct al_buf {
+	al_phys_addr_t addr; /**< Buffer physical address */
+	uint32_t len; /**< Buffer lenght in bytes */
+};
+
+/** Block is a set of buffers that belong to same source or destination */
+struct al_block {
+	struct al_buf *bufs; /**< The buffers of the block */
+	uint32_t num; /**< Number of buffers of the block */
+
+	/**<
+	 * VMID to be assigned to the block descriptors
+	 * Requires VMID in descriptor to be enabled for the specific UDMA
+	 * queue.
+	 */
+	uint16_t vmid;
+};
+
+/** UDMA type */
+enum al_udma_type {
+	UDMA_TX,
+	UDMA_RX
+};
+
+/** UDMA state */
+enum al_udma_state {
+	UDMA_DISABLE = 0,
+	UDMA_IDLE,
+	UDMA_NORMAL,
+	UDMA_ABORT,
+	UDMA_RESET
+};
+
+extern const char *const al_udma_states_name[];
+
+/** UDMA Q specific parameters from upper layer */
+struct al_udma_q_params {
+	uint32_t size;		/**< ring size (in descriptors), submission and
+				 * completion rings must have same size
+				 */
+	union al_udma_desc *desc_base; /**< cpu address for submission ring
+					 * descriptors
+					 */
+	al_phys_addr_t desc_phy_base;	/**< submission ring descriptors
+					 * physical base address
+					 */
+#ifdef __FreeBSD__
+	bus_dma_tag_t desc_phy_base_tag;
+	bus_dmamap_t desc_phy_base_map;
+#endif
+	uint8_t *cdesc_base;	/**< completion descriptors pointer, NULL */
+				/* means no completion update */
+	al_phys_addr_t cdesc_phy_base;	/**< completion descriptors ring
+					 * physical base address
+					 */
+#ifdef __FreeBSD__
+	bus_dma_tag_t cdesc_phy_base_tag;
+	bus_dmamap_t cdesc_phy_base_map;
+#endif
+	uint32_t cdesc_size;	/**< size (in bytes) of a single dma completion
+					* descriptor
+					*/
+
+	uint8_t adapter_rev_id; /**<PCI adapter revision ID */
+};
+
+/** UDMA parameters from upper layer */
+struct al_udma_params {
+	struct unit_regs __iomem *udma_regs_base;
+	enum al_udma_type type;	/**< Tx or Rx */
+	uint8_t num_of_queues; /**< number of queues supported by the UDMA */
+	const char *name; /**< the upper layer must keep the string area */
+};
+
+/* Fordward decleration */
+struct al_udma;
+
+/** SW status of a queue */
+enum al_udma_queue_status {
+	AL_QUEUE_NOT_INITIALIZED = 0,
+	AL_QUEUE_DISABLED,
+	AL_QUEUE_ENABLED,
+	AL_QUEUE_ABORTED
+};
+
+/** UDMA Queue private data structure */
+struct __cache_aligned al_udma_q {
+	uint16_t size_mask;		/**< mask used for pointers wrap around
+					 * equals to size - 1
+					 */
+	union udma_q_regs __iomem *q_regs; /**< pointer to the per queue UDMA
+					   * registers
+					   */
+	union al_udma_desc *desc_base_ptr; /**< base address submission ring
+						* descriptors
+						*/
+	uint16_t next_desc_idx; /**< index to the next available submission
+				      * descriptor
+				      */
+
+	uint32_t desc_ring_id;	/**< current submission ring id */
+
+	uint8_t *cdesc_base_ptr;/**< completion descriptors pointer, NULL */
+				/* means no completion */
+	uint32_t cdesc_size;	/**< size (in bytes) of the udma completion ring
+				 * descriptor
+				 */
+	uint16_t next_cdesc_idx; /**< index in descriptors for next completing
+			      * ring descriptor
+			      */
+	uint8_t *end_cdesc_ptr;	/**< used for wrap around detection */
+	uint16_t comp_head_idx; /**< completion ring head pointer register
+				 *shadow
+				 */
+	volatile union al_udma_cdesc *comp_head_ptr; /**< when working in get_packet mode
+				       * we maintain pointer instead of the
+				       * above idx
+				       */
+
+	uint32_t pkt_crnt_descs; /**< holds the number of processed descriptors
+				  * of the current packet
+				  */
+	uint32_t comp_ring_id;	/**< current completion Ring Id */
+
+
+	al_phys_addr_t desc_phy_base; /**< submission desc. physical base */
+	al_phys_addr_t cdesc_phy_base; /**< completion desc. physical base */
+
+	uint32_t flags; /**< flags used for completion modes */
+	uint32_t size;		/**< ring size in descriptors  */
+	enum al_udma_queue_status status;
+	struct al_udma *udma;	/**< pointer to parent UDMA */
+	uint32_t qid;		/**< the index number of the queue */
+
+	/*
+	 * The following fields are duplicated from the UDMA parent adapter
+	 * due to performance considerations.
+	 */
+	uint8_t adapter_rev_id; /**<PCI adapter revision ID */
+};
+
+/* UDMA */
+struct al_udma {
+	const char *name;
+	enum al_udma_type type;	/* Tx or Rx */
+	enum al_udma_state state;
+	uint8_t num_of_queues; /* number of queues supported by the UDMA */
+	union udma_regs __iomem *udma_regs; /* pointer to the UDMA registers */
+	struct udma_gen_regs *gen_regs;		/* pointer to the Gen registers*/
+	struct al_udma_q udma_q[DMA_MAX_Q];	/* Array of UDMA Qs pointers */
+	unsigned int rev_id; /* UDMA revision ID */
+};
+
+
+/*
+ * Configurations
+ */
+
+/* Initializations functions */
+/**
+ * Initialize the udma engine
+ *
+ * @param udma udma data structure
+ * @param udma_params udma parameters from upper layer
+ *
+ * @return 0 on success. -EINVAL otherwise.
+ */
+int al_udma_init(struct al_udma *udma, struct al_udma_params *udma_params);
+
+/**
+ * Initialize the udma queue data structure
+ *
+ * @param udma
+ * @param qid
+ * @param q_params
+ *
+ * @return 0 if no error found.
+ *	   -EINVAL if the qid is out of range
+ *	   -EIO if queue was already initialized
+ */
+
+int al_udma_q_init(struct al_udma *udma, uint32_t qid,
+		   struct al_udma_q_params *q_params);
+
+/**
+ * Reset a udma queue
+ *
+ * Prior to calling this function make sure:
+ * 1. Queue interrupts are masked
+ * 2. No additional descriptors are written to the descriptor ring of the queue
+ * 3. No completed descriptors are being fetched
+ *
+ * The queue can be initialized again using 'al_udma_q_init'
+ *
+ * @param udma_q
+ *
+ * @return 0 if no error found.
+ */
+
+int al_udma_q_reset(struct al_udma_q *udma_q);
+
+/**
+ * return (by reference) a pointer to a specific queue date structure.
+ * this pointer needed for calling functions (i.e. al_udma_desc_action_add) that
+ * require this pointer as input argument.
+ *
+ * @param udma udma data structure
+ * @param qid queue index
+ * @param q_handle pointer to the location where the queue structure pointer
+ * written to.
+ *
+ * @return  0 on success. -EINVAL otherwise.
+ */
+int al_udma_q_handle_get(struct al_udma *udma, uint32_t qid,
+		      struct al_udma_q **q_handle);
+
+/**
+ * Change the UDMA's state
+ *
+ * @param udma udma data structure
+ * @param state the target state
+ *
+ * @return 0
+ */
+int al_udma_state_set(struct al_udma *udma, enum al_udma_state state);
+
+/**
+ * return the current UDMA hardware state
+ *
+ * @param udma udma handle
+ *
+ * @return the UDMA state as reported by the hardware.
+ */
+enum al_udma_state al_udma_state_get(struct al_udma *udma);
+
+/*
+ * Action handling
+ */
+
+/**
+ * get number of descriptors that can be submitted to the udma.
+ * keep one free descriptor to simplify full/empty management
+ * @param udma_q queue handle
+ *
+ * @return num of free descriptors.
+ */
+static INLINE uint32_t al_udma_available_get(struct al_udma_q *udma_q)
+{
+	uint16_t tmp = udma_q->next_cdesc_idx - (udma_q->next_desc_idx + 1);
+	tmp &= udma_q->size_mask;
+
+	return (uint32_t) tmp;
+}
+
+/**
+ * check if queue has pending descriptors
+ *
+ * @param udma_q queue handle
+ *
+ * @return AL_TRUE if descriptors are submitted to completion ring and still
+ * not completed (with ack). AL_FALSE otherwise.
+ */
+static INLINE al_bool al_udma_is_empty(struct al_udma_q *udma_q)
+{
+	if (((udma_q->next_cdesc_idx - udma_q->next_desc_idx) &
+	     udma_q->size_mask) == 0)
+		return AL_TRUE;
+
+	return AL_FALSE;
+}
+
+/**
+ * get next available descriptor
+ * @param udma_q queue handle
+ *
+ * @return pointer to the next available descriptor
+ */
+static INLINE union al_udma_desc *al_udma_desc_get(struct al_udma_q *udma_q)
+{
+	union al_udma_desc *desc;
+	uint16_t next_desc_idx;
+
+	al_assert(udma_q);
+
+	next_desc_idx = udma_q->next_desc_idx;
+	desc = udma_q->desc_base_ptr + next_desc_idx;
+
+	next_desc_idx++;
+
+	/* if reached end of queue, wrap around */
+	udma_q->next_desc_idx = next_desc_idx & udma_q->size_mask;
+
+	return desc;
+}
+
+/**
+ * get ring id for the last allocated descriptor
+ * @param udma_q
+ *
+ * @return ring id for the last allocated descriptor
+ * this function must be called each time a new descriptor is allocated
+ * by the al_udma_desc_get(), unless ring id is ignored.
+ */
+static INLINE uint32_t al_udma_ring_id_get(struct al_udma_q *udma_q)
+{
+	uint32_t ring_id;
+
+	al_assert(udma_q);
+
+	ring_id = udma_q->desc_ring_id;
+
+	/* calculate the ring id of the next desc */
+	/* if next_desc points to first desc, then queue wrapped around */
+	if (unlikely(udma_q->next_desc_idx) == 0)
+		udma_q->desc_ring_id = (udma_q->desc_ring_id + 1) &
+			DMA_RING_ID_MASK;
+	return ring_id;
+}
+
+/* add DMA action - trigger the engine */
+/**
+ * add num descriptors to the submission queue.
+ *
+ * @param udma_q queue handle
+ * @param num number of descriptors to add to the queues ring.
+ *
+ * @return 0;
+ */
+static INLINE int al_udma_desc_action_add(struct al_udma_q *udma_q,
+					  uint32_t num)
+{
+	uint32_t *addr;
+
+	al_assert(udma_q);
+	al_assert((num > 0) && (num <= udma_q->size));
+
+	addr = &udma_q->q_regs->rings.drtp_inc;
+	/* make sure data written to the descriptors will be visible by the */
+	/* DMA */
+	al_local_data_memory_barrier();
+
+	/*
+	 * As we explicitly invoke the synchronization function
+	 * (al_data_memory_barrier()), then we can use the relaxed version.
+	 */
+	al_reg_write32_relaxed(addr, num);
+
+	return 0;
+}
+
+#define cdesc_is_first(flags) ((flags) & AL_UDMA_CDESC_FIRST)
+#define cdesc_is_last(flags) ((flags) & AL_UDMA_CDESC_LAST)
+
+/**
+ * return pointer to the cdesc + offset desciptors. wrap around when needed.
+ *
+ * @param udma_q queue handle
+ * @param cdesc pointer that set by this function
+ * @param offset offset desciptors
+ *
+ */
+static INLINE volatile union al_udma_cdesc *al_cdesc_next(
+	struct al_udma_q		*udma_q,
+	volatile union al_udma_cdesc	*cdesc,
+	uint32_t			offset)
+{
+	volatile uint8_t *tmp = (volatile uint8_t *) cdesc + offset * udma_q->cdesc_size;
+	al_assert(udma_q);
+	al_assert(cdesc);
+
+	/* if wrap around */
+	if (unlikely((tmp > udma_q->end_cdesc_ptr)))
+		return (union al_udma_cdesc *)
+			(udma_q->cdesc_base_ptr +
+			(tmp - udma_q->end_cdesc_ptr - udma_q->cdesc_size));
+
+	return (volatile union al_udma_cdesc *) tmp;
+}
+
+/**
+ * check if the flags of the descriptor indicates that is new one
+ * the function uses the ring id from the descriptor flags to know whether it
+ * new one by comparing it with the curring ring id of the queue
+ *
+ * @param udma_q queue handle
+ * @param flags the flags of the completion descriptor
+ *
+ * @return AL_TRUE if the completion descriptor is new one.
+ * 	AL_FALSE if it old one.
+ */
+static INLINE al_bool al_udma_new_cdesc(struct al_udma_q *udma_q,
+								uint32_t flags)
+{
+	if (((flags & AL_M2S_DESC_RING_ID_MASK) >> AL_M2S_DESC_RING_ID_SHIFT)
+	    == udma_q->comp_ring_id)
+		return AL_TRUE;
+	return AL_FALSE;
+}
+
+/**
+ * get next completion descriptor
+ * this function will also increment the completion ring id when the ring wraps
+ * around
+ *
+ * @param udma_q queue handle
+ * @param cdesc current completion descriptor
+ *
+ * @return pointer to the completion descriptor that follows the one pointed by
+ * cdesc
+ */
+static INLINE volatile union al_udma_cdesc *al_cdesc_next_update(
+	struct al_udma_q		*udma_q,
+	volatile union al_udma_cdesc	*cdesc)
+{
+	/* if last desc, wrap around */
+	if (unlikely(((volatile uint8_t *) cdesc == udma_q->end_cdesc_ptr))) {
+		udma_q->comp_ring_id =
+		    (udma_q->comp_ring_id + 1) & DMA_RING_ID_MASK;
+		return (union al_udma_cdesc *) udma_q->cdesc_base_ptr;
+	}
+	return (volatile union al_udma_cdesc *) ((volatile uint8_t *) cdesc + udma_q->cdesc_size);
+}
+
+/**
+ * get next completed packet from completion ring of the queue
+ *
+ * @param udma_q udma queue handle
+ * @param desc pointer that set by this function to the first descriptor
+ * note: desc is valid only when return value is not zero
+ * @return number of descriptors that belong to the packet. 0 means no completed
+ * full packet was found.
+ * If the descriptors found in the completion queue don't form full packet (no
+ * desc with LAST flag), then this function will do the following:
+ * (1) save the number of processed descriptors.
+ * (2) save last processed descriptor, so next time it called, it will resume
+ *     from there.
+ * (3) return 0.
+ * note: the descriptors that belong to the completed packet will still be
+ * considered as used, that means the upper layer is safe to access those
+ * descriptors when this function returns. the al_udma_cdesc_ack() should be
+ * called to inform the udma driver that those descriptors are freed.
+ */
+uint32_t al_udma_cdesc_packet_get(
+	struct al_udma_q		*udma_q,
+	volatile union al_udma_cdesc	**desc);
+
+/** get completion descriptor pointer from its index */
+#define al_udma_cdesc_idx_to_ptr(udma_q, idx)				\
+	((volatile union al_udma_cdesc *) ((udma_q)->cdesc_base_ptr +	\
+				(idx) * (udma_q)->cdesc_size))
+
+
+/**
+ * return number of all completed descriptors in the completion ring
+ *
+ * @param udma_q udma queue handle
+ * @param cdesc pointer that set by this function to the first descriptor
+ * note: desc is valid only when return value is not zero
+ * note: pass NULL if not interested
+ * @return number of descriptors. 0 means no completed descriptors were found.
+ * note: the descriptors that belong to the completed packet will still be
+ * considered as used, that means the upper layer is safe to access those
+ * descriptors when this function returns. the al_udma_cdesc_ack() should be
+ * called to inform the udma driver that those descriptors are freed.
+ */
+static INLINE uint32_t al_udma_cdesc_get_all(
+	struct al_udma_q		*udma_q,
+	volatile union al_udma_cdesc	**cdesc)
+{
+	uint16_t count = 0;
+
+	al_assert(udma_q);
+
+	udma_q->comp_head_idx = (uint16_t)
+				(al_reg_read32(&udma_q->q_regs->rings.crhp) &
+						0xFFFF);
+
+	count = (udma_q->comp_head_idx - udma_q->next_cdesc_idx) &
+		udma_q->size_mask;
+
+	if (cdesc)
+		*cdesc = al_udma_cdesc_idx_to_ptr(udma_q, udma_q->next_cdesc_idx);
+
+	return (uint32_t)count;
+}
+
+/**
+ * acknowledge the driver that the upper layer completed processing completion
+ * descriptors
+ *
+ * @param udma_q udma queue handle
+ * @param num number of descriptors to acknowledge
+ *
+ * @return 0
+ */
+static INLINE int al_udma_cdesc_ack(struct al_udma_q *udma_q, uint32_t num)
+{
+	al_assert(udma_q);
+
+	udma_q->next_cdesc_idx += num;
+	udma_q->next_cdesc_idx &= udma_q->size_mask;
+
+	return 0;
+}
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+}
+#endif
+/* *INDENT-ON* */
+
+#endif /* __AL_HAL_UDMA_H__ */
+/** @} end of UDMA group */
diff --git a/sys/contrib/alpine-hal/al_hal_udma_config.c b/sys/contrib/alpine-hal/al_hal_udma_config.c
new file mode 100644
index 000000000000..a06f78983080
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_config.c
@@ -0,0 +1,1373 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @file   al_hal_udma_config.c
+ *
+ * @brief  Universal DMA HAL driver for configurations
+ *
+ */
+
+#include <al_hal_common.h>
+#include <al_hal_udma_regs.h>
+#include <al_hal_udma_config.h>
+
+/**************** Misc configurations *********************/
+/** Configure AXI generic configuration */
+int al_udma_axi_set(struct udma_gen_axi *axi_regs,
+					struct al_udma_axi_conf *axi)
+{
+        uint32_t reg;
+
+        al_reg_write32(&axi_regs->cfg_1, axi->axi_timeout);
+
+        reg = al_reg_read32(&axi_regs->cfg_2);
+        reg &= ~UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK;
+        reg |= axi->arb_promotion;
+        al_reg_write32(&axi_regs->cfg_2, reg);
+
+        reg = al_reg_read32(&axi_regs->endian_cfg);
+        if (axi->swap_8_bytes == AL_TRUE)
+                reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN;
+        else
+                reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN;
+
+        if (axi->swap_s2m_data == AL_TRUE)
+                reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA;
+        else
+                reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA;
+
+        if (axi->swap_s2m_desc == AL_TRUE)
+                reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC;
+        else
+                reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC;
+
+        if (axi->swap_m2s_data == AL_TRUE)
+                reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA;
+        else
+                reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA;
+
+        if (axi->swap_m2s_desc == AL_TRUE)
+                reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC;
+        else
+                reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC;
+
+        al_reg_write32(&axi_regs->endian_cfg, reg);
+        return 0;
+}
+
+/* Configure UDMA AXI M2S configuration */
+/** Configure AXI M2S submaster */
+static int al_udma_m2s_axi_sm_set(struct al_udma_axi_submaster *m2s_sm,
+				      uint32_t *cfg_1, uint32_t *cfg_2,
+				      uint32_t *cfg_max_beats)
+{
+	uint32_t reg;
+	reg = al_reg_read32(cfg_1);
+	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK;
+	reg |= m2s_sm->id & UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK;
+	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_MASK;
+	reg |= (m2s_sm->cache_type <<
+			UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_SHIFT) &
+		UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_MASK;
+	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_MASK;
+	reg |= (m2s_sm->burst << UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_SHIFT) &
+		UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_MASK;
+	al_reg_write32(cfg_1, reg);
+
+	reg = al_reg_read32(cfg_2);
+	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK;
+	reg |= m2s_sm->used_ext & UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK;
+	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_MASK;
+	reg |= (m2s_sm->bus_size <<
+			UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_SHIFT) &
+		UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_MASK;
+	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_MASK;
+	reg |= (m2s_sm->qos << UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_SHIFT) &
+		UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_MASK;
+	reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_MASK;
+	reg |= (m2s_sm->prot << UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_SHIFT) &
+		UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_MASK;
+	al_reg_write32(cfg_2, reg);
+
+	reg = al_reg_read32(cfg_max_beats);
+	reg &= ~UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
+	reg |= m2s_sm->max_beats &
+			UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
+	al_reg_write32(cfg_max_beats, reg);
+
+	return 0;
+}
+
+/** Configure UDMA AXI M2S configuration */
+int al_udma_m2s_axi_set(struct al_udma *udma,
+					struct al_udma_m2s_axi_conf *axi_m2s)
+{
+	uint32_t reg;
+
+	al_udma_m2s_axi_sm_set(&axi_m2s->comp_write,
+			       &udma->udma_regs->m2s.axi_m2s.comp_wr_cfg_1,
+			       &udma->udma_regs->m2s.axi_m2s.comp_wr_cfg_2,
+			       &udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1);
+
+	al_udma_m2s_axi_sm_set(&axi_m2s->data_read,
+			       &udma->udma_regs->m2s.axi_m2s.data_rd_cfg_1,
+			       &udma->udma_regs->m2s.axi_m2s.data_rd_cfg_2,
+			       &udma->udma_regs->m2s.axi_m2s.data_rd_cfg);
+
+	al_udma_m2s_axi_sm_set(&axi_m2s->desc_read,
+			       &udma->udma_regs->m2s.axi_m2s.desc_rd_cfg_1,
+			       &udma->udma_regs->m2s.axi_m2s.desc_rd_cfg_2,
+			       &udma->udma_regs->m2s.axi_m2s.desc_rd_cfg_3);
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.data_rd_cfg);
+	if (axi_m2s->break_on_max_boundary == AL_TRUE)
+		reg |= UDMA_AXI_M2S_DATA_RD_CFG_ALWAYS_BREAK_ON_MAX_BOUDRY;
+	else
+		reg &= ~UDMA_AXI_M2S_DATA_RD_CFG_ALWAYS_BREAK_ON_MAX_BOUDRY;
+	al_reg_write32(&udma->udma_regs->m2s.axi_m2s.data_rd_cfg, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1);
+	reg &= ~UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK;
+	reg |= (axi_m2s->min_axi_beats <<
+			UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT) &
+		UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK;
+	al_reg_write32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.ostand_cfg);
+	reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_MASK;
+	reg |= axi_m2s->ostand_max_data_read &
+			UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_MASK;
+	reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_MASK;
+	reg |= (axi_m2s->ostand_max_desc_read <<
+			UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_SHIFT) &
+		UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_MASK;
+	reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_MASK;
+	reg |= (axi_m2s->ostand_max_comp_req <<
+			UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_SHIFT) &
+		UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_MASK;
+	reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_MASK;
+	reg |= (axi_m2s->ostand_max_comp_write <<
+			UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_SHIFT) &
+		UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_MASK;
+	al_reg_write32(&udma->udma_regs->m2s.axi_m2s.ostand_cfg, reg);
+	return 0;
+}
+
+/** Configure AXI S2M submaster */
+static int al_udma_s2m_axi_sm_set(struct al_udma_axi_submaster *s2m_sm,
+				      uint32_t *cfg_1, uint32_t *cfg_2,
+				      uint32_t *cfg_max_beats)
+{
+	uint32_t reg;
+	reg = al_reg_read32(cfg_1);
+	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_MASK;
+	reg |= s2m_sm->id & UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_MASK;
+	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_MASK;
+	reg |= (s2m_sm->cache_type <<
+			UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_SHIFT) &
+		UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_MASK;
+	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_MASK;
+	reg |= (s2m_sm->burst << UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_SHIFT) &
+		UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_MASK;
+	al_reg_write32(cfg_1, reg);
+
+	reg = al_reg_read32(cfg_2);
+	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_MASK;
+	reg |= s2m_sm->used_ext & UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_MASK;
+	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_MASK;
+	reg |= (s2m_sm->bus_size << UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_SHIFT) &
+		UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_MASK;
+	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_MASK;
+	reg |= (s2m_sm->qos << UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_SHIFT) &
+		UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_MASK;
+	reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_MASK;
+	reg |= (s2m_sm->prot << UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_SHIFT) &
+		UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_MASK;
+	al_reg_write32(cfg_2, reg);
+
+	reg = al_reg_read32(cfg_max_beats);
+	reg &= ~UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
+	reg |= s2m_sm->max_beats &
+			UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
+	al_reg_write32(cfg_max_beats, reg);
+
+	return 0;
+}
+
+/** Configure UDMA AXI S2M configuration */
+int al_udma_s2m_axi_set(struct al_udma *udma,
+				struct al_udma_s2m_axi_conf *axi_s2m)
+{
+
+	uint32_t reg;
+
+	al_udma_s2m_axi_sm_set(&axi_s2m->data_write,
+			       &udma->udma_regs->s2m.axi_s2m.data_wr_cfg_1,
+			       &udma->udma_regs->s2m.axi_s2m.data_wr_cfg_2,
+			       &udma->udma_regs->s2m.axi_s2m.data_wr_cfg);
+
+	al_udma_s2m_axi_sm_set(&axi_s2m->desc_read,
+			       &udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_4,
+			       &udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_5,
+			       &udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_3);
+
+	al_udma_s2m_axi_sm_set(&axi_s2m->comp_write,
+			       &udma->udma_regs->s2m.axi_s2m.comp_wr_cfg_1,
+			       &udma->udma_regs->s2m.axi_s2m.comp_wr_cfg_2,
+			       &udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1);
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_3);
+	if (axi_s2m->break_on_max_boundary == AL_TRUE)
+		reg |= UDMA_AXI_S2M_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY;
+	else
+		reg &= ~UDMA_AXI_S2M_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY;
+	al_reg_write32(&udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_3, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1);
+	reg &= ~UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK;
+	reg |= (axi_s2m->min_axi_beats <<
+			UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT) &
+		UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK;
+	al_reg_write32(&udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_rd);
+	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_MASK;
+	reg |= axi_s2m->ostand_max_desc_read &
+			UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_MASK;
+
+	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_MASK;
+	reg |= (axi_s2m->ack_fifo_depth <<
+			UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_SHIFT) &
+		UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_MASK;
+
+	al_reg_write32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_rd, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_wr);
+	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_MASK;
+	reg |= axi_s2m->ostand_max_data_req &
+			UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_MASK;
+	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_MASK;
+	reg |= (axi_s2m->ostand_max_data_write <<
+		UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_SHIFT) &
+		UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_MASK;
+	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_MASK;
+	reg |= (axi_s2m->ostand_max_comp_req <<
+			UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_SHIFT) &
+		UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_MASK;
+	reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_MASK;
+	reg |= (axi_s2m->ostand_max_comp_write <<
+		UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_SHIFT) &
+		UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_MASK;
+	al_reg_write32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_wr, reg);
+	return 0;
+}
+
+/** M2S packet len configuration */
+int al_udma_m2s_packet_size_cfg_set(struct al_udma *udma,
+				struct al_udma_m2s_pkt_len_conf *conf)
+{
+	uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s.cfg_len);
+	uint32_t max_supported_size = UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_MASK;
+
+	al_assert(udma->type == UDMA_TX);
+
+	if (conf->encode_64k_as_zero == AL_TRUE)
+		max_supported_size += 1;	/* 64K */
+
+	if (conf->max_pkt_size > max_supported_size) {
+		al_err("udma [%s]: requested max_pkt_size (0x%x) exceeds the"
+			"supported limit (0x%x)\n", udma->name,
+			 conf->max_pkt_size, max_supported_size);
+		return -EINVAL;
+	}
+
+	reg &= ~UDMA_M2S_CFG_LEN_ENCODE_64K;
+	if (conf->encode_64k_as_zero == AL_TRUE)
+		reg |= UDMA_M2S_CFG_LEN_ENCODE_64K;
+	else
+		reg &= ~UDMA_M2S_CFG_LEN_ENCODE_64K;
+
+	reg &= ~UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_MASK;
+	reg |= conf->max_pkt_size;
+
+	al_reg_write32(&udma->udma_regs->m2s.m2s.cfg_len, reg);
+	return 0;
+}
+
+/** Report Error - to be used for abort */
+void al_udma_err_report(struct al_udma *udma __attribute__((__unused__)))
+{
+	return;
+}
+
+/** Statistics - TBD */
+void al_udma_stats_get(struct al_udma *udma __attribute__((__unused__)))
+{
+	return;
+}
+
+/** Configure UDMA M2S descriptor prefetch */
+int al_udma_m2s_pref_set(struct al_udma *udma,
+				struct al_udma_m2s_desc_pref_conf *conf)
+{
+	uint32_t reg;
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1);
+	reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK;
+	reg |= conf->desc_fifo_depth;
+	al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2);
+
+	if (conf->sch_mode == SRR)
+		reg |= UDMA_M2S_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
+	else if (conf->sch_mode == STRICT)
+		reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
+	else {
+		al_err("udma [%s]: requested descriptor preferch arbiter "
+			"mode (%d) is invalid\n", udma->name, conf->sch_mode);
+		return -EINVAL;
+	}
+	reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK;
+	reg |= conf->max_desc_per_packet &
+		UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK;
+	al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3);
+	reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
+	reg |= conf->min_burst_below_thr &
+		UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
+
+	reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK;
+	reg |=(conf->min_burst_above_thr <<
+	       UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT) &
+		UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK;
+
+	reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK;
+	reg |= (conf->pref_thr <<
+			UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT) &
+		UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK;
+
+	al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.data_cfg);
+	reg &= ~UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK;
+	reg |= conf->data_fifo_depth &
+			UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK;
+
+	reg &= ~UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_MASK;
+	reg |= (conf->max_pkt_limit
+			<< UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_SHIFT) &
+		UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_MASK;
+	al_reg_write32(&udma->udma_regs->m2s.m2s_rd.data_cfg, reg);
+
+	return 0;
+}
+
+/** Ger the M2S UDMA descriptor prefetch */
+int al_udma_m2s_pref_get(struct al_udma *udma,
+				struct al_udma_m2s_desc_pref_conf *conf)
+{
+	uint32_t reg;
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1);
+	conf->desc_fifo_depth =
+	    AL_REG_FIELD_GET(reg, UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK,
+			UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_SHIFT);
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2);
+	if (reg & UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK)
+		conf->sch_mode = SRR;
+	else
+		conf->sch_mode = STRICT;
+	conf->max_desc_per_packet =
+	    AL_REG_FIELD_GET(reg,
+			UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK,
+			UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_SHIFT);
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3);
+
+	conf->min_burst_below_thr =
+	    AL_REG_FIELD_GET(reg,
+			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK,
+			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_SHIFT);
+
+	conf->min_burst_above_thr =
+	    AL_REG_FIELD_GET(reg,
+			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK,
+			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT);
+
+	conf->pref_thr = AL_REG_FIELD_GET(reg,
+				UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK,
+				UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT);
+	return 0;
+}
+
+/* set max descriptors */
+int al_udma_m2s_max_descs_set(struct al_udma *udma, uint8_t max_descs)
+{
+	uint32_t pref_thr = max_descs;
+	uint32_t min_burst_above_thr = 4;
+	al_assert(max_descs <= AL_UDMA_M2S_MAX_ALLOWED_DESCS_PER_PACKET);
+	al_assert(max_descs > 0);
+
+	/* increase min_burst_above_thr so larger burst can be used to fetch
+	 * descriptors */
+	if (pref_thr >= 8)
+		min_burst_above_thr = 8;
+	else {
+	/* don't set prefetch threshold too low so we can have the
+	 * min_burst_above_thr >= 4 */
+		pref_thr = 4;
+	}
+
+	al_reg_write32_masked(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2,
+			      UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK,
+			      max_descs << UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_SHIFT);
+
+	al_reg_write32_masked(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3,
+			      UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK |
+			      UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK,
+			      (pref_thr << UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT) |
+			      (min_burst_above_thr << UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT));
+
+	return 0;
+}
+
+/* set s2m max descriptors */
+int al_udma_s2m_max_descs_set(struct al_udma *udma, uint8_t max_descs)
+{
+	uint32_t pref_thr = max_descs;
+	uint32_t min_burst_above_thr = 4;
+	al_assert(max_descs <= AL_UDMA_S2M_MAX_ALLOWED_DESCS_PER_PACKET);
+	al_assert(max_descs > 0);
+
+	/* increase min_burst_above_thr so larger burst can be used to fetch
+	 * descriptors */
+	if (pref_thr >= 8)
+		min_burst_above_thr = 8;
+	else
+	/* don't set prefetch threshold too low so we can have the
+	 * min_burst_above_thr >= 4 */
+		pref_thr = 4;
+
+	al_reg_write32_masked(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_3,
+			      UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_MASK |
+			      UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK,
+			      (pref_thr << UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT) |
+			      (min_burst_above_thr << UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT));
+
+	return 0;
+}
+
+int al_udma_s2m_full_line_write_set(struct al_udma *udma, al_bool enable)
+{
+	uint32_t	val = 0;
+
+	if (enable == AL_TRUE) {
+		val = UDMA_S2M_WR_DATA_CFG_2_FULL_LINE_MODE;
+		al_info("udma [%s]: full line write enabled\n", udma->name);
+	}
+
+	al_reg_write32_masked(&udma->udma_regs->s2m.s2m_wr.data_cfg_2,
+			UDMA_S2M_WR_DATA_CFG_2_FULL_LINE_MODE,
+			val);
+	return 0;
+}
+
+/** Configure S2M UDMA descriptor prefetch */
+int al_udma_s2m_pref_set(struct al_udma *udma,
+				struct al_udma_s2m_desc_pref_conf *conf)
+{
+	uint32_t reg;
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_1);
+	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK;
+	reg |= conf->desc_fifo_depth;
+	al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_1, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_2);
+
+	if (conf->sch_mode == SRR)
+		reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
+	else if (conf->sch_mode == STRICT)
+		reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
+	else {
+		al_err("udma [%s]: requested descriptor preferch arbiter "
+			"mode (%d) is invalid\n", udma->name, conf->sch_mode);
+		return -EINVAL;
+	}
+	if (conf->q_promotion == AL_TRUE)
+		reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_Q_PROMOTION;
+	else
+		reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_Q_PROMOTION;
+
+	if (conf->force_promotion == AL_TRUE)
+		reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_FORCE_PROMOTION;
+	else
+		reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_FORCE_PROMOTION;
+
+	if (conf->en_pref_prediction == AL_TRUE)
+		reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_EN_PREF_PREDICTION;
+	else
+		reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_EN_PREF_PREDICTION;
+
+	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_MASK;
+	reg |= (conf->promotion_th
+			<< UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_SHIFT) &
+		UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_MASK;
+
+	al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_2, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_3);
+	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_MASK;
+	reg |= (conf->pref_thr << UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT) &
+		UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_MASK;
+
+	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
+	reg |= conf->min_burst_below_thr &
+		UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
+
+	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK;
+	reg |=(conf->min_burst_above_thr <<
+	       UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT) &
+		UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
+
+	al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_3, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_4);
+	reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK;
+	reg |= conf->a_full_thr & UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK;
+	al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_4, reg);
+
+
+	return 0;
+}
+
+/* Configure S2M UDMA data write */
+int al_udma_s2m_data_write_set(struct al_udma *udma,
+				struct al_udma_s2m_data_write_conf *conf)
+{
+	uint32_t reg;
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_1);
+	reg &= ~UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_MASK;
+	reg |= conf->data_fifo_depth &
+			UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_MASK;
+	reg &= ~UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_MASK;
+	reg |= (conf->max_pkt_limit <<
+				UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_SHIFT) &
+			UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_MASK;
+	reg &= ~UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_MASK;
+	reg |= (conf->fifo_margin <<
+				UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_SHIFT) &
+			UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_MASK;
+	al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_1, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2);
+	reg &= ~UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK;
+	reg |= conf->desc_wait_timer &
+			UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK;
+	reg &= ~(UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC |
+		 UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC |
+		 UDMA_S2M_WR_DATA_CFG_2_WAIT_FOR_PREF |
+		 UDMA_S2M_WR_DATA_CFG_2_FULL_LINE_MODE |
+		 UDMA_S2M_WR_DATA_CFG_2_DIRECT_HDR_USE_BUF1);
+	reg |= conf->flags &
+		(UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC |
+		 UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC |
+		 UDMA_S2M_WR_DATA_CFG_2_WAIT_FOR_PREF |
+		 UDMA_S2M_WR_DATA_CFG_2_FULL_LINE_MODE |
+		 UDMA_S2M_WR_DATA_CFG_2_DIRECT_HDR_USE_BUF1);
+	al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2, reg);
+
+	return 0;
+}
+
+/* Configure S2M UDMA completion */
+int al_udma_s2m_completion_set(struct al_udma *udma,
+				struct al_udma_s2m_completion_conf *conf)
+{
+	uint32_t reg = al_reg_read32(&udma->udma_regs->s2m.s2m_comp.cfg_1c);
+	reg &= ~UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK;
+	reg |= conf->desc_size & UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK;
+	if (conf->cnt_words == AL_TRUE)
+		reg |= UDMA_S2M_COMP_CFG_1C_CNT_WORDS;
+	else
+		reg &= ~UDMA_S2M_COMP_CFG_1C_CNT_WORDS;
+	if (conf->q_promotion == AL_TRUE)
+		reg |= UDMA_S2M_COMP_CFG_1C_Q_PROMOTION;
+	else
+		reg &= ~UDMA_S2M_COMP_CFG_1C_Q_PROMOTION;
+	if (conf->force_rr == AL_TRUE)
+		reg |= UDMA_S2M_COMP_CFG_1C_FORCE_RR;
+	else
+		reg &= ~UDMA_S2M_COMP_CFG_1C_FORCE_RR;
+	reg &= ~UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_MASK;
+	reg |= (conf->q_free_min << UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_SHIFT) &
+		UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_MASK;
+	al_reg_write32(&udma->udma_regs->s2m.s2m_comp.cfg_1c, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_comp.cfg_2c);
+	reg &= ~UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_MASK;
+	reg |= conf->comp_fifo_depth
+				& UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_MASK;
+	reg &= ~UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_MASK;
+	reg |= (conf->unack_fifo_depth
+			<< UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_SHIFT) &
+			UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_MASK;
+	al_reg_write32(&udma->udma_regs->s2m.s2m_comp.cfg_2c, reg);
+
+	al_reg_write32(&udma->udma_regs->s2m.s2m_comp.cfg_application_ack,
+		       conf->timeout);
+	return 0;
+}
+
+/** Configure the M2S UDMA scheduling mode */
+int al_udma_m2s_sc_set(struct al_udma *udma,
+					struct al_udma_m2s_dwrr_conf *sched)
+{
+	uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_dwrr.cfg_sched);
+
+	if (sched->enable_dwrr == AL_TRUE)
+		reg |= UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR;
+	else
+		reg &= ~UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR;
+
+	if (sched->pkt_mode == AL_TRUE)
+		reg |= UDMA_M2S_DWRR_CFG_SCHED_PKT_MODE_EN;
+	else
+		reg &= ~UDMA_M2S_DWRR_CFG_SCHED_PKT_MODE_EN;
+
+	reg &= ~UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_MASK;
+	reg |= sched->weight << UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_SHIFT;
+	reg &= ~UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_MASK;
+	reg |= sched->inc_factor << UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_SHIFT;
+	al_reg_write32(&udma->udma_regs->m2s.m2s_dwrr.cfg_sched, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_dwrr.ctrl_deficit_cnt);
+	reg &= ~UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_MASK;
+	reg |= sched->deficit_init_val;
+	al_reg_write32(&udma->udma_regs->m2s.m2s_dwrr.ctrl_deficit_cnt, reg);
+
+	return 0;
+}
+
+/** Configure the M2S UDMA rate limitation */
+int al_udma_m2s_rlimit_set(struct al_udma *udma,
+					struct al_udma_m2s_rlimit_mode *mode)
+{
+	uint32_t reg = al_reg_read32(
+				&udma->udma_regs->m2s.m2s_rate_limiter.gen_cfg);
+
+	if (mode->pkt_mode_en == AL_TRUE)
+		reg |= UDMA_M2S_RATE_LIMITER_GEN_CFG_PKT_MODE_EN;
+	else
+		reg &= ~UDMA_M2S_RATE_LIMITER_GEN_CFG_PKT_MODE_EN;
+	reg &= ~UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_MASK;
+	reg |= mode->short_cycle_sz &
+	    UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_MASK;
+	al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.gen_cfg, reg);
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_token);
+	reg &= ~UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_MASK;
+	reg |= mode->token_init_val &
+			UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_MASK;
+	al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_token, reg);
+
+	return 0;
+}
+
+int al_udma_m2s_rlimit_reset(struct al_udma *udma)
+{
+	uint32_t reg = al_reg_read32(
+			&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_cycle_cnt);
+	reg |= UDMA_M2S_RATE_LIMITER_CTRL_CYCLE_CNT_RST;
+	al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_cycle_cnt,
+						reg);
+	return 0;
+}
+
+/** Configure the Stream/Q rate limitation */
+static int al_udma_common_rlimit_set(struct udma_rlimit_common *regs,
+					  struct al_udma_m2s_rlimit_cfg *conf)
+{
+	uint32_t reg = al_reg_read32(&regs->cfg_1s);
+	/* mask max burst size, and enable/pause control bits */
+	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_MASK;
+	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_EN;
+	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_PAUSE;
+	reg |= conf->max_burst_sz &
+		UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_MASK;
+	al_reg_write32(&regs->cfg_1s, reg);
+
+	reg = al_reg_read32(&regs->cfg_cycle);
+	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_MASK;
+	reg |= conf->long_cycle_sz &
+		UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_MASK;
+	al_reg_write32(&regs->cfg_cycle, reg);
+
+	reg = al_reg_read32(&regs->cfg_token_size_1);
+	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK;
+	reg |= conf->long_cycle &
+		UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK;
+	al_reg_write32(&regs->cfg_token_size_1, reg);
+
+	reg = al_reg_read32(&regs->cfg_token_size_2);
+	reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK;
+	reg |= conf->short_cycle &
+		UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK;
+	al_reg_write32(&regs->cfg_token_size_2, reg);
+
+	reg = al_reg_read32(&regs->mask);
+	reg &= ~0xf;		/* only bits 0-3 defined */
+	reg |= conf->mask & 0xf;
+	al_reg_write32(&regs->mask, reg);
+
+	return 0;
+}
+
+static int al_udma_common_rlimit_act(struct udma_rlimit_common *regs,
+					  enum al_udma_m2s_rlimit_action act)
+{
+	uint32_t reg;
+
+	switch (act) {
+	case AL_UDMA_STRM_RLIMIT_ENABLE:
+		reg = al_reg_read32(&regs->cfg_1s);
+		reg |= UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_EN;
+		al_reg_write32(&regs->cfg_1s, reg);
+		break;
+	case AL_UDMA_STRM_RLIMIT_PAUSE:
+		reg = al_reg_read32(&regs->cfg_1s);
+		reg |= UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_PAUSE;
+		al_reg_write32(&regs->cfg_1s, reg);
+		break;
+	case AL_UDMA_STRM_RLIMIT_RESET:
+		reg = al_reg_read32(&regs->sw_ctrl);
+		reg |= UDMA_M2S_STREAM_RATE_LIMITER_SW_CTRL_RST_TOKEN_CNT;
+		al_reg_write32(&regs->sw_ctrl, reg);
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/** Configure the M2S Stream rate limitation */
+int al_udma_m2s_strm_rlimit_set(struct al_udma *udma,
+				struct al_udma_m2s_rlimit_cfg *conf)
+{
+	struct udma_rlimit_common *rlimit_regs =
+	    &udma->udma_regs->m2s.m2s_stream_rate_limiter.rlimit;
+
+	return al_udma_common_rlimit_set(rlimit_regs, conf);
+}
+
+int al_udma_m2s_strm_rlimit_act(struct al_udma *udma,
+				enum al_udma_m2s_rlimit_action act)
+{
+	struct udma_rlimit_common *rlimit_regs =
+	    &udma->udma_regs->m2s.m2s_stream_rate_limiter.rlimit;
+
+	if (al_udma_common_rlimit_act(rlimit_regs, act) == -EINVAL) {
+		al_err("udma [%s]: udma stream rate limit invalid action "
+			"(%d)\n", udma->name, act);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/** Configure the M2S UDMA Q rate limitation */
+int al_udma_m2s_q_rlimit_set(struct al_udma_q *udma_q,
+				struct al_udma_m2s_rlimit_cfg *conf)
+{
+	struct udma_rlimit_common *rlimit_regs = &udma_q->q_regs->m2s_q.rlimit;
+
+	return al_udma_common_rlimit_set(rlimit_regs, conf);
+}
+
+int al_udma_m2s_q_rlimit_act(struct al_udma_q *udma_q,
+				enum al_udma_m2s_rlimit_action act)
+{
+	struct udma_rlimit_common *rlimit_regs = &udma_q->q_regs->m2s_q.rlimit;
+
+	if (al_udma_common_rlimit_act(rlimit_regs, act) == -EINVAL) {
+		al_err("udma [%s %d]: udma stream rate limit invalid action "
+				"(%d)\n",
+				udma_q->udma->name, udma_q->qid, act);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+/** Configure the M2S UDMA Q scheduling mode */
+int al_udma_m2s_q_sc_set(struct al_udma_q *udma_q,
+					struct al_udma_m2s_q_dwrr_conf *conf)
+{
+	uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_1);
+
+	reg &= ~UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_MASK;
+	reg |= conf->max_deficit_cnt_sz &
+		UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_MASK;
+	if (conf->strict == AL_TRUE)
+		reg |= UDMA_M2S_Q_DWRR_CFG_1_STRICT;
+	else
+		reg &= ~UDMA_M2S_Q_DWRR_CFG_1_STRICT;
+	al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_1, reg);
+
+	reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_2);
+	reg &= ~UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK;
+	reg |= (conf->axi_qos << UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_SHIFT) &
+	    UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK;
+	reg &= ~UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK;
+	reg |= conf->q_qos & UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK;
+	al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_2, reg);
+
+	reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_3);
+	reg &= ~UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK;
+	reg |= conf->weight & UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK;
+	al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_3, reg);
+
+	return 0;
+}
+
+int al_udma_m2s_q_sc_pause(struct al_udma_q *udma_q, al_bool set)
+{
+	uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_1);
+
+	if (set == AL_TRUE)
+		reg |= UDMA_M2S_Q_DWRR_CFG_1_PAUSE;
+	else
+		reg &= ~UDMA_M2S_Q_DWRR_CFG_1_PAUSE;
+	al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_1, reg);
+
+	return 0;
+}
+
+int al_udma_m2s_q_sc_reset(struct al_udma_q *udma_q)
+{
+	uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_sw_ctrl);
+
+	reg |= UDMA_M2S_Q_DWRR_SW_CTRL_RST_CNT;
+	al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_sw_ctrl, reg);
+
+	return 0;
+}
+
+/** M2S UDMA completion and application timeouts */
+int al_udma_m2s_comp_timeouts_set(struct al_udma *udma,
+				struct al_udma_m2s_comp_timeouts *conf)
+{
+	uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_1c);
+
+	if (conf->sch_mode == SRR)
+		reg |= UDMA_M2S_COMP_CFG_1C_FORCE_RR;
+	else if (conf->sch_mode == STRICT)
+		reg &= ~UDMA_M2S_COMP_CFG_1C_FORCE_RR;
+	else {
+		al_err("udma [%s]: requested completion descriptor preferch "
+				"arbiter mode (%d) is invalid\n",
+				udma->name, conf->sch_mode);
+		return -EINVAL;
+	}
+	if (conf->enable_q_promotion == AL_TRUE)
+		reg |= UDMA_M2S_COMP_CFG_1C_Q_PROMOTION;
+	else
+		reg &= ~UDMA_M2S_COMP_CFG_1C_Q_PROMOTION;
+	reg &= ~UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_MASK;
+	reg |=
+	    conf->comp_fifo_depth << UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_SHIFT;
+
+	reg &= ~UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_MASK;
+	reg |= conf->unack_fifo_depth
+				<< UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_SHIFT;
+	al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_1c, reg);
+
+	al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_coal
+							, conf->coal_timeout);
+
+	reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_application_ack);
+	reg &= ~UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_MASK;
+	reg |= conf->app_timeout << UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_SHIFT;
+	al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_application_ack, reg);
+	return 0;
+}
+
+int al_udma_m2s_comp_timeouts_get(struct al_udma *udma,
+					struct al_udma_m2s_comp_timeouts *conf)
+{
+	uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_1c);
+
+	if (reg & UDMA_M2S_COMP_CFG_1C_FORCE_RR)
+		conf->sch_mode = SRR;
+	else
+		conf->sch_mode = STRICT;
+
+	if (reg & UDMA_M2S_COMP_CFG_1C_Q_PROMOTION)
+		conf->enable_q_promotion = AL_TRUE;
+	else
+		conf->enable_q_promotion = AL_FALSE;
+
+	conf->comp_fifo_depth =
+	    AL_REG_FIELD_GET(reg,
+			     UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_MASK,
+			     UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_SHIFT);
+	conf->unack_fifo_depth =
+	    AL_REG_FIELD_GET(reg,
+			     UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_MASK,
+			     UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_SHIFT);
+
+	conf->coal_timeout = al_reg_read32(
+				&udma->udma_regs->m2s.m2s_comp.cfg_coal);
+
+	reg = al_reg_read32(
+			&udma->udma_regs->m2s.m2s_comp.cfg_application_ack);
+
+	conf->app_timeout =
+	    AL_REG_FIELD_GET(reg,
+			     UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_MASK,
+			     UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_SHIFT);
+
+	return 0;
+}
+
+/**
+ * S2M UDMA configure no descriptors behaviour
+ */
+int al_udma_s2m_no_desc_cfg_set(struct al_udma *udma, al_bool drop_packet, al_bool gen_interrupt, uint32_t wait_for_desc_timeout)
+{
+	uint32_t reg;
+
+	reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2);
+
+	if ((drop_packet == AL_TRUE) && (wait_for_desc_timeout == 0)) {
+		al_err("udam [%s]: setting timeout to 0 will cause the udma to wait forever instead of dropping the packet", udma->name);
+		return -EINVAL;
+	}
+
+	if (drop_packet == AL_TRUE)
+		reg |= UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC;
+	else
+		reg &= ~UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC;
+
+	if (gen_interrupt == AL_TRUE)
+		reg |= UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC;
+	else
+		reg &= ~UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC;
+
+	AL_REG_FIELD_SET(reg, UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK, UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_SHIFT, wait_for_desc_timeout);
+
+	al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2, reg);
+
+	return 0;
+}
+
+/* S2M UDMA configure a queue's completion update */
+int al_udma_s2m_q_compl_updade_config(struct al_udma_q *udma_q, al_bool enable)
+{
+	uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
+
+	if (enable == AL_TRUE)
+		reg |= UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
+	else
+		reg &= ~UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
+
+	al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
+
+	return 0;
+}
+
+/* S2M UDMA configure a queue's completion descriptors coalescing */
+int al_udma_s2m_q_compl_coal_config(struct al_udma_q *udma_q, al_bool enable, uint32_t
+		coal_timeout)
+{
+	uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
+
+	if (enable == AL_TRUE)
+		reg &= ~UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
+	else
+		reg |= UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
+
+	al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
+
+	al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg_2, coal_timeout);
+	return 0;
+}
+
+/* S2M UDMA configure completion descriptors write burst parameters */
+int al_udma_s2m_compl_desc_burst_config(struct al_udma *udma, uint16_t
+		burst_size)
+{
+	if ((burst_size != 64) && (burst_size != 128) && (burst_size != 256)) {
+		al_err("%s: invalid burst_size value (%d)\n", __func__,
+				burst_size);
+		return -EINVAL;
+	}
+
+	/* convert burst size from bytes to beats (16 byte) */
+	burst_size = burst_size / 16;
+	al_reg_write32_masked(&udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1,
+			UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK |
+			UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK,
+			burst_size << UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT |
+			burst_size << UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_SHIFT);
+	return 0;
+}
+
+/* S2M UDMA configure a queue's completion descriptors header split */
+int al_udma_s2m_q_compl_hdr_split_config(struct al_udma_q *udma_q, al_bool enable,
+					 al_bool force_hdr_split, uint32_t hdr_len)
+{
+	uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.pkt_cfg);
+
+	reg &= ~UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
+	reg &= ~UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
+	reg &= ~UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
+
+	if (enable == AL_TRUE) {
+		reg |= hdr_len & UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
+		reg |= UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
+
+		if (force_hdr_split == AL_TRUE)
+			reg |= UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
+	}
+
+	al_reg_write32(&udma_q->q_regs->s2m_q.pkt_cfg, reg);
+
+	return 0;
+}
+
+/* S2M UDMA per queue completion configuration */
+int al_udma_s2m_q_comp_set(struct al_udma_q *udma_q,
+					struct al_udma_s2m_q_comp_conf *conf)
+{
+	uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
+	if (conf->en_comp_ring_update == AL_TRUE)
+		reg |= UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
+	else
+		reg &= ~UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
+
+	if (conf->dis_comp_coal == AL_TRUE)
+		reg |= UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
+	else
+		reg &= ~UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
+
+	al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
+
+	al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg_2, conf->comp_timer);
+
+	reg = al_reg_read32(&udma_q->q_regs->s2m_q.pkt_cfg);
+
+	reg &= ~UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
+	reg |= conf->hdr_split_size & UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
+	if (conf->force_hdr_split == AL_TRUE)
+		reg |= UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
+	else
+		reg &= ~UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
+	if (conf->en_hdr_split == AL_TRUE)
+		reg |= UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
+	else
+		reg &= ~UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
+
+	al_reg_write32(&udma_q->q_regs->s2m_q.pkt_cfg, reg);
+
+	reg = al_reg_read32(&udma_q->q_regs->s2m_q.qos_cfg);
+	reg &= ~UDMA_S2M_QOS_CFG_Q_QOS_MASK;
+	reg |= conf->q_qos & UDMA_S2M_QOS_CFG_Q_QOS_MASK;
+	al_reg_write32(&udma_q->q_regs->s2m_q.qos_cfg, reg);
+
+	return 0;
+}
+
+/* UDMA VMID control configuration */
+void al_udma_gen_vmid_conf_set(
+	struct unit_regs		*unit_regs,
+	struct al_udma_gen_vmid_conf	*conf)
+{
+	unsigned int rev_id;
+
+	al_reg_write32_masked(
+		&unit_regs->gen.vmid.cfg_vmid_0,
+		UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_DESC_EN_MASK |
+		UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_QUEUE_EN_MASK |
+		UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_DESC_EN_MASK |
+		UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_QUEUE_EN_MASK,
+		(((conf->tx_q_conf[0].desc_en << 0) |
+		(conf->tx_q_conf[1].desc_en << 1) |
+		(conf->tx_q_conf[2].desc_en << 2) |
+		(conf->tx_q_conf[3].desc_en << 3)) <<
+		UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_DESC_EN_SHIFT) |
+		(((conf->tx_q_conf[0].queue_en << 0) |
+		(conf->tx_q_conf[1].queue_en << 1) |
+		(conf->tx_q_conf[2].queue_en << 2) |
+		(conf->tx_q_conf[3].queue_en << 3)) <<
+		UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_QUEUE_EN_SHIFT) |
+		(((conf->rx_q_conf[0].desc_en << 0) |
+		(conf->rx_q_conf[1].desc_en << 1) |
+		(conf->rx_q_conf[2].desc_en << 2) |
+		(conf->rx_q_conf[3].desc_en << 3)) <<
+		UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_DESC_EN_SHIFT) |
+		(((conf->rx_q_conf[0].queue_en << 0) |
+		(conf->rx_q_conf[1].queue_en << 1) |
+		(conf->rx_q_conf[2].queue_en << 2) |
+		(conf->rx_q_conf[3].queue_en << 3)) <<
+		UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_QUEUE_EN_SHIFT));
+
+	/* VMID per queue */
+	al_reg_write32(
+		&unit_regs->gen.vmid.cfg_vmid_1,
+		(conf->tx_q_conf[0].vmid <<
+		UDMA_GEN_VMID_CFG_VMID_1_TX_Q_0_VMID_SHIFT) |
+		(conf->tx_q_conf[1].vmid <<
+		UDMA_GEN_VMID_CFG_VMID_1_TX_Q_1_VMID_SHIFT));
+
+	al_reg_write32(
+		&unit_regs->gen.vmid.cfg_vmid_2,
+		(conf->tx_q_conf[2].vmid <<
+		UDMA_GEN_VMID_CFG_VMID_2_TX_Q_2_VMID_SHIFT) |
+		(conf->tx_q_conf[3].vmid <<
+		UDMA_GEN_VMID_CFG_VMID_2_TX_Q_3_VMID_SHIFT));
+
+	al_reg_write32(
+		&unit_regs->gen.vmid.cfg_vmid_3,
+		(conf->rx_q_conf[0].vmid <<
+		UDMA_GEN_VMID_CFG_VMID_3_RX_Q_0_VMID_SHIFT) |
+		(conf->rx_q_conf[1].vmid <<
+		UDMA_GEN_VMID_CFG_VMID_3_RX_Q_1_VMID_SHIFT));
+
+	al_reg_write32(
+		&unit_regs->gen.vmid.cfg_vmid_4,
+		(conf->rx_q_conf[2].vmid <<
+		UDMA_GEN_VMID_CFG_VMID_4_RX_Q_2_VMID_SHIFT) |
+		(conf->rx_q_conf[3].vmid <<
+		UDMA_GEN_VMID_CFG_VMID_4_RX_Q_3_VMID_SHIFT));
+
+	/* VMADDR per queue */
+	rev_id = al_udma_get_revision(unit_regs);
+	if (rev_id >= AL_UDMA_REV_ID_REV2) {
+		al_reg_write32(
+			&unit_regs->gen.vmaddr.cfg_vmaddr_0,
+			(conf->tx_q_conf[0].vmaddr <<
+			UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_0_VMADDR_SHIFT) |
+			(conf->tx_q_conf[1].vmaddr <<
+			UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_1_VMADDR_SHIFT));
+
+		al_reg_write32(
+			&unit_regs->gen.vmaddr.cfg_vmaddr_1,
+			(conf->tx_q_conf[2].vmaddr <<
+			UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_2_VMADDR_SHIFT) |
+			(conf->tx_q_conf[3].vmaddr <<
+			UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_3_VMADDR_SHIFT));
+
+		al_reg_write32(
+			&unit_regs->gen.vmaddr.cfg_vmaddr_2,
+			(conf->rx_q_conf[0].vmaddr <<
+			UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_0_VMADDR_SHIFT) |
+			(conf->rx_q_conf[1].vmaddr <<
+			UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_1_VMADDR_SHIFT));
+
+		al_reg_write32(
+			&unit_regs->gen.vmaddr.cfg_vmaddr_3,
+			(conf->rx_q_conf[2].vmaddr <<
+			UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_2_VMADDR_SHIFT) |
+			(conf->rx_q_conf[3].vmaddr <<
+			UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_3_VMADDR_SHIFT));
+	}
+}
+
+/* UDMA VMID MSIX control configuration */
+void al_udma_gen_vmid_msix_conf_set(
+	struct unit_regs			*unit_regs,
+	struct al_udma_gen_vmid_msix_conf	*conf)
+{
+	al_reg_write32_masked(
+		&unit_regs->gen.vmid.cfg_vmid_0,
+		UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_ACCESS_EN |
+		UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_SEL,
+		(conf->access_en ? UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_ACCESS_EN : 0) |
+		(conf->sel ? UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_SEL : 0));
+}
+
+/* UDMA VMID control advanced Tx queue configuration */
+void al_udma_gen_vmid_advanced_tx_q_conf(
+	struct al_udma_q				*q,
+	struct al_udma_gen_vmid_advanced_tx_q_conf	*conf)
+{
+	struct udma_gen_regs *gen_regs = q->udma->gen_regs;
+	struct udma_gen_vmpr *vmpr = &gen_regs->vmpr[q->qid];
+
+	al_reg_write32_masked(
+		&vmpr->cfg_vmpr_0,
+		UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_MASK |
+		UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_DATA_VMID_EN |
+		UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_PREF_VMID_EN |
+		UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_CMPL_VMID_EN,
+		conf->tx_q_addr_hi_sel |
+		((conf->tx_q_data_vmid_en == AL_TRUE) ?
+		 UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_DATA_VMID_EN : 0) |
+		((conf->tx_q_prefetch_vmid_en == AL_TRUE) ?
+		 UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_PREF_VMID_EN : 0) |
+		((conf->tx_q_compl_vmid_en == AL_TRUE) ?
+		 UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_CMPL_VMID_EN : 0));
+
+	al_reg_write32(
+		&vmpr->cfg_vmpr_1,
+		conf->tx_q_addr_hi);
+
+	al_reg_write32_masked(
+		&vmpr->cfg_vmpr_2,
+		UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_VMID_MASK |
+		UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_VMID_MASK,
+		(conf->tx_q_prefetch_vmid <<
+		 UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_VMID_SHIFT) |
+		(conf->tx_q_compl_vmid <<
+		 UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_VMID_SHIFT));
+
+	al_reg_write32_masked(
+		&vmpr->cfg_vmpr_3,
+		UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_MASK |
+		UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SEL_MASK,
+		(conf->tx_q_data_vmid <<
+		 UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SHIFT) |
+		(conf->tx_q_data_vmid_mask <<
+		 UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SEL_SHIFT));
+}
+
+/** UDMA VMID control advanced Rx queue configuration */
+void al_udma_gen_vmid_advanced_rx_q_conf(
+	struct al_udma_q				*q,
+	struct al_udma_gen_vmid_advanced_rx_q_conf	*conf)
+{
+	struct udma_gen_regs *gen_regs = q->udma->gen_regs;
+	struct udma_gen_vmpr *vmpr = &gen_regs->vmpr[q->qid];
+
+	al_reg_write32_masked(
+		&vmpr->cfg_vmpr_4,
+		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_MASK |
+		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_VMID_EN |
+		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_MASK |
+		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_VMID_EN |
+		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_MASK |
+		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_VMID_EN |
+		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_PREF_VMID_EN |
+		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_CMPL_VMID_EN,
+		(conf->rx_q_addr_hi_sel <<
+		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_SHIFT) |
+		((conf->rx_q_data_vmid_en == AL_TRUE) ?
+		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_VMID_EN : 0) |
+		(conf->rx_q_data_buff2_addr_hi_sel <<
+		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_SHIFT) |
+		((conf->rx_q_data_buff2_vmid_en == AL_TRUE) ?
+		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_VMID_EN : 0) |
+		(conf->rx_q_ddp_addr_hi_sel <<
+		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_SHIFT) |
+		((conf->rx_q_ddp_vmid_en == AL_TRUE) ?
+		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_VMID_EN : 0) |
+		((conf->rx_q_prefetch_vmid_en == AL_TRUE) ?
+		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_PREF_VMID_EN : 0) |
+		((conf->rx_q_compl_vmid_en == AL_TRUE) ?
+		 UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_CMPL_VMID_EN : 0));
+
+	al_reg_write32_masked(
+		&vmpr->cfg_vmpr_6,
+		UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_VMID_MASK |
+		UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_VMID_MASK,
+		(conf->rx_q_prefetch_vmid <<
+		 UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_VMID_SHIFT) |
+		(conf->rx_q_compl_vmid <<
+		 UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_VMID_SHIFT));
+
+	al_reg_write32_masked(
+		&vmpr->cfg_vmpr_7,
+		UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_MASK |
+		UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SEL_MASK,
+		(conf->rx_q_data_vmid <<
+		 UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SHIFT) |
+		(conf->rx_q_data_vmid_mask <<
+		 UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SEL_SHIFT));
+
+	al_reg_write32_masked(
+		&vmpr->cfg_vmpr_8,
+		UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_MASK |
+		UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SEL_MASK,
+		(conf->rx_q_data_buff2_vmid <<
+		 UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SHIFT) |
+		(conf->rx_q_data_buff2_mask <<
+		 UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SEL_SHIFT));
+
+	al_reg_write32_masked(
+		&vmpr->cfg_vmpr_9,
+		UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_MASK |
+		UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SEL_MASK,
+		(conf->rx_q_ddp_vmid <<
+		 UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SHIFT) |
+		(conf->rx_q_ddp_mask <<
+		 UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SEL_SHIFT));
+
+	al_reg_write32(
+		&vmpr->cfg_vmpr_10,
+		conf->rx_q_addr_hi);
+
+	al_reg_write32(
+		&vmpr->cfg_vmpr_11,
+		conf->rx_q_data_buff2_addr_hi);
+
+	al_reg_write32(
+		&vmpr->cfg_vmpr_12,
+		conf->rx_q_ddp_addr_hi);
+}
+
+/* UDMA header split buffer 2 Rx queue configuration */
+void al_udma_gen_hdr_split_buff2_rx_q_conf(
+	struct al_udma_q				*q,
+	struct al_udma_gen_hdr_split_buff2_q_conf	*conf)
+{
+	struct udma_gen_regs *gen_regs = q->udma->gen_regs;
+	struct udma_gen_vmpr *vmpr = &gen_regs->vmpr[q->qid];
+
+	al_reg_write32_masked(
+		&vmpr->cfg_vmpr_4,
+		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_MASK,
+		conf->add_msb_sel <<
+		UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_SHIFT);
+
+	al_reg_write32(
+		&vmpr->cfg_vmpr_5,
+		conf->addr_msb);
+}
+
diff --git a/sys/contrib/alpine-hal/al_hal_udma_config.h b/sys/contrib/alpine-hal/al_hal_udma_config.h
new file mode 100644
index 000000000000..b742e1824c92
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_config.h
@@ -0,0 +1,755 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_udma_config UDMA Config
+ * @ingroup group_udma_api
+ *  UDMA Config API
+ *  @{
+ * @file   al_hal_udma_config.h
+ *
+ * @brief C Header file for the Universal DMA HAL driver for configuration APIs
+ *
+ */
+
+#ifndef __AL_HAL_UDMA_CONFIG_H__
+#define __AL_HAL_UDMA_CONFIG_H__
+
+#include <al_hal_udma.h>
+
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/** Scheduling mode */
+enum al_udma_sch_mode {
+	STRICT,			/* Strict */
+	SRR,			/* Simple Sound Rubin */
+	DWRR			/* Deficit Weighted Round Rubin */
+};
+
+/** AXI configuration */
+struct al_udma_axi_conf {
+	uint32_t axi_timeout;	/* Timeout for AXI transactions  */
+	uint8_t arb_promotion;	/* arbitration promotion */
+	al_bool swap_8_bytes;	/* enable 8 bytes swap instead of 4 bytes */
+	al_bool swap_s2m_data;
+	al_bool swap_s2m_desc;
+	al_bool swap_m2s_data;
+	al_bool swap_m2s_desc;
+};
+
+/** UDMA AXI M2S configuration */
+struct al_udma_axi_submaster {
+	uint8_t id; /* AXI ID */
+	uint8_t cache_type;
+	uint8_t burst;
+	uint16_t used_ext;
+	uint8_t bus_size;
+	uint8_t qos;
+	uint8_t prot;
+	uint8_t max_beats;
+};
+
+/** UDMA AXI M2S configuration */
+struct al_udma_m2s_axi_conf {
+	struct al_udma_axi_submaster comp_write;
+	struct al_udma_axi_submaster data_read;
+	struct al_udma_axi_submaster desc_read;
+	al_bool break_on_max_boundary; /* Data read break on max boundary */
+	uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
+	uint8_t ostand_max_data_read;
+	uint8_t ostand_max_desc_read;
+	uint8_t ostand_max_comp_req;
+	uint8_t ostand_max_comp_write;
+};
+
+/** UDMA AXI S2M configuration */
+struct al_udma_s2m_axi_conf {
+	struct al_udma_axi_submaster data_write;
+	struct al_udma_axi_submaster desc_read;
+	struct al_udma_axi_submaster comp_write;
+	al_bool break_on_max_boundary; /* Data read break on max boundary */
+	uint8_t min_axi_beats; /* Minimum burst for writing completion desc. */
+	uint8_t ostand_max_data_req;
+	uint8_t ostand_max_data_write;
+	uint8_t ostand_max_comp_req;
+	uint8_t ostand_max_comp_write;
+	uint8_t ostand_max_desc_read;
+	uint8_t ack_fifo_depth;	/* size of the stream application ack fifo */
+};
+
+/** M2S error logging */
+struct al_udma_err_log {
+	uint32_t error_status;
+	uint32_t header[4];
+};
+
+/** M2S max packet size configuration */
+struct al_udma_m2s_pkt_len_conf {
+	uint32_t max_pkt_size;
+	al_bool encode_64k_as_zero;
+};
+
+/** M2S Descriptor Prefetch configuration */
+struct al_udma_m2s_desc_pref_conf {
+	uint8_t desc_fifo_depth;
+	enum al_udma_sch_mode sch_mode;	/* Scheduling mode
+					* (either strict or RR) */
+
+	uint8_t max_desc_per_packet;	/* max number of descriptors to
+					 * prefetch */
+	/* in one burst (5b) */
+	uint8_t pref_thr;
+	uint8_t min_burst_above_thr;	/* min burst size when fifo above
+					* pref_thr (4b)
+					*/
+	uint8_t min_burst_below_thr;	/* min burst size when fifo below
+					* pref_thr (4b)
+					*/
+	uint8_t max_pkt_limit;		/* maximum number of packets in the data
+					* read FIFO, defined based on header
+					* FIFO size
+					*/
+	uint16_t data_fifo_depth;	/* maximum number of data beats in the
+					* data read FIFO,
+					* defined based on header FIFO size
+					*/
+};
+
+/** S2M Descriptor Prefetch configuration */
+struct al_udma_s2m_desc_pref_conf {
+	uint8_t desc_fifo_depth;
+	enum al_udma_sch_mode sch_mode;	/* Scheduling mode *
+					* (either strict or RR)
+					*/
+
+	al_bool q_promotion;		/* enable promotion */
+	al_bool force_promotion;	/* force promotion  */
+	al_bool en_pref_prediction;	/* enable prefetch prediction */
+	uint8_t promotion_th;		/* Threshold for queue promotion */
+
+	uint8_t pref_thr;
+	uint8_t min_burst_above_thr;	/* min burst size when fifo above
+	 	 	 	 	 * pref_thr (4b)
+	 	 	 	 	 */
+	uint8_t min_burst_below_thr;	/* min burst size when fifo below
+	 	 	 	 	 * pref_thr (4b)
+	 	 	 	 	 */
+	uint8_t a_full_thr;		/* almost full threshold */
+};
+
+/** S2M Data write configuration */
+struct al_udma_s2m_data_write_conf {
+	uint16_t data_fifo_depth;	/* maximum number of data beats in the
+					 * data write FIFO, defined based on
+					 * header FIFO size
+					 */
+	uint8_t max_pkt_limit;		/* maximum number of packets in the
+					* data write FIFO,defined based on
+					* header FIFO size
+					*/
+	uint8_t fifo_margin;
+	uint32_t desc_wait_timer;	/* waiting time for the host to write
+					* new descriptor to the queue
+					* (for the current packet in process)
+					*/
+	uint32_t flags;			/* bitwise of flags of s2m
+					 * data_cfg_2 register
+					 */
+};
+
+/** S2M Completion configuration */
+struct al_udma_s2m_completion_conf {
+	uint8_t desc_size;		/* Size of completion descriptor
+					 * in words
+					 */
+	al_bool cnt_words;		/* Completion fifo in use counter:
+	 	 	 	 	 * AL_TRUE words, AL_FALS descriptors
+	 	 	 	 	 */
+	al_bool q_promotion;		/* Enable promotion of the current
+					 * unack in progress */
+					/* in the completion write scheduler */
+	al_bool force_rr;		/* force RR arbitration in the
+					*  scheduler
+					*/
+  //	uint8_t ack_fifo_depth;		/* size of the stream application ack fifo */
+	uint8_t q_free_min;		/* minimum number of free completion
+					 * entries
+					 */
+					/* to qualify for promotion */
+
+	uint16_t comp_fifo_depth;	/* Size of completion fifo in words */
+	uint16_t unack_fifo_depth;	/* Size of unacked fifo in descs */
+	uint32_t timeout;		/* Ack timout from stream interface */
+};
+
+/** M2S UDMA DWRR configuration */
+struct al_udma_m2s_dwrr_conf {
+	al_bool enable_dwrr;
+	uint8_t inc_factor;
+	uint8_t weight;
+	al_bool pkt_mode;
+	uint32_t deficit_init_val;
+};
+
+/** M2S DMA Rate Limitation mode */
+struct al_udma_m2s_rlimit_mode {
+	al_bool pkt_mode_en;
+	uint16_t short_cycle_sz;
+	uint32_t token_init_val;
+};
+
+/** M2S Stream/Q Rate Limitation */
+struct al_udma_m2s_rlimit_cfg {
+	uint32_t max_burst_sz;	/* maximum number of accumulated bytes in the
+				 * token counter
+				 */
+	uint16_t long_cycle_sz;	/* number of short cycles between token fill */
+	uint32_t long_cycle;	/* number of bits to add in each long cycle */
+	uint32_t short_cycle;	/* number of bits to add in each cycle */
+	uint32_t mask;		/* mask the different types of rate limiters */
+};
+
+enum al_udma_m2s_rlimit_action {
+	AL_UDMA_STRM_RLIMIT_ENABLE,
+	AL_UDMA_STRM_RLIMIT_PAUSE,
+	AL_UDMA_STRM_RLIMIT_RESET
+};
+
+/** M2S UDMA Q scheduling configuration */
+struct al_udma_m2s_q_dwrr_conf {
+	uint32_t max_deficit_cnt_sz;	/*maximum number of accumulated bytes
+					* in the deficit counter
+					*/
+	al_bool strict;		/* bypass DWRR */
+	uint8_t axi_qos;
+	uint16_t q_qos;
+	uint8_t weight;
+};
+
+/** M2S UDMA / UDMA Q scheduling configuration */
+struct al_udma_m2s_sc {
+	enum al_udma_sch_mode sch_mode;	/* Scheduling Mode */
+	struct al_udma_m2s_dwrr_conf dwrr;	/* DWRR configuration */
+};
+
+/** UDMA / UDMA Q rate limitation configuration */
+struct al_udma_m2s_rlimit {
+	struct al_udma_m2s_rlimit_mode rlimit_mode;
+						/* rate limitation enablers */
+#if 0
+	struct al_udma_tkn_bkt_conf token_bkt;        /* Token Bucket configuration */
+#endif
+};
+
+/** UDMA Data read configuration */
+struct al_udma_m2s_data_rd_conf {
+	uint8_t max_rd_d_beats;		/* max burst size for reading data
+					 * (in AXI beats-128b) (5b)
+					 */
+	uint8_t max_rd_d_out_req;	/* max number of outstanding data
+					 * read requests (6b)
+					 */
+	uint16_t max_rd_d_out_beats;	/* max num. of data read beats (10b) */
+};
+
+/** M2S UDMA completion and application timeouts */
+struct al_udma_m2s_comp_timeouts {
+	enum al_udma_sch_mode sch_mode;	/* Scheduling mode
+					 * (either strict or RR)
+					 */
+	al_bool enable_q_promotion;
+	uint8_t unack_fifo_depth;	/* unacked desc fifo size */
+	uint8_t comp_fifo_depth;	/* desc fifo size */
+	uint32_t coal_timeout;	/* (24b) */
+	uint32_t app_timeout;	/* (24b) */
+};
+
+/** S2M UDMA per queue completion configuration */
+struct al_udma_s2m_q_comp_conf {
+	al_bool dis_comp_coal;		/* disable completion coalescing */
+	al_bool en_comp_ring_update;	/* enable writing completion descs */
+	uint32_t comp_timer;		/* completion coalescing timer */
+	al_bool en_hdr_split;		/* enable header split */
+	al_bool force_hdr_split;	/* force header split */
+	uint16_t hdr_split_size;	/* size used for the header split */
+	uint8_t q_qos;			/* queue QoS */
+};
+
+/** UDMA per queue VMID control configuration */
+struct al_udma_gen_vmid_q_conf {
+	/* Enable usage of the VMID per queue according to 'vmid' */
+	al_bool queue_en;
+
+	/* Enable usage of the VMID from the descriptor buffer address 63:48 */
+	al_bool desc_en;
+
+	/* VMID to be applied when 'queue_en' is asserted */
+	uint16_t vmid;
+
+	/* VMADDR to be applied to msbs when 'desc_en' is asserted.
+	 * Relevant for revisions >= AL_UDMA_REV_ID_REV2 */
+	uint16_t vmaddr;
+};
+
+/** UDMA VMID control configuration */
+struct al_udma_gen_vmid_conf {
+	/* TX queue configuration */
+	struct al_udma_gen_vmid_q_conf tx_q_conf[DMA_MAX_Q];
+
+	/* RX queue configuration */
+	struct al_udma_gen_vmid_q_conf rx_q_conf[DMA_MAX_Q];
+};
+
+/** UDMA VMID MSIX control configuration */
+struct al_udma_gen_vmid_msix_conf {
+	/* Enable write to all VMID_n registers in the MSI-X Controller */
+	al_bool access_en;
+
+	/* use VMID_n [7:0] from MSI-X Controller for MSI-X message */
+	al_bool sel;
+};
+
+/** UDMA per Tx queue advanced VMID control configuration */
+struct al_udma_gen_vmid_advanced_tx_q_conf {
+	/**********************************************************************
+	 * Tx Data VMID
+	 **********************************************************************/
+	/* Tx data VMID enable */
+	al_bool tx_q_data_vmid_en;
+
+	/*
+	 * For Tx data reads, replacement bits for the original address.
+	 * The number of bits replaced is determined according to
+	 * 'tx_q_addr_hi_sel'
+	 */
+	unsigned int tx_q_addr_hi;
+
+	/*
+	 * For Tx data reads, 6 bits serving the number of bits taken from the
+	 * extra register on account of bits coming from the original address
+	 * field.
+	 * When 'tx_q_addr_hi_sel'=32 all of 'tx_q_addr_hi' will be taken.
+	 * When 'tx_q_addr_hi_sel'=0 none of it will be taken, and when any
+	 * value in between, it will start from the MSB bit and sweep down as
+	 * many bits as needed. For example if 'tx_q_addr_hi_sel'=8, the final
+	 * address [63:56] will carry 'tx_q_addr_hi'[31:24] while [55:32] will
+	 * carry the original buffer address[55:32].
+	 */
+	unsigned int tx_q_addr_hi_sel;
+
+	/*
+	 * Tx data read VMID
+	 * Masked per bit with 'tx_q_data_vmid_mask'
+	 */
+	unsigned int tx_q_data_vmid;
+
+	/*
+	 * Tx data read VMID mask
+	 * Each '1' selects from the buffer address, each '0' selects from
+	 * 'tx_q_data_vmid'
+	 */
+	unsigned int tx_q_data_vmid_mask;
+
+	/**********************************************************************
+	 * Tx prefetch VMID
+	 **********************************************************************/
+	/* Tx prefetch VMID enable */
+	al_bool tx_q_prefetch_vmid_en;
+
+	/* Tx prefetch VMID */
+	unsigned int tx_q_prefetch_vmid;
+
+	/**********************************************************************
+	 * Tx completion VMID
+	 **********************************************************************/
+	/* Tx completion VMID enable */
+	al_bool tx_q_compl_vmid_en;
+
+	/* Tx completion VMID */
+	unsigned int tx_q_compl_vmid;
+};
+
+/** UDMA per Rx queue advanced VMID control configuration */
+struct al_udma_gen_vmid_advanced_rx_q_conf {
+	/**********************************************************************
+	 * Rx Data VMID
+	 **********************************************************************/
+	/* Rx data VMID enable */
+	al_bool rx_q_data_vmid_en;
+
+	/*
+	 * For Rx data writes, replacement bits for the original address.
+	 * The number of bits replaced is determined according to
+	 * 'rx_q_addr_hi_sel'
+	 */
+	unsigned int rx_q_addr_hi;
+
+	/*
+	 * For Rx data writes, 6 bits serving the number of bits taken from the
+	 * extra register on account of bits coming from the original address
+	 * field.
+	 */
+	unsigned int rx_q_addr_hi_sel;
+
+	/*
+	 * Rx data write VMID
+	 * Masked per bit with 'rx_q_data_vmid_mask'
+	 */
+	unsigned int rx_q_data_vmid;
+
+	/* Rx data write VMID mask */
+	unsigned int rx_q_data_vmid_mask;
+
+	/**********************************************************************
+	 * Rx Data Buffer 2 VMID
+	 **********************************************************************/
+	/* Rx data buff2 VMID enable */
+	al_bool rx_q_data_buff2_vmid_en;
+
+	/*
+	 * For Rx data buff2 writes, replacement bits for the original address.
+	 * The number of bits replaced is determined according to
+	 * 'rx_q_data_buff2_addr_hi_sel'
+	 */
+	unsigned int rx_q_data_buff2_addr_hi;
+
+	/*
+	 * For Rx data buff2 writes, 6 bits serving the number of bits taken
+	 * from the extra register on account of bits coming from the original
+	 * address field.
+	 */
+	unsigned int rx_q_data_buff2_addr_hi_sel;
+
+	/*
+	 * Rx data buff2 write VMID
+	 * Masked per bit with 'rx_q_data_buff2_mask'
+	 */
+	unsigned int rx_q_data_buff2_vmid;
+
+	/* Rx data buff2 write VMID mask */
+	unsigned int rx_q_data_buff2_mask;
+
+	/**********************************************************************
+	 * Rx DDP VMID
+	 **********************************************************************/
+	/* Rx DDP write VMID enable */
+	al_bool rx_q_ddp_vmid_en;
+
+	/*
+	 * For Rx DDP writes, replacement bits for the original address.
+	 * The number of bits replaced is determined according to
+	 * 'rx_q_ddp_addr_hi_sel'
+	 */
+	unsigned int rx_q_ddp_addr_hi;
+
+	/*
+	 * For Rx DDP writes, 6 bits serving the number of bits taken from the
+	 * extra register on account of bits coming from the original address
+	 * field.
+	 */
+	unsigned int rx_q_ddp_addr_hi_sel;
+
+	/*
+	 * Rx DDP write VMID
+	 * Masked per bit with 'rx_q_ddp_mask'
+	 */
+	unsigned int rx_q_ddp_vmid;
+
+	/* Rx DDP write VMID mask */
+	unsigned int rx_q_ddp_mask;
+
+	/**********************************************************************
+	 * Rx prefetch VMID
+	 **********************************************************************/
+	/* Rx prefetch VMID enable */
+	al_bool rx_q_prefetch_vmid_en;
+
+	/* Rx prefetch VMID */
+	unsigned int rx_q_prefetch_vmid;
+
+	/**********************************************************************
+	 * Rx completion VMID
+	 **********************************************************************/
+	/* Rx completion VMID enable */
+	al_bool rx_q_compl_vmid_en;
+
+	/* Rx completion VMID */
+	unsigned int rx_q_compl_vmid;
+};
+
+/**
+ * Header split, buffer 2 per queue configuration
+ * When header split is enabled, Buffer_2 is used as an address for the header
+ * data. Buffer_2 is defined as 32-bits in the RX descriptor and it is defined
+ * that the MSB ([63:32]) of Buffer_1 is used as address [63:32] for the header
+ * address.
+ */
+struct al_udma_gen_hdr_split_buff2_q_conf {
+	/*
+	 * MSB of the 64-bit address (bits [63:32]) that can be used for header
+	 * split for this queue
+	 */
+	unsigned int addr_msb;
+
+	/*
+	 * Determine how to select the MSB (bits [63:32]) of the address when
+	 * header split is enabled (4 bits, one per byte)
+	 * - Bits [3:0]:
+	 *	[0] – selector for bits [39:32]
+	 *	[1] – selector for bits [47:40]
+	 *	[2] – selector for bits [55:48]
+	 *	[3] – selector for bits [63:55]
+	 * - Bit value:
+	 *	0 – Use Buffer_1 (legacy operation)
+	 *	1 – Use the queue configuration 'addr_msb'
+	 */
+	unsigned int add_msb_sel;
+};
+
+/* Report Error - to be used for abort */
+void al_udma_err_report(struct al_udma *udma);
+
+/* Statistics - TBD */
+void al_udma_stats_get(struct al_udma *udma);
+
+/* Misc configurations */
+/* Configure AXI configuration */
+int al_udma_axi_set(struct udma_gen_axi *axi_regs,
+		    struct al_udma_axi_conf *axi);
+
+/* Configure UDMA AXI M2S configuration */
+int al_udma_m2s_axi_set(struct al_udma *udma,
+			struct al_udma_m2s_axi_conf *axi_m2s);
+
+/* Configure UDMA AXI S2M configuration */
+int al_udma_s2m_axi_set(struct al_udma *udma,
+			struct al_udma_s2m_axi_conf *axi_s2m);
+
+/* Configure M2S packet len */
+int al_udma_m2s_packet_size_cfg_set(struct al_udma *udma,
+				    struct al_udma_m2s_pkt_len_conf *conf);
+
+/* Configure M2S UDMA descriptor prefetch */
+int al_udma_m2s_pref_set(struct al_udma *udma,
+			 struct al_udma_m2s_desc_pref_conf *conf);
+int al_udma_m2s_pref_get(struct al_udma *udma,
+			 struct al_udma_m2s_desc_pref_conf *conf);
+
+/* set m2s packet's max descriptors (including meta descriptors) */
+#define AL_UDMA_M2S_MAX_ALLOWED_DESCS_PER_PACKET	31
+int al_udma_m2s_max_descs_set(struct al_udma *udma, uint8_t max_descs);
+
+/* set s2m packets' max descriptors */
+#define AL_UDMA_S2M_MAX_ALLOWED_DESCS_PER_PACKET	31
+int al_udma_s2m_max_descs_set(struct al_udma *udma, uint8_t max_descs);
+
+
+/* Configure S2M UDMA descriptor prefetch */
+int al_udma_s2m_pref_set(struct al_udma *udma,
+			 struct al_udma_s2m_desc_pref_conf *conf);
+int al_udma_m2s_pref_get(struct al_udma *udma,
+			 struct al_udma_m2s_desc_pref_conf *conf);
+
+/* Configure S2M UDMA data write */
+int al_udma_s2m_data_write_set(struct al_udma *udma,
+			       struct al_udma_s2m_data_write_conf *conf);
+
+/* Configure the s2m full line write feature */
+int al_udma_s2m_full_line_write_set(struct al_udma *umda, al_bool enable);
+
+/* Configure S2M UDMA completion */
+int al_udma_s2m_completion_set(struct al_udma *udma,
+			       struct al_udma_s2m_completion_conf *conf);
+
+/* Configure the M2S UDMA scheduling mode */
+int al_udma_m2s_sc_set(struct al_udma *udma,
+		       struct al_udma_m2s_dwrr_conf *sched);
+
+/* Configure the M2S UDMA rate limitation */
+int al_udma_m2s_rlimit_set(struct al_udma *udma,
+			   struct al_udma_m2s_rlimit_mode *mode);
+int al_udma_m2s_rlimit_reset(struct al_udma *udma);
+
+/* Configure the M2S Stream rate limitation */
+int al_udma_m2s_strm_rlimit_set(struct al_udma *udma,
+				struct al_udma_m2s_rlimit_cfg *conf);
+int al_udma_m2s_strm_rlimit_act(struct al_udma *udma,
+				enum al_udma_m2s_rlimit_action act);
+
+/* Configure the M2S UDMA Q rate limitation */
+int al_udma_m2s_q_rlimit_set(struct al_udma_q *udma_q,
+			     struct al_udma_m2s_rlimit_cfg *conf);
+int al_udma_m2s_q_rlimit_act(struct al_udma_q *udma_q,
+			     enum al_udma_m2s_rlimit_action act);
+
+/* Configure the M2S UDMA Q scheduling mode */
+int al_udma_m2s_q_sc_set(struct al_udma_q *udma_q,
+			 struct al_udma_m2s_q_dwrr_conf *conf);
+int al_udma_m2s_q_sc_pause(struct al_udma_q *udma_q, al_bool set);
+int al_udma_m2s_q_sc_reset(struct al_udma_q *udma_q);
+
+/* M2S UDMA completion and application timeouts */
+int al_udma_m2s_comp_timeouts_set(struct al_udma *udma,
+				  struct al_udma_m2s_comp_timeouts *conf);
+int al_udma_m2s_comp_timeouts_get(struct al_udma *udma,
+				  struct al_udma_m2s_comp_timeouts *conf);
+
+/* UDMA get revision */
+static INLINE unsigned int al_udma_get_revision(struct unit_regs __iomem *unit_regs)
+{
+	return (al_reg_read32(&unit_regs->gen.dma_misc.revision)
+			& UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_MASK) >>
+			UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_SHIFT;
+}
+
+/**
+ * S2M UDMA Configure the expected behavior of Rx/S2M UDMA when there are no Rx Descriptors.
+ *
+ * @param udma
+ * @param drop_packet when set to true, the UDMA will drop packet.
+ * @param gen_interrupt when set to true, the UDMA will generate
+ *        no_desc_hint interrupt when a packet received and the UDMA
+ *	  doesn't find enough free descriptors for it.
+ * @param wait_for_desc_timeout timeout in SB cycles to wait for new
+ *	  descriptors before dropping the packets.
+ *	  Notes:
+ *		- The hint interrupt is raised immediately without waiting
+ *		for new descs.
+ *		- value 0 means wait for ever.
+ *
+ * Notes:
+ * - When get_interrupt is set, the API won't program the iofic to unmask this
+ * interrupt, in this case the callee should take care for doing that unmask
+ * using the al_udma_iofic_config() API.
+ *
+ * - The hardware's default configuration is: no drop packet, generate hint
+ * interrupt.
+ * - This API must be called once and before enabling the UDMA
+ *
+ * @return 0 if no error found.
+ */
+int al_udma_s2m_no_desc_cfg_set(struct al_udma *udma, al_bool drop_packet, al_bool gen_interrupt, uint32_t wait_for_desc_timeout);
+
+/**
+ * S2M UDMA configure a queue's completion update
+ *
+ * @param q_udma
+ * @param enable set to true to enable completion update
+ *
+ * completion update better be disabled for tx queues as those descriptors
+ * doesn't carry useful information, thus disabling it saves DMA accesses.
+ *
+ * @return 0 if no error found.
+ */
+int al_udma_s2m_q_compl_updade_config(struct al_udma_q *udma_q, al_bool enable);
+
+/**
+ * S2M UDMA configure a queue's completion descriptors coalescing
+ *
+ * @param q_udma
+ * @param enable set to true to enable completion coalescing
+ * @param coal_timeout in South Bridge cycles.
+ *
+ * @return 0 if no error found.
+ */
+int al_udma_s2m_q_compl_coal_config(struct al_udma_q *udma_q, al_bool enable, uint32_t coal_timeout);
+
+/**
+ * S2M UDMA configure completion descriptors write burst parameters
+ *
+ * @param udma
+ * @param burst_size completion descriptors write burst size in bytes.
+ *
+ * @return 0 if no error found.
+ */int al_udma_s2m_compl_desc_burst_config(struct al_udma *udma, uint16_t
+		 burst_size);
+
+/**
+ * S2M UDMA configure a queue's completion header split
+ *
+ * @param q_udma
+ * @param enable set to true to enable completion header split
+ * @param force_hdr_split the header split length will be taken from the queue configuration
+ * @param hdr_len header split length.
+ *
+ * @return 0 if no error found.
+ */
+int al_udma_s2m_q_compl_hdr_split_config(struct al_udma_q *udma_q,
+					 al_bool enable,
+					 al_bool force_hdr_split,
+					 uint32_t hdr_len);
+
+/* S2M UDMA per queue completion configuration */
+int al_udma_s2m_q_comp_set(struct al_udma_q *udma_q,
+			   struct al_udma_s2m_q_comp_conf *conf);
+
+/** UDMA VMID control configuration */
+void al_udma_gen_vmid_conf_set(
+	struct unit_regs __iomem	*unit_regs,
+	struct al_udma_gen_vmid_conf	*conf);
+
+/** UDMA VMID MSIX control configuration */
+void al_udma_gen_vmid_msix_conf_set(
+	struct unit_regs __iomem		*unit_regs,
+	struct al_udma_gen_vmid_msix_conf	*conf);
+
+/** UDMA VMID control advanced Tx queue configuration */
+void al_udma_gen_vmid_advanced_tx_q_conf(
+	struct al_udma_q				*q,
+	struct al_udma_gen_vmid_advanced_tx_q_conf	*conf);
+
+/** UDMA VMID control advanced Rx queue configuration */
+void al_udma_gen_vmid_advanced_rx_q_conf(
+	struct al_udma_q				*q,
+	struct al_udma_gen_vmid_advanced_rx_q_conf	*conf);
+
+/** UDMA header split buffer 2 Rx queue configuration */
+void al_udma_gen_hdr_split_buff2_rx_q_conf(
+	struct al_udma_q				*q,
+	struct al_udma_gen_hdr_split_buff2_q_conf	*conf);
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+}
+#endif
+/* *INDENT-ON* */
+/** @} end of UDMA config group */
+#endif /* __AL_HAL_UDMA_CONFIG_H__ */
diff --git a/sys/contrib/alpine-hal/al_hal_udma_debug.c b/sys/contrib/alpine-hal/al_hal_udma_debug.c
new file mode 100644
index 000000000000..c6b9bf4b9bf0
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_debug.c
@@ -0,0 +1,497 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @file   al_hal_udma_debug.c
+ *
+ * @brief  Universal DMA HAL driver for debug
+ *
+ */
+
+#define DEBUG
+
+#include <al_hal_common.h>
+#include <al_hal_udma_regs.h>
+#include <al_hal_udma_debug.h>
+
+static void al_udma_regs_m2s_axi_print(struct al_udma *udma)
+{
+	al_dbg("M2S AXI regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, comp_wr_cfg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, comp_wr_cfg_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, data_rd_cfg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, data_rd_cfg_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_rd_cfg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_rd_cfg_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, data_rd_cfg);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_rd_cfg_3);
+
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, desc_wr_cfg_1);
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, axi_m2s,
+			desc_wr_cfg_1,
+			max_axi_beats,
+			UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS);
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, axi_m2s,
+			desc_wr_cfg_1,
+			min_axi_beats,
+			UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS);
+
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, axi_m2s, ostand_cfg);
+}
+
+static void al_udma_regs_m2s_general_print(struct al_udma *udma)
+{
+	al_dbg("M2S general regs:\n");
+
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, state);
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s, state,
+			comp_ctrl,
+			UDMA_M2S_STATE_COMP_CTRL);
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s, state,
+			stream_if,
+			UDMA_M2S_STATE_STREAM_IF);
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s, state,
+			rd_ctrl,
+			UDMA_M2S_STATE_DATA_RD_CTRL);
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s, state,
+			desc_pref,
+			UDMA_M2S_STATE_DESC_PREF);
+
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, err_log_mask);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_0);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, log_3);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, data_fifo_status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, header_fifo_status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, unack_fifo_status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, check_en);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, fifo_en);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, cfg_len);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, stream_cfg);
+}
+
+static void al_udma_regs_m2s_rd_print(struct al_udma *udma)
+{
+	al_dbg("M2S read regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, desc_pref_cfg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, desc_pref_cfg_2);
+
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, desc_pref_cfg_3);
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_rd,
+			desc_pref_cfg_3,
+			min_burst_below_thr,
+			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR);
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_rd,
+			desc_pref_cfg_3,
+			min_burst_above_thr,
+			UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR);
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_rd,
+			desc_pref_cfg_3,
+			pref_thr,
+			UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR);
+
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rd, data_cfg);
+}
+
+static void al_udma_regs_m2s_dwrr_print(struct al_udma *udma)
+{
+	al_dbg("M2S DWRR regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_dwrr, cfg_sched);
+}
+
+static void al_udma_regs_m2s_rate_limiter_print(struct al_udma *udma)
+{
+	al_dbg("M2S rate limiter regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_rate_limiter, gen_cfg);
+}
+
+static void al_udma_regs_m2s_stream_rate_limiter_print(struct al_udma *udma)
+{
+	al_dbg("M2S stream rate limiter regs:\n");
+
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter,
+			rlimit.cfg_1s);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter,
+			rlimit.cfg_cycle);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter,
+			rlimit.cfg_token_size_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter,
+			rlimit.cfg_token_size_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stream_rate_limiter,
+			rlimit.mask);
+}
+
+static void al_udma_regs_m2s_comp_print(struct al_udma *udma)
+{
+	al_dbg("M2S completion regs:\n");
+
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_comp, cfg_1c);
+
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_comp, cfg_1c,
+			comp_fifo_depth,
+			UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH);
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_comp, cfg_1c,
+			unack_fifo_depth,
+			UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH);
+	AL_UDMA_PRINT_REG_BIT(udma, "  ", "\n", m2s, m2s_comp, cfg_1c,
+			q_promotion,
+			UDMA_M2S_COMP_CFG_1C_Q_PROMOTION);
+	AL_UDMA_PRINT_REG_BIT(udma, "  ", "\n", m2s, m2s_comp, cfg_1c,
+			force_rr,
+			UDMA_M2S_COMP_CFG_1C_FORCE_RR);
+	AL_UDMA_PRINT_REG_FIELD(udma, "  ", "\n", "%d", m2s, m2s_comp, cfg_1c,
+			q_free_min,
+			UDMA_M2S_COMP_CFG_1C_Q_FREE_MIN);
+
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_comp, cfg_coal);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_comp, cfg_application_ack);
+}
+
+static void al_udma_regs_m2s_stat_print(struct al_udma *udma)
+{
+	al_dbg("M2S statistics regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, cfg_st);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, tx_pkt);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, tx_bytes_low);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, tx_bytes_high);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, prefed_desc);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, comp_pkt);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, comp_desc);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_stat, ack_pkts);
+}
+
+static void al_udma_regs_m2s_feature_print(struct al_udma *udma)
+{
+	al_dbg("M2S feature regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_3);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_4);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_feature, reg_5);
+}
+
+static void al_udma_regs_m2s_q_print(struct al_udma *udma, uint32_t qid)
+{
+	al_dbg("M2S Q[%d] status regs:\n", qid);
+	al_reg_write32(&udma->udma_regs->m2s.m2s.indirect_ctrl, qid);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_pref_fifo_status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_comp_fifo_status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_rate_limit_status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s, sel_dwrr_status);
+
+	al_dbg("M2S Q[%d] regs:\n", qid);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], cfg);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrbp_low);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrbp_high);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrl);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrhp);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdrtp);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tdcp);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tcrbp_low);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tcrbp_high);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], tcrhp);
+
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], rlimit.cfg_1s);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], rlimit.cfg_cycle);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid],
+			rlimit.cfg_token_size_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid],
+			rlimit.cfg_token_size_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], rlimit.mask);
+
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], dwrr_cfg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], dwrr_cfg_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], dwrr_cfg_3);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], comp_cfg);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", m2s, m2s_q[qid], q_tx_pkt);
+}
+
+static void al_udma_regs_s2m_axi_print(struct al_udma *udma)
+{
+	al_dbg("S2M AXI regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, data_wr_cfg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, data_wr_cfg_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_rd_cfg_4);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_rd_cfg_5);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, comp_wr_cfg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, comp_wr_cfg_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, data_wr_cfg);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_rd_cfg_3);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, desc_wr_cfg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, ostand_cfg_rd);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, axi_s2m, ostand_cfg_wr);
+}
+
+static void al_udma_regs_s2m_general_print(struct al_udma *udma)
+{
+	al_dbg("S2M general regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, state);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, err_log_mask);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_0);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, log_3);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, s_data_fifo_status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, s_header_fifo_status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, axi_data_fifo_status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, unack_fifo_status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, check_en);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, fifo_en);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, stream_cfg);
+}
+
+static void al_udma_regs_s2m_rd_print(struct al_udma *udma)
+{
+	al_dbg("S2M read regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_3);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_rd, desc_pref_cfg_4);
+}
+
+static void al_udma_regs_s2m_wr_print(struct al_udma *udma)
+{
+	al_dbg("S2M write regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_wr, data_cfg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_wr, data_cfg_1);
+}
+
+static void al_udma_regs_s2m_comp_print(struct al_udma *udma)
+{
+	al_dbg("S2M completion regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_comp, cfg_1c);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_comp, cfg_2c);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_comp, cfg_application_ack);
+}
+
+static void al_udma_regs_s2m_stat_print(struct al_udma *udma)
+{
+	al_dbg("S2M statistics regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, drop_pkt);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, rx_bytes_low);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, rx_bytes_high);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, prefed_desc);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, comp_pkt);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, comp_desc);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_stat, ack_pkts);
+}
+
+static void al_udma_regs_s2m_feature_print(struct al_udma *udma)
+{
+	al_dbg("S2M feature regs:\n");
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_1);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_3);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_4);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_5);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_feature, reg_6);
+}
+
+static void al_udma_regs_s2m_q_print(struct al_udma *udma, uint32_t qid)
+{
+	al_dbg("S2M Q[%d] status regs:\n", qid);
+	al_reg_write32(&udma->udma_regs->m2s.m2s.indirect_ctrl, qid);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, sel_pref_fifo_status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m, sel_comp_fifo_status);
+
+	al_dbg("S2M Q[%d] regs:\n", qid);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], cfg);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], status);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrbp_low);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrbp_high);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrl);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrhp);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdrtp);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rdcp);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrbp_low);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrbp_high);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrhp);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], rcrhp_internal);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], comp_cfg);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], comp_cfg_2);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], pkt_cfg);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], qos_cfg);
+	AL_UDMA_PRINT_REG(udma, " ", "\n", s2m, s2m_q[qid], q_rx_pkt);
+}
+
+void al_udma_regs_print(struct al_udma *udma, unsigned int mask)
+{
+	uint32_t i;
+
+	if (!udma)
+		return;
+
+	if (udma->type == UDMA_TX) {
+		if (mask & AL_UDMA_DEBUG_AXI)
+			al_udma_regs_m2s_axi_print(udma);
+		if (mask & AL_UDMA_DEBUG_GENERAL)
+			al_udma_regs_m2s_general_print(udma);
+		if (mask & AL_UDMA_DEBUG_READ)
+			al_udma_regs_m2s_rd_print(udma);
+		if (mask & AL_UDMA_DEBUG_DWRR)
+			al_udma_regs_m2s_dwrr_print(udma);
+		if (mask & AL_UDMA_DEBUG_RATE_LIMITER)
+			al_udma_regs_m2s_rate_limiter_print(udma);
+		if (mask & AL_UDMA_DEBUG_STREAM_RATE_LIMITER)
+			al_udma_regs_m2s_stream_rate_limiter_print(udma);
+		if (mask & AL_UDMA_DEBUG_COMP)
+			al_udma_regs_m2s_comp_print(udma);
+		if (mask & AL_UDMA_DEBUG_STAT)
+			al_udma_regs_m2s_stat_print(udma);
+		if (mask & AL_UDMA_DEBUG_FEATURE)
+			al_udma_regs_m2s_feature_print(udma);
+		for (i = 0; i < DMA_MAX_Q; i++) {
+			if (mask & AL_UDMA_DEBUG_QUEUE(i))
+				al_udma_regs_m2s_q_print(udma, i);
+		}
+	} else {
+		if (mask & AL_UDMA_DEBUG_AXI)
+			al_udma_regs_s2m_axi_print(udma);
+		if (mask & AL_UDMA_DEBUG_GENERAL)
+			al_udma_regs_s2m_general_print(udma);
+		if (mask & AL_UDMA_DEBUG_READ)
+			al_udma_regs_s2m_rd_print(udma);
+		if (mask & AL_UDMA_DEBUG_WRITE)
+			al_udma_regs_s2m_wr_print(udma);
+		if (mask & AL_UDMA_DEBUG_COMP)
+			al_udma_regs_s2m_comp_print(udma);
+		if (mask & AL_UDMA_DEBUG_STAT)
+			al_udma_regs_s2m_stat_print(udma);
+		if (mask & AL_UDMA_DEBUG_FEATURE)
+			al_udma_regs_s2m_feature_print(udma);
+		for (i = 0; i < DMA_MAX_Q; i++) {
+			if (mask & AL_UDMA_DEBUG_QUEUE(i))
+				al_udma_regs_s2m_q_print(udma, i);
+		}
+	}
+}
+
+void al_udma_q_struct_print(struct al_udma *udma, uint32_t qid)
+{
+	struct al_udma_q *queue;
+
+	if (!udma)
+		return;
+
+	if (qid >= DMA_MAX_Q)
+		return;
+
+	queue = &udma->udma_q[qid];
+
+	al_dbg("Q[%d] struct:\n", qid);
+	al_dbg(" size_mask = 0x%08x\n", (uint32_t)queue->size_mask);
+	al_dbg(" q_regs = %p\n", queue->q_regs);
+	al_dbg(" desc_base_ptr = %p\n", queue->desc_base_ptr);
+	al_dbg(" next_desc_idx = %d\n", (uint16_t)queue->next_desc_idx);
+	al_dbg(" desc_ring_id = %d\n", (uint32_t)queue->desc_ring_id);
+	al_dbg(" cdesc_base_ptr = %p\n", queue->cdesc_base_ptr);
+	al_dbg(" cdesc_size = %d\n", (uint32_t)queue->cdesc_size);
+	al_dbg(" next_cdesc_idx = %d\n", (uint16_t)queue->next_cdesc_idx);
+	al_dbg(" end_cdesc_ptr = %p\n", queue->end_cdesc_ptr);
+	al_dbg(" comp_head_idx = %d\n", (uint16_t)queue->comp_head_idx);
+	al_dbg(" comp_head_ptr = %p\n", queue->comp_head_ptr);
+	al_dbg(" pkt_crnt_descs = %d\n", (uint32_t)queue->pkt_crnt_descs);
+	al_dbg(" comp_ring_id = %d\n", (uint32_t)queue->comp_ring_id);
+	al_dbg(" desc_phy_base = 0x%016llx\n", (uint64_t)queue->desc_phy_base);
+	al_dbg(" cdesc_phy_base = 0x%016llx\n",
+			(uint64_t)queue->cdesc_phy_base);
+	al_dbg(" flags = 0x%08x\n", (uint32_t)queue->flags);
+	al_dbg(" size = %d\n", (uint32_t)queue->size);
+	al_dbg(" status = %d\n", (uint32_t)queue->status);
+	al_dbg(" udma = %p\n", queue->udma);
+	al_dbg(" qid = %d\n", (uint32_t)queue->qid);
+}
+
+void al_udma_ring_print(struct al_udma *udma, uint32_t qid,
+		enum al_udma_ring_type rtype)
+{
+	struct al_udma_q *queue;
+	uint32_t desc_size;
+	void *base_ptr;
+	uint32_t i;
+
+	if (!udma)
+		return;
+
+	if (qid >= DMA_MAX_Q)
+		return;
+
+	queue = &udma->udma_q[qid];
+	if (rtype == AL_RING_SUBMISSION) {
+		base_ptr = queue->desc_base_ptr;
+		desc_size = sizeof(union al_udma_desc);
+		if (base_ptr)
+			al_dbg("Q[%d] submission ring pointers:\n", qid);
+		else {
+			al_dbg("Q[%d] submission ring is not allocated\n", qid);
+			return;
+		}
+	} else {
+		base_ptr = queue->cdesc_base_ptr;
+		desc_size = queue->cdesc_size;
+		if (base_ptr)
+			al_dbg("Q[%d] completion ring pointers:\n", qid);
+		else {
+			al_dbg("Q[%d] completion ring is not allocated\n", qid);
+			return;
+		}
+	}
+
+	for (i = 0; i < queue->size; i++) {
+		uint32_t *curr_addr = (void*)((uint32_t)base_ptr + i * desc_size);
+		if (desc_size == 16)
+			al_dbg("[%04d](%p): %08x %08x %08x %08x\n",
+					i,
+					curr_addr,
+					(uint32_t)*curr_addr,
+					(uint32_t)*(curr_addr+1),
+					(uint32_t)*(curr_addr+2),
+					(uint32_t)*(curr_addr+3));
+		else if (desc_size == 8)
+			al_dbg("[%04d](%p): %08x %08x\n",
+					i,
+					curr_addr,
+					(uint32_t)*curr_addr,
+					(uint32_t)*(curr_addr+1));
+		else if (desc_size == 4)
+			al_dbg("[%04d](%p): %08x\n",
+					i,
+					curr_addr,
+					(uint32_t)*curr_addr);
+		else
+			break;
+	}
+}
diff --git a/sys/contrib/alpine-hal/al_hal_udma_debug.h b/sys/contrib/alpine-hal/al_hal_udma_debug.h
new file mode 100644
index 000000000000..7bd1d972917a
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_debug.h
@@ -0,0 +1,134 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_udma_debug UDMA Debug
+ * @ingroup group_udma_api
+ *  UDMA Debug
+ *  @{
+ * @file   al_hal_udma_debug.h
+ *
+ * @brief C Header file for the Universal DMA HAL driver for debug APIs
+ *
+ */
+
+#ifndef __AL_HAL_UDMA_DEBUG_H__
+#define __AL_HAL_UDMA_DEBUG_H__
+
+#include <al_hal_udma.h>
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/* UDMA register print helper macros */
+#define AL_UDMA_PRINT_REG(UDMA, PREFIX, POSTFIX, TYPE, GROUP, REG) \
+	al_dbg(PREFIX #REG " = 0x%08x" POSTFIX, al_reg_read32( \
+		&(UDMA->udma_regs->TYPE.GROUP.REG)))
+
+#define AL_UDMA_PRINT_REG_FIELD( \
+		UDMA, PREFIX, POSTFIX, FMT, TYPE, GROUP, REG, LBL, FIELD) \
+	al_dbg(PREFIX #LBL " = " FMT POSTFIX, al_reg_read32( \
+			&(UDMA->udma_regs->TYPE.GROUP.REG)) \
+			& FIELD ## _MASK >> FIELD ## _SHIFT)
+
+#define AL_UDMA_PRINT_REG_BIT( \
+		UDMA, PREFIX, POSTFIX, TYPE, GROUP, REG, LBL, FIELD) \
+	al_dbg(PREFIX #LBL " = %d" POSTFIX, ((al_reg_read32( \
+			&(UDMA->udma_regs->TYPE.GROUP.REG)) \
+			& FIELD) != 0))
+
+/* UDMA register print mask definitions */
+#define AL_UDMA_DEBUG_QUEUE(n)			AL_BIT(n)
+#define AL_UDMA_DEBUG_AXI			AL_BIT(DMA_MAX_Q)
+#define AL_UDMA_DEBUG_GENERAL			AL_BIT(DMA_MAX_Q + 1)
+#define AL_UDMA_DEBUG_READ			AL_BIT(DMA_MAX_Q + 2)
+#define AL_UDMA_DEBUG_WRITE			AL_BIT(DMA_MAX_Q + 3)
+#define AL_UDMA_DEBUG_DWRR			AL_BIT(DMA_MAX_Q + 4)
+#define AL_UDMA_DEBUG_RATE_LIMITER		AL_BIT(DMA_MAX_Q + 5)
+#define AL_UDMA_DEBUG_STREAM_RATE_LIMITER	AL_BIT(DMA_MAX_Q + 6)
+#define AL_UDMA_DEBUG_COMP			AL_BIT(DMA_MAX_Q + 7)
+#define AL_UDMA_DEBUG_STAT			AL_BIT(DMA_MAX_Q + 8)
+#define AL_UDMA_DEBUG_FEATURE			AL_BIT(DMA_MAX_Q + 9)
+#define AL_UDMA_DEBUG_ALL			0xFFFFFFFF
+
+/* Debug functions */
+
+/**
+ * Print udma registers according to the provided mask
+ *
+ * @param udma udma data structure
+ * @param mask mask that specifies which registers groups to print
+ * e.g. AL_UDMA_DEBUG_AXI prints AXI registers, AL_UDMA_DEBUG_ALL prints all
+ * registers
+ */
+void al_udma_regs_print(struct al_udma *udma, unsigned int mask);
+
+/**
+ * Print udma queue software structure
+ *
+ * @param udma udma data structure
+ * @param qid queue index
+ */
+void al_udma_q_struct_print(struct al_udma *udma, uint32_t qid);
+
+/** UDMA ring type */
+enum al_udma_ring_type {
+	AL_RING_SUBMISSION,
+	AL_RING_COMPLETION
+};
+
+/**
+ * Print the ring entries for the specified queue index and ring type
+ * (submission/completion)
+ *
+ * @param udma udma data structure
+ * @param qid queue index
+ * @param rtype udma ring type
+ */
+void al_udma_ring_print(struct al_udma *udma, uint32_t qid,
+		enum al_udma_ring_type rtype);
+
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+}
+#endif
+/* *INDENT-ON* */
+#endif /* __AL_HAL_UDMA_DEBUG_H__ */
+/** @} end of UDMA debug group */
diff --git a/sys/contrib/alpine-hal/al_hal_udma_iofic.c b/sys/contrib/alpine-hal/al_hal_udma_iofic.c
new file mode 100644
index 000000000000..d6ba485296c3
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_iofic.c
@@ -0,0 +1,151 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ *  @{
+ * @file   al_hal_udma_iofic.c
+ *
+ * @brief  unit interrupts configurations
+ *
+ */
+
+#include "al_hal_udma_iofic.h"
+#include "al_hal_udma_regs.h"
+
+/*
+ * configure the interrupt registers, interrupts will are kept masked
+ */
+static int al_udma_main_iofic_config(struct al_iofic_regs __iomem *base,
+				    enum al_iofic_mode mode)
+{
+	switch (mode) {
+	case AL_IOFIC_MODE_LEGACY:
+		al_iofic_config(base, AL_INT_GROUP_A,
+				INT_CONTROL_GRP_SET_ON_POSEDGE |
+				INT_CONTROL_GRP_MASK_MSI_X |
+				INT_CONTROL_GRP_CLEAR_ON_READ);
+		al_iofic_config(base, AL_INT_GROUP_B,
+				INT_CONTROL_GRP_CLEAR_ON_READ |
+				INT_CONTROL_GRP_MASK_MSI_X);
+		al_iofic_config(base, AL_INT_GROUP_C,
+				INT_CONTROL_GRP_CLEAR_ON_READ |
+				INT_CONTROL_GRP_MASK_MSI_X);
+		al_iofic_config(base, AL_INT_GROUP_D,
+				INT_CONTROL_GRP_SET_ON_POSEDGE |
+				INT_CONTROL_GRP_MASK_MSI_X |
+				INT_CONTROL_GRP_CLEAR_ON_READ);
+		break;
+	case AL_IOFIC_MODE_MSIX_PER_Q:
+		al_iofic_config(base, AL_INT_GROUP_A,
+				INT_CONTROL_GRP_SET_ON_POSEDGE |
+				INT_CONTROL_GRP_AUTO_MASK |
+				INT_CONTROL_GRP_AUTO_CLEAR);
+		al_iofic_config(base, AL_INT_GROUP_B,
+				INT_CONTROL_GRP_AUTO_CLEAR |
+				INT_CONTROL_GRP_AUTO_MASK |
+				INT_CONTROL_GRP_CLEAR_ON_READ);
+		al_iofic_config(base, AL_INT_GROUP_C,
+				INT_CONTROL_GRP_AUTO_CLEAR |
+				INT_CONTROL_GRP_AUTO_MASK |
+				INT_CONTROL_GRP_CLEAR_ON_READ);
+		al_iofic_config(base, AL_INT_GROUP_D,
+				INT_CONTROL_GRP_SET_ON_POSEDGE |
+				INT_CONTROL_GRP_CLEAR_ON_READ |
+				INT_CONTROL_GRP_MASK_MSI_X);
+		break;
+	case AL_IOFIC_MODE_MSIX_PER_GROUP:
+		al_iofic_config(base, AL_INT_GROUP_A,
+				INT_CONTROL_GRP_SET_ON_POSEDGE |
+				INT_CONTROL_GRP_AUTO_CLEAR |
+				INT_CONTROL_GRP_AUTO_MASK);
+		al_iofic_config(base, AL_INT_GROUP_B,
+				INT_CONTROL_GRP_CLEAR_ON_READ |
+				INT_CONTROL_GRP_MASK_MSI_X);
+		al_iofic_config(base, AL_INT_GROUP_C,
+				INT_CONTROL_GRP_CLEAR_ON_READ |
+				INT_CONTROL_GRP_MASK_MSI_X);
+		al_iofic_config(base, AL_INT_GROUP_D,
+				INT_CONTROL_GRP_SET_ON_POSEDGE |
+				INT_CONTROL_GRP_CLEAR_ON_READ |
+				INT_CONTROL_GRP_MASK_MSI_X);
+		break;
+	default:
+		al_err("%s: invalid mode (%d)\n", __func__, mode);
+		return -EINVAL;
+	}
+
+	al_dbg("%s: base.%p mode %d\n", __func__, base, mode);
+	return 0;
+}
+
+/*
+ * configure the UDMA interrupt registers, interrupts are kept masked
+ */
+int al_udma_iofic_config(struct unit_regs __iomem *regs, enum al_iofic_mode mode,
+			uint32_t	m2s_errors_disable,
+			uint32_t	m2s_aborts_disable,
+			uint32_t	s2m_errors_disable,
+			uint32_t	s2m_aborts_disable)
+{
+	int rc;
+
+	rc = al_udma_main_iofic_config(&regs->gen.interrupt_regs.main_iofic, mode);
+	if (rc != 0)
+		return rc;
+
+	al_iofic_unmask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_A, ~m2s_errors_disable);
+	al_iofic_abort_mask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_A, m2s_aborts_disable);
+
+	al_iofic_unmask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_B, ~s2m_errors_disable);
+	al_iofic_abort_mask(&regs->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_B, s2m_aborts_disable);
+
+	al_dbg("%s base.%p mode %d\n", __func__, regs, mode);
+	return 0;
+}
+
+/*
+ * return the offset of the unmask register for a given group
+ */
+uint32_t __iomem * al_udma_iofic_unmask_offset_get(
+	struct unit_regs __iomem	*regs,
+	enum al_udma_iofic_level	level,
+	int				group)
+{
+	al_assert(al_udma_iofic_level_and_group_valid(level, group));
+	return al_iofic_unmask_offset_get(al_udma_iofic_reg_base_get(regs, level), group);
+}
+
+/** @} end of UDMA group */
diff --git a/sys/contrib/alpine-hal/al_hal_udma_iofic.h b/sys/contrib/alpine-hal/al_hal_udma_iofic.h
new file mode 100644
index 000000000000..9e7950048374
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_iofic.h
@@ -0,0 +1,614 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_udma_interrupts UDMA I/O Fabric Interrupt Controller
+ * @ingroup group_udma_api
+ *  UDMA IOFIC API
+ *  @{
+ * @file   al_hal_udma_iofic.h
+ *
+ * @brief C Header file for programming the interrupt controller that found
+ * in UDMA based units. These APIs rely and use some the Interrupt controller
+ * API under al_hal_iofic.h
+ */
+
+#ifndef __AL_HAL_UDMA_IOFIC_H__
+#define __AL_HAL_UDMA_IOFIC_H__
+
+#include <al_hal_common.h>
+#include <al_hal_iofic.h>
+#include <al_hal_udma_regs.h>
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/**
+ * Interrupt Mode
+ * This is the interrupt mode for the primary interrupt level The secondary
+ * interrupt level does not have mode and it is always a level sensitive
+ * interrupt that is reflected in group D of the primary.
+ */
+enum al_iofic_mode {
+	AL_IOFIC_MODE_LEGACY, /**< level-sensitive interrupt wire */
+	AL_IOFIC_MODE_MSIX_PER_Q, /**< per UDMA queue MSI-X interrupt */
+	AL_IOFIC_MODE_MSIX_PER_GROUP
+};
+
+/** interrupt controller level (primary/secondary) */
+enum al_udma_iofic_level {
+	AL_UDMA_IOFIC_LEVEL_PRIMARY,
+	AL_UDMA_IOFIC_LEVEL_SECONDARY
+};
+
+/*
+ * The next four groups represents the standard 4 groups in the primary
+ * interrupt controller of each bus-master unit in the I/O Fabric.
+ * The first two groups can be used when accessing the secondary interrupt
+ * controller as well.
+ */
+#define AL_INT_GROUP_A		0 /**< summary of the below events */
+#define AL_INT_GROUP_B		1 /**< RX completion queues */
+#define AL_INT_GROUP_C		2 /**< TX completion queues */
+#define AL_INT_GROUP_D		3 /**< Misc */
+
+/*******************************************************************************
+ * Primary interrupt controller, group A bits
+ ******************************************************************************/
+/* Group A bits which are just summary bits of GROUP B, C and D */
+#define AL_INT_GROUP_A_GROUP_B_SUM	AL_BIT(0)
+#define AL_INT_GROUP_A_GROUP_C_SUM	AL_BIT(1)
+#define AL_INT_GROUP_A_GROUP_D_SUM	AL_BIT(2)
+
+/*******************************************************************************
+ * MSIX entry indices
+ ******************************************************************************/
+/** MSIX entry index for summary of group D in group A */
+#define AL_INT_MSIX_GROUP_A_SUM_D_IDX 	2
+/** MSIX entry index for RX completion queue 0 */
+#define AL_INT_MSIX_RX_COMPLETION_START	3
+
+/*******************************************************************************
+ * Primary interrupt controller, group D bits
+ ******************************************************************************/
+#define AL_INT_GROUP_D_CROSS_MAIL_BOXES	\
+			(AL_BIT(0) | AL_BIT(1) | AL_BIT(2) | AL_BIT(3))
+/** Summary of secondary interrupt controller, group A) */
+#define AL_INT_GROUP_D_M2S	AL_BIT(8)
+/** Summary of secondary interrupt controller, group B) */
+#define AL_INT_GROUP_D_S2M	AL_BIT(9)
+#define AL_INT_GROUP_D_SW_TIMER_INT	AL_BIT(10)
+#define AL_INT_GROUP_D_APP_EXT_INT	AL_BIT(11)
+#define AL_INT_GROUP_D_ALL			\
+			AL_INT_GROUP_D_CROSS_MAIL_BOXES | \
+			AL_INT_GROUP_D_M2S | \
+			AL_INT_GROUP_D_S2M | \
+			AL_INT_GROUP_D_SW_TIMER_INT | \
+			AL_INT_GROUP_D_APP_EXT_INT
+
+/*
+ * Until this point, all description above is for Groups A/B/C/D in the PRIMARY
+ * Interrupt controller.
+ * Following are definitions related to the secondary interrupt controller with
+ * two cause registers (group A and group B) that covers UDMA M2S/S2M errors.
+ * Secondary interrupt controller summary bits are not mapped to the Processor
+ * GIC directly, rather they are represented in Group D of the primary interrupt
+ * controller.
+ */
+
+/******************************************************************************
+ * Secondary interrupt Controller, Group A, which holds the TX (M2S) error
+ * interrupt bits
+ ******************************************************************************/
+
+/**
+ * MSIx response
+ * MSIX Bus generator response error, the Bus response received with error indication
+ */
+#define AL_INT_2ND_GROUP_A_M2S_MSIX_RESP		AL_BIT(27)
+/**
+ * MSIx timeout	MSIX Bus generator timeout error.
+ * The generator didn't receive bus response for the MSIx write transaction.
+ */
+#define AL_INT_2ND_GROUP_A_M2S_MSIX_TO			AL_BIT(26)
+/** Prefetch header buffer parity error */
+#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_HDR_PARITY	AL_BIT(25)
+/** Prefetch descriptor buffer parity error */
+#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_DESC_PARITY	AL_BIT(24)
+/** Data buffer parity error */
+#define AL_INT_2ND_GROUP_A_M2S_DATA_PARITY		AL_BIT(23)
+/** Data header buffer parity error */
+#define AL_INT_2ND_GROUP_A_M2S_HDR_PARITY		AL_BIT(22)
+/** Completion coalescing buffer parity error */
+#define AL_INT_2ND_GROUP_A_M2S_COMPL_COAL_PARITY	AL_BIT(21)
+/** UNACK packets buffer parity error */
+#define AL_INT_2ND_GROUP_A_M2S_UNACK_PKT_PARITY		AL_BIT(20)
+/** ACK packets buffer parity error */
+#define AL_INT_2ND_GROUP_A_M2S_ACK_PKT_PARITY		AL_BIT(19)
+/** AXI data buffer parity error */
+#define AL_INT_2ND_GROUP_A_M2S_AX_DATA_PARITY		AL_BIT(18)
+/**
+ * Prefetch Ring ID error
+ * A wrong RingId was received while prefetching submission descriptor. This
+ * could indicate a software bug or hardware failure, unless the UDMA is
+ * working in a mode to ignore RingId (the al_udma_iofic_config() API can be
+ * used to configure the UDMA to ignore the Ring ID check)
+ */
+#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_RING_ID		AL_BIT(17)
+/**
+ * Prefetch last
+ * Error in last bit indication of the descriptor
+ * Descriptor with Last bit asserted is read from the queue to the prefetch
+ * FIFO when the prefetch engine is not in a middle of packet processing (a
+ * descriptor with First bit asserted should be read first to indicate start of
+ * packet)
+ */
+#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_LAST		AL_BIT(16)
+/**
+ * Prefetch first
+ * Error in first bit indication of the descriptor
+ * Descriptor with First bit asserted is read from the queue to the prefetch
+ * FIFO while the prefetch engine is in a middle of packet processing ( a
+ * descriptor with Last bit asserted should be read to indicate end of packet
+ * before starting a new one)
+ */
+#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_FIRST		AL_BIT(15)
+/**
+ * Prefetch max descriptors
+ * Number of descriptors per packet exceeds the configurable maximum
+ * descriptors per packet. This could indicate a software bug or a hardware
+ * failure.  (The al_udma_m2s_max_descs_set() API is used to configure the
+ * maximum descriptors per packet)
+ */
+#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_MAX_DESC	AL_BIT(14)
+/**
+ * Packet length
+ * Packet length exceeds the configurable maximum packet size.  The
+ * al_udma_m2s_packet_size_cfg_set() API is used to configure the maximum
+ * packet size)
+ */
+#define AL_INT_2ND_GROUP_A_M2S_PKT_LEN			AL_BIT(13)
+/**
+ * Prefetch AXI timeout
+ * Bus request to I/O Fabric timeout error
+ */
+#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_AXI_TO		AL_BIT(12)
+/**
+ * Prefetch AXI response
+ * Bus response from I/O Fabric error
+ */
+#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_AXI_RESP	AL_BIT(11)
+/**
+ * Prefetch AXI parity
+ * Bus parity error on descriptor being prefetched
+ */
+#define AL_INT_2ND_GROUP_A_M2S_PREFETCH_AXI_PARITY	AL_BIT(10)
+/**
+ * Data AXI timeout
+ * Bus request to I/O Fabric timeout error
+ */
+#define AL_INT_2ND_GROUP_A_M2S_DATA_AXI_TO		AL_BIT(9)
+/**
+ * Data AXI response
+ * Bus response from I/O Fabric error
+ */
+#define AL_INT_2ND_GROUP_A_M2S_DATA_AXI_RESP		AL_BIT(8)
+/**
+ * Data AXI parity
+ * Bus parity error on data being read
+ */
+#define AL_INT_2ND_GROUP_A_M2S_DATA_AXI_PARITY		AL_BIT(7)
+/**
+ * Completion AXI timeout
+ * Bus request to I/O Fabric timeout error
+ */
+#define AL_INT_2ND_GROUP_A_M2S_CONPL_AXI_TO		AL_BIT(6)
+/**
+ * Completion AXI response
+ * Bus response from I/O Fabric error
+ */
+#define AL_INT_2ND_GROUP_A_M2S_COMPL_AXI_RESP		AL_BIT(5)
+/**
+ * Completion AXI parity
+ * Bus generator internal SRAM parity error
+ */
+#define AL_INT_2ND_GROUP_A_M2S_COMP_AXI_PARITY		AL_BIT(4)
+/**
+ * Stream timeout
+ * Application stream interface timeout indicating a failure at the Application
+ * layer (RAID, Ethernet etc)
+ */
+#define AL_INT_2ND_GROUP_A_M2S_STRM_TO			AL_BIT(3)
+/**
+ * Stream response
+ * Application stream interface response error indicating a failure at the
+ * Application layer (RAID, Ethernet etc)
+ */
+#define AL_INT_2ND_GROUP_A_M2S_STRM_RESP		AL_BIT(2)
+/**
+ * Stream parity
+ * Application stream interface parity error indicating a failure at the
+ * Application layer (RAID, Ethernet etc)
+ */
+#define AL_INT_2ND_GROUP_A_M2S_STRM_PARITY		 AL_BIT(1)
+/**
+ * Stream completion mismatch
+ * Application stream interface, packet serial mismatch error indicating a
+ * failure at the Application layer (RAID, Ethernet etc)
+ */
+#define AL_INT_2ND_GROUP_A_M2S_STRM_COMPL_MISMATCH	AL_BIT(0)
+
+/*******************************************************************************
+ * Secondary interrupt Controller, Group B, which holds the RX (S2M) error
+ * interrupt bits
+ ******************************************************************************/
+
+/** Prefetch descriptor buffer parity error */
+#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_DESC_PARITY	AL_BIT(30)
+/** Completion coalescing buffer parity error */
+#define AL_INT_2ND_GROUP_B_S2M_COMPL_COAL_PARITY	AL_BIT(29)
+/** PRE-UNACK packets buffer parity error */
+#define AL_INT_2ND_GROUP_B_S2M_PRE_UNACK_PKT_PARITY	AL_BIT(28)
+/** UNACK packets buffer parity error */
+#define AL_INT_2ND_GROUP_B_S2M_UNACK_PKT_PARITY		AL_BIT(27)
+/** Data buffer parity error */
+#define AL_INT_2ND_GROUP_B_S2M_DATA_PARITY		AL_BIT(26)
+/** Data header buffer parity error */
+#define AL_INT_2ND_GROUP_B_S2M_DATA_HDR_PARITY		AL_BIT(25)
+/**
+ * Packet length
+ * Application stream interface, Data counter length mismatch with metadata
+ * packet length indicating a failure at the Application layer (RAID, Ethernet
+ * etc)
+ */
+#define AL_INT_2ND_GROUP_B_S2M_PKT_LEN			AL_BIT(24)
+/**
+ * Stream last
+ * Application stream interface, error in Last bit indication, this error is
+ * asserted when a 'last' indication is asserted on the stream interface
+ * (between the application and the UDMA) when the interface is not in the
+ * middle of packet, meaning that there was no 'first' indication before. This
+ * indicates a failure at the application layer.
+ */
+#define AL_INT_2ND_GROUP_B_S2M_STRM_LAST		AL_BIT(23)
+/**
+ * Stream first
+ * Application stream interface error in first bit indication, this error is
+ * asserted when a 'first' indication is asserted on the stream interface
+ * (between the application and the UDMA) when the interface is in the middle
+ * of packet, meaning that there was a 'first' indication before and the UDMA
+ * is waiting for a 'last' indication to end the packet. This indicates a
+ * failure at the application layer.
+ */
+#define AL_INT_2ND_GROUP_B_S2M_STRM_FIRST		AL_BIT(22)
+/**
+ * Stream data
+ * Application stream interface, error indication during data transaction
+ */
+#define AL_INT_2ND_GROUP_B_S2M_STRM_DATA		AL_BIT(21)
+/**
+ * Stream Data parity
+ * Application stream interface, parity error during data transaction
+ */
+#define AL_INT_2ND_GROUP_B_S2M_STRM_DATA_PARITY		AL_BIT(20)
+/**
+ * Stream Header error
+ * Application stream interface, error indication during header transaction
+ */
+#define AL_INT_2ND_GROUP_B_S2M_STRM_HDR			AL_BIT(19)
+/**
+ * Stream Header parity
+ * Application stream interface, parity error during header transaction
+ */
+#define AL_INT_2ND_GROUP_B_S2M_STRM_HDR_PARITY		AL_BIT(18)
+/**
+ * Completion UNACK
+ * Completion write, UNACK timeout due to completion FIFO back pressure
+ */
+#define AL_INT_2ND_GROUP_B_S2M_COMPL_UNACK		AL_BIT(17)
+/**
+ * Completion stream
+ * Completion write, UNACK timeout due to stream ACK FIFO back pressure
+ */
+#define AL_INT_2ND_GROUP_B_S2M_COMPL_STRM		AL_BIT(16)
+/**
+ * Completion AXI timeout
+ * Bus request to I/O Fabric timeout error
+ */
+#define AL_INT_2ND_GROUP_B_S2M_COMPL_AXI_TO		AL_BIT(15)
+/**
+ * Completion AXI response
+ * Bus response from I/O Fabric error
+ */
+#define AL_INT_2ND_GROUP_B_S2M_COMPL_AXI_RESP		AL_BIT(14)
+/**
+ * Completion AXI parity
+ * Completion Bus generator internal SRAM parity error
+ */
+#define AL_INT_2ND_GROUP_B_S2M_COMPL_AXI_PARITY		AL_BIT(13)
+/**
+ * Prefetch saturate
+ * Prefetch engine, packet length counter saturated (32 bit) , this is caused
+ * by an error at the application layer which sends packet data without
+ * 'last'/'first' indication.
+ */
+#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_SAT		AL_BIT(12)
+/**
+ * Prefetch ring ID
+ * Prefetch engine, Ring ID is not matching the expected RingID. This could
+ * indicate a software bug or hardware failure, unless the UDMA is working in a
+ * mode to ignore RingId  (the al_udma_iofic_config() API can be used to
+ * configure the UDMA to ignore the Ring ID check)
+ */
+#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_RING_ID		AL_BIT(11)
+/**
+ * Prefetch AXI timeout
+ * Bus request to I/O Fabric timeout error
+ */
+#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_AXI_TO		AL_BIT(10)
+/**
+ * Prefetch AXI response
+ * Bus response from I/O Fabric error
+ */
+#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_AXI_RESP	AL_BIT(9)
+/**
+ * Prefetch AXI parity
+ * Bus parity error on descriptor being prefetched
+ */
+#define AL_INT_2ND_GROUP_B_S2M_PREFETCH_AXI_PARITY	AL_BIT(8)
+/**
+ * No descriptors hint
+ * Data write, Hint to the SW that there are not enough descriptors in the
+ * queue for the current received packet. This is considered a hint and not an
+ * error, as it could be a normal situation in certain application. The S2M
+ * UDMA behavior when it runs out of Rx Descriptor is controlled by driver
+ * which can use this hint to add more descriptors to the Rx queue.
+ */
+#define AL_INT_2ND_GROUP_B_S2M_NO_DESC_HINT		AL_BIT(7)
+/**
+ * No descriptors timeout
+ * Data write, Timeout indication when there are not enough descriptors for the
+ * current packet and the timeout expires. The S2M UDMA behavior when it runs
+ * out of Rx Descriptor is controlled by driver which can use this hint to add
+ * more descriptors to the Rx queue. The al_udma_s2m_no_desc_cfg_set() is used
+ * to configure theUDMA S2M timeout and behavior when there are no Rx
+ * descriptors for the received packet.
+ */
+#define AL_INT_2ND_GROUP_B_S2M_NO_DESC_TO		AL_BIT(6)
+/**
+ * Promotion indication
+ * Data write, the data write engine checks the queue number of the two packets
+ * at the head of the data FIFO, the data write engine notify the prefetch
+ * engine to promote these queue numbers in the prefetch scheduler to make sure
+ * that these queue will have RX descriptors for these packets. This error
+ * indicates that the prefetch promotion didn't work for the second packet in
+ * the FIFO. This is an indication used for system debug and not an error.
+ */
+#define AL_INT_2ND_GROUP_B_S2M_PROM_IND			AL_BIT(5)
+/**
+ * Header split ignored
+ * Data write, The application requested header split but the buffer descriptor
+ * doesn't include a second buffer for the header
+ */
+#define AL_INT_2ND_GROUP_B_S2M_HDR_SPLT_IGNORED		AL_BIT(4)
+/**
+ * Header split length
+ * Data write, The application requested header split and the length of the
+ * second buffer allocated for the header is not enough for the requested
+ * header length. The remaining of the header is written to buffer 1 (data
+ * buffer).
+ */
+#define AL_INT_2ND_GROUP_B_S2M_HDR_SPLT_LEN		AL_BIT(3)
+/**
+ * Data AXI timeout
+ * Bus request to I/O Fabric timeout error
+ */
+#define AL_INT_2ND_GROUP_B_S2M_DATA_AXI_TO		AL_BIT(2)
+/**
+ * Data AXI response
+ * Bus response from I/O Fabric error
+ */
+#define AL_INT_2ND_GROUP_B_S2M_DATA_AXI_RESP		AL_BIT(1)
+/**
+ * Data AXI parity
+ * Bus parity error on data being read
+ */
+#define AL_INT_2ND_GROUP_B_S2M_DATA_AXI_PARITY		AL_BIT(0)
+
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/**
+ * Configure the UDMA interrupt controller registers, interrupts will are kept
+ * masked.
+ * This is a static setting that should be called while initialized the
+ * interrupt controller within a given UDMA, and should not be modified during
+ * runtime unless the UDMA is completely disabled. The first argument sets the
+ * interrupt and MSIX modes. The m2s/s2m errors/abort are a set of bit-wise
+ * masks to define the behaviour of the UDMA once an error happens: The _abort
+ * will put the UDMA in abort state once an error happens The _error bitmask
+ * will indicate and error in the secondary cause register but will not abort.
+ * The bit-mask that the _errors_disable and _aborts_disable are described in
+ * 'AL_INT_2ND_GROUP_A_*' and 'AL_INT_2ND_GROUP_B_*'
+ *
+ * @param regs pointer to unit registers
+ * @param mode interrupt scheme mode (legacy, MSI-X..)
+ * @param m2s_errors_disable
+ * 	  This is a bit-wise mask, to indicate which one of the error causes in
+ * 	  secondary interrupt group_A should generate an interrupt. When a bit is
+ * 	  set, the error cause is ignored.
+ * 	  Recommended value: 0 (enable all errors).
+ * @param m2s_aborts_disable
+ * 	  This is a bit-wise mask, to indicate which one of the error causes in
+ * 	  secondary interrupt group_A should automatically put the UDMA in
+ * 	  abort state. When a bit is set, the error cause does cause an abort.
+ * 	  Recommended value: 0 (enable all aborts).
+ * @param s2m_errors_disable
+ * 	  This is a bit-wise mask, to indicate which one of the error causes in
+ * 	  secondary interrupt group_A should generate an interrupt. When a bit is
+ * 	  set, the error cause is ignored.
+ * 	  Recommended value: 0xE0 (disable hint errors).
+ * @param s2m_aborts_disable
+ * 	  This is a bit-wise mask, to indicate which one of the error causes in
+ * 	  secondary interrupt group_A should automatically put the UDMA in
+ * 	  abort state. When a bit is set, the error cause does cause an abort.
+ * 	  Recommended value: 0xE0 (disable hint aborts).
+ *
+ * @return 0 on success. -EINVAL otherwise.
+ */
+int al_udma_iofic_config(struct unit_regs __iomem *regs,
+			enum al_iofic_mode mode,
+			uint32_t	m2s_errors_disable,
+			uint32_t	m2s_aborts_disable,
+			uint32_t	s2m_errors_disable,
+			uint32_t	s2m_aborts_disable);
+/**
+ * return the offset of the unmask register for a given group.
+ * this function can be used when the upper layer wants to directly
+ * access the unmask regiter and bypass the al_udma_iofic_unmask() API.
+ *
+ * @param regs pointer to udma registers
+ * @param level the interrupt controller level (primary / secondary)
+ * @param group the interrupt group ('AL_INT_GROUP_*')
+ * @return the offset of the unmask register.
+ */
+uint32_t __iomem * al_udma_iofic_unmask_offset_get(
+	struct unit_regs __iomem	*regs,
+	enum al_udma_iofic_level	level,
+	int				group);
+
+/**
+ * Get the interrupt controller base address for either the primary or secondary
+ * interrupt controller
+ *
+ * @param regs pointer to udma unit registers
+ * @param level the interrupt controller level (primary / secondary)
+ *
+ * @returns	The interrupt controller base address
+ *
+ */
+static INLINE void __iomem *al_udma_iofic_reg_base_get(
+	struct unit_regs __iomem	*regs,
+	enum al_udma_iofic_level	level)
+{
+	void __iomem *iofic_regs = (level == AL_UDMA_IOFIC_LEVEL_PRIMARY) ?
+		(void __iomem *)&regs->gen.interrupt_regs.main_iofic :
+		(void __iomem *)&regs->gen.interrupt_regs.secondary_iofic_ctrl;
+
+	return iofic_regs;
+}
+
+/**
+ * Check the interrupt controller level/group validity
+ *
+ * @param level the interrupt controller level (primary / secondary)
+ * @param group the interrupt group ('AL_INT_GROUP_*')
+ *
+ * @returns	0 - invalid, 1 - valid
+ *
+ */
+static INLINE int al_udma_iofic_level_and_group_valid(
+	enum al_udma_iofic_level	level,
+	int				group)
+{
+	if (((level == AL_UDMA_IOFIC_LEVEL_PRIMARY) && (group >= 0) && (group < 4)) ||
+		((level == AL_UDMA_IOFIC_LEVEL_SECONDARY) && (group >= 0) && (group < 2)))
+		return 1;
+
+	return 0;
+}
+/**
+ * unmask specific interrupts for a given group
+ * this functions uses the interrupt mask clear register to guarantee atomicity
+ * it's safe to call it while the mask is changed by the HW (auto mask) or another cpu.
+ *
+ * @param regs pointer to udma unit registers
+ * @param level the interrupt controller level (primary / secondary)
+ * @param group the interrupt group ('AL_INT_GROUP_*')
+ * @param mask bitwise of interrupts to unmask, set bits will be unmasked.
+ */
+static INLINE void al_udma_iofic_unmask(
+	struct unit_regs __iomem	*regs,
+	enum al_udma_iofic_level	level,
+	int				group,
+	uint32_t			mask)
+{
+	al_assert(al_udma_iofic_level_and_group_valid(level, group));
+	al_iofic_unmask(al_udma_iofic_reg_base_get(regs, level), group, mask);
+}
+
+/**
+ * mask specific interrupts for a given group
+ * this functions modifies interrupt mask register, the callee must make sure
+ * the mask is not changed by another cpu.
+ *
+ * @param regs pointer to udma unit registers
+ * @param level the interrupt controller level (primary / secondary)
+ * @param group the interrupt group ('AL_INT_GROUP_*')
+ * @param mask bitwise of interrupts to mask, set bits will be masked.
+ */
+static INLINE void al_udma_iofic_mask(
+	struct unit_regs __iomem	*regs,
+	enum al_udma_iofic_level	level,
+	int				group,
+	uint32_t			mask)
+{
+	al_assert(al_udma_iofic_level_and_group_valid(level, group));
+	al_iofic_mask(al_udma_iofic_reg_base_get(regs, level), group, mask);
+}
+
+/**
+ * read interrupt cause register for a given group
+ * this will clear the set bits if the Clear on Read mode enabled.
+ * @param regs pointer to udma unit registers
+ * @param level the interrupt controller level (primary / secondary)
+ * @param group the interrupt group ('AL_INT_GROUP_*')
+ */
+static INLINE uint32_t al_udma_iofic_read_cause(
+	struct unit_regs __iomem	*regs,
+	enum al_udma_iofic_level	level,
+	int				group)
+{
+	al_assert(al_udma_iofic_level_and_group_valid(level, group));
+	return al_iofic_read_cause(al_udma_iofic_reg_base_get(regs, level), group);
+}
+
+#endif
+/** @} end of UDMA group */
diff --git a/sys/contrib/alpine-hal/al_hal_udma_iofic_regs.h b/sys/contrib/alpine-hal/al_hal_udma_iofic_regs.h
new file mode 100644
index 000000000000..8e53aa673cce
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_iofic_regs.h
@@ -0,0 +1,66 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+#ifndef __AL_HAL_UDMA_IOFIC_REG_H
+#define __AL_HAL_UDMA_IOFIC_REG_H
+
+#include "al_hal_iofic_regs.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This structure covers all interrupt registers of a given UDMA, which is
+ * built of an al_iofic_regs, which is the common I/O Fabric Interrupt
+ * controller (IOFIC), and additional two interrupts groups dedicated for the
+ * application-specific engine attached to the UDMA, the interrupt summary
+ * of those two groups routed to gourp D of the main controller.
+ */
+struct udma_iofic_regs {
+	struct al_iofic_regs	main_iofic;
+	uint32_t rsrvd1[(0x1c00) >> 2];
+	struct al_iofic_grp_ctrl secondary_iofic_ctrl[2];
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_UDMA_IOFIC_REG_H */
+
+
+
+
diff --git a/sys/contrib/alpine-hal/al_hal_udma_main.c b/sys/contrib/alpine-hal/al_hal_udma_main.c
new file mode 100644
index 000000000000..6e9919b3596c
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_main.c
@@ -0,0 +1,618 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ *  @{
+ * @file   al_hal_udma_main.c
+ *
+ * @brief  Universal DMA HAL driver for main functions (initialization, data path)
+ *
+ */
+
+#include <al_hal_udma.h>
+#include <al_hal_udma_config.h>
+
+#define AL_UDMA_Q_RST_TOUT	10000	/* Queue reset timeout [uSecs] */
+
+#define UDMA_STATE_IDLE		0x0
+#define UDMA_STATE_NORMAL	0x1
+#define UDMA_STATE_ABORT	0x2
+#define UDMA_STATE_RESERVED	0x3
+
+const char *const al_udma_states_name[] = {
+	"Disable",
+	"Idle",
+	"Normal",
+	"Abort",
+	"Reset"
+};
+
+#define AL_UDMA_INITIAL_RING_ID	1
+
+/*  dma_q flags */
+#define AL_UDMA_Q_FLAGS_IGNORE_RING_ID	AL_BIT(0)
+#define AL_UDMA_Q_FLAGS_NO_COMP_UPDATE	AL_BIT(1)
+#define AL_UDMA_Q_FLAGS_EN_COMP_COAL	AL_BIT(2)
+
+
+static void al_udma_set_defaults(struct al_udma *udma)
+{
+	uint32_t tmp;
+	uint8_t rev_id = udma->rev_id;
+
+	if (udma->type == UDMA_TX) {
+		struct unit_regs* tmp_unit_regs =
+			(struct unit_regs*)udma->udma_regs;
+
+		/* Setting the data fifo depth to 4K (256 strips of 16B)
+		 * This allows the UDMA to have 16 outstanding writes */
+		if (rev_id >= AL_UDMA_REV_ID_2) {
+			al_reg_write32_masked(&tmp_unit_regs->m2s.m2s_rd.data_cfg,
+			      UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK,
+			      256 << UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_SHIFT);
+		}
+
+		if (rev_id == AL_UDMA_REV_ID_0)
+			/* disable AXI timeout for M0*/
+			al_reg_write32(&tmp_unit_regs->gen.axi.cfg_1, 0);
+		else
+			/* set AXI timeout to 1M (~2.6 ms) */
+			al_reg_write32(&tmp_unit_regs->gen.axi.cfg_1, 1000000);
+
+		al_reg_write32(&tmp_unit_regs->m2s.m2s_comp.cfg_application_ack
+					, 0); /* Ack time out */
+
+
+		if (rev_id == AL_UDMA_REV_ID_0) {
+			tmp = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1);
+			tmp &= ~UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
+			tmp |= 4 << UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_SHIFT;
+			al_reg_write32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1
+									, tmp);
+		}
+
+	}
+	if (udma->type == UDMA_RX) {
+		al_reg_write32(
+			&udma->udma_regs->s2m.s2m_comp.cfg_application_ack, 0);
+					/* Ack time out */
+
+	}
+}
+/**
+ * misc queue configurations
+ *
+ * @param udma_q udma queue data structure
+ *
+ * @return 0
+ */
+static int al_udma_q_config(struct al_udma_q *udma_q)
+{
+	uint32_t *reg_addr;
+	uint32_t val;
+
+	if (udma_q->udma->type == UDMA_TX) {
+		reg_addr = &udma_q->q_regs->m2s_q.rlimit.mask;
+
+		val = al_reg_read32(reg_addr);
+		// enable DMB
+		val &= ~UDMA_M2S_Q_RATE_LIMIT_MASK_INTERNAL_PAUSE_DMB;
+		al_reg_write32(reg_addr, val);
+	}
+	return 0;
+}
+
+/**
+ * set the queue's completion configuration register
+ *
+ * @param udma_q udma queue data structure
+ *
+ * @return 0
+ */
+static int al_udma_q_config_compl(struct al_udma_q *udma_q)
+{
+	uint32_t *reg_addr;
+	uint32_t val;
+
+	if (udma_q->udma->type == UDMA_TX)
+		reg_addr = &udma_q->q_regs->m2s_q.comp_cfg;
+	else
+		reg_addr = &udma_q->q_regs->s2m_q.comp_cfg;
+
+	val = al_reg_read32(reg_addr);
+
+	if (udma_q->flags & AL_UDMA_Q_FLAGS_NO_COMP_UPDATE)
+		val &= ~UDMA_M2S_Q_COMP_CFG_EN_COMP_RING_UPDATE;
+	else
+		val |= UDMA_M2S_Q_COMP_CFG_EN_COMP_RING_UPDATE;
+
+	if (udma_q->flags & AL_UDMA_Q_FLAGS_EN_COMP_COAL)
+		val &= ~UDMA_M2S_Q_COMP_CFG_DIS_COMP_COAL;
+	else
+		val |= UDMA_M2S_Q_COMP_CFG_DIS_COMP_COAL;
+
+	al_reg_write32(reg_addr, val);
+
+	/* set the completion queue size */
+	if (udma_q->udma->type == UDMA_RX) {
+		val = al_reg_read32(
+				&udma_q->udma->udma_regs->s2m.s2m_comp.cfg_1c);
+		val &= ~UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK;
+		/* the register expects it to be in words */
+		val |= (udma_q->cdesc_size >> 2)
+				& UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK;
+		al_reg_write32(&udma_q->udma->udma_regs->s2m.s2m_comp.cfg_1c
+							, val);
+	}
+	return 0;
+}
+
+/**
+ * reset the queues pointers (Head, Tail, etc) and set the base addresses
+ *
+ * @param udma_q udma queue data structure
+ */
+static int al_udma_q_set_pointers(struct al_udma_q *udma_q)
+{
+	/* reset the descriptors ring pointers */
+	/* assert descriptor base address aligned. */
+	al_assert((AL_ADDR_LOW(udma_q->desc_phy_base) &
+		   ~UDMA_M2S_Q_TDRBP_LOW_ADDR_MASK) == 0);
+	al_reg_write32(&udma_q->q_regs->rings.drbp_low,
+		       AL_ADDR_LOW(udma_q->desc_phy_base));
+	al_reg_write32(&udma_q->q_regs->rings.drbp_high,
+		       AL_ADDR_HIGH(udma_q->desc_phy_base));
+
+	al_reg_write32(&udma_q->q_regs->rings.drl, udma_q->size);
+
+	/* if completion ring update disabled */
+	if (udma_q->cdesc_base_ptr == NULL) {
+		udma_q->flags |= AL_UDMA_Q_FLAGS_NO_COMP_UPDATE;
+	} else {
+		/* reset the completion descriptors ring pointers */
+		/* assert completion base address aligned. */
+		al_assert((AL_ADDR_LOW(udma_q->cdesc_phy_base) &
+			   ~UDMA_M2S_Q_TCRBP_LOW_ADDR_MASK) == 0);
+		al_reg_write32(&udma_q->q_regs->rings.crbp_low,
+			       AL_ADDR_LOW(udma_q->cdesc_phy_base));
+		al_reg_write32(&udma_q->q_regs->rings.crbp_high,
+			       AL_ADDR_HIGH(udma_q->cdesc_phy_base));
+	}
+	al_udma_q_config_compl(udma_q);
+	return 0;
+}
+
+/**
+ * enable/disable udma queue
+ *
+ * @param udma_q udma queue data structure
+ * @param enable none zero value enables the queue, zero means disable
+ *
+ * @return 0
+ */
+static int al_udma_q_enable(struct al_udma_q *udma_q, int enable)
+{
+	uint32_t reg = al_reg_read32(&udma_q->q_regs->rings.cfg);
+
+	if (enable) {
+		reg |= (UDMA_M2S_Q_CFG_EN_PREF | UDMA_M2S_Q_CFG_EN_SCHEDULING);
+		udma_q->status = AL_QUEUE_ENABLED;
+	} else {
+		reg &= ~(UDMA_M2S_Q_CFG_EN_PREF | UDMA_M2S_Q_CFG_EN_SCHEDULING);
+		udma_q->status = AL_QUEUE_DISABLED;
+	}
+	al_reg_write32(&udma_q->q_regs->rings.cfg, reg);
+	return 0;
+}
+
+
+/************************ API functions ***************************************/
+
+/* Initializations functions */
+/*
+ * Initialize the udma engine
+ */
+int al_udma_init(struct al_udma *udma, struct al_udma_params *udma_params)
+{
+	int i;
+
+	al_assert(udma);
+
+	if (udma_params->num_of_queues > DMA_MAX_Q) {
+		al_err("udma: invalid num_of_queues parameter\n");
+		return -EINVAL;
+	}
+
+	udma->type = udma_params->type;
+	udma->num_of_queues = udma_params->num_of_queues;
+	udma->gen_regs = &udma_params->udma_regs_base->gen;
+
+	if (udma->type == UDMA_TX)
+		udma->udma_regs = (union udma_regs *)&udma_params->udma_regs_base->m2s;
+	else
+		udma->udma_regs = (union udma_regs *)&udma_params->udma_regs_base->s2m;
+
+	udma->rev_id = al_udma_get_revision(udma_params->udma_regs_base);
+
+	if (udma_params->name == NULL)
+		udma->name = "";
+	else
+		udma->name = udma_params->name;
+
+	udma->state = UDMA_DISABLE;
+	for (i = 0; i < DMA_MAX_Q; i++) {
+		udma->udma_q[i].status = AL_QUEUE_NOT_INITIALIZED;
+	}
+	/* initialize configuration registers to correct values */
+	al_udma_set_defaults(udma);
+	al_dbg("udma [%s] initialized. base %p\n", udma->name,
+		udma->udma_regs);
+	return 0;
+}
+
+/*
+ * Initialize the udma queue data structure
+ */
+int al_udma_q_init(struct al_udma *udma, uint32_t qid,
+					struct al_udma_q_params *q_params)
+{
+	struct al_udma_q *udma_q;
+
+	al_assert(udma);
+	al_assert(q_params);
+
+	if (qid >= udma->num_of_queues) {
+		al_err("udma: invalid queue id (%d)\n", qid);
+		return -EINVAL;
+	}
+
+	if (udma->udma_q[qid].status == AL_QUEUE_ENABLED) {
+		al_err("udma: queue (%d) already enabled!\n", qid);
+		return -EIO;
+	}
+
+	if (q_params->size < AL_UDMA_MIN_Q_SIZE) {
+		al_err("udma: queue (%d) size too small\n", qid);
+		return -EINVAL;
+	}
+
+	if (q_params->size > AL_UDMA_MAX_Q_SIZE) {
+		al_err("udma: queue (%d) size too large\n", qid);
+		return -EINVAL;
+	}
+
+	if (q_params->size & (q_params->size - 1)) {
+		al_err("udma: queue (%d) size (%d) must be power of 2\n",
+			 q_params->size, qid);
+		return -EINVAL;
+	}
+
+	udma_q = &udma->udma_q[qid];
+	/* set the queue's regs base address */
+	if (udma->type == UDMA_TX)
+		udma_q->q_regs = (union udma_q_regs __iomem *)
+					&udma->udma_regs->m2s.m2s_q[qid];
+	else
+		udma_q->q_regs = (union udma_q_regs __iomem *)
+					&udma->udma_regs->s2m.s2m_q[qid];
+
+	udma_q->adapter_rev_id = q_params->adapter_rev_id;
+	udma_q->size = q_params->size;
+	udma_q->size_mask = q_params->size - 1;
+	udma_q->desc_base_ptr = q_params->desc_base;
+	udma_q->desc_phy_base = q_params->desc_phy_base;
+	udma_q->cdesc_base_ptr = q_params->cdesc_base;
+	udma_q->cdesc_phy_base = q_params->cdesc_phy_base;
+	udma_q->cdesc_size = q_params->cdesc_size;
+
+	udma_q->next_desc_idx = 0;
+	udma_q->next_cdesc_idx = 0;
+	udma_q->end_cdesc_ptr = (uint8_t *) udma_q->cdesc_base_ptr +
+	    (udma_q->size - 1) * udma_q->cdesc_size;
+	udma_q->comp_head_idx = 0;
+	udma_q->comp_head_ptr = (union al_udma_cdesc *)udma_q->cdesc_base_ptr;
+	udma_q->desc_ring_id = AL_UDMA_INITIAL_RING_ID;
+	udma_q->comp_ring_id = AL_UDMA_INITIAL_RING_ID;
+#if 0
+	udma_q->desc_ctrl_bits = AL_UDMA_INITIAL_RING_ID <<
+						AL_M2S_DESC_RING_ID_SHIFT;
+#endif
+	udma_q->pkt_crnt_descs = 0;
+	udma_q->flags = 0;
+	udma_q->status = AL_QUEUE_DISABLED;
+	udma_q->udma = udma;
+	udma_q->qid = qid;
+
+	/* start hardware configuration: */
+	al_udma_q_config(udma_q);
+	/* reset the queue pointers */
+	al_udma_q_set_pointers(udma_q);
+
+	/* enable the q */
+	al_udma_q_enable(udma_q, 1);
+
+	al_dbg("udma [%s %d]: %s q init. size 0x%x\n"
+			"  desc ring info: phys base 0x%llx virt base %p\n"
+			"  cdesc ring info: phys base 0x%llx virt base %p "
+				"entry size 0x%x",
+			udma_q->udma->name, udma_q->qid,
+			udma->type == UDMA_TX ? "Tx" : "Rx",
+			q_params->size,
+			(unsigned long long)q_params->desc_phy_base,
+			q_params->desc_base,
+			(unsigned long long)q_params->cdesc_phy_base,
+			q_params->cdesc_base,
+			q_params->cdesc_size);
+
+	return 0;
+}
+
+/*
+ * Reset a udma queue
+ */
+int al_udma_q_reset(struct al_udma_q *udma_q)
+{
+	unsigned int remaining_time = AL_UDMA_Q_RST_TOUT;
+	uint32_t *status_reg;
+	uint32_t *dcp_reg;
+	uint32_t *crhp_reg;
+	uint32_t *q_sw_ctrl_reg;
+
+	al_assert(udma_q);
+
+	/* De-assert scheduling and prefetch */
+	al_udma_q_enable(udma_q, 0);
+
+	/* Wait for scheduling and prefetch to stop */
+	status_reg = &udma_q->q_regs->rings.status;
+
+	while (remaining_time) {
+		uint32_t status = al_reg_read32(status_reg);
+
+		if (!(status & (UDMA_M2S_Q_STATUS_PREFETCH |
+						UDMA_M2S_Q_STATUS_SCHEDULER)))
+			break;
+
+		remaining_time--;
+		al_udelay(1);
+	}
+
+	if (!remaining_time) {
+		al_err("udma [%s %d]: %s timeout waiting for prefetch and "
+			"scheduler disable\n", udma_q->udma->name, udma_q->qid,
+			__func__);
+		return -ETIMEDOUT;
+	}
+
+	/* Wait for the completion queue to reach to the same pointer as the
+	 * prefetch stopped at ([TR]DCP == [TR]CRHP) */
+	dcp_reg = &udma_q->q_regs->rings.dcp;
+	crhp_reg = &udma_q->q_regs->rings.crhp;
+
+	while (remaining_time) {
+		uint32_t dcp = al_reg_read32(dcp_reg);
+		uint32_t crhp = al_reg_read32(crhp_reg);
+
+		if (dcp == crhp)
+			break;
+
+		remaining_time--;
+		al_udelay(1);
+	};
+
+	if (!remaining_time) {
+		al_err("udma [%s %d]: %s timeout waiting for dcp==crhp\n",
+			udma_q->udma->name, udma_q->qid, __func__);
+		return -ETIMEDOUT;
+	}
+
+	/* Assert the queue reset */
+	if (udma_q->udma->type == UDMA_TX)
+		q_sw_ctrl_reg = &udma_q->q_regs->m2s_q.q_sw_ctrl;
+	else
+		q_sw_ctrl_reg = &udma_q->q_regs->s2m_q.q_sw_ctrl;
+
+	al_reg_write32(q_sw_ctrl_reg, UDMA_M2S_Q_SW_CTRL_RST_Q);
+
+	return 0;
+}
+
+/*
+ * return (by reference) a pointer to a specific queue date structure.
+ */
+int al_udma_q_handle_get(struct al_udma *udma, uint32_t qid,
+						struct al_udma_q **q_handle)
+{
+
+	al_assert(udma);
+	al_assert(q_handle);
+
+	if (unlikely(qid >= udma->num_of_queues)) {
+		al_err("udma [%s]: invalid queue id (%d)\n", udma->name, qid);
+		return -EINVAL;
+	}
+	*q_handle = &udma->udma_q[qid];
+	return 0;
+}
+
+/*
+ * Change the UDMA's state
+ */
+int al_udma_state_set(struct al_udma *udma, enum al_udma_state state)
+{
+	uint32_t reg;
+
+	al_assert(udma != NULL);
+	if (state == udma->state)
+		al_dbg("udma [%s]: requested state identical to "
+			"current state (%d)\n", udma->name, state);
+
+	al_dbg("udma [%s]: change state from (%s) to (%s)\n",
+		 udma->name, al_udma_states_name[udma->state],
+		 al_udma_states_name[state]);
+
+	reg = 0;
+	switch (state) {
+	case UDMA_DISABLE:
+		reg |= UDMA_M2S_CHANGE_STATE_DIS;
+		break;
+	case UDMA_NORMAL:
+		reg |= UDMA_M2S_CHANGE_STATE_NORMAL;
+		break;
+	case UDMA_ABORT:
+		reg |= UDMA_M2S_CHANGE_STATE_ABORT;
+		break;
+	default:
+		al_err("udma: invalid state (%d)\n", state);
+		return -EINVAL;
+	}
+
+	if (udma->type == UDMA_TX)
+		al_reg_write32(&udma->udma_regs->m2s.m2s.change_state, reg);
+	else
+		al_reg_write32(&udma->udma_regs->s2m.s2m.change_state, reg);
+
+	udma->state = state;
+	return 0;
+}
+
+/*
+ * return the current UDMA hardware state
+ */
+enum al_udma_state al_udma_state_get(struct al_udma *udma)
+{
+	uint32_t state_reg;
+	uint32_t comp_ctrl;
+	uint32_t stream_if;
+	uint32_t data_rd;
+	uint32_t desc_pref;
+
+	if (udma->type == UDMA_TX)
+		state_reg = al_reg_read32(&udma->udma_regs->m2s.m2s.state);
+	else
+		state_reg = al_reg_read32(&udma->udma_regs->s2m.s2m.state);
+
+	comp_ctrl = AL_REG_FIELD_GET(state_reg,
+				     UDMA_M2S_STATE_COMP_CTRL_MASK,
+				     UDMA_M2S_STATE_COMP_CTRL_SHIFT);
+	stream_if = AL_REG_FIELD_GET(state_reg,
+				     UDMA_M2S_STATE_STREAM_IF_MASK,
+				     UDMA_M2S_STATE_STREAM_IF_SHIFT);
+	data_rd = AL_REG_FIELD_GET(state_reg,
+				   UDMA_M2S_STATE_DATA_RD_CTRL_MASK,
+				   UDMA_M2S_STATE_DATA_RD_CTRL_SHIFT);
+	desc_pref = AL_REG_FIELD_GET(state_reg,
+				     UDMA_M2S_STATE_DESC_PREF_MASK,
+				     UDMA_M2S_STATE_DESC_PREF_SHIFT);
+
+	al_assert(comp_ctrl != UDMA_STATE_RESERVED);
+	al_assert(stream_if != UDMA_STATE_RESERVED);
+	al_assert(data_rd != UDMA_STATE_RESERVED);
+	al_assert(desc_pref != UDMA_STATE_RESERVED);
+
+	/* if any of the states is abort then return abort */
+	if ((comp_ctrl == UDMA_STATE_ABORT) || (stream_if == UDMA_STATE_ABORT)
+			|| (data_rd == UDMA_STATE_ABORT)
+			|| (desc_pref == UDMA_STATE_ABORT))
+		return UDMA_ABORT;
+
+	/* if any of the states is normal then return normal */
+	if ((comp_ctrl == UDMA_STATE_NORMAL)
+			|| (stream_if == UDMA_STATE_NORMAL)
+			|| (data_rd == UDMA_STATE_NORMAL)
+			|| (desc_pref == UDMA_STATE_NORMAL))
+		return UDMA_NORMAL;
+
+	return UDMA_IDLE;
+}
+
+/*
+ * Action handling
+ */
+
+/*
+ * get next completed packet from completion ring of the queue
+ */
+uint32_t al_udma_cdesc_packet_get(
+	struct al_udma_q		*udma_q,
+	volatile union al_udma_cdesc	**cdesc)
+{
+	uint32_t count;
+	volatile union al_udma_cdesc *curr;
+	uint32_t comp_flags;
+
+	/* this function requires the completion ring update */
+	al_assert(!(udma_q->flags & AL_UDMA_Q_FLAGS_NO_COMP_UPDATE));
+
+	/* comp_head points to the last comp desc that was processed */
+	curr = udma_q->comp_head_ptr;
+	comp_flags = swap32_from_le(curr->al_desc_comp_tx.ctrl_meta);
+
+	/* check if the completion descriptor is new */
+	if (unlikely(al_udma_new_cdesc(udma_q, comp_flags) == AL_FALSE))
+		return 0;
+	/* if new desc found, increment the current packets descriptors */
+	count = udma_q->pkt_crnt_descs + 1;
+	while (!cdesc_is_last(comp_flags)) {
+		curr = al_cdesc_next_update(udma_q, curr);
+		comp_flags = swap32_from_le(curr->al_desc_comp_tx.ctrl_meta);
+		if (unlikely(al_udma_new_cdesc(udma_q, comp_flags)
+								== AL_FALSE)) {
+			/* the current packet here doesn't have all  */
+			/* descriptors completed. log the current desc */
+			/* location and number of completed descriptors so */
+			/*  far. then return */
+			udma_q->pkt_crnt_descs = count;
+			udma_q->comp_head_ptr = curr;
+			return 0;
+		}
+		count++;
+		/* check against max descs per packet. */
+		al_assert(count <= udma_q->size);
+	}
+	/* return back the first descriptor of the packet */
+	*cdesc = al_udma_cdesc_idx_to_ptr(udma_q, udma_q->next_cdesc_idx);
+	udma_q->pkt_crnt_descs = 0;
+	udma_q->comp_head_ptr = al_cdesc_next_update(udma_q, curr);
+
+	al_dbg("udma [%s %d]: packet completed. first desc %p (ixd 0x%x)"
+		 " descs %d\n", udma_q->udma->name, udma_q->qid, *cdesc,
+		 udma_q->next_cdesc_idx, count);
+
+	return count;
+}
+
+/** @} end of UDMA group */
diff --git a/sys/contrib/alpine-hal/al_hal_udma_regs.h b/sys/contrib/alpine-hal/al_hal_udma_regs.h
new file mode 100644
index 000000000000..ed37215ae445
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_regs.h
@@ -0,0 +1,104 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ *  @{
+ * @file   al_hal_udma_regs.h
+ *
+ * @brief  udma registers definition
+ *
+ *
+ */
+#ifndef __AL_HAL_UDMA_REG_H
+#define __AL_HAL_UDMA_REG_H
+
+#include "al_hal_udma_regs_m2s.h"
+#include "al_hal_udma_regs_s2m.h"
+#include "al_hal_udma_regs_gen.h"
+
+#define AL_UDMA_REV_ID_REV0   0
+#define AL_UDMA_REV_ID_REV1   1
+#define AL_UDMA_REV_ID_REV2   2
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** UDMA registers, either m2s or s2m */
+union udma_regs {
+	struct udma_m2s_regs m2s;
+	struct udma_s2m_regs s2m;
+};
+
+struct unit_regs {
+	struct udma_m2s_regs m2s;
+	uint32_t rsrvd0[(0x10000 - sizeof(struct udma_m2s_regs)) >> 2];
+	struct udma_s2m_regs s2m;
+	uint32_t rsrvd1[((0x1C000 - 0x10000) - sizeof(struct udma_s2m_regs)) >> 2];
+	struct udma_gen_regs gen;
+};
+
+/** UDMA submission and completion registers, M2S and S2M UDMAs have same stucture */
+struct udma_rings_regs {
+	uint32_t rsrvd0[8];
+	uint32_t cfg;		/* Descriptor ring configuration */
+	uint32_t status;	/* Descriptor ring status and information */
+	uint32_t drbp_low;	/* Descriptor Ring Base Pointer [31:4] */
+	uint32_t drbp_high;	/* Descriptor Ring Base Pointer [63:32] */
+	uint32_t drl;		/* Descriptor Ring Length[23:2] */
+	uint32_t drhp;		/* Descriptor Ring Head Pointer */
+	uint32_t drtp_inc;	/* Descriptor Tail Pointer increment */
+	uint32_t drtp;		/* Descriptor Tail Pointer */
+	uint32_t dcp;		/* Descriptor Current Pointer */
+	uint32_t crbp_low;	/* Completion Ring Base Pointer [31:4] */
+	uint32_t crbp_high;	/* Completion Ring Base Pointer [63:32] */
+	uint32_t crhp;		/* Completion Ring Head Pointer */
+	uint32_t crhp_internal;	/* Completion Ring Head Pointer internal, before AX ... */
+};
+
+/** M2S and S2M generic structure of Q registers */
+union udma_q_regs {
+	struct udma_rings_regs	rings;
+	struct udma_m2s_q	m2s_q;
+	struct udma_s2m_q	s2m_q;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_UDMA_REG_H */
+/** @} end of UDMA group */
diff --git a/sys/contrib/alpine-hal/al_hal_udma_regs_gen.h b/sys/contrib/alpine-hal/al_hal_udma_regs_gen.h
new file mode 100644
index 000000000000..89f94b85a56b
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_regs_gen.h
@@ -0,0 +1,414 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @file   al_hal_udma_regs_gen.h
+ *
+ * @brief C Header file for the UDMA general registers
+ *
+ */
+
+#ifndef __AL_HAL_UDMA_GEN_REG_H
+#define __AL_HAL_UDMA_GEN_REG_H
+
+#include "al_hal_udma_iofic_regs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+
+
+struct udma_gen_dma_misc {
+	/* [0x0] Reserved register for the interrupt controller */
+	uint32_t int_cfg;
+	/* [0x4] Revision register */
+	uint32_t revision;
+	/* [0x8] Reserved for future use */
+	uint32_t general_cfg_1;
+	/* [0xc] Reserved for future use */
+	uint32_t general_cfg_2;
+	/* [0x10] Reserved for future use */
+	uint32_t general_cfg_3;
+	/* [0x14] Reserved for future use */
+	uint32_t general_cfg_4;
+	/* [0x18] General timer configuration */
+	uint32_t general_cfg_5;
+	uint32_t rsrvd[57];
+};
+struct udma_gen_mailbox {
+	/*
+	 * [0x0] Mailbox interrupt generator.
+	 * Generates interrupt to neighbor DMA
+	 */
+	uint32_t interrupt;
+	/* [0x4] Mailbox message data out */
+	uint32_t msg_out;
+	/* [0x8] Mailbox message data in */
+	uint32_t msg_in;
+	uint32_t rsrvd[13];
+};
+struct udma_gen_axi {
+	/* [0x0] Configuration of the AXI masters */
+	uint32_t cfg_1;
+	/* [0x4] Configuration of the AXI masters */
+	uint32_t cfg_2;
+	/* [0x8] Configuration of the AXI masters. Endianess configuration */
+	uint32_t endian_cfg;
+	uint32_t rsrvd[61];
+};
+struct udma_gen_sram_ctrl {
+	/* [0x0] Timing configuration */
+	uint32_t timing;
+};
+struct udma_gen_vmid {
+	/* [0x0] VMID control */
+	uint32_t cfg_vmid_0;
+	/* [0x4] TX queue 0/1 VMID */
+	uint32_t cfg_vmid_1;
+	/* [0x8] TX queue 2/3 VMID */
+	uint32_t cfg_vmid_2;
+	/* [0xc] RX queue 0/1 VMID */
+	uint32_t cfg_vmid_3;
+	/* [0x10] RX queue 2/3 VMID */
+	uint32_t cfg_vmid_4;
+};
+struct udma_gen_vmaddr {
+	/* [0x0] TX queue 0/1 VMADDR */
+	uint32_t cfg_vmaddr_0;
+	/* [0x4] TX queue 2/3 VMADDR */
+	uint32_t cfg_vmaddr_1;
+	/* [0x8] RX queue 0/1 VMADDR */
+	uint32_t cfg_vmaddr_2;
+	/* [0xc] RX queue 2/3 VMADDR */
+	uint32_t cfg_vmaddr_3;
+};
+struct udma_gen_vmpr {
+	/* [0x0] TX VMPR control */
+	uint32_t cfg_vmpr_0;
+	/* [0x4] TX VMPR Address High Regsiter */
+	uint32_t cfg_vmpr_1;
+	/* [0x8] TX queue VMID values */
+	uint32_t cfg_vmpr_2;
+	/* [0xc] TX queue VMID values */
+	uint32_t cfg_vmpr_3;
+	/* [0x10] RX VMPR control */
+	uint32_t cfg_vmpr_4;
+	/* [0x14] RX VMPR Buffer2 MSB address */
+	uint32_t cfg_vmpr_5;
+	/* [0x18] RX queue VMID values */
+	uint32_t cfg_vmpr_6;
+	/* [0x1c] RX queue BUF1 VMID values */
+	uint32_t cfg_vmpr_7;
+	/* [0x20] RX queue BUF2 VMID values */
+	uint32_t cfg_vmpr_8;
+	/* [0x24] RX queue Direct Data Placement VMID values */
+	uint32_t cfg_vmpr_9;
+	/* [0x28] RX VMPR BUF1 Address High Regsiter */
+	uint32_t cfg_vmpr_10;
+	/* [0x2c] RX VMPR BUF2 Address High Regsiter */
+	uint32_t cfg_vmpr_11;
+	/* [0x30] RX VMPR DDP Address High Regsiter */
+	uint32_t cfg_vmpr_12;
+	uint32_t rsrvd[3];
+};
+
+struct udma_gen_regs {
+	struct udma_iofic_regs interrupt_regs;					/* [0x0000] */
+	struct udma_gen_dma_misc dma_misc;                   /* [0x2080] */
+	struct udma_gen_mailbox mailbox[4];                  /* [0x2180] */
+	struct udma_gen_axi axi;                             /* [0x2280] */
+	struct udma_gen_sram_ctrl sram_ctrl[25];             /* [0x2380] */
+	uint32_t rsrvd_1[2];
+	struct udma_gen_vmid vmid;                           /* [0x23ec] */
+	struct udma_gen_vmaddr vmaddr;                       /* [0x2400] */
+	uint32_t rsrvd_2[252];
+	struct udma_gen_vmpr vmpr[4];                        /* [0x2800] */
+};
+
+
+/*
+* Registers Fields
+*/
+
+
+/**** int_cfg register ****/
+/*
+ * MSIX data width
+ * 1 - 64 bit
+ * 0 – 32 bit
+ */
+#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_64 (1 << 0)
+/* General configuration */
+#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_3_1_MASK 0x0000000E
+#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_3_1_SHIFT 1
+/* MSIx AXI QoS */
+#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_AXI_QOS_MASK 0x00000070
+#define UDMA_GEN_DMA_MISC_INT_CFG_MSIX_AXI_QOS_SHIFT 4
+
+#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_31_7_MASK 0xFFFFFF80
+#define UDMA_GEN_DMA_MISC_INT_CFG_RESERVED_31_7_SHIFT 7
+
+/**** revision register ****/
+/* Design programming interface  revision ID */
+#define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_MASK 0x00000FFF
+#define UDMA_GEN_DMA_MISC_REVISION_PROGRAMMING_ID_SHIFT 0
+/* Design minor revision ID */
+#define UDMA_GEN_DMA_MISC_REVISION_MINOR_ID_MASK 0x00FFF000
+#define UDMA_GEN_DMA_MISC_REVISION_MINOR_ID_SHIFT 12
+/* Design major revision ID */
+#define UDMA_GEN_DMA_MISC_REVISION_MAJOR_ID_MASK 0xFF000000
+#define UDMA_GEN_DMA_MISC_REVISION_MAJOR_ID_SHIFT 24
+
+/**** Interrupt register ****/
+/* Generate interrupt to another DMA */
+#define UDMA_GEN_MAILBOX_INTERRUPT_SET   (1 << 0)
+
+/**** cfg_2 register ****/
+/*
+ * Enable arbitration promotion.
+ * Increment master priority after configured number of arbitration cycles
+ */
+#define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK 0x0000000F
+#define UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_SHIFT 0
+
+/**** endian_cfg register ****/
+/* Swap M2S descriptor read and completion descriptor write.  */
+#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC (1 << 0)
+/* Swap M2S data read. */
+#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA (1 << 1)
+/* Swap S2M descriptor read and completion descriptor write.  */
+#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC (1 << 2)
+/* Swap S2M data write. */
+#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA (1 << 3)
+/*
+ * Swap 32 or 64 bit mode:
+ * 0 - Swap groups of 4 bytes
+ * 1 - Swap groups of 8 bytes
+ */
+#define UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN (1 << 4)
+
+/**** timing register ****/
+/* Write margin */
+#define UDMA_GEN_SRAM_CTRL_TIMING_RMA_MASK 0x0000000F
+#define UDMA_GEN_SRAM_CTRL_TIMING_RMA_SHIFT 0
+/* Write margin enable */
+#define UDMA_GEN_SRAM_CTRL_TIMING_RMEA   (1 << 8)
+/* Read margin */
+#define UDMA_GEN_SRAM_CTRL_TIMING_RMB_MASK 0x000F0000
+#define UDMA_GEN_SRAM_CTRL_TIMING_RMB_SHIFT 16
+/* Read margin enable */
+#define UDMA_GEN_SRAM_CTRL_TIMING_RMEB   (1 << 24)
+
+/**** cfg_vmid_0 register ****/
+/* For M2S queues 3:0, enable usage of the VMID from the buffer address 63:56 */
+#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_DESC_EN_MASK 0x0000000F
+#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_DESC_EN_SHIFT 0
+/*
+ * For M2S queues 3:0, enable usage of the VMID from the configuration register
+ * (cfg_vmid_1/2 used for M2S queue_x)
+ */
+#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_QUEUE_EN_MASK 0x000000F0
+#define UDMA_GEN_VMID_CFG_VMID_0_TX_Q_VMID_QUEUE_EN_SHIFT 4
+/* use VMID_n [7:0] from MSI-X Controller for MSI-X message  */
+#define UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_SEL (1 << 8)
+/* Enable write to all VMID_n registers in the MSI-X Controller */
+#define UDMA_GEN_VMID_CFG_VMID_0_MSIX_VMID_ACCESS_EN (1 << 9)
+/* For S2M queues 3:0, enable usage of the VMID from the buffer address 63:56 */
+#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_DESC_EN_MASK 0x000F0000
+#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_DESC_EN_SHIFT 16
+/*
+ * For S2M queues 3:0, enable usage of the VMID from the configuration register
+ * (cfg_vmid_3/4 used for M2S queue_x)
+ */
+#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_QUEUE_EN_MASK 0x00F00000
+#define UDMA_GEN_VMID_CFG_VMID_0_RX_Q_VMID_QUEUE_EN_SHIFT 20
+
+/**** cfg_vmid_1 register ****/
+/* TX queue 0 VMID value */
+#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_0_VMID_MASK 0x0000FFFF
+#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_0_VMID_SHIFT 0
+/* TX queue 1 VMID value */
+#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_1_VMID_MASK 0xFFFF0000
+#define UDMA_GEN_VMID_CFG_VMID_1_TX_Q_1_VMID_SHIFT 16
+
+/**** cfg_vmid_2 register ****/
+/* TX queue 2 VMID value */
+#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_2_VMID_MASK 0x0000FFFF
+#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_2_VMID_SHIFT 0
+/* TX queue 3 VMID value */
+#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_3_VMID_MASK 0xFFFF0000
+#define UDMA_GEN_VMID_CFG_VMID_2_TX_Q_3_VMID_SHIFT 16
+
+/**** cfg_vmid_3 register ****/
+/* RX queue 0 VMID value */
+#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_0_VMID_MASK 0x0000FFFF
+#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_0_VMID_SHIFT 0
+/* RX queue 1 VMID value */
+#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_1_VMID_MASK 0xFFFF0000
+#define UDMA_GEN_VMID_CFG_VMID_3_RX_Q_1_VMID_SHIFT 16
+
+/**** cfg_vmid_4 register ****/
+/* RX queue 2 VMID value */
+#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_2_VMID_MASK 0x0000FFFF
+#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_2_VMID_SHIFT 0
+/* RX queue 3 VMID value */
+#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_3_VMID_MASK 0xFFFF0000
+#define UDMA_GEN_VMID_CFG_VMID_4_RX_Q_3_VMID_SHIFT 16
+
+/**** cfg_vmaddr_0 register ****/
+/* TX queue 0 VMADDR value */
+#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_0_VMADDR_MASK 0x0000FFFF
+#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_0_VMADDR_SHIFT 0
+/* TX queue 1 VMADDR value */
+#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_1_VMADDR_MASK 0xFFFF0000
+#define UDMA_GEN_VMADDR_CFG_VMADDR_0_TX_Q_1_VMADDR_SHIFT 16
+
+/**** cfg_vmaddr_1 register ****/
+/* TX queue 2 VMADDR value */
+#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_2_VMADDR_MASK 0x0000FFFF
+#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_2_VMADDR_SHIFT 0
+/* TX queue 3 VMADDR value */
+#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_3_VMADDR_MASK 0xFFFF0000
+#define UDMA_GEN_VMADDR_CFG_VMADDR_1_TX_Q_3_VMADDR_SHIFT 16
+
+/**** cfg_vmaddr_2 register ****/
+/* RX queue 0 VMADDR value */
+#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_0_VMADDR_MASK 0x0000FFFF
+#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_0_VMADDR_SHIFT 0
+/* RX queue 1 VMADDR value */
+#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_1_VMADDR_MASK 0xFFFF0000
+#define UDMA_GEN_VMADDR_CFG_VMADDR_2_RX_Q_1_VMADDR_SHIFT 16
+
+/**** cfg_vmaddr_3 register ****/
+/* RX queue 2 VMADDR value */
+#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_2_VMADDR_MASK 0x0000FFFF
+#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_2_VMADDR_SHIFT 0
+/* RX queue 3 VMADDR value */
+#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_3_VMADDR_MASK 0xFFFF0000
+#define UDMA_GEN_VMADDR_CFG_VMADDR_3_RX_Q_3_VMADDR_SHIFT 16
+
+/**** cfg_vmpr_0 register ****/
+/* TX High Address Select Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_MASK 0x0000003F
+#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_HISEL_SHIFT 0
+/* TX Data VMID Enable Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_DATA_VMID_EN (1 << 7)
+/* TX Prefetch VMID Enable Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_PREF_VMID_EN (1 << 28)
+/* TX Completions VMID Enable Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_0_TX_Q_CMPL_VMID_EN (1 << 29)
+
+/**** cfg_vmpr_2 register ****/
+/* TX queue Prefetch VMID */
+#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_VMID_MASK 0x0000FFFF
+#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_PREF_VMID_SHIFT 0
+/* TX queue Completion VMID */
+#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_VMID_MASK 0xFFFF0000
+#define UDMA_GEN_VMPR_CFG_VMPR_2_TX_Q_CMPL_VMID_SHIFT 16
+
+/**** cfg_vmpr_3 register ****/
+/* TX queue Data VMID */
+#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_MASK 0x0000FFFF
+#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SHIFT 0
+/* TX queue Data VMID select */
+#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SEL_MASK 0xFFFF0000
+#define UDMA_GEN_VMPR_CFG_VMPR_3_TX_Q_DATA_VMID_SEL_SHIFT 16
+
+/**** cfg_vmpr_4 register ****/
+/* RX Data Buffer1 - High Address Select Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_MASK 0x0000003F
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_HISEL_SHIFT 0
+/* RX Data Buffer1 VMID Enable Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF1_VMID_EN (1 << 7)
+/* RX Data Buffer2 - High Address Select Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_MASK 0x00003F00
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_HISEL_SHIFT 8
+/* RX Data Buffer2 VMID Enable Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_VMID_EN (1 << 15)
+/* RX Direct Data Placement - High Address Select Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_MASK 0x003F0000
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_HISEL_SHIFT 16
+/* RX Direct Data Placement VMID Enable Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_DDP_VMID_EN (1 << 23)
+/* RX Buffer 2 MSB address word selects per bytes, per queue */
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_MASK 0x0F000000
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_BUF2_MSB_ADDR_SEL_SHIFT 24
+/* RX Prefetch VMID Enable Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_PREF_VMID_EN (1 << 28)
+/* RX Completions VMID Enable Per Q */
+#define UDMA_GEN_VMPR_CFG_VMPR_4_RX_Q_CMPL_VMID_EN (1 << 29)
+
+/**** cfg_vmpr_6 register ****/
+/* RX queue Prefetch VMID */
+#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_VMID_MASK 0x0000FFFF
+#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_PREF_VMID_SHIFT 0
+/* RX queue Completion VMID */
+#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_VMID_MASK 0xFFFF0000
+#define UDMA_GEN_VMPR_CFG_VMPR_6_RX_Q_CMPL_VMID_SHIFT 16
+
+/**** cfg_vmpr_7 register ****/
+/* RX queue Data Buffer 1 VMID */
+#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_MASK 0x0000FFFF
+#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SHIFT 0
+/* RX queue Data Buffer 1 VMID select */
+#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SEL_MASK 0xFFFF0000
+#define UDMA_GEN_VMPR_CFG_VMPR_7_RX_Q_BUF1_VMID_SEL_SHIFT 16
+
+/**** cfg_vmpr_8 register ****/
+/* RX queue Data Buffer 2 VMID */
+#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_MASK 0x0000FFFF
+#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SHIFT 0
+/* RX queue Data Buffer 2 VMID select */
+#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SEL_MASK 0xFFFF0000
+#define UDMA_GEN_VMPR_CFG_VMPR_8_RX_Q_BUF2_VMID_SEL_SHIFT 16
+
+/**** cfg_vmpr_9 register ****/
+/* RX queue DDP VMID */
+#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_MASK 0x0000FFFF
+#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SHIFT 0
+/* RX queue DDP VMID select */
+#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SEL_MASK 0xFFFF0000
+#define UDMA_GEN_VMPR_CFG_VMPR_9_RX_Q_DDP_VMID_SEL_SHIFT 16
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_UDMA_GEN_REG_H */
diff --git a/sys/contrib/alpine-hal/al_hal_udma_regs_m2s.h b/sys/contrib/alpine-hal/al_hal_udma_regs_m2s.h
new file mode 100644
index 000000000000..06cea8db8f6d
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_regs_m2s.h
@@ -0,0 +1,1159 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @file   al_hal_udma_regs_m2s.h
+ *
+ * @brief C Header file for the UDMA M2S registers
+ *
+ */
+
+#ifndef __AL_HAL_UDMA_M2S_REG_H
+#define __AL_HAL_UDMA_M2S_REG_H
+
+#include "al_hal_plat_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+
+
+struct udma_axi_m2s {
+	/* [0x0] Completion write master configuration */
+	uint32_t comp_wr_cfg_1;
+	/* [0x4] Completion write master configuration */
+	uint32_t comp_wr_cfg_2;
+	/* [0x8] Data read master configuration */
+	uint32_t data_rd_cfg_1;
+	/* [0xc] Data read master configuration */
+	uint32_t data_rd_cfg_2;
+	/* [0x10] Descriptor read master configuration */
+	uint32_t desc_rd_cfg_1;
+	/* [0x14] Descriptor read master configuration */
+	uint32_t desc_rd_cfg_2;
+	/* [0x18] Data read master configuration */
+	uint32_t data_rd_cfg;
+	/* [0x1c] Descriptors read master configuration */
+	uint32_t desc_rd_cfg_3;
+	/* [0x20] Descriptors write master configuration (completion) */
+	uint32_t desc_wr_cfg_1;
+	/* [0x24] AXI outstanding  configuration */
+	uint32_t ostand_cfg;
+	uint32_t rsrvd[54];
+};
+struct udma_m2s {
+	/*
+	 * [0x0] DMA state.
+	 * 00  - No pending tasks
+	 * 01 – Normal (active)
+	 * 10 – Abort (error condition)
+	 * 11 – Reserved
+	 */
+	uint32_t state;
+	/* [0x4] CPU request to change DMA state */
+	uint32_t change_state;
+	uint32_t rsrvd_0;
+	/*
+	 * [0xc] M2S DMA error log mask.
+	 * Each error has an interrupt controller cause bit.
+	 * This register determines if these errors cause the M2S DMA to log the
+	 * error condition.
+	 * 0 - Log is enabled.
+	 * 1 - Log is masked.
+	 */
+	uint32_t err_log_mask;
+	uint32_t rsrvd_1;
+	/*
+	 * [0x14] DMA header log.
+	 * Sample the packet header that caused the error.
+	 */
+	uint32_t log_0;
+	/*
+	 * [0x18] DMA header log.
+	 * Sample the packet header that caused the error.
+	 */
+	uint32_t log_1;
+	/*
+	 * [0x1c] DMA header log.
+	 * Sample the packet header that caused the error.
+	 */
+	uint32_t log_2;
+	/*
+	 * [0x20] DMA header log.
+	 * Sample the packet header that caused the error.
+	 */
+	uint32_t log_3;
+	/* [0x24] DMA clear error log */
+	uint32_t clear_err_log;
+	/* [0x28] M2S data FIFO status */
+	uint32_t data_fifo_status;
+	/* [0x2c] M2S header FIFO status */
+	uint32_t header_fifo_status;
+	/* [0x30] M2S unack FIFO status */
+	uint32_t unack_fifo_status;
+	/* [0x34] Select queue for debug */
+	uint32_t indirect_ctrl;
+	/*
+	 * [0x38] M2S prefetch FIFO status.
+	 * Status of the selected queue in M2S_indirect_ctrl
+	 */
+	uint32_t sel_pref_fifo_status;
+	/*
+	 * [0x3c] M2S completion FIFO status.
+	 * Status of the selected queue in M2S_indirect_ctrl
+	 */
+	uint32_t sel_comp_fifo_status;
+	/*
+	 * [0x40] M2S rate limit status.
+	 * Status of the selected queue in M2S_indirect_ctrl
+	 */
+	uint32_t sel_rate_limit_status;
+	/*
+	 * [0x44] M2S DWRR scheduler status.
+	 * Status of the selected queue in M2S_indirect_ctrl
+	 */
+	uint32_t sel_dwrr_status;
+	/* [0x48] M2S state machine and FIFO clear control */
+	uint32_t clear_ctrl;
+	/* [0x4c] Misc Check enable */
+	uint32_t check_en;
+	/* [0x50] M2S FIFO enable control, internal */
+	uint32_t fifo_en;
+	/* [0x54] M2S packet length configuration */
+	uint32_t cfg_len;
+	/* [0x58] Stream interface configuration */
+	uint32_t stream_cfg;
+	uint32_t rsrvd[41];
+};
+struct udma_m2s_rd {
+	/* [0x0] M2S descriptor prefetch configuration */
+	uint32_t desc_pref_cfg_1;
+	/* [0x4] M2S descriptor prefetch configuration */
+	uint32_t desc_pref_cfg_2;
+	/* [0x8] M2S descriptor prefetch configuration */
+	uint32_t desc_pref_cfg_3;
+	uint32_t rsrvd_0;
+	/* [0x10] Data burst read configuration */
+	uint32_t data_cfg;
+	uint32_t rsrvd[11];
+};
+struct udma_m2s_dwrr {
+	/* [0x0] Tx DMA DWRR scheduler configuration */
+	uint32_t cfg_sched;
+	/* [0x4] Token bucket rate limit control */
+	uint32_t ctrl_deficit_cnt;
+	uint32_t rsrvd[14];
+};
+struct udma_m2s_rate_limiter {
+	/* [0x0] Token bucket rate limit configuration */
+	uint32_t gen_cfg;
+	/*
+	 * [0x4] Token bucket rate limit control.
+	 * Controls the cycle counters.
+	 */
+	uint32_t ctrl_cycle_cnt;
+	/*
+	 * [0x8] Token bucket rate limit control.
+	 * Controls the token bucket counter.
+	 */
+	uint32_t ctrl_token;
+	uint32_t rsrvd[13];
+};
+
+struct udma_rlimit_common {
+	/* [0x0] Token bucket configuration */
+	uint32_t cfg_1s;
+	/* [0x4] Token bucket rate limit configuration */
+	uint32_t cfg_cycle;
+	/* [0x8] Token bucket rate limit configuration */
+	uint32_t cfg_token_size_1;
+	/* [0xc] Token bucket rate limit configuration */
+	uint32_t cfg_token_size_2;
+	/* [0x10] Token bucket rate limit configuration */
+	uint32_t sw_ctrl;
+	/*
+	 * [0x14] Mask the different types of rate limiter.
+	 * 0 - Rate limit is active.
+	 * 1 - Rate limit is masked.
+	 */
+	uint32_t mask;
+};
+
+struct udma_m2s_stream_rate_limiter {
+	struct udma_rlimit_common rlimit;
+	uint32_t rsrvd[10];
+};
+struct udma_m2s_comp {
+	/* [0x0] Completion controller configuration */
+	uint32_t cfg_1c;
+	/* [0x4] Completion controller coalescing configuration */
+	uint32_t cfg_coal;
+	/* [0x8] Completion controller application acknowledge configuration */
+	uint32_t cfg_application_ack;
+	uint32_t rsrvd[61];
+};
+struct udma_m2s_stat {
+	/* [0x0] Statistics counters configuration */
+	uint32_t cfg_st;
+	/* [0x4] Counting number of descriptors with First-bit set. */
+	uint32_t tx_pkt;
+	/*
+	 * [0x8] Counting the net length of the data buffers [64-bit]
+	 * Should be read before tx_bytes_high
+	 */
+	uint32_t tx_bytes_low;
+	/*
+	 * [0xc] Counting the net length of the data buffers [64-bit],
+	 * Should be read after tx_bytes_low (value is sampled when reading
+	 * Should be read before tx_bytes_low
+	 */
+	uint32_t tx_bytes_high;
+	/* [0x10] Total number of descriptors read from the host memory */
+	uint32_t prefed_desc;
+	/* [0x14] Number of packets read from the unack FIFO */
+	uint32_t comp_pkt;
+	/* [0x18] Number of descriptors written into the completion ring */
+	uint32_t comp_desc;
+	/*
+	 * [0x1c] Number of acknowledged packets.
+	 * (acknowledge received from the stream interface)
+	 */
+	uint32_t ack_pkts;
+	uint32_t rsrvd[56];
+};
+struct udma_m2s_feature {
+	/*
+	 * [0x0] M2S Feature register.
+	 * M2S instantiation parameters
+	 */
+	uint32_t reg_1;
+	/* [0x4] Reserved M2S feature register */
+	uint32_t reg_2;
+	/*
+	 * [0x8] M2S Feature register.
+	 * M2S instantiation parameters
+	 */
+	uint32_t reg_3;
+	/*
+	 * [0xc] M2S Feature register.
+	 * M2S instantiation parameters
+	 */
+	uint32_t reg_4;
+	/*
+	 * [0x10] M2S Feature register.
+	 * M2S instantiation parameters
+	 */
+	uint32_t reg_5;
+	uint32_t rsrvd[59];
+};
+struct udma_m2s_q {
+	uint32_t rsrvd_0[8];
+	/* [0x20] M2S descriptor ring configuration */
+	uint32_t cfg;
+	/* [0x24] M2S descriptor ring status and information */
+	uint32_t status;
+	/* [0x28] TX Descriptor Ring Base Pointer [31:4] */
+	uint32_t tdrbp_low;
+	/* [0x2c] TX Descriptor Ring Base Pointer [63:32] */
+	uint32_t tdrbp_high;
+	/*
+	 * [0x30] TX Descriptor Ring Length[23:2]
+	 */
+	uint32_t tdrl;
+	/* [0x34] TX Descriptor Ring Head Pointer */
+	uint32_t tdrhp;
+	/* [0x38] Tx Descriptor Tail Pointer increment */
+	uint32_t tdrtp_inc;
+	/* [0x3c] Tx Descriptor Tail Pointer */
+	uint32_t tdrtp;
+	/* [0x40] TX Descriptor Current Pointer */
+	uint32_t tdcp;
+	/* [0x44] Tx Completion Ring Base Pointer [31:4] */
+	uint32_t tcrbp_low;
+	/* [0x48] TX Completion Ring Base Pointer [63:32] */
+	uint32_t tcrbp_high;
+	/* [0x4c] TX Completion Ring Head Pointer */
+	uint32_t tcrhp;
+	/*
+	 * [0x50] Tx Completion Ring Head Pointer internal (Before the
+	 * coalescing FIFO)
+	 */
+	uint32_t tcrhp_internal;
+	uint32_t rsrvd_1[3];
+	/* [0x60] Rate limit configuration */
+	struct udma_rlimit_common rlimit;
+	uint32_t rsrvd_2[2];
+	/* [0x80] DWRR scheduler configuration */
+	uint32_t dwrr_cfg_1;
+	/* [0x84] DWRR scheduler configuration */
+	uint32_t dwrr_cfg_2;
+	/* [0x88] DWRR scheduler configuration */
+	uint32_t dwrr_cfg_3;
+	/* [0x8c] DWRR scheduler software control */
+	uint32_t dwrr_sw_ctrl;
+	uint32_t rsrvd_3[4];
+	/* [0xa0] Completion controller configuration */
+	uint32_t comp_cfg;
+	uint32_t rsrvd_4[3];
+	/* [0xb0] SW control  */
+	uint32_t q_sw_ctrl;
+	uint32_t rsrvd_5[3];
+	/* [0xc0] Number of M2S Tx packets after the scheduler */
+	uint32_t q_tx_pkt;
+	uint32_t rsrvd[975];
+};
+
+struct udma_m2s_regs {
+	uint32_t rsrvd_0[64];
+	struct udma_axi_m2s axi_m2s;                     /* [0x100] */
+	struct udma_m2s m2s;                             /* [0x200] */
+	struct udma_m2s_rd m2s_rd;                       /* [0x300] */
+	struct udma_m2s_dwrr m2s_dwrr;                   /* [0x340] */
+	struct udma_m2s_rate_limiter m2s_rate_limiter;   /* [0x380] */
+	struct udma_m2s_stream_rate_limiter m2s_stream_rate_limiter; /* [0x3c0] */
+	struct udma_m2s_comp m2s_comp;                   /* [0x400] */
+	struct udma_m2s_stat m2s_stat;                   /* [0x500] */
+	struct udma_m2s_feature m2s_feature;             /* [0x600] */
+	uint32_t rsrvd_1[576];
+	struct udma_m2s_q m2s_q[4];                      /* [0x1000] */
+};
+
+
+/*
+* Registers Fields
+*/
+
+
+/**** comp_wr_cfg_1 register ****/
+/* AXI write  ID (AWID) */
+#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK 0x000000FF
+#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_SHIFT 0
+/* Cache Type */
+#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_MASK 0x000F0000
+#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_SHIFT 16
+/* Burst type */
+#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_MASK 0x03000000
+#define UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_SHIFT 24
+
+/**** comp_wr_cfg_2 register ****/
+/* User extension */
+#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK 0x000FFFFF
+#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_SHIFT 0
+/* Bus size, 128-bit */
+#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_MASK 0x00700000
+#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_SHIFT 20
+/*
+ * AXI Master QoS.
+ * Used for arbitration between AXI masters
+ */
+#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_MASK 0x07000000
+#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_SHIFT 24
+/* Protection Type */
+#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_MASK 0x70000000
+#define UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_SHIFT 28
+
+/**** data_rd_cfg_1 register ****/
+/* AXI read  ID (ARID) */
+#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARID_MASK 0x000000FF
+#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARID_SHIFT 0
+/* Cache Type */
+#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARCACHE_MASK 0x000F0000
+#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARCACHE_SHIFT 16
+/* Burst type */
+#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARBURST_MASK 0x03000000
+#define UDMA_AXI_M2S_DATA_RD_CFG_1_ARBURST_SHIFT 24
+
+/**** data_rd_cfg_2 register ****/
+/* User extension */
+#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARUSER_MASK 0x000FFFFF
+#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARUSER_SHIFT 0
+/* Bus size, 128-bit */
+#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARSIZE_MASK 0x00700000
+#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARSIZE_SHIFT 20
+/*
+ * AXI Master QoS.
+ * Used for arbitration between AXI masters
+ */
+#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARQOS_MASK 0x07000000
+#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARQOS_SHIFT 24
+/* Protection Type */
+#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARPROT_MASK 0x70000000
+#define UDMA_AXI_M2S_DATA_RD_CFG_2_ARPROT_SHIFT 28
+
+/**** desc_rd_cfg_1 register ****/
+/* AXI read  ID (ARID) */
+#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARID_MASK 0x000000FF
+#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARID_SHIFT 0
+/* Cache Type */
+#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARCACHE_MASK 0x000F0000
+#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARCACHE_SHIFT 16
+/* Burst type */
+#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARBURST_MASK 0x03000000
+#define UDMA_AXI_M2S_DESC_RD_CFG_1_ARBURST_SHIFT 24
+
+/**** desc_rd_cfg_2 register ****/
+/* User extension */
+#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARUSER_MASK 0x000FFFFF
+#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARUSER_SHIFT 0
+/* Bus size, 128-bit */
+#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARSIZE_MASK 0x00700000
+#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARSIZE_SHIFT 20
+/*
+ * AXI Master QoS
+ * Used for arbitration between AXI masters
+ */
+#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARQOS_MASK 0x07000000
+#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARQOS_SHIFT 24
+/* Protection Type */
+#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARPROT_MASK 0x70000000
+#define UDMA_AXI_M2S_DESC_RD_CFG_2_ARPROT_SHIFT 28
+
+/**** data_rd_cfg register ****/
+/*
+ * Defines the maximum number of AXI beats for a single AXI burst.
+ * This value is used for a burst split decision.
+ */
+#define UDMA_AXI_M2S_DATA_RD_CFG_MAX_AXI_BEATS_MASK 0x000000FF
+#define UDMA_AXI_M2S_DATA_RD_CFG_MAX_AXI_BEATS_SHIFT 0
+/*
+ * Enable breaking data read request.
+ * Aligned to max_AXI_beats when the total read size is less than max_AXI_beats
+ */
+#define UDMA_AXI_M2S_DATA_RD_CFG_ALWAYS_BREAK_ON_MAX_BOUDRY (1 << 16)
+
+/**** desc_rd_cfg_3 register ****/
+/*
+ * Defines the maximum number of AXI beats for a single AXI burst.
+ * This value is used for a burst split decision.
+ * Maximum burst size for reading data( in AXI beats, 128-bits)
+ * (default – 16 beats, 256 bytes)
+ */
+#define UDMA_AXI_M2S_DESC_RD_CFG_3_MAX_AXI_BEATS_MASK 0x000000FF
+#define UDMA_AXI_M2S_DESC_RD_CFG_3_MAX_AXI_BEATS_SHIFT 0
+/*
+ * Enable breaking descriptor read request.
+ * Aligned to max_AXI_beats when the total read size is less than max_AXI_beats.
+ */
+#define UDMA_AXI_M2S_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY (1 << 16)
+
+/**** desc_wr_cfg_1 register ****/
+/*
+ * Defines the maximum number of AXI beats for a single AXI burst.
+ * This value is used for a burst split decision.
+ */
+#define UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK 0x000000FF
+#define UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_SHIFT 0
+/*
+ * Minimum burst for writing completion descriptors.
+ * Defined in AXI beats
+ * 4 Descriptors per beat.
+ * Value must be aligned to cache lines (64 bytes).
+ * Default value is 2 cache lines, 32 descriptors, 8 beats.
+ */
+#define UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK 0x00FF0000
+#define UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT 16
+
+/**** ostand_cfg register ****/
+/* Maximum number of outstanding data reads to the AXI (AXI transactions) */
+#define UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_MASK 0x0000003F
+#define UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_SHIFT 0
+/*
+ * Maximum number of outstanding descriptor reads to the AXI (AXI transactions)
+ */
+#define UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_MASK 0x00003F00
+#define UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_SHIFT 8
+/*
+ * Maximum number of outstanding descriptor writes to the AXI (AXI transactions)
+ */
+#define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_MASK 0x003F0000
+#define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_SHIFT 16
+/*
+ * Maximum number of outstanding data beats for descriptor write to AXI (AXI
+ * beats)
+ */
+#define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_MASK 0xFF000000
+#define UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_SHIFT 24
+
+/**** state register ****/
+/* Completion control */
+#define UDMA_M2S_STATE_COMP_CTRL_MASK 0x00000003
+#define UDMA_M2S_STATE_COMP_CTRL_SHIFT 0
+/* Stream interface */
+#define UDMA_M2S_STATE_STREAM_IF_MASK 0x00000030
+#define UDMA_M2S_STATE_STREAM_IF_SHIFT 4
+/* Data read control */
+#define UDMA_M2S_STATE_DATA_RD_CTRL_MASK 0x00000300
+#define UDMA_M2S_STATE_DATA_RD_CTRL_SHIFT 8
+/* Descriptor prefetch */
+#define UDMA_M2S_STATE_DESC_PREF_MASK 0x00003000
+#define UDMA_M2S_STATE_DESC_PREF_SHIFT 12
+
+/**** change_state register ****/
+/* Start normal operation */
+#define UDMA_M2S_CHANGE_STATE_NORMAL (1 << 0)
+/* Stop normal operation */
+#define UDMA_M2S_CHANGE_STATE_DIS    (1 << 1)
+/*
+ * Stop all machines.
+ * (Prefetch, scheduling, completion and stream interface)
+ */
+#define UDMA_M2S_CHANGE_STATE_ABORT  (1 << 2)
+
+/**** err_log_mask register ****/
+/*
+ * Mismatch of packet serial number.
+ * (between first packet in the unacknowledged FIFO and received ack from the
+ * stream)
+ */
+#define UDMA_M2S_ERR_LOG_MASK_COMP_PKT_MISMATCH (1 << 0)
+/* Parity error */
+#define UDMA_M2S_ERR_LOG_MASK_STREAM_AXI_PARITY (1 << 1)
+/* AXI response error */
+#define UDMA_M2S_ERR_LOG_MASK_STREAM_AXI_RESPONSE (1 << 2)
+/* AXI timeout (ack not received) */
+#define UDMA_M2S_ERR_LOG_MASK_STREAM_AXI_TOUT (1 << 3)
+/* Parity error */
+#define UDMA_M2S_ERR_LOG_MASK_COMP_AXI_PARITY (1 << 4)
+/* AXI response error */
+#define UDMA_M2S_ERR_LOG_MASK_COMP_AXI_RESPONSE (1 << 5)
+/* AXI timeout */
+#define UDMA_M2S_ERR_LOG_MASK_COMP_AXI_TOUT (1 << 6)
+/* Parity error */
+#define UDMA_M2S_ERR_LOG_MASK_DATA_AXI_PARITY (1 << 7)
+/* AXI response error */
+#define UDMA_M2S_ERR_LOG_MASK_DATA_AXI_RESPONSE (1 << 8)
+/* AXI timeout */
+#define UDMA_M2S_ERR_LOG_MASK_DATA_AXI_TOUT (1 << 9)
+/* Parity error */
+#define UDMA_M2S_ERR_LOG_MASK_PREF_AXI_PARITY (1 << 10)
+/* AXI response error */
+#define UDMA_M2S_ERR_LOG_MASK_PREF_AXI_RESPONSE (1 << 11)
+/* AXI timeout */
+#define UDMA_M2S_ERR_LOG_MASK_PREF_AXI_TOUT (1 << 12)
+/* Packet length error */
+#define UDMA_M2S_ERR_LOG_MASK_PREF_PKT_LEN_OVERFLOW (1 << 13)
+/* Maximum number of descriptors per packet error */
+#define UDMA_M2S_ERR_LOG_MASK_PREF_MAX_DESC_CNT (1 << 14)
+/* Error in first bit indication of the descriptor */
+#define UDMA_M2S_ERR_LOG_MASK_PREF_FIRST (1 << 15)
+/* Error in last bit indication of the descriptor */
+#define UDMA_M2S_ERR_LOG_MASK_PREF_LAST (1 << 16)
+/* Ring_ID error */
+#define UDMA_M2S_ERR_LOG_MASK_PREF_RING_ID (1 << 17)
+/* Data buffer parity error */
+#define UDMA_M2S_ERR_LOG_MASK_DATA_BUFF_PARITY (1 << 18)
+/* Internal error */
+#define UDMA_M2S_ERR_LOG_MASK_INTERNAL_MASK 0xFFF80000
+#define UDMA_M2S_ERR_LOG_MASK_INTERNAL_SHIFT 19
+
+/**** clear_err_log register ****/
+/* Clear error log */
+#define UDMA_M2S_CLEAR_ERR_LOG_CLEAR (1 << 0)
+
+/**** data_fifo_status register ****/
+/* FIFO used indication */
+#define UDMA_M2S_DATA_FIFO_STATUS_USED_MASK 0x0000FFFF
+#define UDMA_M2S_DATA_FIFO_STATUS_USED_SHIFT 0
+/* FIFO empty indication */
+#define UDMA_M2S_DATA_FIFO_STATUS_EMPTY (1 << 24)
+/* FIFO full indication */
+#define UDMA_M2S_DATA_FIFO_STATUS_FULL (1 << 28)
+
+/**** header_fifo_status register ****/
+/* FIFO used indication */
+#define UDMA_M2S_HEADER_FIFO_STATUS_USED_MASK 0x0000FFFF
+#define UDMA_M2S_HEADER_FIFO_STATUS_USED_SHIFT 0
+/* FIFO empty indication */
+#define UDMA_M2S_HEADER_FIFO_STATUS_EMPTY (1 << 24)
+/* FIFO full indication */
+#define UDMA_M2S_HEADER_FIFO_STATUS_FULL (1 << 28)
+
+/**** unack_fifo_status register ****/
+/* FIFO used indication */
+#define UDMA_M2S_UNACK_FIFO_STATUS_USED_MASK 0x0000FFFF
+#define UDMA_M2S_UNACK_FIFO_STATUS_USED_SHIFT 0
+/* FIFO empty indication */
+#define UDMA_M2S_UNACK_FIFO_STATUS_EMPTY (1 << 24)
+/* FIFO full indication */
+#define UDMA_M2S_UNACK_FIFO_STATUS_FULL (1 << 28)
+
+/**** indirect_ctrl register ****/
+/* Selected queue for status read */
+#define UDMA_M2S_INDIRECT_CTRL_Q_NUM_MASK 0x00000FFF
+#define UDMA_M2S_INDIRECT_CTRL_Q_NUM_SHIFT 0
+
+/**** sel_pref_fifo_status register ****/
+/* FIFO used indication */
+#define UDMA_M2S_SEL_PREF_FIFO_STATUS_USED_MASK 0x0000FFFF
+#define UDMA_M2S_SEL_PREF_FIFO_STATUS_USED_SHIFT 0
+/* FIFO empty indication */
+#define UDMA_M2S_SEL_PREF_FIFO_STATUS_EMPTY (1 << 24)
+/* FIFO full indication */
+#define UDMA_M2S_SEL_PREF_FIFO_STATUS_FULL (1 << 28)
+
+/**** sel_comp_fifo_status register ****/
+/* FIFO used indication */
+#define UDMA_M2S_SEL_COMP_FIFO_STATUS_USED_MASK 0x0000FFFF
+#define UDMA_M2S_SEL_COMP_FIFO_STATUS_USED_SHIFT 0
+/* FIFO empty indication */
+#define UDMA_M2S_SEL_COMP_FIFO_STATUS_EMPTY (1 << 24)
+/* FIFO full indication */
+#define UDMA_M2S_SEL_COMP_FIFO_STATUS_FULL (1 << 28)
+
+/**** sel_rate_limit_status register ****/
+/* Token counter */
+#define UDMA_M2S_SEL_RATE_LIMIT_STATUS_TOKEN_CNT_MASK 0x00FFFFFF
+#define UDMA_M2S_SEL_RATE_LIMIT_STATUS_TOKEN_CNT_SHIFT 0
+
+/**** sel_dwrr_status register ****/
+/* Deficit counter */
+#define UDMA_M2S_SEL_DWRR_STATUS_DEFICIT_CNT_MASK 0x00FFFFFF
+#define UDMA_M2S_SEL_DWRR_STATUS_DEFICIT_CNT_SHIFT 0
+
+/**** cfg_len register ****/
+/* Maximum packet size for the M2S */
+#define UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_MASK 0x000FFFFF
+#define UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_SHIFT 0
+/*
+ * Length encoding for 64K.
+ * 0 - length 0x0000 = 0
+ * 1 - length 0x0000 = 64k
+ */
+#define UDMA_M2S_CFG_LEN_ENCODE_64K  (1 << 24)
+
+/**** stream_cfg register ****/
+/*
+ * Disables the stream interface operation.
+ * Changing to 1 stops at the end of packet transmission.
+ */
+#define UDMA_M2S_STREAM_CFG_DISABLE  (1 << 0)
+/*
+ * Configuration of the stream FIFO read control.
+ * 0 - Cut through
+ * 1 - Threshold based
+ */
+#define UDMA_M2S_STREAM_CFG_RD_MODE  (1 << 1)
+/* Minimum number of beats to start packet transmission. */
+#define UDMA_M2S_STREAM_CFG_RD_TH_MASK 0x0003FF00
+#define UDMA_M2S_STREAM_CFG_RD_TH_SHIFT 8
+
+/**** desc_pref_cfg_1 register ****/
+/* Size of the descriptor prefetch FIFO (in descriptors) */
+#define UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK 0x000000FF
+#define UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_SHIFT 0
+
+/**** desc_pref_cfg_2 register ****/
+/* Maximum number of descriptors per packet */
+#define UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK 0x0000001F
+#define UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_SHIFT 0
+/*
+ * Force RR arbitration in the prefetch arbiter.
+ * 0 -Standard arbitration based on queue QoS
+ * 1 - Force Round Robin arbitration
+ */
+#define UDMA_M2S_RD_DESC_PREF_CFG_2_PREF_FORCE_RR (1 << 16)
+
+/**** desc_pref_cfg_3 register ****/
+/*
+ * Minimum descriptor burst size when prefetch FIFO level is below the
+ * descriptor prefetch threshold
+ * (must be 1)
+ */
+#define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK 0x0000000F
+#define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_SHIFT 0
+/*
+ * Minimum descriptor burst size when prefetch FIFO level is above the
+ * descriptor prefetch threshold
+ */
+#define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK 0x000000F0
+#define UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT 4
+/*
+ * Descriptor fetch threshold.
+ * Used as a threshold to determine the allowed minimum descriptor burst size.
+ * (Must be at least max_desc_per_pkt)
+ */
+#define UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK 0x0000FF00
+#define UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT 8
+
+/**** data_cfg register ****/
+/*
+ * Maximum number of data beats in the data read FIFO.
+ * Defined based on data FIFO size
+ * (default FIFO size 2KB → 128 beats)
+ */
+#define UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK 0x000003FF
+#define UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_SHIFT 0
+/*
+ * Maximum number of packets in the data read FIFO.
+ * Defined based on header FIFO size
+ */
+#define UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_MASK 0x00FF0000
+#define UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_SHIFT 16
+
+/**** cfg_sched register ****/
+/*
+ * Enable the DWRR scheduler.
+ * If this bit is 0, queues with same QoS will be served with RR scheduler.
+ */
+#define UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR (1 << 0)
+/*
+ * Scheduler operation mode.
+ * 0 - Byte mode
+ * 1 - Packet mode
+ */
+#define UDMA_M2S_DWRR_CFG_SCHED_PKT_MODE_EN (1 << 4)
+/*
+ * Enable incrementing the weight factor between DWRR iterations.
+ * 00 - Don't increase the increment factor.
+ * 01 - Increment once
+ * 10 - Increment exponential
+ * 11 - Reserved
+ */
+#define UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_MASK 0x00000300
+#define UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_SHIFT 8
+/*
+ * Increment factor power of 2.
+ * 7 --> 128 bytes
+ * This is the factor used to multiply the weight.
+ */
+#define UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_MASK 0x000F0000
+#define UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_SHIFT 16
+
+/**** ctrl_deficit_cnt register ****/
+/*
+ * Init value for the deficit counter.
+ * Initializes the deficit counters of all queues to this value any time this
+ * register is written.
+ */
+#define UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_MASK 0x00FFFFFF
+#define UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_SHIFT 0
+
+/**** gen_cfg register ****/
+/* Size of the basic token fill cycle, system clock cycles */
+#define UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_MASK 0x0000FFFF
+#define UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_SHIFT 0
+/*
+ * Rate limiter operation mode.
+ * 0 - Byte mode
+ * 1 - Packet mode
+ */
+#define UDMA_M2S_RATE_LIMITER_GEN_CFG_PKT_MODE_EN (1 << 24)
+
+/**** ctrl_cycle_cnt register ****/
+/* Reset the short and long cycle counters. */
+#define UDMA_M2S_RATE_LIMITER_CTRL_CYCLE_CNT_RST (1 << 0)
+
+/**** ctrl_token register ****/
+/*
+ * Init value for the token counter.
+ * Initializes the token counters of all queues to this value any time this
+ * register is written.
+ */
+#define UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_MASK 0x00FFFFFF
+#define UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_SHIFT 0
+
+/**** cfg_1s register ****/
+/* Maximum number of accumulated bytes in the token counter */
+#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_MASK 0x00FFFFFF
+#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_SHIFT 0
+/* Enable the rate limiter. */
+#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_EN (1 << 24)
+/* Stop token fill. */
+#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_PAUSE (1 << 25)
+
+/**** cfg_cycle register ****/
+/* Number of short cycles between token fills */
+#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_MASK 0x0000FFFF
+#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_SHIFT 0
+
+/**** cfg_token_size_1 register ****/
+/* Number of bits to add in each long cycle */
+#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK 0x0007FFFF
+#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_SHIFT 0
+
+/**** cfg_token_size_2 register ****/
+/* Number of bits to add in each short cycle */
+#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK 0x0007FFFF
+#define UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_SHIFT 0
+
+/**** sw_ctrl register ****/
+/* Reset the token bucket counter. */
+#define UDMA_M2S_STREAM_RATE_LIMITER_SW_CTRL_RST_TOKEN_CNT (1 << 0)
+
+/**** mask register ****/
+/* Mask the external rate limiter. */
+#define UDMA_M2S_STREAM_RATE_LIMITER_MASK_EXTERNAL_RATE_LIMITER (1 << 0)
+/* Mask the internal rate limiter. */
+#define UDMA_M2S_STREAM_RATE_LIMITER_MASK_INTERNAL_RATE_LIMITER (1 << 1)
+/* Mask the external application pause interface. */
+#define UDMA_M2S_STREAM_RATE_LIMITER_MASK_EXTERNAL_PAUSE (1 << 3)
+
+/**** cfg_1c register ****/
+/*
+ * Completion FIFO size
+ *  (descriptors per queue)
+ */
+#define UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_MASK 0x000000FF
+#define UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_SHIFT 0
+/*
+ * Unacknowledged FIFO size.
+ * (descriptors)
+ */
+#define UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_MASK 0x0001FF00
+#define UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_SHIFT 8
+/*
+ * Enable promotion.
+ * Enable the promotion of the current queue in progress for the completion
+ * write scheduler.
+ */
+#define UDMA_M2S_COMP_CFG_1C_Q_PROMOTION (1 << 24)
+/* Force RR arbitration in the completion arbiter */
+#define UDMA_M2S_COMP_CFG_1C_FORCE_RR (1 << 25)
+/* Minimum number of free completion entries to qualify for promotion */
+#define UDMA_M2S_COMP_CFG_1C_Q_FREE_MIN_MASK 0xF0000000
+#define UDMA_M2S_COMP_CFG_1C_Q_FREE_MIN_SHIFT 28
+
+/**** cfg_application_ack register ****/
+/*
+ * Acknowledge timeout timer.
+ * ACK from the application through the stream interface)
+ */
+#define UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_MASK 0x00FFFFFF
+#define UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_SHIFT 0
+
+/**** cfg_st register ****/
+/* Use additional length value for all statistics counters. */
+#define UDMA_M2S_STAT_CFG_ST_USE_EXTRA_LEN (1 << 0)
+
+/**** reg_1 register ****/
+/*
+ * Read the size of the descriptor prefetch FIFO
+ * (descriptors).
+ */
+#define UDMA_M2S_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_MASK 0x000000FF
+#define UDMA_M2S_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_SHIFT 0
+
+/**** reg_3 register ****/
+/*
+ * Maximum number of data beats in the data read FIFO.
+ * Defined based on data FIFO size
+ * (default FIFO size 2KB → 128 beats)
+ */
+#define UDMA_M2S_FEATURE_REG_3_DATA_FIFO_DEPTH_MASK 0x000003FF
+#define UDMA_M2S_FEATURE_REG_3_DATA_FIFO_DEPTH_SHIFT 0
+/*
+ * Maximum number of packets in the data read FIFO.
+ * Defined based on header FIFO size
+ */
+#define UDMA_M2S_FEATURE_REG_3_DATA_RD_MAX_PKT_LIMIT_MASK 0x00FF0000
+#define UDMA_M2S_FEATURE_REG_3_DATA_RD_MAX_PKT_LIMIT_SHIFT 16
+
+/**** reg_4 register ****/
+/*
+ * Size of the completion FIFO of each queue
+ * (words)
+ */
+#define UDMA_M2S_FEATURE_REG_4_COMP_FIFO_DEPTH_MASK 0x000000FF
+#define UDMA_M2S_FEATURE_REG_4_COMP_FIFO_DEPTH_SHIFT 0
+/* Size of the unacknowledged FIFO (descriptors) */
+#define UDMA_M2S_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_MASK 0x0001FF00
+#define UDMA_M2S_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_SHIFT 8
+
+/**** reg_5 register ****/
+/* Maximum number of outstanding data reads to AXI */
+#define UDMA_M2S_FEATURE_REG_5_MAX_DATA_RD_OSTAND_MASK 0x0000003F
+#define UDMA_M2S_FEATURE_REG_5_MAX_DATA_RD_OSTAND_SHIFT 0
+/* Maximum number of outstanding descriptor reads to AXI */
+#define UDMA_M2S_FEATURE_REG_5_MAX_DESC_RD_OSTAND_MASK 0x00003F00
+#define UDMA_M2S_FEATURE_REG_5_MAX_DESC_RD_OSTAND_SHIFT 8
+/*
+ * Maximum number of outstanding descriptor writes to AXI.
+ * (AXI transactions)
+ */
+#define UDMA_M2S_FEATURE_REG_5_MAX_COMP_REQ_MASK 0x003F0000
+#define UDMA_M2S_FEATURE_REG_5_MAX_COMP_REQ_SHIFT 16
+/*
+ * Maximum number of outstanding data beats for descriptor write to AXI.
+ * (AXI beats)
+ */
+#define UDMA_M2S_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_MASK 0xFF000000
+#define UDMA_M2S_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_SHIFT 24
+
+/**** cfg register ****/
+/*
+ * Length offset to be used for each packet from this queue.
+ * (length offset is used for the scheduler and rate limiter).
+ */
+#define UDMA_M2S_Q_CFG_PKT_LEN_OFFSET_MASK 0x0000FFFF
+#define UDMA_M2S_Q_CFG_PKT_LEN_OFFSET_SHIFT 0
+/*
+ * Enable operation of this queue.
+ * Start prefetch.
+ */
+#define UDMA_M2S_Q_CFG_EN_PREF       (1 << 16)
+/*
+ * Enable operation of this queue.
+ * Start scheduling.
+ */
+#define UDMA_M2S_Q_CFG_EN_SCHEDULING (1 << 17)
+/* Allow prefetch of less than minimum prefetch burst size. */
+#define UDMA_M2S_Q_CFG_ALLOW_LT_MIN_PREF (1 << 20)
+/* Configure the AXI AWCACHE for completion write.  */
+#define UDMA_M2S_Q_CFG_AXI_AWCACHE_COMP_MASK 0x0F000000
+#define UDMA_M2S_Q_CFG_AXI_AWCACHE_COMP_SHIFT 24
+/*
+ * AXI QoS for the selected queue.
+ * This value is used in AXI transactions associated with this queue and the
+ * prefetch and completion arbiters.
+ */
+#define UDMA_M2S_Q_CFG_AXI_QOS_MASK  0x70000000
+#define UDMA_M2S_Q_CFG_AXI_QOS_SHIFT 28
+
+/**** status register ****/
+/* Indicates how many entries are used in the queue */
+#define UDMA_M2S_Q_STATUS_Q_USED_MASK 0x01FFFFFF
+#define UDMA_M2S_Q_STATUS_Q_USED_SHIFT 0
+/*
+ * prefetch status
+ * 0 – prefetch operation is stopped
+ * 1 – prefetch is operational
+ */
+#define UDMA_M2S_Q_STATUS_PREFETCH   (1 << 28)
+/*
+ * Queue scheduler status
+ * 0 – queue is not active and not participating in scheduling
+ * 1 – queue is active and participating in the scheduling process
+ */
+#define UDMA_M2S_Q_STATUS_SCHEDULER  (1 << 29)
+/* Queue is suspended due to DMB */
+#define UDMA_M2S_Q_STATUS_Q_DMB      (1 << 30)
+/*
+ * Queue full indication.
+ * (used by the host when head pointer equals tail pointer).
+ */
+#define UDMA_M2S_Q_STATUS_Q_FULL     (1 << 31)
+/*
+ * M2S Descriptor Ring Base address [31:4].
+ * Value of the base address of the M2S descriptor ring
+ * [3:0] - 0 - 16B alignment is enforced
+ * ([11:4] should be 0 for 4KB alignment)
+ */
+#define UDMA_M2S_Q_TDRBP_LOW_ADDR_MASK 0xFFFFFFF0
+#define UDMA_M2S_Q_TDRBP_LOW_ADDR_SHIFT 4
+
+/**** TDRL register ****/
+/*
+ * Length of the descriptor ring.
+ * (descriptors)
+ * Associated with the ring base address, ends at maximum burst size alignment.
+ */
+#define UDMA_M2S_Q_TDRL_OFFSET_MASK  0x00FFFFFF
+#define UDMA_M2S_Q_TDRL_OFFSET_SHIFT 0
+
+/**** TDRHP register ****/
+/*
+ * Relative offset of the next descriptor that needs to be read into the
+ * prefetch FIFO.
+ * Incremented when the DMA reads valid descriptors from the host memory to the
+ * prefetch FIFO.
+ * Note that this is the offset in # of descriptors and not in byte address.
+ */
+#define UDMA_M2S_Q_TDRHP_OFFSET_MASK 0x00FFFFFF
+#define UDMA_M2S_Q_TDRHP_OFFSET_SHIFT 0
+/* Ring ID */
+#define UDMA_M2S_Q_TDRHP_RING_ID_MASK 0xC0000000
+#define UDMA_M2S_Q_TDRHP_RING_ID_SHIFT 30
+
+/**** TDRTP_inc register ****/
+/* Increments the value in Q_TDRTP (descriptors) */
+#define UDMA_M2S_Q_TDRTP_INC_VAL_MASK 0x00FFFFFF
+#define UDMA_M2S_Q_TDRTP_INC_VAL_SHIFT 0
+
+/**** TDRTP register ****/
+/*
+ * Relative offset of the next free descriptor in the host memory.
+ * Note that this is the offset in # of descriptors and not in byte address.
+ */
+#define UDMA_M2S_Q_TDRTP_OFFSET_MASK 0x00FFFFFF
+#define UDMA_M2S_Q_TDRTP_OFFSET_SHIFT 0
+/* Ring ID */
+#define UDMA_M2S_Q_TDRTP_RING_ID_MASK 0xC0000000
+#define UDMA_M2S_Q_TDRTP_RING_ID_SHIFT 30
+
+/**** TDCP register ****/
+/*
+ * Relative offset of the first descriptor in the prefetch FIFO.
+ * This is the next descriptor that will be read by the scheduler.
+ */
+#define UDMA_M2S_Q_TDCP_OFFSET_MASK  0x00FFFFFF
+#define UDMA_M2S_Q_TDCP_OFFSET_SHIFT 0
+/* Ring ID */
+#define UDMA_M2S_Q_TDCP_RING_ID_MASK 0xC0000000
+#define UDMA_M2S_Q_TDCP_RING_ID_SHIFT 30
+/*
+ * M2S Descriptor Ring Base address [31:4].
+ * Value of the base address of the M2S descriptor ring
+ * [3:0] - 0 - 16B alignment is enforced
+ * ([11:4] should be 0 for 4KB alignment)
+ * NOTE:
+ * Length of the descriptor ring (in descriptors) associated with the ring base
+ * address. Ends at maximum burst size alignment.
+ */
+#define UDMA_M2S_Q_TCRBP_LOW_ADDR_MASK 0xFFFFFFF0
+#define UDMA_M2S_Q_TCRBP_LOW_ADDR_SHIFT 4
+
+/**** TCRHP register ****/
+/*
+ * Relative offset of the next descriptor that needs to be updated by the
+ * completion controller.
+ * Note: This is in descriptors and not in byte address.
+ */
+#define UDMA_M2S_Q_TCRHP_OFFSET_MASK 0x00FFFFFF
+#define UDMA_M2S_Q_TCRHP_OFFSET_SHIFT 0
+/* Ring ID */
+#define UDMA_M2S_Q_TCRHP_RING_ID_MASK 0xC0000000
+#define UDMA_M2S_Q_TCRHP_RING_ID_SHIFT 30
+
+/**** TCRHP_internal register ****/
+/*
+ * Relative offset of the next descriptor that needs to be updated by the
+ * completion controller.
+ * Note: This is in descriptors and not in byte address.
+ */
+#define UDMA_M2S_Q_TCRHP_INTERNAL_OFFSET_MASK 0x00FFFFFF
+#define UDMA_M2S_Q_TCRHP_INTERNAL_OFFSET_SHIFT 0
+/* Ring ID */
+#define UDMA_M2S_Q_TCRHP_INTERNAL_RING_ID_MASK 0xC0000000
+#define UDMA_M2S_Q_TCRHP_INTERNAL_RING_ID_SHIFT 30
+
+/**** rate_limit_cfg_1 register ****/
+/* Maximum number of accumulated bytes in the token counter. */
+#define UDMA_M2S_Q_RATE_LIMIT_CFG_1_MAX_BURST_SIZE_MASK 0x00FFFFFF
+#define UDMA_M2S_Q_RATE_LIMIT_CFG_1_MAX_BURST_SIZE_SHIFT 0
+/* Enable the rate limiter. */
+#define UDMA_M2S_Q_RATE_LIMIT_CFG_1_EN (1 << 24)
+/* Stop token fill. */
+#define UDMA_M2S_Q_RATE_LIMIT_CFG_1_PAUSE (1 << 25)
+
+/**** rate_limit_cfg_cycle register ****/
+/* Number of short cycles between token fills */
+#define UDMA_M2S_Q_RATE_LIMIT_CFG_CYCLE_LONG_CYCLE_SIZE_MASK 0x0000FFFF
+#define UDMA_M2S_Q_RATE_LIMIT_CFG_CYCLE_LONG_CYCLE_SIZE_SHIFT 0
+
+/**** rate_limit_cfg_token_size_1 register ****/
+/* Number of bits to add in each long cycle */
+#define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK 0x0007FFFF
+#define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_1_LONG_CYCLE_SHIFT 0
+
+/**** rate_limit_cfg_token_size_2 register ****/
+/* Number of bits to add in each cycle */
+#define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK 0x0007FFFF
+#define UDMA_M2S_Q_RATE_LIMIT_CFG_TOKEN_SIZE_2_SHORT_CYCLE_SHIFT 0
+
+/**** rate_limit_sw_ctrl register ****/
+/* Reset the token bucket counter. */
+#define UDMA_M2S_Q_RATE_LIMIT_SW_CTRL_RST_TOKEN_CNT (1 << 0)
+
+/**** rate_limit_mask register ****/
+/* Mask the external rate limiter. */
+#define UDMA_M2S_Q_RATE_LIMIT_MASK_EXTERNAL_RATE_LIMITER (1 << 0)
+/* Mask the internal rate limiter. */
+#define UDMA_M2S_Q_RATE_LIMIT_MASK_INTERNAL_RATE_LIMITER (1 << 1)
+/*
+ * Mask the internal pause mechanism for DMB.
+ * (Data Memory Barrier).
+ */
+#define UDMA_M2S_Q_RATE_LIMIT_MASK_INTERNAL_PAUSE_DMB (1 << 2)
+/* Mask the external application pause interface. */
+#define UDMA_M2S_Q_RATE_LIMIT_MASK_EXTERNAL_PAUSE (1 << 3)
+
+/**** dwrr_cfg_1 register ****/
+/* Maximum number of accumulated bytes in the deficit counter */
+#define UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_MASK 0x00FFFFFF
+#define UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_SHIFT 0
+/* Bypass the DWRR.  */
+#define UDMA_M2S_Q_DWRR_CFG_1_STRICT (1 << 24)
+/* Stop deficit counter increment. */
+#define UDMA_M2S_Q_DWRR_CFG_1_PAUSE  (1 << 25)
+
+/**** dwrr_cfg_2 register ****/
+/*
+ * Value for the queue QoS.
+ * Queues with the same QoS value are scheduled with RR/DWRR.
+ * Only LOG(number of queues) is used.
+ */
+#define UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK 0x000000FF
+#define UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_SHIFT 0
+
+/**** dwrr_cfg_3 register ****/
+/* Queue weight */
+#define UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK 0x000000FF
+#define UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_SHIFT 0
+
+/**** dwrr_sw_ctrl register ****/
+/* Reset the DWRR deficit counter. */
+#define UDMA_M2S_Q_DWRR_SW_CTRL_RST_CNT (1 << 0)
+
+/**** comp_cfg register ****/
+/* Enable writing to the completion ring */
+#define UDMA_M2S_Q_COMP_CFG_EN_COMP_RING_UPDATE (1 << 0)
+/* Disable the completion coalescing function. */
+#define UDMA_M2S_Q_COMP_CFG_DIS_COMP_COAL (1 << 1)
+
+/**** q_sw_ctrl register ****/
+/*
+ * Reset the DMB hardware barrier
+ * (enable queue operation).
+ */
+#define UDMA_M2S_Q_SW_CTRL_RST_DMB (1 << 0)
+/* Reset the tail pointer hardware. */
+#define UDMA_M2S_Q_SW_CTRL_RST_TAIL_PTR (1 << 1)
+/* Reset the head pointer hardware. */
+#define UDMA_M2S_Q_SW_CTRL_RST_HEAD_PTR (1 << 2)
+/* Reset the current pointer hardware. */
+#define UDMA_M2S_Q_SW_CTRL_RST_CURRENT_PTR (1 << 3)
+/* Reset the queue */
+#define UDMA_M2S_Q_SW_CTRL_RST_Q   (1 << 8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_UDMA_M2S_REG_H */
diff --git a/sys/contrib/alpine-hal/al_hal_udma_regs_s2m.h b/sys/contrib/alpine-hal/al_hal_udma_regs_s2m.h
new file mode 100644
index 000000000000..4b3149b97ae6
--- /dev/null
+++ b/sys/contrib/alpine-hal/al_hal_udma_regs_s2m.h
@@ -0,0 +1,998 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @file   al_hal_udma_regs_s2m.h
+ *
+ * @brief C Header file for the UDMA S2M registers
+ *
+ */
+
+#ifndef __AL_HAL_UDMA_S2M_REG_H
+#define __AL_HAL_UDMA_S2M_REG_H
+
+#include "al_hal_plat_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+
+
+struct udma_axi_s2m {
+	/* [0x0] Data write master configuration */
+	uint32_t data_wr_cfg_1;
+	/* [0x4] Data write master configuration */
+	uint32_t data_wr_cfg_2;
+	/* [0x8] Descriptor read master configuration */
+	uint32_t desc_rd_cfg_4;
+	/* [0xc] Descriptor read master configuration */
+	uint32_t desc_rd_cfg_5;
+	/* [0x10] Completion  write master configuration */
+	uint32_t comp_wr_cfg_1;
+	/* [0x14] Completion  write master configuration */
+	uint32_t comp_wr_cfg_2;
+	/* [0x18] Data write master configuration */
+	uint32_t data_wr_cfg;
+	/* [0x1c] Descriptors read master configuration */
+	uint32_t desc_rd_cfg_3;
+	/* [0x20] Completion descriptors write master configuration */
+	uint32_t desc_wr_cfg_1;
+	/* [0x24] AXI outstanding read configuration */
+	uint32_t ostand_cfg_rd;
+	/* [0x28] AXI outstanding write configuration */
+	uint32_t ostand_cfg_wr;
+	uint32_t rsrvd[53];
+};
+struct udma_s2m {
+	/*
+	 * [0x0] DMA state
+	 * 00  - No pending tasks
+	 * 01 – Normal (active)
+	 * 10 – Abort (error condition)
+	 * 11 – Reserved
+	 */
+	uint32_t state;
+	/* [0x4] CPU request to change DMA state */
+	uint32_t change_state;
+	uint32_t rsrvd_0;
+	/*
+	 * [0xc] S2M DMA error log mask.
+	 * Each error has an interrupt controller cause bit.
+	 * This register determines if these errors cause the S2M DMA to log the
+	 * error condition.
+	 * 0 - Log is enable
+	 * 1 - Log is masked.
+	 */
+	uint32_t err_log_mask;
+	uint32_t rsrvd_1;
+	/*
+	 * [0x14] DMA header log
+	 * Sample the packet header that caused the error
+	 */
+	uint32_t log_0;
+	/*
+	 * [0x18] DMA header log
+	 * Sample the packet header that caused the error.
+	 */
+	uint32_t log_1;
+	/*
+	 * [0x1c] DMA header log
+	 * Sample the packet header that caused the error.
+	 */
+	uint32_t log_2;
+	/*
+	 * [0x20] DMA header log
+	 * Sample the packet header that caused the error
+	 */
+	uint32_t log_3;
+	/* [0x24] DMA clear error log */
+	uint32_t clear_err_log;
+	/* [0x28] S2M stream data FIFO status */
+	uint32_t s_data_fifo_status;
+	/* [0x2c] S2M stream header FIFO status */
+	uint32_t s_header_fifo_status;
+	/* [0x30] S2M AXI data FIFO status */
+	uint32_t axi_data_fifo_status;
+	/* [0x34] S2M unack FIFO status */
+	uint32_t unack_fifo_status;
+	/* [0x38] Select queue for debug */
+	uint32_t indirect_ctrl;
+	/*
+	 * [0x3c] S2M prefetch FIFO status.
+	 * Status of the selected queue in S2M_indirect_ctrl
+	 */
+	uint32_t sel_pref_fifo_status;
+	/*
+	 * [0x40] S2M completion FIFO status.
+	 * Status of the selected queue in S2M_indirect_ctrl
+	 */
+	uint32_t sel_comp_fifo_status;
+	/* [0x44] S2M state machine and FIFO clear control */
+	uint32_t clear_ctrl;
+	/* [0x48] S2M Misc Check enable */
+	uint32_t check_en;
+	/* [0x4c] S2M FIFO enable control, internal */
+	uint32_t fifo_en;
+	/* [0x50] Stream interface configuration */
+	uint32_t stream_cfg;
+	uint32_t rsrvd[43];
+};
+struct udma_s2m_rd {
+	/* [0x0] S2M descriptor prefetch configuration */
+	uint32_t desc_pref_cfg_1;
+	/* [0x4] S2M descriptor prefetch configuration */
+	uint32_t desc_pref_cfg_2;
+	/* [0x8] S2M descriptor prefetch configuration */
+	uint32_t desc_pref_cfg_3;
+	/* [0xc] S2M descriptor prefetch configuration */
+	uint32_t desc_pref_cfg_4;
+	uint32_t rsrvd[12];
+};
+struct udma_s2m_wr {
+	/* [0x0] Stream data FIFO configuration */
+	uint32_t data_cfg_1;
+	/* [0x4] Data write configuration */
+	uint32_t data_cfg_2;
+	uint32_t rsrvd[14];
+};
+struct udma_s2m_comp {
+	/* [0x0] Completion controller configuration */
+	uint32_t cfg_1c;
+	/* [0x4] Completion controller configuration */
+	uint32_t cfg_2c;
+	uint32_t rsrvd_0;
+	/* [0xc] Completion controller application acknowledge configuration */
+	uint32_t cfg_application_ack;
+	uint32_t rsrvd[12];
+};
+struct udma_s2m_stat {
+	uint32_t rsrvd_0;
+	/* [0x4] Number of dropped packets */
+	uint32_t drop_pkt;
+	/*
+	 * [0x8] Counting the net length of the data buffers [64-bit]
+	 * Should be read before rx_bytes_high
+	 */
+	uint32_t rx_bytes_low;
+	/*
+	 * [0xc] Counting the net length of the data buffers [64-bit]
+	 * Should be read after tx_bytes_low (value is sampled when reading
+	 * Should be read before rx_bytes_low
+	 */
+	uint32_t rx_bytes_high;
+	/* [0x10] Total number of descriptors read from the host memory */
+	uint32_t prefed_desc;
+	/* [0x14] Number of packets written into the completion ring */
+	uint32_t comp_pkt;
+	/* [0x18] Number of descriptors written into the completion ring */
+	uint32_t comp_desc;
+	/*
+	 * [0x1c] Number of acknowledged packets.
+	 * (acknowledge sent to the stream interface)
+	 */
+	uint32_t ack_pkts;
+	uint32_t rsrvd[56];
+};
+struct udma_s2m_feature {
+	/*
+	 * [0x0] S2M Feature register
+	 * S2M instantiation parameters
+	 */
+	uint32_t reg_1;
+	/* [0x4] Reserved S2M feature register */
+	uint32_t reg_2;
+	/*
+	 * [0x8] S2M Feature register
+	 * S2M instantiation parameters
+	 */
+	uint32_t reg_3;
+	/*
+	 * [0xc] S2M Feature register.
+	 * S2M instantiation parameters.
+	 */
+	uint32_t reg_4;
+	/*
+	 * [0x10] S2M Feature register.
+	 * S2M instantiation parameters.
+	 */
+	uint32_t reg_5;
+	/* [0x14] S2M Feature register. S2M instantiation parameters. */
+	uint32_t reg_6;
+	uint32_t rsrvd[58];
+};
+struct udma_s2m_q {
+	uint32_t rsrvd_0[8];
+	/* [0x20] S2M Descriptor ring configuration */
+	uint32_t cfg;
+	/* [0x24] S2M Descriptor ring status and information */
+	uint32_t status;
+	/* [0x28] Rx Descriptor Ring Base Pointer [31:4] */
+	uint32_t rdrbp_low;
+	/* [0x2c] Rx Descriptor Ring Base Pointer [63:32] */
+	uint32_t rdrbp_high;
+	/*
+	 * [0x30] Rx Descriptor Ring Length[23:2]
+	 */
+	uint32_t rdrl;
+	/* [0x34] RX Descriptor Ring Head Pointer */
+	uint32_t rdrhp;
+	/* [0x38] Rx Descriptor Tail Pointer increment */
+	uint32_t rdrtp_inc;
+	/* [0x3c] Rx Descriptor Tail Pointer */
+	uint32_t rdrtp;
+	/* [0x40] RX Descriptor Current Pointer */
+	uint32_t rdcp;
+	/* [0x44] Rx Completion Ring Base Pointer [31:4] */
+	uint32_t rcrbp_low;
+	/* [0x48] Rx Completion Ring Base Pointer [63:32] */
+	uint32_t rcrbp_high;
+	/* [0x4c] Rx Completion Ring Head Pointer */
+	uint32_t rcrhp;
+	/*
+	 * [0x50] RX Completion Ring Head Pointer internal.
+	 * (Before the coalescing FIFO)
+	 */
+	uint32_t rcrhp_internal;
+	/* [0x54] Completion controller configuration for the queue */
+	uint32_t comp_cfg;
+	/* [0x58] Completion controller configuration for the queue */
+	uint32_t comp_cfg_2;
+	/* [0x5c] Packet handler configuration */
+	uint32_t pkt_cfg;
+	/* [0x60] Queue QoS configuration */
+	uint32_t qos_cfg;
+	/* [0x64] DMB software control */
+	uint32_t q_sw_ctrl;
+	/* [0x68] Number of S2M Rx packets after completion  */
+	uint32_t q_rx_pkt;
+	uint32_t rsrvd[997];
+};
+
+struct udma_s2m_regs {
+	uint32_t rsrvd_0[64];
+	struct udma_axi_s2m axi_s2m;                     /* [0x100] */
+	struct udma_s2m s2m;                             /* [0x200] */
+	struct udma_s2m_rd s2m_rd;                       /* [0x300] */
+	struct udma_s2m_wr s2m_wr;                       /* [0x340] */
+	struct udma_s2m_comp s2m_comp;                   /* [0x380] */
+	uint32_t rsrvd_1[80];
+	struct udma_s2m_stat s2m_stat;                   /* [0x500] */
+	struct udma_s2m_feature s2m_feature;             /* [0x600] */
+	uint32_t rsrvd_2[576];
+	struct udma_s2m_q s2m_q[4];                      /* [0x1000] */
+};
+
+
+/*
+* Registers Fields
+*/
+
+
+/**** data_wr_cfg_1 register ****/
+/* AXI write  ID (AWID) */
+#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWID_MASK 0x000000FF
+#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWID_SHIFT 0
+/* Cache Type */
+#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWCACHE_MASK 0x000F0000
+#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWCACHE_SHIFT 16
+/* Burst type */
+#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWBURST_MASK 0x03000000
+#define UDMA_AXI_S2M_DATA_WR_CFG_1_AWBURST_SHIFT 24
+
+/**** data_wr_cfg_2 register ****/
+/* User extension */
+#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWUSER_MASK 0x000FFFFF
+#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWUSER_SHIFT 0
+/* Bus size, 128-bit */
+#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWSIZE_MASK 0x00700000
+#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWSIZE_SHIFT 20
+/*
+ * AXI Master QoS.
+ * Used for arbitration between AXI masters
+ */
+#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWQOS_MASK 0x07000000
+#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWQOS_SHIFT 24
+/* Protection Type */
+#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWPROT_MASK 0x70000000
+#define UDMA_AXI_S2M_DATA_WR_CFG_2_AWPROT_SHIFT 28
+
+/**** desc_rd_cfg_4 register ****/
+/* AXI read  ID (ARID) */
+#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARID_MASK 0x000000FF
+#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARID_SHIFT 0
+/* Cache Type */
+#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARCACHE_MASK 0x000F0000
+#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARCACHE_SHIFT 16
+/* Burst type */
+#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARBURST_MASK 0x03000000
+#define UDMA_AXI_S2M_DESC_RD_CFG_4_ARBURST_SHIFT 24
+
+/**** desc_rd_cfg_5 register ****/
+/* User extension */
+#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARUSER_MASK 0x000FFFFF
+#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARUSER_SHIFT 0
+/* Bus size, 128-bit */
+#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARSIZE_MASK 0x00700000
+#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARSIZE_SHIFT 20
+/*
+ * AXI Master QoS.
+ * Used for arbitration between AXI masters
+ */
+#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARQOS_MASK 0x07000000
+#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARQOS_SHIFT 24
+/* Protection Type */
+#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARPROT_MASK 0x70000000
+#define UDMA_AXI_S2M_DESC_RD_CFG_5_ARPROT_SHIFT 28
+
+/**** comp_wr_cfg_1 register ****/
+/* AXI write  ID (AWID) */
+#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_MASK 0x000000FF
+#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_SHIFT 0
+/* Cache Type */
+#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_MASK 0x000F0000
+#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_SHIFT 16
+/* Burst type */
+#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_MASK 0x03000000
+#define UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_SHIFT 24
+
+/**** comp_wr_cfg_2 register ****/
+/* User extension */
+#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_MASK 0x000FFFFF
+#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_SHIFT 0
+/* Bus size, 128-bit */
+#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_MASK 0x00700000
+#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_SHIFT 20
+/*
+ * AXI Master QoS.
+ * Used for arbitration between AXI masters
+ */
+#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_MASK 0x07000000
+#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_SHIFT 24
+/* Protection Type */
+#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_MASK 0x70000000
+#define UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_SHIFT 28
+
+/**** data_wr_cfg register ****/
+/*
+ * Defines the maximum number of AXI beats for a single AXI burst. This value is
+ * used for the burst split decision.
+ */
+#define UDMA_AXI_S2M_DATA_WR_CFG_MAX_AXI_BEATS_MASK 0x000000FF
+#define UDMA_AXI_S2M_DATA_WR_CFG_MAX_AXI_BEATS_SHIFT 0
+
+/**** desc_rd_cfg_3 register ****/
+/*
+ * Defines the maximum number of AXI beats for a single AXI burst. This value is
+ * used for the burst split decision.
+ */
+#define UDMA_AXI_S2M_DESC_RD_CFG_3_MAX_AXI_BEATS_MASK 0x000000FF
+#define UDMA_AXI_S2M_DESC_RD_CFG_3_MAX_AXI_BEATS_SHIFT 0
+/*
+ * Enables breaking descriptor read request.
+ * Aligned to max_AXI_beats when the total read size is less than max_AXI_beats.
+ */
+#define UDMA_AXI_S2M_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY (1 << 16)
+
+/**** desc_wr_cfg_1 register ****/
+/*
+ * Defines the maximum number of AXI beats for a single AXI burst. This value is
+ * used for the burst split decision.
+ */
+#define UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK 0x000000FF
+#define UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_SHIFT 0
+/*
+ * Minimum burst for writing completion descriptors.
+ * (AXI beats).
+ * Value must be aligned to cache lines (64 bytes).
+ * Default value is 2 cache lines, 8 beats.
+ */
+#define UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK 0x00FF0000
+#define UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_SHIFT 16
+
+/**** ostand_cfg_rd register ****/
+/*
+ * Maximum number of outstanding descriptor reads to the AXI.
+ * (AXI transactions).
+ */
+#define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_MASK 0x0000003F
+#define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_SHIFT 0
+/* Maximum number of outstanding stream acknowledges. */
+#define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_MASK 0x001F0000
+#define UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_SHIFT 16
+
+/**** ostand_cfg_wr register ****/
+/*
+ * Maximum number of outstanding data writes to the AXI.
+ * (AXI transactions).
+ */
+#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_MASK 0x0000003F
+#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_SHIFT 0
+/*
+ * Maximum number of outstanding data beats for data write to AXI.
+ * (AXI beats).
+ */
+#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_MASK 0x0000FF00
+#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_SHIFT 8
+/*
+ * Maximum number of outstanding descriptor writes to the AXI.
+ * (AXI transactions).
+ */
+#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_MASK 0x003F0000
+#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_SHIFT 16
+/*
+ * Maximum number of outstanding data beats for descriptor write to AXI.
+ * (AXI beats).
+ */
+#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_MASK 0xFF000000
+#define UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_SHIFT 24
+
+/**** state register ****/
+
+#define UDMA_S2M_STATE_COMP_CTRL_MASK 0x00000003
+#define UDMA_S2M_STATE_COMP_CTRL_SHIFT 0
+
+#define UDMA_S2M_STATE_STREAM_IF_MASK 0x00000030
+#define UDMA_S2M_STATE_STREAM_IF_SHIFT 4
+
+#define UDMA_S2M_STATE_DATA_WR_CTRL_MASK 0x00000300
+#define UDMA_S2M_STATE_DATA_WR_CTRL_SHIFT 8
+
+#define UDMA_S2M_STATE_DESC_PREF_MASK 0x00003000
+#define UDMA_S2M_STATE_DESC_PREF_SHIFT 12
+
+#define UDMA_S2M_STATE_AXI_WR_DATA_MASK 0x00030000
+#define UDMA_S2M_STATE_AXI_WR_DATA_SHIFT 16
+
+/**** change_state register ****/
+/* Start normal operation */
+#define UDMA_S2M_CHANGE_STATE_NORMAL (1 << 0)
+/* Stop normal operation */
+#define UDMA_S2M_CHANGE_STATE_DIS    (1 << 1)
+/*
+ * Stop all machines.
+ * (Prefetch, scheduling, completion and stream interface)
+ */
+#define UDMA_S2M_CHANGE_STATE_ABORT  (1 << 2)
+
+/**** clear_err_log register ****/
+/* Clear error log */
+#define UDMA_S2M_CLEAR_ERR_LOG_CLEAR (1 << 0)
+
+/**** s_data_fifo_status register ****/
+/* FIFO used indication */
+#define UDMA_S2M_S_DATA_FIFO_STATUS_USED_MASK 0x0000FFFF
+#define UDMA_S2M_S_DATA_FIFO_STATUS_USED_SHIFT 0
+/* FIFO empty indication */
+#define UDMA_S2M_S_DATA_FIFO_STATUS_EMPTY (1 << 24)
+/* FIFO full indication */
+#define UDMA_S2M_S_DATA_FIFO_STATUS_FULL (1 << 28)
+
+/**** s_header_fifo_status register ****/
+/* FIFO used indication */
+#define UDMA_S2M_S_HEADER_FIFO_STATUS_USED_MASK 0x0000FFFF
+#define UDMA_S2M_S_HEADER_FIFO_STATUS_USED_SHIFT 0
+/* FIFO empty indication */
+#define UDMA_S2M_S_HEADER_FIFO_STATUS_EMPTY (1 << 24)
+/* FIFO full indication */
+#define UDMA_S2M_S_HEADER_FIFO_STATUS_FULL (1 << 28)
+
+/**** axi_data_fifo_status register ****/
+/* FIFO used indication */
+#define UDMA_S2M_AXI_DATA_FIFO_STATUS_USED_MASK 0x0000FFFF
+#define UDMA_S2M_AXI_DATA_FIFO_STATUS_USED_SHIFT 0
+/* FIFO empty indication */
+#define UDMA_S2M_AXI_DATA_FIFO_STATUS_EMPTY (1 << 24)
+/* FIFO full indication */
+#define UDMA_S2M_AXI_DATA_FIFO_STATUS_FULL (1 << 28)
+
+/**** unack_fifo_status register ****/
+/* FIFO used indication */
+#define UDMA_S2M_UNACK_FIFO_STATUS_USED_MASK 0x0000FFFF
+#define UDMA_S2M_UNACK_FIFO_STATUS_USED_SHIFT 0
+/* FIFO empty indication */
+#define UDMA_S2M_UNACK_FIFO_STATUS_EMPTY (1 << 24)
+/* FIFO full indication */
+#define UDMA_S2M_UNACK_FIFO_STATUS_FULL (1 << 28)
+
+/**** indirect_ctrl register ****/
+/* Selected queue for status read */
+#define UDMA_S2M_INDIRECT_CTRL_Q_NUM_MASK 0x00000FFF
+#define UDMA_S2M_INDIRECT_CTRL_Q_NUM_SHIFT 0
+
+/**** sel_pref_fifo_status register ****/
+/* FIFO used indication */
+#define UDMA_S2M_SEL_PREF_FIFO_STATUS_USED_MASK 0x0000FFFF
+#define UDMA_S2M_SEL_PREF_FIFO_STATUS_USED_SHIFT 0
+/* FIFO empty indication */
+#define UDMA_S2M_SEL_PREF_FIFO_STATUS_EMPTY (1 << 24)
+/* FIFO full indication */
+#define UDMA_S2M_SEL_PREF_FIFO_STATUS_FULL (1 << 28)
+
+/**** sel_comp_fifo_status register ****/
+/* FIFO used indication */
+#define UDMA_S2M_SEL_COMP_FIFO_STATUS_USED_MASK 0x0000FFFF
+#define UDMA_S2M_SEL_COMP_FIFO_STATUS_USED_SHIFT 0
+/* Coalescing ACTIVE FSM state indication. */
+#define UDMA_S2M_SEL_COMP_FIFO_STATUS_COAL_ACTIVE_STATE_MASK 0x00300000
+#define UDMA_S2M_SEL_COMP_FIFO_STATUS_COAL_ACTIVE_STATE_SHIFT 20
+/* FIFO empty indication */
+#define UDMA_S2M_SEL_COMP_FIFO_STATUS_EMPTY (1 << 24)
+/* FIFO full indication */
+#define UDMA_S2M_SEL_COMP_FIFO_STATUS_FULL (1 << 28)
+
+/**** stream_cfg register ****/
+/*
+ * Disables the stream interface operation.
+ * Changing to 1 stops at the end of packet reception.
+ */
+#define UDMA_S2M_STREAM_CFG_DISABLE  (1 << 0)
+/*
+ * Flush the stream interface operation.
+ * Changing to 1 stops at the end of packet reception and assert ready to the
+ * stream I/F.
+ */
+#define UDMA_S2M_STREAM_CFG_FLUSH    (1 << 4)
+/* Stop descriptor prefetch when the stream is disabled and the S2M is idle. */
+#define UDMA_S2M_STREAM_CFG_STOP_PREFETCH (1 << 8)
+
+/**** desc_pref_cfg_1 register ****/
+/*
+ * Size of the descriptor prefetch FIFO.
+ * (descriptors)
+ */
+#define UDMA_S2M_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK 0x000000FF
+#define UDMA_S2M_RD_DESC_PREF_CFG_1_FIFO_DEPTH_SHIFT 0
+
+/**** desc_pref_cfg_2 register ****/
+/* Enable promotion of the current queue in progress */
+#define UDMA_S2M_RD_DESC_PREF_CFG_2_Q_PROMOTION (1 << 0)
+/* Force promotion of the current queue in progress */
+#define UDMA_S2M_RD_DESC_PREF_CFG_2_FORCE_PROMOTION (1 << 1)
+/* Enable prefetch prediction of next packet in line. */
+#define UDMA_S2M_RD_DESC_PREF_CFG_2_EN_PREF_PREDICTION (1 << 2)
+/*
+ * Threshold for queue promotion.
+ * Queue is promoted for prefetch if there are less descriptors in the prefetch
+ * FIFO than the threshold
+ */
+#define UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_MASK 0x0000FF00
+#define UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_SHIFT 8
+/*
+ * Force RR arbitration in the prefetch arbiter.
+ * 0 - Standard arbitration based on queue QoS
+ * 1 - Force round robin arbitration
+ */
+#define UDMA_S2M_RD_DESC_PREF_CFG_2_PREF_FORCE_RR (1 << 16)
+
+/**** desc_pref_cfg_3 register ****/
+/*
+ * Minimum descriptor burst size when prefetch FIFO level is below the
+ * descriptor prefetch threshold
+ * (must be 1)
+ */
+#define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK 0x0000000F
+#define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_SHIFT 0
+/*
+ * Minimum descriptor burst size when prefetch FIFO level is above the
+ * descriptor prefetch threshold
+ */
+#define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK 0x000000F0
+#define UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_SHIFT 4
+/*
+ * Descriptor fetch threshold.
+ * Used as a threshold to determine the allowed minimum descriptor burst size.
+ * (Must be at least "max_desc_per_pkt")
+ */
+#define UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_MASK 0x0000FF00
+#define UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT 8
+
+/**** desc_pref_cfg_4 register ****/
+/*
+ * Used as a threshold for generating almost FULL indication to the application
+ */
+#define UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK 0x000000FF
+#define UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_SHIFT 0
+
+/**** data_cfg_1 register ****/
+/*
+ * Maximum number of data beats in the data write FIFO.
+ * Defined based on data FIFO size
+ * (default FIFO size 512B → 32 beats)
+ */
+#define UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_MASK 0x000003FF
+#define UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_SHIFT 0
+/*
+ * Maximum number of packets in the data write FIFO.
+ * Defined based on header FIFO size
+ */
+#define UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_MASK 0x00FF0000
+#define UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_SHIFT 16
+/*
+ * Internal use
+ * Data FIFO margin
+ */
+#define UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_MASK 0xFF000000
+#define UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_SHIFT 24
+
+/**** data_cfg_2 register ****/
+/*
+ * Drop timer.
+ * Waiting time for the host to write new descriptor to the queue
+ * (for the current packet in process)
+ */
+#define UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK 0x00FFFFFF
+#define UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_SHIFT 0
+/*
+ * Drop enable.
+ * Enable packet drop if there are no available descriptors in the system for
+ * this queue
+ */
+#define UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC (1 << 27)
+/*
+ * Lack of descriptors hint.
+ * Generate interrupt when a packet is waiting but there are no available
+ * descriptors in the queue
+ */
+#define UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC (1 << 28)
+/*
+ * Drop conditions
+ * Wait until a descriptor is available in the prefetch FIFO or the host before
+ * dropping packet.
+ * 1 - Drop if a descriptor is not available in the prefetch.
+ * 0 - Drop if a descriptor is not available in the system
+ */
+#define UDMA_S2M_WR_DATA_CFG_2_WAIT_FOR_PREF (1 << 29)
+/*
+ * DRAM write optimization
+ * 0 - Data write with byte enable
+ * 1 - Data write is always in Full AXI bus width (128 bit)
+ */
+#define UDMA_S2M_WR_DATA_CFG_2_FULL_LINE_MODE (1 << 30)
+/*
+ * Direct data write address
+ * 1 - Use buffer 1 instead of buffer 2 when direct data placement is used with
+ * header split.
+ * 0 - Use buffer 2 for the header.
+ */
+#define UDMA_S2M_WR_DATA_CFG_2_DIRECT_HDR_USE_BUF1 (1 << 31)
+
+/**** cfg_1c register ****/
+/*
+ * Completion descriptor size.
+ * (words)
+ */
+#define UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK 0x0000000F
+#define UDMA_S2M_COMP_CFG_1C_DESC_SIZE_SHIFT 0
+/*
+ * Completion queue counter configuration.
+ * Completion FIFO in use counter measured in words or descriptors
+ * 1 - Words
+ * 0 - Descriptors
+ */
+#define UDMA_S2M_COMP_CFG_1C_CNT_WORDS (1 << 8)
+/*
+ * Enable promotion of the current queue in progress in the completion write
+ * scheduler.
+ */
+#define UDMA_S2M_COMP_CFG_1C_Q_PROMOTION (1 << 12)
+/* Force RR arbitration in the completion arbiter */
+#define UDMA_S2M_COMP_CFG_1C_FORCE_RR (1 << 16)
+/* Minimum number of free completion entries to qualify for promotion */
+#define UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_MASK 0xF0000000
+#define UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_SHIFT 28
+
+/**** cfg_2c register ****/
+/*
+ * Completion FIFO size.
+ * (words per queue)
+ */
+#define UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_MASK 0x00000FFF
+#define UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_SHIFT 0
+/*
+ * Unacknowledged FIFO size.
+ * (descriptors)
+ */
+#define UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_MASK 0x0FFF0000
+#define UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_SHIFT 16
+
+/**** reg_1 register ****/
+/*
+ * Descriptor prefetch FIFO size
+ * (descriptors)
+ */
+#define UDMA_S2M_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_MASK 0x000000FF
+#define UDMA_S2M_FEATURE_REG_1_DESC_PREFERCH_FIFO_DEPTH_SHIFT 0
+
+/**** reg_3 register ****/
+/*
+ * Maximum number of data beats in the data write FIFO.
+ * Defined based on data FIFO size
+ * (default FIFO size 512B →32 beats)
+ */
+#define UDMA_S2M_FEATURE_REG_3_DATA_FIFO_DEPTH_MASK 0x000003FF
+#define UDMA_S2M_FEATURE_REG_3_DATA_FIFO_DEPTH_SHIFT 0
+/*
+ * Maximum number of packets in the data write FIFO.
+ * Defined based on header FIFO size
+ */
+#define UDMA_S2M_FEATURE_REG_3_DATA_WR_MAX_PKT_LIMIT_MASK 0x00FF0000
+#define UDMA_S2M_FEATURE_REG_3_DATA_WR_MAX_PKT_LIMIT_SHIFT 16
+
+/**** reg_4 register ****/
+/*
+ * Completion FIFO size.
+ * (words per queue)
+ */
+#define UDMA_S2M_FEATURE_REG_4_COMP_FIFO_DEPTH_MASK 0x00000FFF
+#define UDMA_S2M_FEATURE_REG_4_COMP_FIFO_DEPTH_SHIFT 0
+/*
+ * Unacknowledged FIFO size.
+ * (descriptors)
+ */
+#define UDMA_S2M_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_MASK 0x0FFF0000
+#define UDMA_S2M_FEATURE_REG_4_COMP_UNACK_FIFO_DEPTH_SHIFT 16
+
+/**** reg_5 register ****/
+/* Maximum number of outstanding data writes to the AXI */
+#define UDMA_S2M_FEATURE_REG_5_MAX_DATA_WR_OSTAND_MASK 0x0000003F
+#define UDMA_S2M_FEATURE_REG_5_MAX_DATA_WR_OSTAND_SHIFT 0
+/*
+ * Maximum number of outstanding data beats for data write to AXI.
+ * (AXI beats)
+ */
+#define UDMA_S2M_FEATURE_REG_5_MAX_DATA_BEATS_WR_OSTAND_MASK 0x0000FF00
+#define UDMA_S2M_FEATURE_REG_5_MAX_DATA_BEATS_WR_OSTAND_SHIFT 8
+/*
+ * Maximum number of outstanding descriptor reads to the AXI.
+ * (AXI transactions)
+ */
+#define UDMA_S2M_FEATURE_REG_5_MAX_COMP_REQ_MASK 0x003F0000
+#define UDMA_S2M_FEATURE_REG_5_MAX_COMP_REQ_SHIFT 16
+/*
+ * Maximum number of outstanding data beats for descriptor write to AXI.
+ * (AXI beats)
+ */
+#define UDMA_S2M_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_MASK 0xFF000000
+#define UDMA_S2M_FEATURE_REG_5_MAX_COMP_DATA_WR_OSTAND_SHIFT 24
+
+/**** reg_6 register ****/
+/* Maximum number of outstanding descriptor reads to the AXI */
+#define UDMA_S2M_FEATURE_REG_6_MAX_DESC_RD_OSTAND_MASK 0x0000003F
+#define UDMA_S2M_FEATURE_REG_6_MAX_DESC_RD_OSTAND_SHIFT 0
+/* Maximum number of outstanding stream acknowledges */
+#define UDMA_S2M_FEATURE_REG_6_MAX_STREAM_ACK_MASK 0x001F0000
+#define UDMA_S2M_FEATURE_REG_6_MAX_STREAM_ACK_SHIFT 16
+
+/**** cfg register ****/
+/*
+ * Configure the AXI AWCACHE
+ * for header write.
+ */
+#define UDMA_S2M_Q_CFG_AXI_AWCACHE_HDR_MASK 0x0000000F
+#define UDMA_S2M_Q_CFG_AXI_AWCACHE_HDR_SHIFT 0
+/*
+ * Configure the AXI AWCACHE
+ * for data write.
+ */
+#define UDMA_S2M_Q_CFG_AXI_AWCACHE_DATA_MASK 0x000000F0
+#define UDMA_S2M_Q_CFG_AXI_AWCACHE_DATA_SHIFT 4
+/*
+ * Enable operation of this queue.
+ * Start prefetch.
+ */
+#define UDMA_S2M_Q_CFG_EN_PREF       (1 << 16)
+/* Enables the reception of packets from the stream to this queue */
+#define UDMA_S2M_Q_CFG_EN_STREAM     (1 << 17)
+/* Allow prefetch of less than minimum prefetch burst size. */
+#define UDMA_S2M_Q_CFG_ALLOW_LT_MIN_PREF (1 << 20)
+/*
+ * Configure the AXI AWCACHE
+ * for completion descriptor write
+ */
+#define UDMA_S2M_Q_CFG_AXI_AWCACHE_COMP_MASK 0x0F000000
+#define UDMA_S2M_Q_CFG_AXI_AWCACHE_COMP_SHIFT 24
+/*
+ * AXI QoS
+ * This value is used in AXI transactions associated with this queue and the
+ * prefetch and completion arbiters.
+ */
+#define UDMA_S2M_Q_CFG_AXI_QOS_MASK  0x70000000
+#define UDMA_S2M_Q_CFG_AXI_QOS_SHIFT 28
+
+/**** status register ****/
+/* Indicates how many entries are used in the Queue */
+#define UDMA_S2M_Q_STATUS_Q_USED_MASK 0x01FFFFFF
+#define UDMA_S2M_Q_STATUS_Q_USED_SHIFT 0
+/*
+ * prefetch status
+ * 0 – prefetch operation is stopped
+ * 1 – prefetch is operational
+ */
+#define UDMA_S2M_Q_STATUS_PREFETCH   (1 << 28)
+/*
+ * Queue receive status
+ * 0 -queue RX operation is stopped
+ * 1 – RX queue is active and processing packets
+ */
+#define UDMA_S2M_Q_STATUS_RX         (1 << 29)
+/*
+ * Indicates if the queue is full.
+ * (Used by the host when head pointer equals tail pointer)
+ */
+#define UDMA_S2M_Q_STATUS_Q_FULL     (1 << 31)
+/*
+ * S2M Descriptor Ring Base address [31:4].
+ * Value of the base address of the S2M descriptor ring
+ * [3:0] - 0 - 16B alignment is enforced
+ * ([11:4] should be 0 for 4KB alignment)
+ */
+#define UDMA_S2M_Q_RDRBP_LOW_ADDR_MASK 0xFFFFFFF0
+#define UDMA_S2M_Q_RDRBP_LOW_ADDR_SHIFT 4
+
+/**** RDRL register ****/
+/*
+ * Length of the descriptor ring.
+ * (descriptors)
+ * Associated with the ring base address ends at maximum burst size alignment
+ */
+#define UDMA_S2M_Q_RDRL_OFFSET_MASK  0x00FFFFFF
+#define UDMA_S2M_Q_RDRL_OFFSET_SHIFT 0
+
+/**** RDRHP register ****/
+/*
+ * Relative offset of the next descriptor that needs to be read into the
+ * prefetch FIFO.
+ * Incremented when the DMA reads valid descriptors from the host memory to the
+ * prefetch FIFO.
+ * Note that this is the offset in # of descriptors and not in byte address.
+ */
+#define UDMA_S2M_Q_RDRHP_OFFSET_MASK 0x00FFFFFF
+#define UDMA_S2M_Q_RDRHP_OFFSET_SHIFT 0
+/* Ring ID */
+#define UDMA_S2M_Q_RDRHP_RING_ID_MASK 0xC0000000
+#define UDMA_S2M_Q_RDRHP_RING_ID_SHIFT 30
+
+/**** RDRTP_inc register ****/
+/*
+ * Increments the value in Q_RDRTP with the value written to this field in
+ * number of descriptors.
+ */
+#define UDMA_S2M_Q_RDRTP_INC_VAL_MASK 0x00FFFFFF
+#define UDMA_S2M_Q_RDRTP_INC_VAL_SHIFT 0
+
+/**** RDRTP register ****/
+/*
+ * Relative offset of the next free descriptor in the host memory.
+ * Note that this is the offset in # of descriptors and not in byte address.
+ */
+#define UDMA_S2M_Q_RDRTP_OFFSET_MASK 0x00FFFFFF
+#define UDMA_S2M_Q_RDRTP_OFFSET_SHIFT 0
+/* Ring ID */
+#define UDMA_S2M_Q_RDRTP_RING_ID_MASK 0xC0000000
+#define UDMA_S2M_Q_RDRTP_RING_ID_SHIFT 30
+
+/**** RDCP register ****/
+/* Relative offset of the first descriptor in the prefetch FIFO.  */
+#define UDMA_S2M_Q_RDCP_OFFSET_MASK  0x00FFFFFF
+#define UDMA_S2M_Q_RDCP_OFFSET_SHIFT 0
+/* Ring ID */
+#define UDMA_S2M_Q_RDCP_RING_ID_MASK 0xC0000000
+#define UDMA_S2M_Q_RDCP_RING_ID_SHIFT 30
+/*
+ * S2M Descriptor Ring Base address [31:4].
+ * Value of the base address of the S2M descriptor ring
+ * [3:0] - 0 - 16B alignment is enforced
+ * ([11:4] Must be 0 for 4KB alignment)
+ * NOTE:
+ * Length of the descriptor ring (in descriptors) associated with the ring base
+ * address ends at maximum burst size alignment
+ */
+#define UDMA_S2M_Q_RCRBP_LOW_ADDR_MASK 0xFFFFFFF0
+#define UDMA_S2M_Q_RCRBP_LOW_ADDR_SHIFT 4
+
+/**** RCRHP register ****/
+/*
+ * Relative offset of the next descriptor that needs to be updated by the
+ * completion controller.
+ * Note: This is in descriptors and not in byte address.
+ */
+#define UDMA_S2M_Q_RCRHP_OFFSET_MASK 0x00FFFFFF
+#define UDMA_S2M_Q_RCRHP_OFFSET_SHIFT 0
+/* Ring ID */
+#define UDMA_S2M_Q_RCRHP_RING_ID_MASK 0xC0000000
+#define UDMA_S2M_Q_RCRHP_RING_ID_SHIFT 30
+
+/**** RCRHP_internal register ****/
+/*
+ * Relative offset of the next descriptor that needs to be updated by the
+ * completion controller.
+ * Note: This is in descriptors and not in byte address.
+ */
+#define UDMA_S2M_Q_RCRHP_INTERNAL_OFFSET_MASK 0x00FFFFFF
+#define UDMA_S2M_Q_RCRHP_INTERNAL_OFFSET_SHIFT 0
+/* Ring ID */
+#define UDMA_S2M_Q_RCRHP_INTERNAL_RING_ID_MASK 0xC0000000
+#define UDMA_S2M_Q_RCRHP_INTERNAL_RING_ID_SHIFT 30
+
+/**** comp_cfg register ****/
+/* Enables writing to the completion ring. */
+#define UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE (1 << 0)
+/* Disables the completion coalescing function. */
+#define UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL (1 << 1)
+/* Reserved */
+#define UDMA_S2M_Q_COMP_CFG_FIRST_PKT_PROMOTION (1 << 2)
+/*
+ * Buffer 2 location.
+ * Determines the position of the buffer 2 length in the S2M completion
+ * descriptor.
+ * 0 - WORD 1 [31:16]
+ * 1 - WORD 2 [31:16]
+ */
+#define UDMA_S2M_Q_COMP_CFG_BUF2_LEN_LOCATION (1 << 3)
+
+/**** pkt_cfg register ****/
+/* Header size. (bytes) */
+#define UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK 0x0000FFFF
+#define UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_SHIFT 0
+/* Force header split */
+#define UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT (1 << 16)
+/* Enable header split. */
+#define UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT (1 << 17)
+
+/**** qos_cfg register ****/
+/* Queue QoS */
+#define UDMA_S2M_QOS_CFG_Q_QOS_MASK 0x000000FF
+#define UDMA_S2M_QOS_CFG_Q_QOS_SHIFT 0
+/* Reset the tail pointer hardware. */
+#define UDMA_S2M_Q_SW_CTRL_RST_TAIL_PTR (1 << 1)
+/* Reset the head pointer hardware. */
+#define UDMA_S2M_Q_SW_CTRL_RST_HEAD_PTR (1 << 2)
+/* Reset the current pointer hardware. */
+#define UDMA_S2M_Q_SW_CTRL_RST_CURRENT_PTR (1 << 3)
+/* Reset the prefetch FIFO */
+#define UDMA_S2M_Q_SW_CTRL_RST_PREFETCH (1 << 4)
+/* Reset the queue */
+#define UDMA_S2M_Q_SW_CTRL_RST_Q   (1 << 8)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_UDMA_S2M_REG_H */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_an_lt_wrapper_regs.h b/sys/contrib/alpine-hal/eth/al_hal_an_lt_wrapper_regs.h
new file mode 100644
index 000000000000..72b5cc66fb44
--- /dev/null
+++ b/sys/contrib/alpine-hal/eth/al_hal_an_lt_wrapper_regs.h
@@ -0,0 +1,264 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+	  this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+	  notice, this list of conditions and the following disclaimer in
+	  the documentation and/or other materials provided with the
+	  distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ *  @{
+ * @file   al_hal_an_lt_wrapper_regs.h
+ *
+ * @brief ... registers
+ *
+ */
+
+#ifndef __AL_HAL_AN_LT_wrapper_REGS_H__
+#define __AL_HAL_AN_LT_wrapper_REGS_H__
+
+#include "al_hal_plat_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+
+
+struct al_an_lt_wrapper_gen {
+	/* [0x0] AN LT wrapper Version */
+	uint32_t version;
+	/* [0x4] AN LT general configuration */
+	uint32_t cfg;
+	uint32_t rsrvd[14];
+};
+struct al_an_lt_wrapper_an_lt {
+	/* [0x0] AN LT register file address */
+	uint32_t addr;
+	/* [0x4] PCS register file data */
+	uint32_t data;
+	/* [0x8] AN LT control signals */
+	uint32_t ctrl;
+	/* [0xc] AN LT status signals */
+	uint32_t status;
+	uint32_t rsrvd[4];
+};
+
+enum al_eth_an_lt_unit {
+	AL_ETH_AN_LT_UNIT_32_BIT	= 0,
+	AL_ETH_AN_LT_UNIT_20_BIT	= 1,
+	AL_ETH_AN_LT_UNIT_16_BIT	= 2,
+};
+
+struct al_an_lt_wrapper_regs {
+	uint32_t rsrvd_0[64];
+	struct al_an_lt_wrapper_gen gen;                        /* [0x100] */
+	struct al_an_lt_wrapper_an_lt an_lt[3];                 /* [0x140] */
+};
+
+
+/*
+* Registers Fields
+*/
+
+
+/**** version register ****/
+/*  Revision number (Minor) */
+#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
+#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
+/*  Revision number (Major) */
+#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
+#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
+/*  Date of release */
+#define AN_LT_WRAPPER_GEN_VERSION_DATE_DAY_MASK 0x001F0000
+#define AN_LT_WRAPPER_GEN_VERSION_DATE_DAY_SHIFT 16
+/*  Month of release */
+#define AN_LT_WRAPPER_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
+#define AN_LT_WRAPPER_GEN_VERSION_DATA_MONTH_SHIFT 21
+/*  Year of release (starting from 2000) */
+#define AN_LT_WRAPPER_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
+#define AN_LT_WRAPPER_GEN_VERSION_DATE_YEAR_SHIFT 25
+/*  Reserved */
+#define AN_LT_WRAPPER_GEN_VERSION_RESERVED_MASK 0xC0000000
+#define AN_LT_WRAPPER_GEN_VERSION_RESERVED_SHIFT 30
+
+/**** cfg register ****/
+/*
+ * selection between different bus widths:
+ * 0 – 16
+ * 1 – 20
+ * 2 – 32
+ * 3 – N/A
+ */
+#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK 0x00000003
+#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT 0
+/*
+ * selection between different bus widths:
+ * 0 – 16
+ * 1 – 20
+ * 2 – 32
+ * 3 – N/A
+ */
+#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK 0x0000000C
+#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT 2
+/* bypass the AN/LT block */
+#define AN_LT_WRAPPER_GEN_CFG_BYPASS_RX  (1 << 4)
+/* bypass the AN/LT block */
+#define AN_LT_WRAPPER_GEN_CFG_BYPASS_TX  (1 << 5)
+
+/**** addr register ****/
+/* Address value */
+#define AN_LT_WRAPPER_AN_LT_ADDR_VAL_MASK 0x000007FF
+#define AN_LT_WRAPPER_AN_LT_ADDR_VAL_SHIFT 0
+
+/**** data register ****/
+/* Data value */
+#define AN_LT_WRAPPER_AN_LT_DATA_VAL_MASK 0x0000FFFF
+#define AN_LT_WRAPPER_AN_LT_DATA_VAL_SHIFT 0
+
+/**** ctrl register ****/
+/*
+ * Default Auto-Negotiation Enable. If ‘1’, the auto-negotiation process will
+ * start after reset de-assertion. The application can also start the
+ * auto-negotiation process by writing the KXAN_CONTROL.an_enable bit with ‘1’.
+ * Important: This signal is OR'ed with the KXAN_CONTROL.an_enable bit. Hence,
+ * when asserted (1) the application is unable to disable autonegotiation and
+ * writing the an_enable bit has no effect.
+ * Note: Even if enabled by this pin, the application must write the correct
+ * abilities in the KXAN_ABILITY_1/2/3 registers within 60ms from reset
+ * deassertion (break_link_timer).
+ */
+#define AN_LT_WRAPPER_AN_LT_CTRL_AN_ENA  (1 << 0)
+/*
+ * If set to 1, the Arbitration State Machine reached the TRANSMIT_DISABLE
+ * state.
+ */
+#define AN_LT_WRAPPER_AN_LT_CTRL_AN_DIS_TIMER (1 << 1)
+
+#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS_KX (1 << 4)
+
+#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS_KX4 (1 << 5)
+
+#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS (1 << 6)
+/*
+ * PHY LOS indication selection
+ * 0 - Select input from the SerDes
+ * 1 - Select register value from phy_los_in_def
+ */
+#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_SEL (1 << 8)
+/* PHY LOS default value */
+#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_DEF (1 << 9)
+/* PHY LOS polarity */
+#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_POL (1 << 10)
+/*
+ * PHY LOS indication selection
+ * 0 – select AN output
+ * 1 - Select register value from phy_los_out_def
+ * 2 - Select input from the SerDes
+ * 3 – 0
+ */
+#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_SEL_MASK 0x00003000
+#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_SEL_SHIFT 12
+/* PHY LOS default value */
+#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_DEF (1 << 14)
+/* PHY LOS polarity */
+#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_POL (1 << 15)
+
+/**** status register ****/
+/* Auto-Negotiation Done. If ‘1’, the auto-negotiation process has completed. */
+#define AN_LT_WRAPPER_AN_LT_STATUS_AN_DONE (1 << 0)
+/*
+ * If set to 1, auto-negotiation is enabled on the link. It represents the
+ * enable control bit KXAN_CONTROL.an_enable. When set to 1, the signals
+ * an_status/an_select are valid.
+ */
+#define AN_LT_WRAPPER_AN_LT_STATUS_AN_VAL (1 << 1)
+/*
+ * If set to 0, auto-negotiation is in progress, if set to 1, the Arbitration
+ * State Machine reached the AN_GOOD_CHECK state (i.e. before autonegotiation is
+ * done, but the link no longer is used to transfer DME pages). Stays asserted
+ * also during AN_GOOD (autoneg done).
+ */
+#define AN_LT_WRAPPER_AN_LT_STATUS_AN_STATUS (1 << 2)
+/*
+ * Selected Technology. Becomes valid when an_status is 1.
+ * The selection mode number (from 0 to 24) corresponds to the Technology
+ * Ability (A0-A24) from the ability pages (see 4.3.2.3 page 13). The mode
+ * selection is based on the matching technology abilities and priority.
+ * A value of 31 is an invalid setting that indicates that no common technology
+ * could be resolved. The application should then inspect the base page results
+ * to determine if the link is operable or not.
+ */
+#define AN_LT_WRAPPER_AN_LT_STATUS_AN_SELECT_MASK 0x000001F0
+#define AN_LT_WRAPPER_AN_LT_STATUS_AN_SELECT_SHIFT 4
+/*
+ * If set to 1, the Arbitration State Machine reached the TRANSMIT_DISABLE state
+ */
+#define AN_LT_WRAPPER_AN_LT_STATUS_AN_TR_DIS_STATUS (1 << 16)
+/*
+ * FEC Enable. Asserts when autonegotiation base page exchange identified both
+ * link partners advertising FEC capability and at least one is requesting FEC.
+ * The signal stays constant following base page exchange until autonegotiation
+ * is disabled or restarted.
+ * Note: the information can also be extracted from the base page exchange or
+ * the BP_ETH_STATUS register.
+ */
+#define AN_LT_WRAPPER_AN_LT_STATUS_FEC_ENA (1 << 17)
+/*
+ * Link Training Frame Lock. If set to 1 the training frame delineation has been
+ * acquired.
+ */
+#define AN_LT_WRAPPER_AN_LT_STATUS_LT_LOCK (1 << 20)
+/*
+ * If set to 0, link-training is in progress, if set to 1, the training is
+ * completed and the PCS datapath has been enabled (phy_los_out no longer
+ * gated).
+ */
+#define AN_LT_WRAPPER_AN_LT_STATUS_LT_STATUS (1 << 21)
+/*
+ * If set to 1, link-training is enabled on the link. It represents the enable
+ * control bit PMD Control.taining enable. When set to 1, the signal lt_status
+ * is valid
+ */
+#define AN_LT_WRAPPER_AN_LT_STATUS_LT_VAL (1 << 22)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_AN_LT_wrapper_REGS_H__ */
+
+/** @} end of ... group */
+
+
diff --git a/sys/contrib/alpine-hal/eth/al_hal_eth.h b/sys/contrib/alpine-hal/eth/al_hal_eth.h
new file mode 100644
index 000000000000..86108b0df4c1
--- /dev/null
+++ b/sys/contrib/alpine-hal/eth/al_hal_eth.h
@@ -0,0 +1,2381 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_eth_api API
+ * Ethernet Controller HAL driver API
+ * @ingroup group_eth
+ * @{
+ * @file   al_hal_eth.h
+ *
+ * @brief Header file for Unified GbE and 10GbE Ethernet Controllers This is a
+ * common header file that covers both Standard and Advanced Controller
+ *
+ *
+ */
+
+#ifndef __AL_HAL_ETH_H__
+#define __AL_HAL_ETH_H__
+
+#include "al_hal_common.h"
+#include "al_hal_udma.h"
+#include "al_hal_eth_alu.h"
+#ifdef AL_ETH_EX
+#include "al_hal_eth_ex.h"
+#include "al_hal_eth_ex_internal.h"
+#endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#ifndef AL_ETH_PKT_MAX_BUFS
+#ifndef AL_ETH_EX
+#define AL_ETH_PKT_MAX_BUFS 19
+#else
+#define AL_ETH_PKT_MAX_BUFS 29
+#endif
+#endif
+
+#define AL_ETH_UDMA_TX_QUEUES		4
+#define AL_ETH_UDMA_RX_QUEUES		4
+
+/* PCI Adapter Device/Revision ID */
+#define AL_ETH_DEV_ID_STANDARD		0x0001
+#define AL_ETH_DEV_ID_ADVANCED		0x0002
+#define AL_ETH_REV_ID_0			0 /* Alpine V1 Rev 0 */
+#define AL_ETH_REV_ID_1			1 /* Alpine V1 Rev 1 */
+#define AL_ETH_REV_ID_2			2 /* Alpine V2 basic */
+#define AL_ETH_REV_ID_3			3 /* Alpine V2 advanced */
+
+/* PCI BARs */
+#define AL_ETH_UDMA_BAR			0
+#define AL_ETH_EC_BAR			4
+#define AL_ETH_MAC_BAR			2
+
+#define AL_ETH_MAX_FRAME_LEN		10000
+#define AL_ETH_MIN_FRAME_LEN		60
+
+#define AL_ETH_TSO_MSS_MAX_IDX		8
+#define AL_ETH_TSO_MSS_MIN_VAL		1
+/*TODO: update with correct value*/
+#define AL_ETH_TSO_MSS_MAX_VAL		(AL_ETH_MAX_FRAME_LEN - 200)
+
+enum AL_ETH_PROTO_ID {
+	AL_ETH_PROTO_ID_UNKNOWN = 0,
+	AL_ETH_PROTO_ID_IPv4	= 8,
+	AL_ETH_PROTO_ID_IPv6	= 11,
+	AL_ETH_PROTO_ID_TCP	= 12,
+	AL_ETH_PROTO_ID_UDP	= 13,
+	AL_ETH_PROTO_ID_FCOE    = 21,
+	AL_ETH_PROTO_ID_GRH     = 22, /** RoCE l3 header */
+	AL_ETH_PROTO_ID_BTH     = 23, /** RoCE l4 header */
+	AL_ETH_PROTO_ID_ANY	= 32, /**< for sw usage only */
+};
+#define AL_ETH_PROTOCOLS_NUM		(AL_ETH_PROTO_ID_ANY)
+
+enum AL_ETH_TX_TUNNEL_MODE {
+	AL_ETH_NO_TUNNELING	= 0,
+	AL_ETH_TUNNEL_NO_UDP	= 1, /* NVGRE / IP over IP */
+	AL_ETH_TUNNEL_WITH_UDP	= 3,	/* VXLAN */
+};
+
+#define AL_ETH_RX_THASH_TABLE_SIZE	(1 << 8)
+#define AL_ETH_RX_FSM_TABLE_SIZE	(1 << 7)
+#define AL_ETH_RX_CTRL_TABLE_SIZE	(1 << 11)
+#define AL_ETH_RX_HASH_KEY_NUM		10
+#define AL_ETH_FWD_MAC_NUM			32
+#define AL_ETH_FWD_MAC_HASH_NUM			256
+#define AL_ETH_FWD_PBITS_TABLE_NUM	(1 << 3)
+#define AL_ETH_FWD_PRIO_TABLE_NUM	(1 << 3)
+#define AL_ETH_FWD_VID_TABLE_NUM	(1 << 12)
+#define AL_ETH_FWD_DSCP_TABLE_NUM	(1 << 8)
+#define AL_ETH_FWD_TC_TABLE_NUM	(1 << 8)
+
+/** MAC media mode */
+enum al_eth_mac_mode {
+	AL_ETH_MAC_MODE_RGMII,
+	AL_ETH_MAC_MODE_SGMII,
+	AL_ETH_MAC_MODE_SGMII_2_5G,
+	AL_ETH_MAC_MODE_10GbE_Serial,	/**< Applies to XFI and KR modes */
+	AL_ETH_MAC_MODE_10G_SGMII,	/**< SGMII using the 10G MAC, don't use*/
+	AL_ETH_MAC_MODE_XLG_LL_40G,	/**< applies to 40G mode using the 40G low latency (LL) MAC */
+	AL_ETH_MAC_MODE_KR_LL_25G,	/**< applies to 25G mode using the 10/25G low latency (LL) MAC */
+	AL_ETH_MAC_MODE_XLG_LL_50G	/**< applies to 50G mode using the 40/50G low latency (LL) MAC */
+};
+
+struct al_eth_capabilities {
+	al_bool	speed_10_HD;
+	al_bool	speed_10_FD;
+	al_bool speed_100_HD;
+	al_bool speed_100_FD;
+	al_bool speed_1000_HD;
+	al_bool speed_1000_FD;
+	al_bool speed_10000_HD;
+	al_bool speed_10000_FD;
+	al_bool pfc; /**< priority flow control */
+	al_bool eee; /**< Energy Efficient Ethernet */
+};
+
+/** interface type used for MDIO */
+enum al_eth_mdio_if {
+	AL_ETH_MDIO_IF_1G_MAC = 0,
+	AL_ETH_MDIO_IF_10G_MAC = 1
+};
+
+/** MDIO protocol type */
+enum al_eth_mdio_type {
+	AL_ETH_MDIO_TYPE_CLAUSE_22 = 0,
+	AL_ETH_MDIO_TYPE_CLAUSE_45 = 1
+};
+
+/** flow control mode */
+enum al_eth_flow_control_type {
+	AL_ETH_FLOW_CONTROL_TYPE_LINK_PAUSE,
+	AL_ETH_FLOW_CONTROL_TYPE_PFC
+};
+
+/** Tx to Rx switching decision type */
+enum al_eth_tx_switch_dec_type {
+	AL_ETH_TX_SWITCH_TYPE_MAC = 0,
+	AL_ETH_TX_SWITCH_TYPE_VLAN_TABLE = 1,
+	AL_ETH_TX_SWITCH_TYPE_VLAN_TABLE_AND_MAC = 2,
+	AL_ETH_TX_SWITCH_TYPE_BITMAP = 3
+};
+
+/** Tx to Rx VLAN ID selection type */
+enum al_eth_tx_switch_vid_sel_type {
+	AL_ETH_TX_SWITCH_VID_SEL_TYPE_VLAN1 = 0,
+	AL_ETH_TX_SWITCH_VID_SEL_TYPE_VLAN2 = 1,
+	AL_ETH_TX_SWITCH_VID_SEL_TYPE_NEW_VLAN1 = 2,
+	AL_ETH_TX_SWITCH_VID_SEL_TYPE_NEW_VLAN2 = 3,
+	AL_ETH_TX_SWITCH_VID_SEL_TYPE_DEFAULT_VLAN1 = 4,
+	AL_ETH_TX_SWITCH_VID_SEL_TYPE_FINAL_VLAN1 = 5
+};
+
+/** Rx descriptor configurations */
+/* Note: when selecting rx descriptor field to inner packet, then that field
+* will be set according to inner packet when packet is tunneled, for non-tunneled
+* packets, the field will be set according to the packets header */
+
+/** selection of the LRO_context_value result in the Metadata */
+enum al_eth_rx_desc_lro_context_val_res {
+	AL_ETH_LRO_CONTEXT_VALUE = 0, /**< LRO_context_value */
+	AL_ETH_L4_OFFSET = 1, /**< L4_offset */
+};
+
+/** selection of the L4 offset in the Metadata */
+enum al_eth_rx_desc_l4_offset_sel {
+	AL_ETH_L4_OFFSET_OUTER = 0, /**< set L4 offset of the outer packet */
+	AL_ETH_L4_OFFSET_INNER = 1, /**< set L4 offset of the inner packet */
+};
+
+/** selection of the L4 checksum result in the Metadata */
+enum al_eth_rx_desc_l4_chk_res_sel {
+	AL_ETH_L4_INNER_CHK = 0, /**< L4 checksum */
+	AL_ETH_L4_INNER_OUTER_CHK = 1, /**< Logic AND between outer and inner
+					    L4 checksum result */
+};
+
+/** selection of the L3 checksum result in the Metadata */
+enum al_eth_rx_desc_l3_chk_res_sel {
+	AL_ETH_L3_CHK_TYPE_0 = 0, /**< L3 checksum */
+	AL_ETH_L3_CHK_TYPE_1 = 1, /**< L3 checksum or RoCE/FCoE CRC,
+				       based on outer header */
+	AL_ETH_L3_CHK_TYPE_2 = 2, /**< If tunnel exist = 0,
+					  L3 checksum or RoCE/FCoE CRC,
+					  based on outer header.
+				       Else,
+					  logic AND between outer L3 checksum
+					  (Ipv4) and inner CRC (RoCE or FcoE) */
+	AL_ETH_L3_CHK_TYPE_3 = 3, /**< combination of the L3 checksum result and
+				       CRC result,based on the checksum and
+				       RoCE/FCoE CRC input selections. */
+};
+
+/** selection of the L3 protocol index in the Metadata */
+enum al_eth_rx_desc_l3_proto_idx_sel {
+	AL_ETH_L3_PROTO_IDX_OUTER = 0, /**< set L3 proto index of the outer packet */
+	AL_ETH_L3_PROTO_IDX_INNER = 1, /**< set L3 proto index of the inner packet */
+};
+
+/** selection of the L3 offset in the Metadata */
+enum al_eth_rx_desc_l3_offset_sel {
+	AL_ETH_L3_OFFSET_OUTER = 0, /**< set L3 offset of the outer packet */
+	AL_ETH_L3_OFFSET_INNER = 1, /**< set L3 offset of the inner packet */
+};
+
+
+/** selection of the L4 protocol index in the Metadata */
+enum al_eth_rx_desc_l4_proto_idx_sel {
+	AL_ETH_L4_PROTO_IDX_OUTER = 0, /**< set L4 proto index of the outer packet */
+	AL_ETH_L4_PROTO_IDX_INNER = 1, /**< set L4 proto index of the inner packet */
+};
+
+/** selection of the frag indication in the Metadata */
+enum al_eth_rx_desc_frag_sel {
+	AL_ETH_FRAG_OUTER = 0, /**< set frag of the outer packet */
+	AL_ETH_FRAG_INNER = 1, /**< set frag of the inner packet */
+};
+
+/** Ethernet Rx completion descriptor */
+typedef struct {
+	uint32_t ctrl_meta;
+	uint32_t len;
+	uint32_t word2;
+	uint32_t word3;
+} al_eth_rx_cdesc;
+
+/** Flow Contol parameters */
+struct al_eth_flow_control_params{
+	enum al_eth_flow_control_type type; /**< flow control type */
+	al_bool		obay_enable; /**< stop tx when pause received */
+	al_bool		gen_enable; /**< generate pause frames */
+	uint16_t	rx_fifo_th_high;
+	uint16_t	rx_fifo_th_low;
+	uint16_t	quanta;
+	uint16_t	quanta_th;
+	uint8_t		prio_q_map[4][8]; /**< for each UDMA, defines the mapping between
+					   * PFC priority and queues(in bit mask).
+					   * same mapping used for obay and generation.
+					   * for example:
+					   * if prio_q_map[1][7] = 0xC, then TX queues 2
+					   * and 3 of UDMA 1 will be stopped when pause
+					   * received with priority 7, also, when RX queues
+					   * 2 and 3 of UDMA 1 become almost full, then
+					   * pause frame with priority 7 will be sent.
+					   *
+					   *note:
+					   * 1) if specific a queue is not used, the caller must
+					   * make set the prio_q_map to 0 otherwise that queue
+					   * will make the controller keep sending PAUSE packets.
+					   * 2) queues of unused UDMA must be treated as above.
+					   * 3) when working in LINK PAUSE mode, only entries at
+					   * priority 0 will be considered.
+					   */
+};
+
+/* Packet Tx flags */
+#define AL_ETH_TX_FLAGS_TSO		AL_BIT(7)  /**< Enable TCP/UDP segmentation offloading */
+#define AL_ETH_TX_FLAGS_IPV4_L3_CSUM	AL_BIT(13) /**< Enable IPv4 header checksum calculation */
+#define AL_ETH_TX_FLAGS_L4_CSUM		AL_BIT(14) /**< Enable TCP/UDP checksum calculation */
+#define AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM	AL_BIT(17) /**< L4 partial checksum calculation */
+#define AL_ETH_TX_FLAGS_L2_MACSEC_PKT	AL_BIT(16) /**< L2 Packet type 802_3 or 802_3_MACSEC, V2 */
+#define AL_ETH_TX_FLAGS_ENCRYPT		AL_BIT(16) /**< Enable TX packet encryption, V3 */
+#define AL_ETH_TX_FLAGS_L2_DIS_FCS	AL_BIT(15) /**< Disable CRC calculation*/
+#define AL_ETH_TX_FLAGS_TS		AL_BIT(21) /**< Timestamp the packet */
+
+#define AL_ETH_TX_FLAGS_INT		AL_M2S_DESC_INT_EN
+#define AL_ETH_TX_FLAGS_NO_SNOOP	AL_M2S_DESC_NO_SNOOP_H
+
+/** this structure used for tx packet meta data */
+struct al_eth_meta_data{
+	uint8_t store :1; /**< store the meta into the queues cache */
+	uint8_t words_valid :4; /**< valid bit per word */
+
+	uint8_t vlan1_cfi_sel:2;
+	uint8_t vlan2_vid_sel:2;
+	uint8_t vlan2_cfi_sel:2;
+	uint8_t vlan2_pbits_sel:2;
+	uint8_t vlan2_ether_sel:2;
+
+	uint16_t vlan1_new_vid:12;
+	uint8_t vlan1_new_cfi :1;
+	uint8_t vlan1_new_pbits :3;
+	uint16_t vlan2_new_vid:12;
+	uint8_t vlan2_new_cfi :1;
+	uint8_t vlan2_new_pbits :3;
+
+	uint8_t l3_header_len; /**< in bytes */
+	uint8_t l3_header_offset;
+	uint8_t l4_header_len; /**< in words(32-bits) */
+
+	/* rev 0 specific */
+	uint8_t mss_idx_sel:3; /**< for TSO, select the register that holds the MSS */
+
+	/* rev 1 specific */
+	uint8_t	ts_index:4; /**< index of regiser where to store the tx timestamp */
+	uint16_t mss_val :14; /**< for TSO, set the mss value */
+	uint8_t outer_l3_offset; /**< for tunneling mode. up to 64 bytes */
+	uint8_t outer_l3_len; /**< for tunneling mode. up to 128 bytes */
+};
+
+/* Packet Rx flags when adding buffer to receive queue */
+
+/**<
+ * VMID to be assigned to the packet descriptors
+ * Requires VMID in descriptor to be enabled for the specific UDMA
+ * queue.
+ */
+#define AL_ETH_RX_FLAGS_VMID_MASK	AL_FIELD_MASK(15, 0)
+#define AL_ETH_RX_FLAGS_NO_SNOOP	AL_M2S_DESC_NO_SNOOP_H
+#define AL_ETH_RX_FLAGS_INT		AL_M2S_DESC_INT_EN
+#define AL_ETH_RX_FLAGS_DUAL_BUF	AL_BIT(31)
+
+/* Packet Rx flags set by HW when receiving packet */
+#define AL_ETH_RX_ERROR			AL_BIT(16) /**< layer 2 errors (FCS, bad len, etc) */
+#define AL_ETH_RX_FLAGS_L4_CSUM_ERR	AL_BIT(14)
+#define AL_ETH_RX_FLAGS_L3_CSUM_ERR	AL_BIT(13)
+
+/* Packet Rx flags - word 3 in Rx completion descriptor */
+#define AL_ETH_RX_FLAGS_CRC						AL_BIT(31)
+#define AL_ETH_RX_FLAGS_L3_CSUM_2				AL_BIT(30)
+#define AL_ETH_RX_FLAGS_L4_CSUM_2				AL_BIT(29)
+#define AL_ETH_RX_FLAGS_SW_SRC_PORT_SHIFT		13
+#define AL_ETH_RX_FLAGS_SW_SRC_PORT_MASK		AL_FIELD_MASK(15, 13)
+#define AL_ETH_RX_FLAGS_LRO_CONTEXT_VAL_SHIFT	3
+#define AL_ETH_RX_FLAGS_LRO_CONTEXT_VAL_MASK	AL_FIELD_MASK(10, 3)
+#define AL_ETH_RX_FLAGS_L4_OFFSET_SHIFT			3
+#define AL_ETH_RX_FLAGS_L4_OFFSET_MASK			AL_FIELD_MASK(10, 3)
+#define AL_ETH_RX_FLAGS_PRIORITY_SHIFT			0
+#define AL_ETH_RX_FLAGS_PRIORITY_MASK			AL_FIELD_MASK(2, 0)
+
+/** packet structure. used for packet transmission and reception */
+struct al_eth_pkt{
+	uint32_t flags; /**< see flags above, depends on context(tx or rx) */
+	enum AL_ETH_PROTO_ID l3_proto_idx;
+	enum AL_ETH_PROTO_ID l4_proto_idx;
+	uint8_t source_vlan_count:2;
+	uint8_t vlan_mod_add_count:2;
+	uint8_t vlan_mod_del_count:2;
+	uint8_t vlan_mod_v1_ether_sel:2;
+	uint8_t vlan_mod_v1_vid_sel:2;
+	uint8_t vlan_mod_v1_pbits_sel:2;
+
+	/* rev 1 specific */
+	enum AL_ETH_TX_TUNNEL_MODE tunnel_mode;
+	enum AL_ETH_PROTO_ID outer_l3_proto_idx; /**< for tunneling mode */
+
+	/**<
+	 * VMID to be assigned to the packet descriptors
+	 * Requires VMID in descriptor to be enabled for the specific UDMA
+	 * queue.
+	 */
+	uint16_t vmid;
+
+	uint32_t rx_header_len; /**< header buffer length of rx packet, not used */
+	struct al_eth_meta_data *meta; /**< if null, then no meta added */
+#ifdef AL_ETH_RX_DESC_RAW_GET
+	uint32_t rx_desc_raw[4];
+#endif
+	uint16_t rxhash;
+	uint16_t l3_offset;
+
+#ifdef AL_ETH_EX
+	struct al_eth_ext_metadata *ext_meta_data;
+#endif
+
+	uint8_t num_of_bufs;
+	struct al_buf	bufs[AL_ETH_PKT_MAX_BUFS];
+};
+
+struct al_ec_regs;
+
+
+/** Ethernet Adapter private data structure used by this driver */
+struct al_hal_eth_adapter{
+	uint8_t rev_id; /**<PCI adapter revision ID */
+	uint8_t udma_id; /**< the id of the UDMA used by this adapter */
+	struct unit_regs __iomem * unit_regs;
+	void __iomem *udma_regs_base;
+	struct al_ec_regs __iomem *ec_regs_base;
+	void __iomem *ec_ints_base;
+	struct al_eth_mac_regs __iomem *mac_regs_base;
+	struct interrupt_controller_ctrl __iomem *mac_ints_base;
+
+	char *name; /**< the upper layer must keep the string area */
+
+	struct al_udma tx_udma;
+	/*	uint8_t tx_queues;*//* number of tx queues */
+	struct al_udma rx_udma;
+	/*	uint8_t rx_queues;*//* number of tx queues */
+
+	uint8_t		enable_rx_parser; /**< config and enable rx parsing */
+
+	enum al_eth_flow_control_type fc_type; /**< flow control*/
+
+	enum al_eth_mac_mode mac_mode;
+	enum al_eth_mdio_if	mdio_if; /**< which mac mdio interface to use */
+	enum al_eth_mdio_type mdio_type; /**< mdio protocol type */
+	al_bool	shared_mdio_if; /**< when AL_TRUE, the mdio interface is shared with other controllers.*/
+	uint8_t curr_lt_unit;
+#ifdef AL_ETH_EX
+	struct al_eth_ex_state ex_state;
+#endif
+};
+
+/** parameters from upper layer */
+struct al_eth_adapter_params{
+	uint8_t rev_id; /**<PCI adapter revision ID */
+	uint8_t udma_id; /**< the id of the UDMA used by this adapter */
+	uint8_t	enable_rx_parser; /**< when true, the rx epe parser will be enabled */
+	void __iomem *udma_regs_base; /**< UDMA register base address */
+	void __iomem *ec_regs_base; /**< Ethernet controller registers base address
+				     * can be null if the function is virtual
+				     */
+	void __iomem *mac_regs_base; /**< Ethernet MAC registers base address
+				      * can be null if the function is virtual
+				      */
+	char *name; /**< the upper layer must keep the string area */
+};
+
+/* adapter management */
+/**
+ * initialize the ethernet adapter's DMA
+ * - initialize the adapter data structure
+ * - initialize the Tx and Rx UDMA
+ * - enable the Tx and Rx UDMA, the rings will be still disabled at this point.
+ *
+ * @param adapter pointer to the private structure
+ * @param params the parameters passed from upper layer
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_adapter_init(struct al_hal_eth_adapter *adapter, struct al_eth_adapter_params *params);
+
+/**
+ * stop the DMA of the ethernet adapter
+ *
+ * @param adapter pointer to the private structure
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_adapter_stop(struct al_hal_eth_adapter *adapter);
+
+int al_eth_adapter_reset(struct al_hal_eth_adapter *adapter);
+
+/**
+ * enable the ec and mac interrupts
+ *
+ * @param adapter pointer to the private structure
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_ec_mac_ints_config(struct al_hal_eth_adapter *adapter);
+
+/**
+ * ec and mac interrupt service routine
+ * read and print asserted interrupts
+ *
+ * @param adapter pointer to the private structure
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_ec_mac_isr(struct al_hal_eth_adapter *adapter);
+
+/* Q management */
+/**
+ * Configure and enable a queue ring
+ *
+ * @param adapter pointer to the private structure
+ * @param type tx or rx
+ * @param qid queue index
+ * @param q_params queue parameters
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_queue_config(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid,
+			struct al_udma_q_params *q_params);
+
+
+/**
+ * enable a queue if it was previously disabled
+ *
+ * @param adapter pointer to the private structure
+ * @param type tx or rx
+ * @param qid queue index
+ *
+ * @return -EPERM (not implemented yet).
+ */
+int al_eth_queue_enable(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid);
+
+/**
+ * disable a queue
+ * @param adapter pointer to the private structure
+ * @param type tx or rx
+ * @param qid queue index
+ *
+ * @return -EPERM (not implemented yet).
+ */
+int al_eth_queue_disable(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid);
+
+/* MAC layer */
+
+/**
+ * configure the mac media type.
+ * this function only sets the mode, but not the speed as certain mac modes
+ * support multiple speeds as will be negotiated by the link layer.
+ * @param adapter pointer to the private structure.
+ * @param mode media mode
+ *
+ * @return 0 on success. negative errno on failure.
+ */
+int al_eth_mac_config(struct al_hal_eth_adapter *adapter, enum al_eth_mac_mode mode);
+
+/**
+ * stop the mac tx and rx paths.
+ * @param adapter pointer to the private structure.
+ *
+ * @return 0 on success. negative error on failure.
+ */
+int al_eth_mac_stop(struct al_hal_eth_adapter *adapter);
+
+/**
+ * start the mac tx and rx paths.
+ * @param adapter pointer to the private structure.
+ *
+ * @return 0 on success. negative error on failure.
+ */
+int al_eth_mac_start(struct al_hal_eth_adapter *adapter);
+
+
+/**
+ * get the adapter capabilities (speed, duplex,..)
+ * this function must not be called before configuring the mac mode using al_eth_mac_config()
+ * @param adapter pointer to the private structure.
+ * @param caps pointer to structure that will be updated by this function
+ *
+ * @return 0 on success. negative errno on failure.
+ */
+int al_eth_capabilities_get(struct al_hal_eth_adapter *adapter, struct al_eth_capabilities *caps);
+
+/**
+ * update link auto negotiation speed and duplex mode
+ * this function assumes the mac mode already set using the al_eth_mac_config()
+ * function.
+ *
+ * @param adapter pointer to the private structure
+ * @param force_1000_base_x set to AL_TRUE to force the mac to work on 1000baseX
+ *	  (not relevant to RGMII)
+ * @param an_enable set to AL_TRUE to enable auto negotiation
+ *	  (not relevant to RGMII)
+ * @param speed in mega bits, e.g 1000 stands for 1Gbps (relevant only in case
+ *	  an_enable is AL_FALSE)
+ * @param full_duplex set to AL_TRUE to enable full duplex mode (relevant only
+ *	  in case an_enable is AL_FALSE)
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_mac_link_config(struct al_hal_eth_adapter *adapter,
+			   al_bool force_1000_base_x,
+			   al_bool an_enable,
+			   uint32_t speed,
+			   al_bool full_duplex);
+/**
+ * Enable/Disable Loopback mode
+ *
+ * @param adapter pointer to the private structure
+ * @param enable set to AL_TRUE to enable full duplex mode
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_mac_loopback_config(struct al_hal_eth_adapter *adapter, int enable);
+
+/**
+ * configure minimum and maximum rx packet length
+ *
+ * @param adapter pointer to the private structure
+ * @param min_rx_len minimum rx packet length
+ * @param max_rx_len maximum rx packet length
+ * both length limits in bytes and it includes the MAC Layer header and FCS.
+ * @return 0 on success, otherwise on failure.
+ */
+int al_eth_rx_pkt_limit_config(struct al_hal_eth_adapter *adapter, uint32_t min_rx_len, uint32_t max_rx_len);
+
+
+/* MDIO */
+
+/* Reference clock frequency (platform specific) */
+enum al_eth_ref_clk_freq {
+	AL_ETH_REF_FREQ_375_MHZ		= 0,
+	AL_ETH_REF_FREQ_187_5_MHZ	= 1,
+	AL_ETH_REF_FREQ_250_MHZ		= 2,
+	AL_ETH_REF_FREQ_500_MHZ		= 3,
+	AL_ETH_REF_FREQ_428_MHZ         = 4,
+};
+
+/**
+ * configure the MDIO hardware interface
+ * @param adapter pointer to the private structure
+ * @param mdio_type clause type
+ * @param shared_mdio_if set to AL_TRUE if multiple controllers using the same
+ * @param ref_clk_freq reference clock frequency
+ * @param mdio_clk_freq_khz the required MDC/MDIO clock frequency [Khz]
+ * MDIO pins of the chip.
+ *
+ * @return 0 on success, otherwise on failure.
+ */
+int al_eth_mdio_config(struct al_hal_eth_adapter *adapter,
+		       enum al_eth_mdio_type mdio_type,
+		       al_bool shared_mdio_if,
+		       enum al_eth_ref_clk_freq ref_clk_freq,
+		       unsigned int mdio_clk_freq_khz);
+
+/**
+ * read mdio register
+ * this function uses polling mode, and as the mdio is slow interface, it might
+ * block the cpu for long time (milliseconds).
+ * @param adapter pointer to the private structure
+ * @param phy_addr address of mdio phy
+ * @param device address of mdio device (used only in CLAUSE 45)
+ * @param reg index of the register
+ * @param val pointer for read value of the register
+ *
+ * @return 0 on success, negative errno on failure
+ */
+int al_eth_mdio_read(struct al_hal_eth_adapter *adapter, uint32_t phy_addr,
+		     uint32_t device, uint32_t reg, uint16_t *val);
+
+/**
+ * write mdio register
+ * this function uses polling mode, and as the mdio is slow interface, it might
+ * block the cpu for long time (milliseconds).
+ * @param adapter pointer to the private structure
+ * @param phy_addr address of mdio phy
+ * @param device address of mdio device (used only in CLAUSE 45)
+ * @param reg index of the register
+ * @param val value to write
+ *
+ * @return 0 on success, negative errno on failure
+ */
+int al_eth_mdio_write(struct al_hal_eth_adapter *adapter, uint32_t phy_addr,
+		      uint32_t device, uint32_t reg, uint16_t val);
+
+/* TX */
+/**
+ * get number of free tx descriptors
+ *
+ * @param adapter adapter handle
+ * @param qid queue index
+ *
+ * @return num of free descriptors.
+ */
+static INLINE uint32_t al_eth_tx_available_get(struct al_hal_eth_adapter *adapter,
+					       uint32_t qid)
+{
+	struct al_udma_q *udma_q;
+
+	al_udma_q_handle_get(&adapter->tx_udma, qid, &udma_q);
+
+	return al_udma_available_get(udma_q);
+}
+
+/**
+ * prepare packet descriptors in tx queue.
+ *
+ * This functions prepares the descriptors for the given packet in the tx
+ * submission ring. the caller must call al_eth_tx_pkt_action() below
+ * in order to notify the hardware about the new descriptors.
+ *
+ * @param tx_dma_q pointer to UDMA tx queue
+ * @param pkt the packet to transmit
+ *
+ * @return number of descriptors used for this packet, 0 if no free
+ * room in the descriptors ring
+ */
+int al_eth_tx_pkt_prepare(struct al_udma_q *tx_dma_q, struct al_eth_pkt *pkt);
+
+
+/**
+ * Trigger the DMA about previously added tx descriptors.
+ *
+ * @param tx_dma_q pointer to UDMA tx queue
+ * @param tx_descs number of descriptors to notify the DMA about.
+ * the tx_descs can be sum of descriptor numbers of multiple prepared packets,
+ * this way the caller can use this function to notify the DMA about multiple
+ * packets.
+ */
+void al_eth_tx_dma_action(struct al_udma_q *tx_dma_q, uint32_t tx_descs);
+
+/**
+ * get number of completed tx descriptors, upper layer should derive from
+ * this information which packets were completed.
+ *
+ * @param tx_dma_q pointer to UDMA tx queue
+ *
+ * @return number of completed tx descriptors.
+ */
+int al_eth_comp_tx_get(struct al_udma_q *tx_dma_q);
+
+/**
+ * configure a TSO MSS val
+ *
+ * the TSO MSS vals are preconfigured values for MSS stored in hardware and the
+ * packet could use them when not working in MSS explicit mode.
+ * @param adapter pointer to the private structure
+ * @param idx the mss index
+ * @param mss_val the MSS value
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_tso_mss_config(struct al_hal_eth_adapter *adapter, uint8_t idx, uint32_t mss_val);
+
+/* RX */
+/**
+ * Config the RX descriptor fields
+ *
+ * @param adapter pointer to the private structure
+ * @param lro_sel select LRO context or l4 offset
+ * @param l4_offset_sel select l4 offset source
+ * @param l4_sel  select the l4 checksum result
+ * @param l3_sel  select the l3 checksum result
+ * @param l3_proto_sel select the l3 protocol index source
+ * @param l4_proto_sel select the l4 protocol index source
+ * @param frag_sel select the frag indication source
+ */
+void al_eth_rx_desc_config(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_rx_desc_lro_context_val_res lro_sel,
+			enum al_eth_rx_desc_l4_offset_sel l4_offset_sel,
+			enum al_eth_rx_desc_l3_offset_sel l3_offset_sel,
+			enum al_eth_rx_desc_l4_chk_res_sel l4_sel,
+			enum al_eth_rx_desc_l3_chk_res_sel l3_sel,
+			enum al_eth_rx_desc_l3_proto_idx_sel l3_proto_sel,
+			enum al_eth_rx_desc_l4_proto_idx_sel l4_proto_sel,
+			enum al_eth_rx_desc_frag_sel frag_sel);
+
+/**
+ * Configure RX header split
+ *
+ * @param adapter pointer to the private structure
+ * @param enable header split when AL_TRUE
+ * @param header_split_len length in bytes of the header split, this value used when
+ * CTRL TABLE header split len select is set to
+ * AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_REG, in this case the controller will
+ * store the first header_split_len bytes into buf2, then the rest (if any) into buf1.
+ * when CTRL_TABLE header split len select set to other value, then the header_len
+ * determined according to the parser, and the header_split_len parameter is not
+ * used.
+ *
+ * return 0 on success. otherwise on failure.
+ */
+int al_eth_rx_header_split_config(struct al_hal_eth_adapter *adapter, al_bool enable, uint32_t header_len);
+
+/**
+ * enable / disable header split in the udma queue.
+ * length will be taken from the udma configuration to enable different length per queue.
+ *
+ * @param adapter pointer to the private structure
+ * @param enable header split when AL_TRUE
+ * @param qid the queue id to enable/disable header split
+ * @param header_len in what len the udma will cut the header
+ *
+ * return 0 on success.
+ */
+int al_eth_rx_header_split_force_len_config(struct al_hal_eth_adapter *adapter,
+					al_bool enable,
+					uint32_t qid,
+					uint32_t header_len);
+
+/**
+ * add buffer to receive queue
+ *
+ * @param rx_dma_q pointer to UDMA rx queue
+ * @param buf pointer to data buffer
+ * @param flags bitwise of AL_ETH_RX_FLAGS
+ * @param header_buf this is not used for far and header_buf should be set to
+ * NULL.
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_rx_buffer_add(struct al_udma_q *rx_dma_q,
+			      struct al_buf *buf, uint32_t flags,
+			      struct al_buf *header_buf);
+
+/**
+ * notify the hw engine about rx descriptors that were added to the receive queue
+ *
+ * @param rx_dma_q pointer to UDMA rx queue
+ * @param descs_num number of rx descriptors
+ */
+void al_eth_rx_buffer_action(struct al_udma_q *rx_dma_q,
+				uint32_t descs_num);
+
+/**
+ * get packet from RX completion ring
+ *
+ * @param rx_dma_q pointer to UDMA rx queue
+ * @param pkt pointer to a packet data structure, this function fills this
+ * structure with the information about the received packet. the buffers
+ * structures filled only with the length of the data written into the buffer,
+ * the address fields are not updated as the upper layer can retrieve this
+ * information by itself because the hardware uses the buffers in the same order
+ * were those buffers inserted into the ring of the receive queue.
+ * this structure should be allocated by the caller function.
+ *
+ * @return return number of descriptors or 0 if no completed packet found.
+ */
+ uint32_t al_eth_pkt_rx(struct al_udma_q *rx_dma_q, struct al_eth_pkt *pkt);
+
+
+/* RX parser table */
+struct al_eth_epe_p_reg_entry {
+	uint32_t data;
+	uint32_t mask;
+	uint32_t ctrl;
+};
+
+struct al_eth_epe_control_entry {
+	uint32_t data[6];
+};
+
+/**
+ * update rx parser entry
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the protocol index to update
+ * @param reg_entry contents of parser register entry
+ * @param control entry contents of control table entry
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_rx_parser_entry_update(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_epe_p_reg_entry *reg_entry,
+		struct al_eth_epe_control_entry *control_entry);
+
+/* Flow Steering and filtering */
+int al_eth_thash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma, uint32_t queue);
+
+/* FSM table bits */
+/** FSM table has 7 bits input address:
+ *  bits[2:0] are the outer packet's type (IPv4, TCP...)
+ *  bits[5:3] are the inner packet's type
+ *  bit[6] is set when packet is tunneled.
+ *
+ * The output of each entry:
+ *  bits[1:0] - input selection: selects the input for the thash (2/4 tuple, inner/outer)
+ *  bit[2] - selects whether to use thash output, or default values for the queue and udma
+ *  bits[6:3] default UDMA mask: the UDMAs to select when bit 2 above was unset
+ *  bits[9:5] defualt queue: the queue index to select when bit 2 above was unset
+ */
+
+#define AL_ETH_FSM_ENTRY_IPV4_TCP	   0
+#define AL_ETH_FSM_ENTRY_IPV4_UDP	   1
+#define AL_ETH_FSM_ENTRY_IPV6_TCP	   2
+#define AL_ETH_FSM_ENTRY_IPV6_UDP	   3
+#define AL_ETH_FSM_ENTRY_IPV6_NO_UDP_TCP   4
+#define AL_ETH_FSM_ENTRY_IPV4_NO_UDP_TCP   5
+#define AL_ETH_FSM_ENTRY_IPV4_FRAGMENTED   6
+#define AL_ETH_FSM_ENTRY_NOT_IP		   7
+
+#define AL_ETH_FSM_ENTRY_OUTER(idx)	   ((idx) & 7)
+#define AL_ETH_FSM_ENTRY_INNER(idx)	   (((idx) >> 3) & 7)
+#define AL_ETH_FSM_ENTRY_TUNNELED(idx)	   (((idx) >> 6) & 1)
+
+/* FSM DATA format */
+#define AL_ETH_FSM_DATA_OUTER_2_TUPLE	0
+#define AL_ETH_FSM_DATA_OUTER_4_TUPLE	1
+#define AL_ETH_FSM_DATA_INNER_2_TUPLE	2
+#define AL_ETH_FSM_DATA_INNER_4_TUPLE	3
+
+#define AL_ETH_FSM_DATA_HASH_SEL	(1 << 2)
+
+#define AL_ETH_FSM_DATA_DEFAULT_Q_SHIFT		5
+#define AL_ETH_FSM_DATA_DEFAULT_UDMA_SHIFT	3
+
+/* set fsm table entry */
+int al_eth_fsm_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry);
+
+enum AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT {
+	AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_0 = 0,
+	AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_1 = 1,
+	AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_ANY = 2,
+};
+
+enum AL_ETH_FWD_CTRL_IDX_TUNNEL {
+	AL_ETH_FWD_CTRL_IDX_TUNNEL_NOT_EXIST = 0,
+	AL_ETH_FWD_CTRL_IDX_TUNNEL_EXIST = 1,
+	AL_ETH_FWD_CTRL_IDX_TUNNEL_ANY = 2,
+};
+
+enum AL_ETH_FWD_CTRL_IDX_VLAN {
+	AL_ETH_FWD_CTRL_IDX_VLAN_NOT_EXIST = 0,
+	AL_ETH_FWD_CTRL_IDX_VLAN_EXIST = 1,
+	AL_ETH_FWD_CTRL_IDX_VLAN_ANY = 2,
+};
+
+enum AL_ETH_FWD_CTRL_IDX_MAC_TABLE {
+	AL_ETH_FWD_CTRL_IDX_MAC_TABLE_NO_MATCH = 0,
+	AL_ETH_FWD_CTRL_IDX_MAC_TABLE_MATCH = 1,
+	AL_ETH_FWD_CTRL_IDX_MAC_TABLE_ANY = 2,
+};
+
+enum AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE {
+	AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_UC = 0, /**< unicast */
+	AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_MC = 1, /**< multicast */
+	AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_BC = 2, /**< broadcast */
+	AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_ANY = 4, /**< for sw usage */
+};
+
+/**
+ * This structure defines the index or group of indeces within the control table.
+ * each field has special enum value (with _ANY postfix) that indicates all
+ * possible values of that field.
+ */
+struct al_eth_fwd_ctrl_table_index {
+	enum AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT	vlan_table_out;
+	enum AL_ETH_FWD_CTRL_IDX_TUNNEL tunnel_exist;
+	enum AL_ETH_FWD_CTRL_IDX_VLAN vlan_exist;
+	enum AL_ETH_FWD_CTRL_IDX_MAC_TABLE mac_table_match;
+	enum AL_ETH_PROTO_ID		protocol_id;
+	enum AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE mac_type;
+};
+
+enum AL_ETH_CTRL_TABLE_PRIO_SEL {
+	AL_ETH_CTRL_TABLE_PRIO_SEL_PBITS_TABLE	= 0,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_DSCP_TABLE	= 1,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_TC_TABLE	= 2,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_REG1		= 3,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_REG2		= 4,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_REG3		= 5,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_REG4		= 6,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_REG5		= 7,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_REG6		= 7,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_REG7		= 9,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_REG8		= 10,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_VAL_3	= 11,
+	AL_ETH_CTRL_TABLE_PRIO_SEL_VAL_0	= 12,
+};
+/** where to select the initial queue from */
+enum AL_ETH_CTRL_TABLE_QUEUE_SEL_1 {
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_PRIO_TABLE	= 0,
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_THASH_TABLE	= 1,
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_MAC_TABLE		= 2,
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_MHASH_TABLE	= 3,
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG1		= 4,
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG2		= 5,
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG3		= 6,
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG4		= 7,
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_VAL_3		= 12,
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_1_VAL_0		= 13,
+};
+
+/** target queue will be built up from the priority and initial queue */
+enum AL_ETH_CTRL_TABLE_QUEUE_SEL_2 {
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_TABLE	= 0, /**< target queue is the output of priority table */
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO		= 1, /**< target queue is the priority */
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_2_PRIO_QUEUE	= 2, /**< target queue is initial queue[0], priority[1] */
+	AL_ETH_CTRL_TABLE_QUEUE_SEL_2_NO_PRIO		= 3, /**< target queue is the initial */
+};
+
+enum AL_ETH_CTRL_TABLE_UDMA_SEL {
+	AL_ETH_CTRL_TABLE_UDMA_SEL_THASH_TABLE		= 0,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_THASH_AND_VLAN	= 1,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_VLAN_TABLE		= 2,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_VLAN_AND_MAC		= 3,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_MAC_TABLE		= 4,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_MAC_AND_MHASH	= 5,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_MHASH_TABLE		= 6,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_REG1			= 7,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_REG2			= 8,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_REG3			= 9,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_REG4			= 10,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_REG5			= 11,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_REG6			= 12,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_REG7			= 13,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_REG8			= 14,
+	AL_ETH_CTRL_TABLE_UDMA_SEL_VAL_0		= 15,
+};
+
+enum AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL {
+	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_0		= 0,
+	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_REG		= 1, /**< select header len from the hdr_split register (set by al_eth_rx_header_split_config())*/
+	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_OUTER_L3_OFFSET = 2,
+	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_OUTER_L4_OFFSET = 3,
+	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_TUNNEL_START_OFFSET = 4,
+	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_INNER_L3_OFFSET = 5,
+	AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_INNER_L4_OFFSET = 6,
+};
+
+struct al_eth_fwd_ctrl_table_entry {
+	enum AL_ETH_CTRL_TABLE_PRIO_SEL		prio_sel;
+	enum AL_ETH_CTRL_TABLE_QUEUE_SEL_1	queue_sel_1; /**< queue id source */
+	enum AL_ETH_CTRL_TABLE_QUEUE_SEL_2	queue_sel_2; /**< mix queue id with priority */
+	enum AL_ETH_CTRL_TABLE_UDMA_SEL		udma_sel;
+	enum AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL hdr_split_len_sel;
+	al_bool 	filter; /**< set to AL_TRUE to enable filtering */
+};
+/**
+ * Configure default control table entry
+ *
+ * @param adapter pointer to the private structure
+ * @param use_table set to AL_TRUE if control table is used, when set to AL_FALSE
+ * then control table will be bypassed and the entry value will be used.
+ * @param entry defines the value to be used when bypassing control table.
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_ctrl_table_def_set(struct al_hal_eth_adapter *adapter,
+			      al_bool use_table,
+			      struct al_eth_fwd_ctrl_table_entry *entry);
+
+/**
+ * Configure control table entry
+ *
+ * @param adapter pointer to the private structure
+ * @param index the entry index within the control table.
+ * @param entry the value to write to the control table entry
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_ctrl_table_set(struct al_hal_eth_adapter *adapter,
+			  struct al_eth_fwd_ctrl_table_index *index,
+			  struct al_eth_fwd_ctrl_table_entry *entry);
+
+int al_eth_ctrl_table_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry);
+int al_eth_ctrl_table_def_raw_set(struct al_hal_eth_adapter *adapter, uint32_t val);
+
+/**
+ * Configure hash key initial registers
+ * Those registers define the initial key values, those values used for
+ * the THASH and MHASH hash functions.
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the register index
+ * @param val the register value
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_hash_key_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t val);
+
+struct al_eth_fwd_mac_table_entry {
+	uint8_t		addr[6]; /**< byte 0 is the first byte seen on the wire */
+	uint8_t		mask[6];
+	al_bool		tx_valid;
+	uint8_t		tx_target;
+	al_bool		rx_valid;
+	uint8_t		udma_mask; /**< target udma */
+	uint8_t		qid; /**< target queue */
+	al_bool		filter; /**< set to AL_TRUE to enable filtering */
+};
+
+/**
+ * Configure mac table entry
+ * The HW traverse this table and looks for match from lowest index,
+ * when the packets MAC DA & mask == addr, and the valid bit is set, then match occurs.
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index within the mac table.
+ * @param entry the contents of the MAC table entry
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_fwd_mac_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+				struct al_eth_fwd_mac_table_entry *entry);
+
+int al_eth_fwd_mac_addr_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+				uint32_t addr_lo, uint32_t addr_hi, uint32_t mask_lo, uint32_t mask_hi);
+int al_eth_fwd_mac_ctrl_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t ctrl);
+
+int al_eth_mac_addr_store(void * __iomem ec_base, uint32_t idx, uint8_t *addr);
+int al_eth_mac_addr_read(void * __iomem ec_base, uint32_t idx, uint8_t *addr);
+
+/**
+ * Configure pbits table entry
+ * The HW uses this table to translate between vlan pbits field to priority.
+ * The vlan pbits is used as the index of this table.
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index within the table.
+ * @param prio the priority to set for this entry
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_fwd_pbits_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio);
+
+/**
+ * Configure priority table entry
+ * The HW uses this table to translate between priority to queue index.
+ * The priority is used as the index of this table.
+ *
+ * @param adapter pointer to the private structure
+ * @param prio the entry index within the table.
+ * @param qid the queue index to set for this entry (priority).
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_fwd_priority_table_set(struct al_hal_eth_adapter *adapter, uint8_t prio, uint8_t qid);
+
+/**
+ * Configure DSCP table entry
+ * The HW uses this table to translate between IPv4 DSCP field to priority.
+ * The IPv4 byte 1 (DSCP+ECN) used as index to this table.
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index within the table.
+ * @param prio the queue index to set for this entry (priority).
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_fwd_dscp_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio);
+
+/**
+ * Configure TC table entry
+ * The HW uses this table to translate between IPv6 TC field to priority.
+ * The IPv6 TC used as index to this table.
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index within the table.
+ * @param prio the queue index to set for this entry (priority).
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_fwd_tc_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio);
+
+/**
+ * Configure MAC HASH table entry
+ * The HW uses 8 bits from the hash result on the MAC DA as index to this table.
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index within the table.
+ * @param udma_mask the target udma to set for this entry.
+ * @param qid the target queue index to set for this entry.
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_fwd_mhash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, uint8_t qid);
+
+struct al_eth_fwd_vid_table_entry {
+	uint8_t	control:1; /**< used as input for the control table */
+	uint8_t filter:1; /**< set to 1 to enable filtering */
+	uint8_t udma_mask:4; /**< target udmas */
+};
+
+/**
+ * Configure default vlan table entry
+ *
+ * @param adapter pointer to the private structure
+ * @param use_table set to AL_TRUE if vlan table is used, when set to AL_FALSE
+ * then vid table will be bypassed and the default_entry value will be used.
+ * @param default_entry defines the value to be used when bypassing vid table.
+ * @param default_vlan defines the value will be used when untagget packet
+ * received. this value will be used only for steering and filtering control,
+ * the packet's data will not be changed.
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_fwd_vid_config_set(struct al_hal_eth_adapter *adapter, al_bool use_table,
+			      struct al_eth_fwd_vid_table_entry *default_entry,
+			      uint32_t default_vlan);
+/**
+ * Configure vlan table entry
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index within the vlan table. The HW uses the vlan id
+ * field of the packet when accessing this table.
+ * @param entry the value to write to the vlan table entry
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+			     struct al_eth_fwd_vid_table_entry *entry);
+
+
+/**
+ * Configure default UDMA register
+ * When the control table entry udma selection set to AL_ETH_CTRL_TABLE_UDMA_SEL_REG<n>,
+ * then the target UDMA will be set according to the register n of the default
+ * UDMA registers.
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the index of the default register.
+ * @param udma_mask the value of the register.
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_fwd_default_udma_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
+				   uint8_t udma_mask);
+
+/**
+ * Configure default queue register
+ * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_QUEUE_SEL_1_REG<n>,
+ * then the target queue will be set according to the register n of the default
+ * queue registers.
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the index of the default register.
+ * @param qid the value of the register.
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_fwd_default_queue_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
+				   uint8_t qid);
+
+/**
+ * Configure default priority register
+ * When the control table entry queue selection 1 set to AL_ETH_CTRL_TABLE_PRIO_SEL_1_REG<n>,
+ * then the target priority will be set according to the register n of the default
+ * priority registers.
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the index of the default register.
+ * @param prio the value of the register.
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_fwd_default_priority_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
+				   uint8_t prio);
+
+
+
+/* filter undetected MAC DA */
+#define AL_ETH_RFW_FILTER_UNDET_MAC          (1 << 0)
+/* filter specific MAC DA based on MAC table output */
+#define AL_ETH_RFW_FILTER_DET_MAC            (1 << 1)
+/* filter all tagged */
+#define AL_ETH_RFW_FILTER_TAGGED             (1 << 2)
+/* filter all untagged */
+#define AL_ETH_RFW_FILTER_UNTAGGED           (1 << 3)
+/* filter all broadcast */
+#define AL_ETH_RFW_FILTER_BC                 (1 << 4)
+/* filter all multicast */
+#define AL_ETH_RFW_FILTER_MC                 (1 << 5)
+/* filter packet based on parser drop */
+#define AL_ETH_RFW_FILTER_PARSE              (1 << 6)
+/* filter packet based on VLAN table output */
+#define AL_ETH_RFW_FILTER_VLAN_VID           (1 << 7)
+/* filter packet based on control table output */
+#define AL_ETH_RFW_FILTER_CTRL_TABLE         (1 << 8)
+/* filter packet based on protocol index */
+#define AL_ETH_RFW_FILTER_PROT_INDEX         (1 << 9)
+/* filter packet based on WoL decision */
+#define AL_ETH_RFW_FILTER_WOL		     (1 << 10)
+
+
+struct al_eth_filter_params {
+	al_bool		enable;
+	uint32_t	filters; /**< bitmask of AL_ETH_RFW_FILTER.. for filters to enable */
+	al_bool		filter_proto[AL_ETH_PROTOCOLS_NUM]; /**< set AL_TRUE for protocols to filter */
+};
+
+struct al_eth_filter_override_params {
+	uint32_t	filters; /**< bitmask of AL_ETH_RFW_FILTER.. for filters to override */
+	uint8_t		udma; /**< target udma id */
+	uint8_t		qid; /**< target queue id */
+};
+
+/**
+ * Configure the receive filters
+ * this function enables/disables filtering packets and which filtering
+ * types to apply.
+ * filters that indicated in tables (MAC table, VLAN and Control tables)
+ * are not configured by this function. This functions only enables/disables
+ * respecting the filter indication from those tables.
+ *
+ * @param adapter pointer to the private structure
+ * @param params the parameters passed from upper layer
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_filter_config(struct al_hal_eth_adapter *adapter, struct al_eth_filter_params *params);
+
+/**
+ * Configure the receive override filters
+ * This function controls whither to force forwarding filtered packets
+ * to a specific UDMA/queue. The override filters apply only for
+ * filters that enabled by al_eth_filter_config().
+ *
+ * @param adapter pointer to the private structure
+ * @param params override config parameters
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_filter_override_config(struct al_hal_eth_adapter *adapter,
+				  struct al_eth_filter_override_params *params);
+
+
+int al_eth_switching_config_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t forward_all_to_mac, uint8_t enable_int_switching,
+					enum al_eth_tx_switch_vid_sel_type vid_sel_type,
+					enum al_eth_tx_switch_dec_type uc_dec,
+					enum al_eth_tx_switch_dec_type mc_dec,
+					enum al_eth_tx_switch_dec_type bc_dec);
+int al_eth_switching_default_bitmap_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t udma_uc_bitmask,
+						uint8_t udma_mc_bitmask,uint8_t udma_bc_bitmask);
+int al_eth_flow_control_config(struct al_hal_eth_adapter *adapter, struct al_eth_flow_control_params *params);
+
+struct al_eth_eee_params{
+	uint8_t enable;
+	uint32_t tx_eee_timer; /**< time in cycles the interface delays prior to entering eee state */
+	uint32_t min_interval; /**< minimum interval in cycles between two eee states */
+	uint32_t stop_cnt; /**< time in cycles to stop Tx mac i/f after getting out of eee state */
+};
+
+/**
+ * configure EEE mode
+ * @param adapter pointer to the private structure.
+ * @param params pointer to the eee input parameters.
+ *
+ * @return return 0 on success. otherwise on failure.
+ */
+int al_eth_eee_config(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params);
+
+/**
+ * get EEE configuration
+ * @param adapter pointer to the private structure.
+ * @param params pointer to the eee output parameters.
+ *
+ * @return return 0 on success. otherwise on failure.
+ */
+int al_eth_eee_get(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params);
+
+int al_eth_vlan_mod_config(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint16_t udma_etype, uint16_t vlan1_data, uint16_t vlan2_data);
+
+/* Timestamp
+ * This is a generic time-stamp mechanism that can be used as generic to
+ * time-stamp every received or transmit packet it can also support IEEE 1588v2
+ * PTP time synchronization protocol.
+ * In addition to time-stamp, an internal system time is maintained. For
+ * further accuracy, the chip support transmit/receive clock synchronization
+ * including recovery of master clock from one of the ports and distributing it
+ * to the rest of the ports - that is outside the scope of the Ethernet
+ * Controller - please refer to Annapurna Labs Alpine Hardware Wiki
+ */
+
+/* Timestamp management APIs */
+
+/**
+ * prepare the adapter for timestamping packets.
+ * Rx timestamps requires using 8 words (8x4 bytes) rx completion descriptor
+ * size as the timestamp value added into word 4.
+ *
+ * This function should be called after al_eth_mac_config() and before
+ * enabling the queues.
+ * @param adapter pointer to the private structure.
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_ts_init(struct al_hal_eth_adapter *adapter);
+
+/* Timestamp data path APIs */
+
+/*
+ * This is the size of the on-chip array that keeps the time-stamp of the
+ * latest transmitted packets
+ */
+#define AL_ETH_PTH_TX_SAMPLES_NUM	16
+
+/**
+ * read Timestamp sample value of previously transmitted packet.
+ *
+ * The adapter includes AL_ETH_PTH_TX_SAMPLES_NUM timestamp samples for tx
+ * packets, those samples shared for all the UDMAs and queues. the al_eth_pkt
+ * data structure includes the index of which sample to use for the packet
+ * to transmit. It's the caller's responsibility to manage those samples,
+ * for example, when using an index, the caller must make sure the packet
+ * is completed and the tx time is sampled before using that index for
+ * another packet.
+ *
+ * This function should be called after the completion indication of the
+ * tx packet. however, there is a little chance that the timestamp sample
+ * won't be updated yet, thus this function must be called again when it
+ * returns -EAGAIN.
+ * @param adapter pointer to the private structure.
+ * @param ts_index the index (out of 16) of the timestamp register
+ * @param timestamp the timestamp value in 2^18 femtoseconds resolution.
+ * @return -EAGAIN if the sample was not updated yet. 0 when the sample
+ * was updated and no errors found.
+ */
+int al_eth_tx_ts_val_get(struct al_hal_eth_adapter *adapter, uint8_t ts_index,
+			 uint32_t *timestamp);
+
+/* Timestamp PTH (PTP Timestamp Handler) control and times management */
+/** structure for describing PTH epoch time */
+struct al_eth_pth_time {
+	uint32_t	seconds; /**< seconds */
+	uint64_t	femto; /**< femto seconds */
+};
+
+/**
+ * Read the systime value
+ * This API should not be used to get the timestamp of packets.
+ * The HW maintains 50 bits for the sub-seconds portion in femto resolution,
+ * but this function reads only the 32 MSB bits since the LSB provides
+ * sub-nanoseconds accuracy, which is not needed.
+ * @param adapter pointer to the private structure.
+ * @param systime pointer to structure where the time will be stored.
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_pth_systime_read(struct al_hal_eth_adapter *adapter,
+			    struct al_eth_pth_time *systime);
+
+/**
+ * Set the clock period to a given value.
+ * The systime will be incremented by this value on each posedge of the
+ * adapters internal clock which driven by the SouthBridge clock.
+ * @param adapter pointer to the private structure.
+ * @param clk_period the clock period in femto seconds.
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_pth_clk_period_write(struct al_hal_eth_adapter *adapter,
+				uint64_t clk_period);
+
+/**< enum for methods when updating systime using triggers */
+enum al_eth_pth_update_method {
+	AL_ETH_PTH_UPDATE_METHOD_SET = 0, /**< Set the time in int/ext update time */
+	AL_ETH_PTH_UPDATE_METHOD_INC = 1, /**< increment */
+	AL_ETH_PTH_UPDATE_METHOD_DEC = 2, /**< decrement */
+	AL_ETH_PTH_UPDATE_METHOD_ADD_TO_LAST = 3, /**< Set to last time + int/ext update time.*/
+};
+
+/**< systime internal update trigger types */
+enum al_eth_pth_int_trig {
+	AL_ETH_PTH_INT_TRIG_OUT_PULSE_0 = 0, /**< use output pulse as trigger */
+	AL_ETH_PTH_INT_TRIG_REG_WRITE = 1, /**< use the int update register
+					    * write as a trigger
+					    */
+};
+
+/**< parameters for internal trigger update */
+struct al_eth_pth_int_update_params {
+	al_bool		enable; /**< enable internal trigger update */
+	enum al_eth_pth_update_method	method; /**< internal trigger update
+						 * method
+						 */
+	enum al_eth_pth_int_trig	trigger; /**< which internal trigger to
+						  * use
+						  */
+};
+
+/**
+ * Configure the systime internal update
+ *
+ * @param adapter pointer to the private structure.
+ * @param params the configuration of the internal update.
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_pth_int_update_config(struct al_hal_eth_adapter *adapter,
+				 struct al_eth_pth_int_update_params *params);
+
+/**
+ * set internal update time
+ *
+ * The update time used when updating the systime with
+ * internal update method.
+ *
+ * @param adapter pointer to the private structure.
+ * @param time the internal update time value
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_pth_int_update_time_set(struct al_hal_eth_adapter *adapter,
+				   struct al_eth_pth_time *time);
+
+/**< parameters for external trigger update */
+struct al_eth_pth_ext_update_params {
+	uint8_t		triggers; /**< bitmask of external triggers to enable */
+	enum al_eth_pth_update_method	method; /**< external trigger update
+						 * method
+						 */
+};
+
+/**
+ * Configure the systime external update.
+ * external update triggered by external signals such as GPIO or pulses
+ * from other eth controllers on the SoC.
+ *
+ * @param adapter pointer to the private structure.
+ * @param params the configuration of the external update.
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_pth_ext_update_config(struct al_hal_eth_adapter *adapter,
+				 struct al_eth_pth_ext_update_params *params);
+
+/**
+ * set external update time
+ *
+ * The update time used when updating the systime with
+ * external update method.
+ * @param adapter pointer to the private structure.
+ * @param time the external update time value
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_pth_ext_update_time_set(struct al_hal_eth_adapter *adapter,
+				   struct al_eth_pth_time *time);
+/**
+ * set the read compensation delay
+ *
+ * When reading the systime, the HW adds this value to compensate
+ * read latency.
+ *
+ * @param adapter pointer to the private structure.
+ * @param subseconds the read latency delay in femto seconds.
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_pth_read_compensation_set(struct al_hal_eth_adapter *adapter,
+				     uint64_t subseconds);
+/**
+ * set the internal write compensation delay
+ *
+ * When updating the systime due to an internal trigger's event, the HW adds
+ * this value to compensate latency.
+ *
+ * @param adapter pointer to the private structure.
+ * @param subseconds the write latency delay in femto seconds.
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_pth_int_write_compensation_set(struct al_hal_eth_adapter *adapter,
+					  uint64_t subseconds);
+
+/**
+ * set the external write compensation delay
+ *
+ * When updating the systime due to an external trigger's event, the HW adds
+ * this value to compensate pulse propagation latency.
+ *
+ * @param adapter pointer to the private structure.
+ * @param subseconds the write latency delay in femto seconds.
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_pth_ext_write_compensation_set(struct al_hal_eth_adapter *adapter,
+					  uint64_t subseconds);
+
+/**
+ * set the sync compensation delay
+ *
+ * When the adapter passes systime from PTH to MAC to do the packets
+ * timestamping, the sync compensation delay is added to systime value to
+ * compensate the latency between the PTH and the MAC.
+ *
+ * @param adapter pointer to the private structure.
+ * @param subseconds the sync latency delay in femto seconds.
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_pth_sync_compensation_set(struct al_hal_eth_adapter *adapter,
+				     uint64_t subseconds);
+
+#define AL_ETH_PTH_PULSE_OUT_NUM	8
+struct al_eth_pth_pulse_out_params {
+	uint8_t		index; /**< id of the pulse (0..7) */
+	al_bool		enable;
+	al_bool		periodic; /**< when true, generate periodic pulse (PPS) */
+	uint8_t		period_sec; /**< for periodic pulse, this is seconds
+				     * portion of the period time
+				     */
+	uint32_t	period_us; /**< this is microseconds portion of the
+				      * period
+				      */
+	struct al_eth_pth_time	start_time; /**< when to start pulse triggering */
+	uint64_t	pulse_width; /**< pulse width in femto seconds */
+};
+
+/**
+ * Configure an output pulse
+ * This function configures an output pulse coming from the internal System
+ * Time. This is typically a 1Hhz pulse that is used to synchronize the
+ * rest of the components of the system. This API configure the Ethernet
+ * Controller pulse. An additional set up is required to configure the chip
+ * General Purpose I/O (GPIO) to enable the chip output pin.
+ *
+ * @param adapter pointer to the private structure.
+ * @param params output pulse configuration.
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_pth_pulse_out_config(struct al_hal_eth_adapter *adapter,
+				struct al_eth_pth_pulse_out_params *params);
+
+/* link */
+struct al_eth_link_status {
+	al_bool		link_up;
+};
+
+/**
+ * get link status
+ *
+ * this function should be used when no external phy is used to get
+ * information about the link
+ *
+ * @param adapter pointer to the private structure.
+ * @param status pointer to struct where to set link information
+ *
+ * @return return 0 on success. otherwise on failure.
+ */
+int al_eth_link_status_get(struct al_hal_eth_adapter *adapter, struct al_eth_link_status *status);
+
+/**
+ * Set LEDs to represent link status.
+ *
+ * @param adapter pointer to the private structure.
+ * @param link_is_up boolean indicating current link status.
+ *	  In case link is down the leds will be turned off.
+ *	  In case link is up the leds will be turned on, that means
+ *	  leds will be blinking on traffic and will be constantly lighting
+ *	  on inactive link
+ * @return return 0 on success. otherwise on failure.
+ */
+int al_eth_led_set(struct al_hal_eth_adapter *adapter, al_bool link_is_up);
+
+/* get statistics */
+
+struct al_eth_mac_stats{
+	/* sum the data and padding octets (i.e. without header and FCS) received with a valid frame. */
+	uint64_t aOctetsReceivedOK;
+	/* sum of Payload and padding octets of frames transmitted without error*/
+	uint64_t aOctetsTransmittedOK;
+	/* total number of packets received. Good and bad packets */
+	uint32_t etherStatsPkts;
+	/* number of received unicast packets */
+	uint32_t ifInUcastPkts;
+	/* number of received multicast packets */
+	uint32_t ifInMulticastPkts;
+	/* number of received broadcast packets */
+	uint32_t ifInBroadcastPkts;
+	/* Number of frames received with FIFO Overflow, CRC, Payload Length, Jabber and Oversized, Alignment or PHY/PCS error indication */
+	uint32_t ifInErrors;
+
+	/* number of transmitted unicast packets */
+	uint32_t ifOutUcastPkts;
+	/* number of transmitted multicast packets */
+	uint32_t ifOutMulticastPkts;
+	/* number of transmitted broadcast packets */
+	uint32_t ifOutBroadcastPkts;
+	/* number of frames transmitted with FIFO Overflow, FIFO Underflow or Controller indicated error */
+	uint32_t ifOutErrors;
+
+	/* number of Frame received without error (Including Pause Frames). */
+	uint32_t aFramesReceivedOK;
+	/* number of Frames transmitter without error (Including Pause Frames) */
+	uint32_t aFramesTransmittedOK;
+	/* number of packets received with less than 64 octets */
+	uint32_t etherStatsUndersizePkts;
+	/* Too short frames with CRC error, available only for RGMII and 1G Serial modes */
+	uint32_t etherStatsFragments;
+	/* Too long frames with CRC error */
+	uint32_t etherStatsJabbers;
+	/* packet that exceeds the valid maximum programmed frame length */
+	uint32_t etherStatsOversizePkts;
+	/* number of frames received with a CRC error */
+	uint32_t aFrameCheckSequenceErrors;
+	/* number of frames received with alignment error */
+	uint32_t aAlignmentErrors;
+	/* number of dropped packets due to FIFO overflow */
+	uint32_t etherStatsDropEvents;
+	/* number of transmitted pause frames. */
+	uint32_t aPAUSEMACCtrlFramesTransmitted;
+	/* number of received pause frames. */
+	uint32_t aPAUSEMACCtrlFramesReceived;
+	/* frame received exceeded the maximum length programmed with register FRM_LGTH, available only for 10G modes */
+	uint32_t aFrameTooLongErrors;
+	/* received frame with bad length/type (between 46 and 0x600 or less
+	 * than 46 for packets longer than 64), available only for 10G modes */
+	uint32_t aInRangeLengthErrors;
+	/* Valid VLAN tagged frames transmitted */
+	uint32_t VLANTransmittedOK;
+	/* Valid VLAN tagged frames received */
+	uint32_t VLANReceivedOK;
+	/* Total number of octets received. Good and bad packets */
+	uint32_t etherStatsOctets;
+
+	/* packets of 64 octets length is received (good and bad frames are counted) */
+	uint32_t etherStatsPkts64Octets;
+	/* Frames (good and bad) with 65 to 127 octets */
+	uint32_t etherStatsPkts65to127Octets;
+	/* Frames (good and bad) with 128 to 255 octets */
+	uint32_t etherStatsPkts128to255Octets;
+	/* Frames (good and bad) with 256 to 511 octets */
+	uint32_t etherStatsPkts256to511Octets;
+	/* Frames (good and bad) with 512 to 1023 octets */
+	uint32_t etherStatsPkts512to1023Octets;
+	/* Frames (good and bad) with 1024 to 1518 octets */
+	uint32_t etherStatsPkts1024to1518Octets;
+	/* frames with 1519 bytes to the maximum length programmed in the register FRAME_LENGTH. */
+	uint32_t etherStatsPkts1519toX;
+
+	uint32_t eee_in;
+	uint32_t eee_out;
+};
+
+/**
+ * get mac statistics
+ * @param adapter pointer to the private structure.
+ * @param stats pointer to structure that will be filled with statistics.
+ *
+ * @return return 0 on success. otherwise on failure.
+ */
+int al_eth_mac_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_mac_stats *stats);
+
+struct al_eth_ec_stats{
+	/* Rx Frequency adjust FIFO input  packets */
+	uint32_t faf_in_rx_pkt;
+	/* Rx Frequency adjust FIFO input  short error packets */
+	uint32_t faf_in_rx_short;
+	/* Rx Frequency adjust FIFO input  long error packets */
+	uint32_t faf_in_rx_long;
+	/* Rx Frequency adjust FIFO output  packets */
+	uint32_t faf_out_rx_pkt;
+	/* Rx Frequency adjust FIFO output  short error packets */
+	uint32_t faf_out_rx_short;
+	/* Rx Frequency adjust FIFO output  long error packets */
+	uint32_t faf_out_rx_long;
+	/* Rx Frequency adjust FIFO output  drop packets */
+	uint32_t faf_out_drop;
+	/* Number of packets written into the Rx FIFO (without FIFO error indication) */
+	uint32_t rxf_in_rx_pkt;
+	/* Number of error packets written into the Rx FIFO (with FIFO error indication, */
+	/* FIFO full indication during packet reception) */
+	uint32_t rxf_in_fifo_err;
+	/* Number of packets read from Rx FIFO 1 */
+	uint32_t lbf_in_rx_pkt;
+	/* Number of packets read from Rx FIFO 2 (loopback FIFO) */
+	uint32_t lbf_in_fifo_err;
+	/* Rx FIFO output drop packets from FIFO 1 */
+	uint32_t rxf_out_rx_1_pkt;
+	/* Rx FIFO output drop packets from FIFO 2 (loop back) */
+	uint32_t rxf_out_rx_2_pkt;
+	/* Rx FIFO output drop packets from FIFO 1 */
+	uint32_t rxf_out_drop_1_pkt;
+	/* Rx FIFO output drop packets from FIFO 2 (loop back) */
+	uint32_t rxf_out_drop_2_pkt;
+	/* Rx Parser 1, input packet counter */
+	uint32_t rpe_1_in_rx_pkt;
+	/* Rx Parser 1, output packet counter */
+	uint32_t rpe_1_out_rx_pkt;
+	/* Rx Parser 2, input packet counter */
+	uint32_t rpe_2_in_rx_pkt;
+	/* Rx Parser 2, output packet counter */
+	uint32_t rpe_2_out_rx_pkt;
+	/* Rx Parser 3 (MACsec), input packet counter */
+	uint32_t rpe_3_in_rx_pkt;
+	/* Rx Parser 3 (MACsec), output packet counter */
+	uint32_t rpe_3_out_rx_pkt;
+	/* Tx parser, input packet counter */
+	uint32_t tpe_in_tx_pkt;
+	/* Tx parser, output packet counter */
+	uint32_t tpe_out_tx_pkt;
+	/* Tx packet modification, input packet counter */
+	uint32_t tpm_tx_pkt;
+	/* Tx forwarding input packet counter */
+	uint32_t tfw_in_tx_pkt;
+	/* Tx forwarding input packet counter */
+	uint32_t tfw_out_tx_pkt;
+	/* Rx forwarding input packet counter */
+	uint32_t rfw_in_rx_pkt;
+	/* Rx Forwarding, packet with VLAN command drop indication */
+	uint32_t rfw_in_vlan_drop;
+	/* Rx Forwarding, packets with parse drop indication */
+	uint32_t rfw_in_parse_drop;
+	/* Rx Forwarding, multicast packets */
+	uint32_t rfw_in_mc;
+	/* Rx Forwarding, broadcast packets */
+	uint32_t rfw_in_bc;
+	/* Rx Forwarding, tagged packets */
+	uint32_t rfw_in_vlan_exist;
+	/* Rx Forwarding, untagged packets */
+	uint32_t rfw_in_vlan_nexist;
+	/* Rx Forwarding, packets with MAC address drop indication (from the MAC address table) */
+	uint32_t rfw_in_mac_drop;
+	/* Rx Forwarding, packets with undetected MAC address */
+	uint32_t rfw_in_mac_ndet_drop;
+	/* Rx Forwarding, packets with drop indication from the control table */
+	uint32_t rfw_in_ctrl_drop;
+	/* Rx Forwarding, packets with L3_protocol_index drop indication */
+	uint32_t rfw_in_prot_i_drop;
+	/* EEE, number of times the system went into EEE state */
+	uint32_t eee_in;
+};
+
+/**
+ * get ec statistics
+ * @param adapter pointer to the private structure.
+ * @param stats pointer to structure that will be filled with statistics.
+ *
+ * @return return 0 on success. otherwise on failure.
+ */
+int al_eth_ec_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_ec_stats *stats);
+
+struct al_eth_ec_stat_udma{
+	/* Rx forwarding output packet counter */
+	uint32_t rfw_out_rx_pkt;
+	/* Rx forwarding output drop packet counter */
+	uint32_t rfw_out_drop;
+	/* Multi-stream write, number of Rx packets */
+	uint32_t msw_in_rx_pkt;
+	/* Multi-stream write, number of dropped packets at SOP,  Q full indication */
+	uint32_t msw_drop_q_full;
+	/* Multi-stream write, number of dropped packets at SOP */
+	uint32_t msw_drop_sop;
+	/* Multi-stream write, number of dropped packets at EOP, */
+	/*EOP was written with error indication (not all packet data was written) */
+	uint32_t msw_drop_eop;
+	/* Multi-stream write, number of packets written to the stream FIFO with EOP and without packet loss */
+	uint32_t msw_wr_eop;
+	/* Multi-stream write, number of packets read from the FIFO into the stream */
+	uint32_t msw_out_rx_pkt;
+	/* Number of transmitted packets without TSO enabled */
+	uint32_t tso_no_tso_pkt;
+	/* Number of transmitted packets with TSO enabled */
+	uint32_t tso_tso_pkt;
+	/* Number of TSO segments that were generated */
+	uint32_t tso_seg_pkt;
+	/* Number of TSO segments that required padding */
+	uint32_t tso_pad_pkt;
+	/* Tx Packet modification, MAC SA spoof error */
+	uint32_t tpm_tx_spoof;
+	/* Tx MAC interface, input packet counter */
+	uint32_t tmi_in_tx_pkt;
+	/* Tx MAC interface, number of packets forwarded to the MAC */
+	uint32_t tmi_out_to_mac;
+	/* Tx MAC interface, number of packets forwarded to the Rx data path */
+	uint32_t tmi_out_to_rx;
+	/* Tx MAC interface, number of transmitted bytes */
+	uint32_t tx_q0_bytes;
+	/* Tx MAC interface, number of transmitted bytes */
+	uint32_t tx_q1_bytes;
+	/* Tx MAC interface, number of transmitted bytes */
+	uint32_t tx_q2_bytes;
+	/* Tx MAC interface, number of transmitted bytes */
+	uint32_t tx_q3_bytes;
+	/* Tx MAC interface, number of transmitted packets */
+	uint32_t tx_q0_pkts;
+	/* Tx MAC interface, number of transmitted packets */
+	uint32_t tx_q1_pkts;
+	/* Tx MAC interface, number of transmitted packets */
+	uint32_t tx_q2_pkts;
+	/* Tx MAC interface, number of transmitted packets */
+	uint32_t tx_q3_pkts;
+};
+
+/**
+ * get per_udma statistics
+ * @param adapter pointer to the private structure.
+ * @param idx udma_id value
+ * @param stats pointer to structure that will be filled with statistics.
+ *
+ * @return return 0 on success. otherwise on failure.
+ */
+int al_eth_ec_stat_udma_get(struct al_hal_eth_adapter *adapter, uint8_t idx, struct al_eth_ec_stat_udma *stats);
+
+/* trafic control */
+
+/**
+ * perform Function Level Reset RMN
+ *
+ * Addressing RMN: 714
+ *
+ * @param pci_read_config_u32 pointer to function that reads register from pci header
+ * @param pci_write_config_u32 pointer to function that writes register from pci header
+ * @param handle pointer passes to the above functions as first parameter
+ * @param mac_base base address of the MAC registers
+ *
+ * @return 0.
+ */
+int al_eth_flr_rmn(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val),
+		   int (* pci_write_config_u32)(void *handle, int where, uint32_t val),
+		   void *handle,
+		   void __iomem	*mac_base);
+
+/**
+ * perform Function Level Reset RMN but restore registers that contain board specific data
+ *
+ * the data that save and restored is the board params and mac addresses
+ *
+ * @param pci_read_config_u32 pointer to function that reads register from pci header
+ * @param pci_write_config_u32 pointer to function that writes register from pci header
+ * @param handle pointer passes to the above functions as first parameter
+ * @param mac_base base address of the MAC registers
+ * @param ec_base base address of the Ethernet Controller registers
+ * @param mac_addresses_num number of mac addresses to restore
+ *
+ * @return 0.
+ */
+int al_eth_flr_rmn_restore_params(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val),
+		int (* pci_write_config_u32)(void *handle, int where, uint32_t val),
+		void *handle,
+		void __iomem	*mac_base,
+		void __iomem	*ec_base,
+		int	mac_addresses_num);
+
+/* board specific information (media type, phy address, etc.. */
+
+
+enum al_eth_board_media_type {
+	AL_ETH_BOARD_MEDIA_TYPE_AUTO_DETECT		= 0,
+	AL_ETH_BOARD_MEDIA_TYPE_RGMII			= 1,
+	AL_ETH_BOARD_MEDIA_TYPE_10GBASE_SR		= 2,
+	AL_ETH_BOARD_MEDIA_TYPE_SGMII			= 3,
+	AL_ETH_BOARD_MEDIA_TYPE_1000BASE_X		= 4,
+	AL_ETH_BOARD_MEDIA_TYPE_AUTO_DETECT_AUTO_SPEED	= 5,
+	AL_ETH_BOARD_MEDIA_TYPE_SGMII_2_5G		= 6,
+	AL_ETH_BOARD_MEDIA_TYPE_NBASE_T			= 7,
+};
+
+enum al_eth_board_mdio_freq {
+	AL_ETH_BOARD_MDIO_FREQ_2_5_MHZ	= 0,
+	AL_ETH_BOARD_MDIO_FREQ_1_MHZ	= 1,
+};
+
+enum al_eth_board_ext_phy_if {
+	AL_ETH_BOARD_PHY_IF_MDIO	= 0,
+	AL_ETH_BOARD_PHY_IF_XMDIO	= 1,
+	AL_ETH_BOARD_PHY_IF_I2C		= 2,
+
+};
+
+enum al_eth_board_auto_neg_mode {
+	AL_ETH_BOARD_AUTONEG_OUT_OF_BAND	= 0,
+	AL_ETH_BOARD_AUTONEG_IN_BAND		= 1,
+
+};
+
+/* declare the 1G mac active speed when auto negotiation disabled */
+enum al_eth_board_1g_speed {
+	AL_ETH_BOARD_1G_SPEED_1000M		= 0,
+	AL_ETH_BOARD_1G_SPEED_100M		= 1,
+	AL_ETH_BOARD_1G_SPEED_10M		= 2,
+};
+
+enum al_eth_retimer_channel {
+	AL_ETH_RETIMER_CHANNEL_A		= 0,
+	AL_ETH_RETIMER_CHANNEL_B		= 1,
+	AL_ETH_RETIMER_CHANNEL_C		= 2,
+	AL_ETH_RETIMER_CHANNEL_D		= 3,
+	AL_ETH_RETIMER_CHANNEL_MAX		= 4
+};
+
+/* list of supported retimers */
+enum al_eth_retimer_type {
+	AL_ETH_RETIMER_BR_210			= 0,
+	AL_ETH_RETIMER_BR_410			= 1,
+
+	AL_ETH_RETIMER_TYPE_MAX			= 4,
+};
+
+/** structure represents the board information. this info set by boot loader
+ * and read by OS driver.
+ */
+struct al_eth_board_params {
+	enum al_eth_board_media_type	media_type;
+	al_bool		phy_exist; /**< external phy exist */
+	uint8_t		phy_mdio_addr; /**< mdio address of external phy */
+	al_bool		sfp_plus_module_exist; /**< SFP+ module connected */
+	al_bool		autoneg_enable; /**< enable Auto-Negotiation */
+	al_bool		kr_lt_enable; /**< enable KR Link-Training */
+	al_bool		kr_fec_enable; /**< enable KR FEC */
+	enum al_eth_board_mdio_freq	mdio_freq; /**< MDIO frequency */
+	uint8_t		i2c_adapter_id; /**< identifier for the i2c adapter to use to access SFP+ module */
+	enum al_eth_board_ext_phy_if	phy_if; /**< phy interface */
+	enum al_eth_board_auto_neg_mode	an_mode; /**< auto-negotiation mode (in-band / out-of-band) */
+	uint8_t		serdes_grp; /**< serdes's group id */
+	uint8_t		serdes_lane; /**< serdes's lane id */
+	enum al_eth_ref_clk_freq	ref_clk_freq; /**< reference clock frequency */
+	al_bool		dont_override_serdes; /**< prevent override serdes parameters */
+	al_bool		force_1000_base_x; /**< set mac to 1000 base-x mode (instead sgmii) */
+	al_bool		an_disable; /**< disable auto negotiation */
+	enum al_eth_board_1g_speed	speed; /**< port speed if AN disabled */
+	al_bool		half_duplex; /**< force half duplex if AN disabled */
+	al_bool		fc_disable; /**< disable flow control */
+	al_bool		retimer_exist; /**< retimer is exist on the board */
+	uint8_t		retimer_bus_id; /**< in what i2c bus the retimer is on */
+	uint8_t		retimer_i2c_addr; /**< i2c address of the retimer */
+	enum al_eth_retimer_channel retimer_channel; /**< what channel connected to this port */
+	al_bool		dac; /**< assume direct attached cable is connected if auto detect is off or failed */
+	uint8_t		dac_len; /**< assume this cable length if auto detect is off or failed  */
+	enum al_eth_retimer_type retimer_type; /**< the type of the specific retimer */
+};
+
+/**
+ * set board parameter of the eth port
+ * this function used to set the board parameters into scratchpad
+ * registers. those paramters can be read later by OS driver.
+ *
+ * @param mac_base the virtual address of the mac registers (PCI BAR 2)
+ * @param params pointer to structure the includes the paramters
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_board_params_set(void * __iomem mac_base, struct al_eth_board_params *params);
+
+/**
+ * get board parameter of the eth port
+ * this function used to get the board parameters from scratchpad
+ * registers.
+ *
+ * @param mac_base the virtual address of the mac registers (PCI BAR 2)
+ * @param params pointer to structure where the parameters will be stored.
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_board_params_get(void * __iomem mac_base, struct al_eth_board_params *params);
+
+/*
+ * Wake-On-Lan (WoL)
+ *
+ * The following few functions configure the Wake-On-Lan packet detection
+ * inside the Integrated Ethernet MAC.
+ *
+ * There are other alternative ways to set WoL, such using the
+ * external 1000Base-T transceiver to set WoL mode.
+ *
+ * These APIs do not set the system-wide power-state, nor responsible on the
+ * transition from Sleep to Normal power state.
+ *
+ * For system level considerations, please refer to Annapurna Labs Alpine Wiki.
+ */
+/* Interrupt enable WoL MAC DA Unicast detected  packet */
+#define AL_ETH_WOL_INT_UNICAST		AL_BIT(0)
+/* Interrupt enable WoL L2 Multicast detected  packet */
+#define AL_ETH_WOL_INT_MULTICAST	AL_BIT(1)
+/* Interrupt enable WoL L2 Broadcast detected  packet */
+#define AL_ETH_WOL_INT_BROADCAST	AL_BIT(2)
+/* Interrupt enable WoL IPv4 detected  packet */
+#define AL_ETH_WOL_INT_IPV4		AL_BIT(3)
+/* Interrupt enable WoL IPv6 detected  packet */
+#define AL_ETH_WOL_INT_IPV6		AL_BIT(4)
+/* Interrupt enable WoL EtherType+MAC DA detected  packet */
+#define AL_ETH_WOL_INT_ETHERTYPE_DA	AL_BIT(5)
+/* Interrupt enable WoL EtherType+L2 Broadcast detected  packet */
+#define AL_ETH_WOL_INT_ETHERTYPE_BC	AL_BIT(6)
+/* Interrupt enable WoL parser detected  packet */
+#define AL_ETH_WOL_INT_PARSER		AL_BIT(7)
+/* Interrupt enable WoL magic detected  packet */
+#define AL_ETH_WOL_INT_MAGIC		AL_BIT(8)
+/* Interrupt enable WoL magic+password detected  packet */
+#define AL_ETH_WOL_INT_MAGIC_PSWD	AL_BIT(9)
+
+/* Forward enable WoL MAC DA Unicast detected  packet */
+#define AL_ETH_WOL_FWRD_UNICAST		AL_BIT(0)
+/* Forward enable WoL L2 Multicast detected  packet */
+#define AL_ETH_WOL_FWRD_MULTICAST	AL_BIT(1)
+/* Forward enable WoL L2 Broadcast detected  packet */
+#define AL_ETH_WOL_FWRD_BROADCAST	AL_BIT(2)
+/* Forward enable WoL IPv4 detected  packet */
+#define AL_ETH_WOL_FWRD_IPV4		AL_BIT(3)
+/* Forward enable WoL IPv6 detected  packet */
+#define AL_ETH_WOL_FWRD_IPV6		AL_BIT(4)
+/* Forward enable WoL EtherType+MAC DA detected  packet */
+#define AL_ETH_WOL_FWRD_ETHERTYPE_DA	AL_BIT(5)
+/* Forward enable WoL EtherType+L2 Broadcast detected  packet */
+#define AL_ETH_WOL_FWRD_ETHERTYPE_BC	AL_BIT(6)
+/* Forward enable WoL parser detected  packet */
+#define AL_ETH_WOL_FWRD_PARSER		AL_BIT(7)
+
+struct al_eth_wol_params {
+	uint8_t *dest_addr; /**< 6 bytes array of destanation address for
+				 magic packet detection */
+	uint8_t *pswd; /**< 6 bytes array of the password to use */
+	uint8_t *ipv4; /**< 4 bytes array of the ipv4 to use.
+			    example: for ip = 192.168.1.2
+			       ipv4[0]=2, ipv4[1]=1, ipv4[2]=168, ipv4[3]=192 */
+	uint8_t *ipv6; /** 16 bytes array of the ipv6 to use.
+			   example: ip = 2607:f0d0:1002:0051:0000:0000:5231:1234
+			       ipv6[0]=34, ipv6[1]=12, ipv6[2]=31 .. */
+	uint16_t ethr_type1; /**< first ethertype to use */
+	uint16_t ethr_type2; /**< secound ethertype to use */
+	uint16_t forward_mask; /**< bitmask of AL_ETH_WOL_FWRD_* of the packet
+				    types needed to be forward. */
+	uint16_t int_mask; /**< bitmask of AL_ETH_WOL_INT_* of the packet types
+				that will send interrupt to wake the system. */
+};
+
+/**
+ * enable the wol mechanism
+ * set what type of packets will wake up the system and what type of packets
+ * neet to forward after the system is up
+ *
+ * beside this function wol filter also need to be set by
+ * calling al_eth_filter_config with AL_ETH_RFW_FILTER_WOL
+ *
+ * @param adapter pointer to the private structure
+ * @param wol the parameters needed to configure the wol
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_wol_enable(
+		struct al_hal_eth_adapter *adapter,
+		struct al_eth_wol_params *wol);
+
+/**
+ * Disable the WoL mechnism.
+ *
+ * @param adapter pointer to the private structure
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_wol_disable(
+		struct al_hal_eth_adapter *adapter);
+
+/**
+ * Configure tx fwd vlan table entry
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index within the vlan table. The HW uses the vlan id
+ * field of the packet when accessing this table.
+ * @param udma_mask vlan table value that indicates that the packet should be forward back to
+ * the udmas, through the Rx path (udma_mask is one-hot representation)
+ * @param fwd_to_mac vlan table value that indicates that the packet should be forward to mac
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_tx_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, al_bool fwd_to_mac);
+
+/** Tx Generic protocol detect Cam compare table entry  */
+struct al_eth_tx_gpd_cam_entry {
+	enum AL_ETH_PROTO_ID l3_proto_idx;
+	enum AL_ETH_PROTO_ID l4_proto_idx;
+	enum AL_ETH_TX_TUNNEL_MODE tunnel_control;
+	uint8_t source_vlan_count:2;
+	uint8_t tx_gpd_cam_ctrl:1;
+	uint8_t l3_proto_idx_mask:5;
+	uint8_t l4_proto_idx_mask:5;
+	uint8_t tunnel_control_mask:3;
+	uint8_t source_vlan_count_mask:2;
+};
+
+/** Rx Generic protocol detect Cam compare table entry  */
+struct al_eth_rx_gpd_cam_entry {
+	enum AL_ETH_PROTO_ID outer_l3_proto_idx;
+	enum AL_ETH_PROTO_ID outer_l4_proto_idx;
+	enum AL_ETH_PROTO_ID inner_l3_proto_idx;
+	enum AL_ETH_PROTO_ID inner_l4_proto_idx;
+	uint8_t parse_ctrl;
+	uint8_t outer_l3_len;
+	uint8_t l3_priority;
+	uint8_t l4_dst_port_lsb;
+	uint8_t rx_gpd_cam_ctrl:1;
+	uint8_t outer_l3_proto_idx_mask:5;
+	uint8_t outer_l4_proto_idx_mask:5;
+	uint8_t inner_l3_proto_idx_mask:5;
+	uint8_t inner_l4_proto_idx_mask:5;
+	uint8_t parse_ctrl_mask;
+	uint8_t outer_l3_len_mask;
+	uint8_t l3_priority_mask;
+	uint8_t l4_dst_port_lsb_mask;
+};
+
+enum AL_ETH_TX_GCP_ALU_OPSEL {
+	AL_ETH_TX_GCP_ALU_L3_OFFSET			= 0,
+	AL_ETH_TX_GCP_ALU_OUTER_L3_OFFSET		= 1,
+	AL_ETH_TX_GCP_ALU_L3_LEN			= 2,
+	AL_ETH_TX_GCP_ALU_OUTER_L3_LEN			= 3,
+	AL_ETH_TX_GCP_ALU_L4_OFFSET			= 4,
+	AL_ETH_TX_GCP_ALU_L4_LEN			= 5,
+	AL_ETH_TX_GCP_ALU_TABLE_VAL			= 10
+};
+
+enum AL_ETH_RX_GCP_ALU_OPSEL {
+	AL_ETH_RX_GCP_ALU_OUTER_L3_OFFSET		= 0,
+	AL_ETH_RX_GCP_ALU_INNER_L3_OFFSET		= 1,
+	AL_ETH_RX_GCP_ALU_OUTER_L4_OFFSET		= 2,
+	AL_ETH_RX_GCP_ALU_INNER_L4_OFFSET		= 3,
+	AL_ETH_RX_GCP_ALU_OUTER_L3_HDR_LEN_LAT		= 4,
+	AL_ETH_RX_GCP_ALU_INNER_L3_HDR_LEN_LAT		= 5,
+	AL_ETH_RX_GCP_ALU_OUTER_L3_HDR_LEN_SEL		= 6,
+	AL_ETH_RX_GCP_ALU_INNER_L3_HDR_LEN_SEL		= 7,
+	AL_ETH_RX_GCP_ALU_PARSE_RESULT_VECTOR_OFFSET_1	= 8,
+	AL_ETH_RX_GCP_ALU_PARSE_RESULT_VECTOR_OFFSET_2	= 9,
+	AL_ETH_RX_GCP_ALU_TABLE_VAL			= 10
+};
+
+/** Tx Generic crc prameters table entry  */
+
+struct al_eth_tx_gcp_table_entry {
+	uint8_t poly_sel:1;
+	uint8_t crc32_bit_comp:1;
+	uint8_t crc32_bit_swap:1;
+	uint8_t crc32_byte_swap:1;
+	uint8_t data_bit_swap:1;
+	uint8_t data_byte_swap:1;
+	uint8_t trail_size:4;
+	uint8_t head_size:8;
+	uint8_t head_calc:1;
+	uint8_t mask_polarity:1;
+	enum AL_ETH_ALU_OPCODE tx_alu_opcode_1;
+	enum AL_ETH_ALU_OPCODE tx_alu_opcode_2;
+	enum AL_ETH_ALU_OPCODE tx_alu_opcode_3;
+	enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_1;
+	enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_2;
+	enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_3;
+	enum AL_ETH_TX_GCP_ALU_OPSEL tx_alu_opsel_4;
+	uint32_t gcp_mask[6];
+	uint32_t crc_init;
+	uint8_t gcp_table_res:7;
+	uint16_t alu_val:9;
+};
+
+/** Rx Generic crc prameters table entry  */
+
+struct al_eth_rx_gcp_table_entry {
+	uint8_t poly_sel:1;
+	uint8_t crc32_bit_comp:1;
+	uint8_t crc32_bit_swap:1;
+	uint8_t crc32_byte_swap:1;
+	uint8_t data_bit_swap:1;
+	uint8_t data_byte_swap:1;
+	uint8_t trail_size:4;
+	uint8_t head_size:8;
+	uint8_t head_calc:1;
+	uint8_t mask_polarity:1;
+	enum AL_ETH_ALU_OPCODE rx_alu_opcode_1;
+	enum AL_ETH_ALU_OPCODE rx_alu_opcode_2;
+	enum AL_ETH_ALU_OPCODE rx_alu_opcode_3;
+	enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_1;
+	enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_2;
+	enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_3;
+	enum AL_ETH_RX_GCP_ALU_OPSEL rx_alu_opsel_4;
+	uint32_t gcp_mask[6];
+	uint32_t crc_init;
+	uint32_t gcp_table_res:27;
+	uint16_t alu_val:9;
+};
+
+/** Tx per_protocol_number crc & l3_checksum & l4_checksum command table entry  */
+
+struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry {
+        al_bool crc_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */
+        al_bool crc_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */
+        al_bool crc_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */
+        al_bool crc_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */
+        al_bool l4_csum_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */
+        al_bool l4_csum_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */
+        al_bool l4_csum_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */
+        al_bool l4_csum_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */
+        al_bool l3_csum_en_00; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 0 */
+        al_bool l3_csum_en_01; /*from Tx_buffer_descriptor: enable_l4_checksum is 0 ,enable_l3_checksum is 1 */
+        al_bool l3_csum_en_10; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 0 */
+        al_bool l3_csum_en_11; /*from Tx_buffer_descriptor: enable_l4_checksum is 1 ,enable_l3_checksum is 1 */
+};
+
+/**
+ * Configure tx_gpd_entry
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index
+ * @param tx_gpd_entry entry data for the Tx protocol detect Cam compare table
+ *
+ * @return 0 on success. otherwise on failure.
+ *
+ */
+int al_eth_tx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_tx_gpd_cam_entry *tx_gpd_entry);
+
+/**
+ * Configure tx_gcp_entry
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index
+ * @param tx_gcp_entry entry data for the Tx Generic crc prameters table
+ *
+ * @return 0 on success. otherwise on failure.
+ *
+ */
+int al_eth_tx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_tx_gcp_table_entry *tx_gcp_entry);
+
+/**
+ * Configure tx_crc_chksum_replace_cmd_entry
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index
+ * @param tx_replace_entry entry data for the Tx crc_&_l3_checksum_&_l4_checksum replace command table
+ *
+ * @return 0 on success. otherwise on failure.
+ *
+ */
+int al_eth_tx_crc_chksum_replace_cmd_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry *tx_replace_entry);
+
+/**
+ * Configure rx_gpd_entry
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index
+ * @param rx_gpd_entry entry data for the Tx protocol detect Cam compare table
+ *
+ * @return 0 on success. otherwise on failure.
+ *
+ */
+int al_eth_rx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_rx_gpd_cam_entry *rx_gpd_entry);
+
+/**
+ * Configure rx_gcp_entry
+ *
+ * @param adapter pointer to the private structure
+ * @param idx the entry index
+ * @param rx_gpd_entry entry data for the Tx protocol detect Cam compare table
+ * @param rx_gcp_entry entry data for the Tx Generic crc prameters table
+ *
+ * @return 0 on success. otherwise on failure.
+ *
+ */
+int al_eth_rx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_rx_gcp_table_entry *rx_gcp_entry);
+
+/**
+ * Configure tx_gpd_table and regs
+ *
+ * @param adapter pointer to the private structure
+ *
+ */
+int al_eth_tx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter);
+
+/**
+ * Configure crc_chksum_replace_cmd_table
+ *
+ * @param adapter pointer to the private structure
+ *
+ */
+int al_eth_tx_crc_chksum_replace_cmd_init(struct al_hal_eth_adapter *adapter);
+
+/**
+ * Configure tx_gcp_table and regs
+ *
+ * @param adapter pointer to the private structure
+ *
+ */
+int al_eth_tx_generic_crc_table_init(struct al_hal_eth_adapter *adapter);
+
+/**
+ * Configure rx_gpd_table and regs
+ *
+ * @param adapter pointer to the private structure
+ *
+ */
+int al_eth_rx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter);
+
+/**
+ * Configure rx_gcp_table and regs
+ *
+ * @param adapter pointer to the private structure
+ *
+ */
+int al_eth_rx_generic_crc_table_init(struct al_hal_eth_adapter *adapter);
+
+#ifdef __cplusplus
+}
+#endif
+/* *INDENT-ON* */
+#endif		/* __AL_HAL_ETH_H__ */
+/** @} end of Ethernet group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_eth_alu.h b/sys/contrib/alpine-hal/eth/al_hal_eth_alu.h
new file mode 100644
index 000000000000..2f5f1fa2301e
--- /dev/null
+++ b/sys/contrib/alpine-hal/eth/al_hal_eth_alu.h
@@ -0,0 +1,95 @@
+/*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+*     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+*     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ * @defgroup group_eth_alu_api API
+ * Ethernet Controller generic ALU API
+ * @ingroup group_eth
+ * @{
+ * @file   al_hal_eth_alu.h
+ *
+ * @brief Header file for control parameters for the generic ALU unit in the Ethernet Datapath for Advanced Ethernet port.
+ *
+ */
+
+#ifndef __AL_HAL_ETH_ALU_H__
+#define __AL_HAL_ETH_ALU_H__
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+enum AL_ETH_ALU_OPCODE
+{
+	AL_ALU_FWD_A                            = 0,
+	AL_ALU_ARITHMETIC_ADD                   = 1,
+	AL_ALU_ARITHMETIC_SUBTRACT              = 2,
+	AL_ALU_BITWISE_AND                      = 3,
+	AL_ALU_BITWISE_OR                       = 4,
+	AL_ALU_SHIFT_RIGHT_A_BY_B               = 5,
+	AL_ALU_SHIFT_LEFT_A_BY_B                = 6,
+	AL_ALU_BITWISE_XOR                      = 7,
+	AL_ALU_FWD_INV_A                        = 16,
+	AL_ALU_ARITHMETIC_ADD_INV_A_AND_B       = 17,
+	AL_ALU_ARITHMETIC_SUBTRACT_INV_A_AND_B  = 18,
+	AL_ALU_BITWISE_AND_INV_A_AND_B          = 19,
+	AL_ALU_BITWISE_OR_INV_A_AND_B           = 20,
+	AL_ALU_SHIFT_RIGHT_INV_A_BY_B           = 21,
+	AL_ALU_SHIFT_LEFT_INV_A_BY_B            = 22,
+	AL_ALU_BITWISE_XOR_INV_A_AND_B          = 23,
+	AL_ALU_ARITHMETIC_ADD_A_AND_INV_B       = 33,
+	AL_ALU_ARITHMETIC_SUBTRACT_A_AND_INV_B  = 34,
+	AL_ALU_BITWISE_AND_A_AND_INV_B          = 35,
+	AL_ALU_BITWISE_OR_A_AND_INV_B           = 36,
+	AL_ALU_SHIFT_RIGHT_A_BY_INV_B           = 37,
+	AL_ALU_SHIFT_LEFT_A_BY_INV_B            = 38,
+	AL_ALU_BITWISE_XOR_A_AND_INV_B          = 39,
+	AL_ALU_ARITHMETIC_ADD_INV_A_AND_INV_B   = 49,
+	AL_ALU_ARITHMETIC_SUBTRACT_INV_A_AND    = 50,
+	AL_ALU_BITWISE_AND_INV_A_AND_INV_B      = 51,
+	AL_ALU_BITWISE_OR_INV_A_AND_INV_B       = 52,
+	AL_ALU_SHIFT_RIGHT_INV_A_BY_INV_B       = 53,
+	AL_ALU_SHIFT_LEFT_INV_A_BY_INV_B        = 54,
+	AL_ALU_BITWISE_XOR_INV_A_AND_INV_B      = 55
+};
+
+#ifdef __cplusplus
+}
+#endif
+/* *INDENT-ON* */
+#endif /* __AL_HAL_ETH_ALU_H__ */
+/** @} end of Ethernet group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_eth_ec_regs.h b/sys/contrib/alpine-hal/eth/al_hal_eth_ec_regs.h
new file mode 100644
index 000000000000..153e0d57a452
--- /dev/null
+++ b/sys/contrib/alpine-hal/eth/al_hal_eth_ec_regs.h
@@ -0,0 +1,3362 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ *  @{
+ * @file   al_hal_eth_ec_regs.h
+ *
+ * @brief Ethernet controller registers
+ *
+ */
+
+#ifndef __AL_HAL_EC_REG_H
+#define __AL_HAL_EC_REG_H
+
+#include "al_hal_plat_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+
+
+struct al_ec_gen {
+	/* [0x0] Ethernet controller Version */
+	uint32_t version;
+	/* [0x4] Enable modules operation. */
+	uint32_t en;
+	/* [0x8] Enable FIFO operation on the EC side. */
+	uint32_t fifo_en;
+	/* [0xc] General L2 configuration for the Ethernet controlle ... */
+	uint32_t l2;
+	/* [0x10] Configure protocol index values */
+	uint32_t cfg_i;
+	/* [0x14] Configure protocol index values (extended protocols ... */
+	uint32_t cfg_i_ext;
+	/* [0x18] Enable modules operation (extended operations). */
+	uint32_t en_ext;
+	uint32_t rsrvd[9];
+};
+struct al_ec_mac {
+	/* [0x0] General configuration of the MAC side of the Ethern ... */
+	uint32_t gen;
+	/* [0x4] Minimum packet size  */
+	uint32_t min_pkt;
+	/* [0x8] Maximum packet size  */
+	uint32_t max_pkt;
+	uint32_t rsrvd[13];
+};
+struct al_ec_rxf {
+	/* [0x0] Rx FIFO input controller configuration 1 */
+	uint32_t cfg_1;
+	/* [0x4] Rx FIFO input controller configuration 2 */
+	uint32_t cfg_2;
+	/* [0x8] Threshold to start reading packet from the Rx FIFO */
+	uint32_t rd_fifo;
+	/* [0xc] Threshold to stop writing packet to the Rx FIFO */
+	uint32_t wr_fifo;
+	/* [0x10] Threshold to stop writing packet to the loopback FI ... */
+	uint32_t lb_fifo;
+	/* [0x14] Rx FIFO input controller loopback FIFO configuratio ... */
+	uint32_t cfg_lb;
+	/* [0x18] Configuration for dropping packet at the FIFO outpu ... */
+	uint32_t out_drop;
+	uint32_t rsrvd[25];
+};
+struct al_ec_epe {
+	/* [0x0] Ethernet parsing engine configuration 1 */
+	uint32_t parse_cfg;
+	/* [0x4] Protocol index action table address */
+	uint32_t act_table_addr;
+	/* [0x8] Protocol index action table data */
+	uint32_t act_table_data_1;
+	/* [0xc] Protocol index action table data */
+	uint32_t act_table_data_2;
+	/* [0x10] Protocol index action table data */
+	uint32_t act_table_data_3;
+	/* [0x14] Protocol index action table data */
+	uint32_t act_table_data_4;
+	/* [0x18] Protocol index action table data */
+	uint32_t act_table_data_5;
+	/* [0x1c] Protocol index action table data */
+	uint32_t act_table_data_6;
+	/* [0x20] Input result vector, default values for parser inpu ... */
+	uint32_t res_def;
+	/* [0x24] Result input vector selection */
+	uint32_t res_in;
+	uint32_t rsrvd[6];
+};
+struct al_ec_epe_res {
+	/* [0x0] Parser result vector pointer */
+	uint32_t p1;
+	/* [0x4] Parser result vector pointer */
+	uint32_t p2;
+	/* [0x8] Parser result vector pointer */
+	uint32_t p3;
+	/* [0xc] Parser result vector pointer */
+	uint32_t p4;
+	/* [0x10] Parser result vector pointer */
+	uint32_t p5;
+	/* [0x14] Parser result vector pointer */
+	uint32_t p6;
+	/* [0x18] Parser result vector pointer */
+	uint32_t p7;
+	/* [0x1c] Parser result vector pointer */
+	uint32_t p8;
+	/* [0x20] Parser result vector pointer */
+	uint32_t p9;
+	/* [0x24] Parser result vector pointer */
+	uint32_t p10;
+	/* [0x28] Parser result vector pointer */
+	uint32_t p11;
+	/* [0x2c] Parser result vector pointer */
+	uint32_t p12;
+	/* [0x30] Parser result vector pointer */
+	uint32_t p13;
+	/* [0x34] Parser result vector pointer */
+	uint32_t p14;
+	/* [0x38] Parser result vector pointer */
+	uint32_t p15;
+	/* [0x3c] Parser result vector pointer */
+	uint32_t p16;
+	/* [0x40] Parser result vector pointer */
+	uint32_t p17;
+	/* [0x44] Parser result vector pointer */
+	uint32_t p18;
+	/* [0x48] Parser result vector pointer */
+	uint32_t p19;
+	/* [0x4c] Parser result vector pointer */
+	uint32_t p20;
+	uint32_t rsrvd[12];
+};
+struct al_ec_epe_h {
+	/* [0x0] Header length, support for header length table for  ... */
+	uint32_t hdr_len;
+};
+struct al_ec_epe_p {
+	/* [0x0] Data  for comparison */
+	uint32_t comp_data;
+	/* [0x4] Mask for comparison */
+	uint32_t comp_mask;
+	/* [0x8] Compare control */
+	uint32_t comp_ctrl;
+	uint32_t rsrvd[4];
+};
+struct al_ec_epe_a {
+	/* [0x0] Protocol index action register */
+	uint32_t prot_act;
+};
+struct al_ec_rfw {
+	/* [0x0] Tuple (4/2) Hash configuration */
+	uint32_t thash_cfg_1;
+	/* [0x4] Tuple (4/2) Hash configuration */
+	uint32_t thash_cfg_2;
+	/* [0x8] MAC Hash configuration */
+	uint32_t mhash_cfg_1;
+	/* [0xc] MAC Hash configuration */
+	uint32_t mhash_cfg_2;
+	/* [0x10] MAC Hash configuration */
+	uint32_t hdr_split;
+	/* [0x14] Masking the errors described in  register rxf_drop  ... */
+	uint32_t meta_err;
+	/* [0x18] Configuration for generating the MetaData for the R ... */
+	uint32_t meta;
+	/* [0x1c] Configuration for generating the MetaData for the R ... */
+	uint32_t filter;
+	/* [0x20] 4 tupple hash table address */
+	uint32_t thash_table_addr;
+	/* [0x24] 4 tupple hash table data */
+	uint32_t thash_table_data;
+	/* [0x28] MAC hash table address */
+	uint32_t mhash_table_addr;
+	/* [0x2c] MAC hash table data */
+	uint32_t mhash_table_data;
+	/* [0x30] VLAN table address */
+	uint32_t vid_table_addr;
+	/* [0x34] VLAN table data */
+	uint32_t vid_table_data;
+	/* [0x38] VLAN p-bits table address */
+	uint32_t pbits_table_addr;
+	/* [0x3c] VLAN p-bits table data */
+	uint32_t pbits_table_data;
+	/* [0x40] DSCP table address */
+	uint32_t dscp_table_addr;
+	/* [0x44] DSCP table data */
+	uint32_t dscp_table_data;
+	/* [0x48] TC table address */
+	uint32_t tc_table_addr;
+	/* [0x4c] TC table data */
+	uint32_t tc_table_data;
+	/* [0x50] Control table address */
+	uint32_t ctrl_table_addr;
+	/* [0x54] Control table data */
+	uint32_t ctrl_table_data;
+	/* [0x58] Forwarding output configuration */
+	uint32_t out_cfg;
+	/* [0x5c] Flow steering mechanism,
+Table address */
+	uint32_t fsm_table_addr;
+	/* [0x60] Flow steering mechanism,
+Table data */
+	uint32_t fsm_table_data;
+	/* [0x64] Selection of data to be used in packet forwarding0  ... */
+	uint32_t ctrl_sel;
+	/* [0x68] Default VLAN data, used for untagged packets */
+	uint32_t default_vlan;
+	/* [0x6c] Default HASH output values */
+	uint32_t default_hash;
+	/* [0x70] Default override values, if a packet was filtered b ... */
+	uint32_t default_or;
+	/* [0x74] Latched information when a drop condition occurred */
+	uint32_t drop_latch;
+	/* [0x78] Check sum calculation configuration */
+	uint32_t checksum;
+	/* [0x7c] LRO offload engine configuration register */
+	uint32_t lro_cfg_1;
+	/* [0x80] LRO offload engine Check rules configurations for I ... */
+	uint32_t lro_check_ipv4;
+	/* [0x84] LRO offload engine IPv4 values configuration */
+	uint32_t lro_ipv4;
+	/* [0x88] LRO offload engine Check rules configurations for I ... */
+	uint32_t lro_check_ipv6;
+	/* [0x8c] LRO offload engine IPv6 values configuration */
+	uint32_t lro_ipv6;
+	/* [0x90] LRO offload engine Check rules configurations for T ... */
+	uint32_t lro_check_tcp;
+	/* [0x94] LRO offload engine IPv6 values configuration */
+	uint32_t lro_tcp;
+	/* [0x98] LRO offload engine Check rules configurations for U ... */
+	uint32_t lro_check_udp;
+	/* [0x9c] LRO offload engine Check rules configurations for U ... */
+	uint32_t lro_check_l2;
+	/* [0xa0] LRO offload engine Check rules configurations for U ... */
+	uint32_t lro_check_gen;
+	/* [0xa4] Rules for storing packet information into the cache ... */
+	uint32_t lro_store;
+	/* [0xa8] VLAN table default */
+	uint32_t vid_table_def;
+	/* [0xac] Control table default */
+	uint32_t ctrl_table_def;
+	/* [0xb0] Additional configuration 0 */
+	uint32_t cfg_a_0;
+	/* [0xb4] Tuple (4/2) Hash configuration (extended for RoCE a ... */
+	uint32_t thash_cfg_3;
+	/* [0xb8] Tuple (4/2) Hash configuration , mask for the input ... */
+	uint32_t thash_mask_outer_ipv6;
+	/* [0xbc] Tuple (4/2) Hash configuration , mask for the input ... */
+	uint32_t thash_mask_outer;
+	/* [0xc0] Tuple (4/2) Hash configuration , mask for the input ... */
+	uint32_t thash_mask_inner_ipv6;
+	/* [0xc4] Tuple (4/2) Hash configuration , mask for the input ... */
+	uint32_t thash_mask_inner;
+	uint32_t rsrvd[10];
+};
+struct al_ec_rfw_udma {
+	/* [0x0] Per UDMA default configuration */
+	uint32_t def_cfg;
+};
+struct al_ec_rfw_hash {
+	/* [0x0] key configuration (320 bits) */
+	uint32_t key;
+};
+struct al_ec_rfw_priority {
+	/* [0x0] Priority to queue mapping configuration */
+	uint32_t queue;
+};
+struct al_ec_rfw_default {
+	/* [0x0] Default forwarding configuration options */
+	uint32_t opt_1;
+};
+struct al_ec_fwd_mac {
+	/* [0x0] MAC address data [31:0] */
+	uint32_t data_l;
+	/* [0x4] MAC address data [15:0] */
+	uint32_t data_h;
+	/* [0x8] MAC address mask [31:0] */
+	uint32_t mask_l;
+	/* [0xc] MAC address mask [15:0] */
+	uint32_t mask_h;
+	/* [0x10] MAC compare control */
+	uint32_t ctrl;
+};
+struct al_ec_msw {
+	/* [0x0] Configuration for unicast packets */
+	uint32_t uc;
+	/* [0x4] Configuration for multicast packets */
+	uint32_t mc;
+	/* [0x8] Configuration for broadcast packets */
+	uint32_t bc;
+	uint32_t rsrvd[3];
+};
+struct al_ec_tso {
+	/* [0x0] Input configuration */
+	uint32_t in_cfg;
+	/* [0x4] MetaData default cache table address */
+	uint32_t cache_table_addr;
+	/* [0x8] MetaData default cache table data */
+	uint32_t cache_table_data_1;
+	/* [0xc] MetaData default cache table data */
+	uint32_t cache_table_data_2;
+	/* [0x10] MetaData default cache table data */
+	uint32_t cache_table_data_3;
+	/* [0x14] MetaData default cache table data */
+	uint32_t cache_table_data_4;
+	/* [0x18] TCP control bit operation for first segment */
+	uint32_t ctrl_first;
+	/* [0x1c] TCP control bit operation for middle segments  */
+	uint32_t ctrl_middle;
+	/* [0x20] TCP control bit operation for last segment */
+	uint32_t ctrl_last;
+	/* [0x24] Additional TSO configurations */
+	uint32_t cfg_add_0;
+	/* [0x28] TSO configuration for tunnelled packets */
+	uint32_t cfg_tunnel;
+	uint32_t rsrvd[13];
+};
+struct al_ec_tso_sel {
+	/* [0x0] MSS value */
+	uint32_t mss;
+};
+struct al_ec_tpe {
+	/* [0x0] Parsing configuration */
+	uint32_t parse;
+	uint32_t rsrvd[15];
+};
+struct al_ec_tpm_udma {
+	/* [0x0] Default VLAN data */
+	uint32_t vlan_data;
+	/* [0x4] UDMA MAC SA information for spoofing */
+	uint32_t mac_sa_1;
+	/* [0x8] UDMA MAC SA information for spoofing */
+	uint32_t mac_sa_2;
+};
+struct al_ec_tpm_sel {
+	/* [0x0] Ethertype values for VLAN modification */
+	uint32_t etype;
+};
+struct al_ec_tfw {
+	/* [0x0] Tx FIFO Wr configuration */
+	uint32_t tx_wr_fifo;
+	/* [0x4] VLAN table address */
+	uint32_t tx_vid_table_addr;
+	/* [0x8] VLAN table data */
+	uint32_t tx_vid_table_data;
+	/* [0xc] Tx FIFO Rd configuration */
+	uint32_t tx_rd_fifo;
+	/* [0x10] Tx FIFO Rd configuration, checksum insertion */
+	uint32_t tx_checksum;
+	/* [0x14] Tx forwarding general configuration register */
+	uint32_t tx_gen;
+	/* [0x18] Tx spoofing configuration */
+	uint32_t tx_spf;
+	/* [0x1c] TX data FIFO status */
+	uint32_t data_fifo;
+	/* [0x20] Tx control FIFO status */
+	uint32_t ctrl_fifo;
+	/* [0x24] Tx header FIFO status */
+	uint32_t hdr_fifo;
+	uint32_t rsrvd[14];
+};
+struct al_ec_tfw_udma {
+	/* [0x0] Default GMDA output bitmap for unicast packet */
+	uint32_t uc_udma;
+	/* [0x4] Default GMDA output bitmap for multicast packet */
+	uint32_t mc_udma;
+	/* [0x8] Default GMDA output bitmap for broadcast packet */
+	uint32_t bc_udma;
+	/* [0xc] Tx spoofing configuration */
+	uint32_t spf_cmd;
+	/* [0x10] Forwarding decision control */
+	uint32_t fwd_dec;
+	uint32_t rsrvd;
+};
+struct al_ec_tmi {
+	/* [0x0] Forward packets back to the Rx data path for local  ... */
+	uint32_t tx_cfg;
+	uint32_t rsrvd[3];
+};
+struct al_ec_efc {
+	/* [0x0] Mask of pause_on  [7:0] for the Ethernet controller ... */
+	uint32_t ec_pause;
+	/* [0x4] Mask of Ethernet controller Almost Full indication  ... */
+	uint32_t ec_xoff;
+	/* [0x8] Mask for generating XON indication pulse */
+	uint32_t xon;
+	/* [0xc] Mask for generating GPIO output XOFF indication fro ... */
+	uint32_t gpio;
+	/* [0x10] Rx FIFO threshold for generating the Almost Full in ... */
+	uint32_t rx_fifo_af;
+	/* [0x14] Rx FIFO threshold for generating the Almost Full in ... */
+	uint32_t rx_fifo_hyst;
+	/* [0x18] Rx FIFO threshold for generating the Almost Full in ... */
+	uint32_t stat;
+	/* [0x1c] XOFF timer for the 1G MACSets the interval (in SB_C ... */
+	uint32_t xoff_timer_1g;
+	/* [0x20] PFC force flow control generation */
+	uint32_t ec_pfc;
+	uint32_t rsrvd[3];
+};
+struct al_ec_fc_udma {
+	/* [0x0] Mask of "pause_on"  [0] for all queues */
+	uint32_t q_pause_0;
+	/* [0x4] Mask of "pause_on"  [1] for all queues */
+	uint32_t q_pause_1;
+	/* [0x8] Mask of "pause_on"  [2] for all queues */
+	uint32_t q_pause_2;
+	/* [0xc] Mask of "pause_on"  [3] for all queues */
+	uint32_t q_pause_3;
+	/* [0x10] Mask of "pause_on"  [4] for all queues */
+	uint32_t q_pause_4;
+	/* [0x14] Mask of "pause_on"  [5] for all queues */
+	uint32_t q_pause_5;
+	/* [0x18] Mask of "pause_on"  [6] for all queues */
+	uint32_t q_pause_6;
+	/* [0x1c] Mask of "pause_on"  [7] for all queues */
+	uint32_t q_pause_7;
+	/* [0x20] Mask of external GPIO input pause [0] for all queue ... */
+	uint32_t q_gpio_0;
+	/* [0x24] Mask of external GPIO input pause [1] for all queue ... */
+	uint32_t q_gpio_1;
+	/* [0x28] Mask of external GPIO input pause [2] for all queue ... */
+	uint32_t q_gpio_2;
+	/* [0x2c] Mask of external GPIO input pause [3] for all queue ... */
+	uint32_t q_gpio_3;
+	/* [0x30] Mask of external GPIO input [4] for all queues */
+	uint32_t q_gpio_4;
+	/* [0x34] Mask of external GPIO input [5] for all queues */
+	uint32_t q_gpio_5;
+	/* [0x38] Mask of external GPIO input [6] for all queues */
+	uint32_t q_gpio_6;
+	/* [0x3c] Mask of external GPIO input [7] for all queues */
+	uint32_t q_gpio_7;
+	/* [0x40] Mask of "pause_on"  [7:0] for the UDMA stream inter ... */
+	uint32_t s_pause;
+	/* [0x44] Mask of Rx Almost Full indication for generating XO ... */
+	uint32_t q_xoff_0;
+	/* [0x48] Mask of Rx Almost Full indication for generating XO ... */
+	uint32_t q_xoff_1;
+	/* [0x4c] Mask of Rx Almost Full indication for generating XO ... */
+	uint32_t q_xoff_2;
+	/* [0x50] Mask of Rx Almost Full indication for generating XO ... */
+	uint32_t q_xoff_3;
+	/* [0x54] Mask of Rx Almost Full indication for generating XO ... */
+	uint32_t q_xoff_4;
+	/* [0x58] Mask of Rx Almost Full indication for generating XO ... */
+	uint32_t q_xoff_5;
+	/* [0x5c] Mask of Rx Almost Full indication for generating XO ... */
+	uint32_t q_xoff_6;
+	/* [0x60] Mask of Rx Almost Full indication for generating XO ... */
+	uint32_t q_xoff_7;
+	uint32_t rsrvd[7];
+};
+struct al_ec_tpg_rpa_res {
+	/* [0x0] NOT used */
+	uint32_t not_used;
+	uint32_t rsrvd[63];
+};
+struct al_ec_eee {
+	/* [0x0] EEE configuration */
+	uint32_t cfg_e;
+	/* [0x4] Number of clocks to get into EEE mode. */
+	uint32_t pre_cnt;
+	/* [0x8] Number of clocks to stop MAC EEE mode after getting ... */
+	uint32_t post_cnt;
+	/* [0xc] Number of clocks to stop the Tx MAC interface after ... */
+	uint32_t stop_cnt;
+	/* [0x10] EEE status */
+	uint32_t stat_eee;
+	uint32_t rsrvd[59];
+};
+struct al_ec_stat {
+	/* [0x0] Rx Frequency adjust FIFO input  packets */
+	uint32_t faf_in_rx_pkt;
+	/* [0x4] Rx Frequency adjust FIFO input short error packets */
+	uint32_t faf_in_rx_short;
+	/* [0x8] Rx Frequency adjust FIFO input  long error packets */
+	uint32_t faf_in_rx_long;
+	/* [0xc] Rx Frequency adjust FIFO output  packets */
+	uint32_t faf_out_rx_pkt;
+	/* [0x10] Rx Frequency adjust FIFO output short error packets ... */
+	uint32_t faf_out_rx_short;
+	/* [0x14] Rx Frequency adjust FIFO output long error packets */
+	uint32_t faf_out_rx_long;
+	/* [0x18] Rx Frequency adjust FIFO output  drop packets */
+	uint32_t faf_out_drop;
+	/* [0x1c] Number of packets written into the Rx FIFO (without ... */
+	uint32_t rxf_in_rx_pkt;
+	/* [0x20] Number of error packets written into the Rx FIFO (w ... */
+	uint32_t rxf_in_fifo_err;
+	/* [0x24] Number of packets written into the loopback FIFO (w ... */
+	uint32_t lbf_in_rx_pkt;
+	/* [0x28] Number of error packets written into the loopback F ... */
+	uint32_t lbf_in_fifo_err;
+	/* [0x2c] Number of packets read from Rx FIFO 1 */
+	uint32_t rxf_out_rx_1_pkt;
+	/* [0x30] Number of packets read from Rx FIFO 2 (loopback FIF ... */
+	uint32_t rxf_out_rx_2_pkt;
+	/* [0x34] Rx FIFO output drop packets from FIFO 1 */
+	uint32_t rxf_out_drop_1_pkt;
+	/* [0x38] Rx FIFO output drop packets from FIFO 2 (loopback) */
+	uint32_t rxf_out_drop_2_pkt;
+	/* [0x3c] Rx Parser 1, input packet counter */
+	uint32_t rpe_1_in_rx_pkt;
+	/* [0x40] Rx Parser 1, output packet counter */
+	uint32_t rpe_1_out_rx_pkt;
+	/* [0x44] Rx Parser 2, input packet counter */
+	uint32_t rpe_2_in_rx_pkt;
+	/* [0x48] Rx Parser 2, output packet counter */
+	uint32_t rpe_2_out_rx_pkt;
+	/* [0x4c] Rx Parser 3 (MACsec), input packet counter */
+	uint32_t rpe_3_in_rx_pkt;
+	/* [0x50] Rx Parser 3 (MACsec), output packet counter */
+	uint32_t rpe_3_out_rx_pkt;
+	/* [0x54] Tx parser, input packet counter */
+	uint32_t tpe_in_tx_pkt;
+	/* [0x58] Tx parser, output packet counter */
+	uint32_t tpe_out_tx_pkt;
+	/* [0x5c] Tx packet modification, input packet counter */
+	uint32_t tpm_tx_pkt;
+	/* [0x60] Tx forwarding input packet counter */
+	uint32_t tfw_in_tx_pkt;
+	/* [0x64] Tx forwarding input packet counter */
+	uint32_t tfw_out_tx_pkt;
+	/* [0x68] Rx forwarding input packet counter */
+	uint32_t rfw_in_rx_pkt;
+	/* [0x6c] Rx Forwarding, packet with VLAN command drop indica ... */
+	uint32_t rfw_in_vlan_drop;
+	/* [0x70] Rx Forwarding, packets with parse drop indication */
+	uint32_t rfw_in_parse_drop;
+	/* [0x74] Rx Forwarding, multicast packets */
+	uint32_t rfw_in_mc;
+	/* [0x78] Rx Forwarding, broadcast packets */
+	uint32_t rfw_in_bc;
+	/* [0x7c] Rx Forwarding, tagged packets */
+	uint32_t rfw_in_vlan_exist;
+	/* [0x80] Rx Forwarding, untagged packets */
+	uint32_t rfw_in_vlan_nexist;
+	/* [0x84] Rx Forwarding, packets with MAC address drop indica ... */
+	uint32_t rfw_in_mac_drop;
+	/* [0x88] Rx Forwarding, packets with undetected MAC address */
+	uint32_t rfw_in_mac_ndet_drop;
+	/* [0x8c] Rx Forwarding, packets with drop indication from th ... */
+	uint32_t rfw_in_ctrl_drop;
+	/* [0x90] Rx Forwarding, packets with L3_protocol_index drop  ... */
+	uint32_t rfw_in_prot_i_drop;
+	/* [0x94] EEE, number of times the system went into EEE state ... */
+	uint32_t eee_in;
+	uint32_t rsrvd[90];
+};
+struct al_ec_stat_udma {
+	/* [0x0] Rx forwarding output packet counter */
+	uint32_t rfw_out_rx_pkt;
+	/* [0x4] Rx forwarding output drop packet counter */
+	uint32_t rfw_out_drop;
+	/* [0x8] Multi-stream write, number of Rx packets */
+	uint32_t msw_in_rx_pkt;
+	/* [0xc] Multi-stream write, number of dropped packets at SO ... */
+	uint32_t msw_drop_q_full;
+	/* [0x10] Multi-stream write, number of dropped packets at SO ... */
+	uint32_t msw_drop_sop;
+	/* [0x14] Multi-stream write, number of dropped packets at EO ... */
+	uint32_t msw_drop_eop;
+	/* [0x18] Multi-stream write, number of packets written to th ... */
+	uint32_t msw_wr_eop;
+	/* [0x1c] Multi-stream write, number of packets read from the ... */
+	uint32_t msw_out_rx_pkt;
+	/* [0x20] Number of transmitted packets without TSO enabled */
+	uint32_t tso_no_tso_pkt;
+	/* [0x24] Number of transmitted packets with TSO enabled */
+	uint32_t tso_tso_pkt;
+	/* [0x28] Number of TSO segments that were generated */
+	uint32_t tso_seg_pkt;
+	/* [0x2c] Number of TSO segments that required padding */
+	uint32_t tso_pad_pkt;
+	/* [0x30] Tx Packet modification, MAC SA spoof error  */
+	uint32_t tpm_tx_spoof;
+	/* [0x34] Tx MAC interface, input packet counter */
+	uint32_t tmi_in_tx_pkt;
+	/* [0x38] Tx MAC interface, number of packets forwarded to th ... */
+	uint32_t tmi_out_to_mac;
+	/* [0x3c] Tx MAC interface, number of packets forwarded to th ... */
+	uint32_t tmi_out_to_rx;
+	/* [0x40] Tx MAC interface, number of transmitted bytes */
+	uint32_t tx_q0_bytes;
+	/* [0x44] Tx MAC interface, number of transmitted bytes */
+	uint32_t tx_q1_bytes;
+	/* [0x48] Tx MAC interface, number of transmitted bytes */
+	uint32_t tx_q2_bytes;
+	/* [0x4c] Tx MAC interface, number of transmitted bytes */
+	uint32_t tx_q3_bytes;
+	/* [0x50] Tx MAC interface, number of transmitted packets */
+	uint32_t tx_q0_pkts;
+	/* [0x54] Tx MAC interface, number of transmitted packets */
+	uint32_t tx_q1_pkts;
+	/* [0x58] Tx MAC interface, number of transmitted packets */
+	uint32_t tx_q2_pkts;
+	/* [0x5c] Tx MAC interface, number of transmitted packets */
+	uint32_t tx_q3_pkts;
+	uint32_t rsrvd[40];
+};
+struct al_ec_msp {
+	/* [0x0] Ethernet parsing engine configuration 1 */
+	uint32_t p_parse_cfg;
+	/* [0x4] Protocol index action table address */
+	uint32_t p_act_table_addr;
+	/* [0x8] Protocol index action table data */
+	uint32_t p_act_table_data_1;
+	/* [0xc] Protocol index action table data */
+	uint32_t p_act_table_data_2;
+	/* [0x10] Protocol index action table data */
+	uint32_t p_act_table_data_3;
+	/* [0x14] Protocol index action table data */
+	uint32_t p_act_table_data_4;
+	/* [0x18] Protocol index action table data */
+	uint32_t p_act_table_data_5;
+	/* [0x1c] Protocol index action table data */
+	uint32_t p_act_table_data_6;
+	/* [0x20] Input result vector, default values for parser inpu ... */
+	uint32_t p_res_def;
+	/* [0x24] Result input vector selection */
+	uint32_t p_res_in;
+	uint32_t rsrvd[6];
+};
+struct al_ec_msp_p {
+	/* [0x0] Header length, support for header length table for  ... */
+	uint32_t h_hdr_len;
+};
+struct al_ec_msp_c {
+	/* [0x0] Data  for comparison */
+	uint32_t p_comp_data;
+	/* [0x4] Mask for comparison */
+	uint32_t p_comp_mask;
+	/* [0x8] Compare control */
+	uint32_t p_comp_ctrl;
+	uint32_t rsrvd[4];
+};
+struct al_ec_wol {
+	/* [0x0] WoL enable configuration,Packet forwarding and inte ... */
+	uint32_t wol_en;
+	/* [0x4] Password for magic_password packet detection - bits ... */
+	uint32_t magic_pswd_l;
+	/* [0x8] Password for magic+password packet detection -  47: ... */
+	uint32_t magic_pswd_h;
+	/* [0xc] Configured L3 Destination IP address for WoL IPv6 p ... */
+	uint32_t ipv6_dip_word0;
+	/* [0x10] Configured L3 Destination IP address for WoL IPv6 p ... */
+	uint32_t ipv6_dip_word1;
+	/* [0x14] Configured L3 Destination IP address for WoL IPv6 p ... */
+	uint32_t ipv6_dip_word2;
+	/* [0x18] Configured L3 Destination IP address for WoL IPv6 p ... */
+	uint32_t ipv6_dip_word3;
+	/* [0x1c] Configured L3 Destination IP address for WoL IPv4 p ... */
+	uint32_t ipv4_dip;
+	/* [0x20] Configured EtherType for WoL EtherType_da/EtherType ... */
+	uint32_t ethertype;
+	uint32_t rsrvd[7];
+};
+struct al_ec_pth {
+	/* [0x0] System time counter (Time of Day) */
+	uint32_t system_time_seconds;
+	/* [0x4] System time subseconds in a second (MSBs) */
+	uint32_t system_time_subseconds_msb;
+	/* [0x8] System time subseconds in a second (LSBs) */
+	uint32_t system_time_subseconds_lsb;
+	/* [0xc] Clock period in femtoseconds (MSB) */
+	uint32_t clock_period_msb;
+	/* [0x10] Clock period in femtoseconds (LSB) */
+	uint32_t clock_period_lsb;
+	/* [0x14] Control register for internal updates to the system ... */
+	uint32_t int_update_ctrl;
+	/* [0x18] Value to update system_time_seconds with */
+	uint32_t int_update_seconds;
+	/* [0x1c] Value to update system_time_subseconds_msb with */
+	uint32_t int_update_subseconds_msb;
+	/* [0x20] Value to update system_time_subseconds_lsb with */
+	uint32_t int_update_subseconds_lsb;
+	/* [0x24] Control register for external updates to the system ... */
+	uint32_t ext_update_ctrl;
+	/* [0x28] Value to update system_time_seconds with */
+	uint32_t ext_update_seconds;
+	/* [0x2c] Value to update system_time_subseconds_msb with */
+	uint32_t ext_update_subseconds_msb;
+	/* [0x30] Value to update system_time_subseconds_lsb with */
+	uint32_t ext_update_subseconds_lsb;
+	/* [0x34] This value represents the APB transaction delay fro ... */
+	uint32_t read_compensation_subseconds_msb;
+	/* [0x38] This value represents the APB transaction delay fro ... */
+	uint32_t read_compensation_subseconds_lsb;
+	/* [0x3c] This value is used for two purposes:1 */
+	uint32_t int_write_compensation_subseconds_msb;
+	/* [0x40] This value is used for two purposes:1 */
+	uint32_t int_write_compensation_subseconds_lsb;
+	/* [0x44] This value represents the number of cycles it for a ... */
+	uint32_t ext_write_compensation_subseconds_msb;
+	/* [0x48] This value represents the number of cycles it for a ... */
+	uint32_t ext_write_compensation_subseconds_lsb;
+	/* [0x4c] Value to be added to system_time before transferrin ... */
+	uint32_t sync_compensation_subseconds_msb;
+	/* [0x50] Value to be added to system_time before transferrin ... */
+	uint32_t sync_compensation_subseconds_lsb;
+	uint32_t rsrvd[11];
+};
+struct al_ec_pth_egress {
+	/* [0x0] Control register for egress trigger #k */
+	uint32_t trigger_ctrl;
+	/* [0x4] threshold for next egress trigger (#k) - secondsWri ... */
+	uint32_t trigger_seconds;
+	/* [0x8] Threshold for next egress trigger (#k) - subseconds ... */
+	uint32_t trigger_subseconds_msb;
+	/* [0xc] threshold for next egress trigger (#k) - subseconds ... */
+	uint32_t trigger_subseconds_lsb;
+	/* [0x10] External output pulse width (subseconds_msb)(Atomic ... */
+	uint32_t pulse_width_subseconds_msb;
+	/* [0x14] External output pulse width (subseconds_lsb)(Atomic ... */
+	uint32_t pulse_width_subseconds_lsb;
+	uint32_t rsrvd[2];
+};
+struct al_ec_pth_db {
+	/* [0x0] timestamp[k], in resolution of 2^18 femtosec =~ 0 */
+	uint32_t ts;
+	/* [0x4] Timestamp entry is valid */
+	uint32_t qual;
+	uint32_t rsrvd[4];
+};
+struct al_ec_gen_v3 {
+	/* [0x0] Bypass enable */
+	uint32_t bypass;
+	/* [0x4] Rx Completion descriptor */
+	uint32_t rx_comp_desc;
+	/* [0x8] general configuration */
+	uint32_t conf;
+	uint32_t rsrvd[13];
+};
+struct al_ec_tfw_v3 {
+	/* [0x0] Generic protocol detect Cam compare table address */
+	uint32_t tx_gpd_cam_addr;
+	/* [0x4] Tx Generic protocol detect Cam compare data_1 (low) ... */
+	uint32_t tx_gpd_cam_data_1;
+	/* [0x8] Tx Generic protocol detect Cam compare data_2 (high ... */
+	uint32_t tx_gpd_cam_data_2;
+	/* [0xc] Tx Generic protocol detect Cam compare mask_1 (low) ... */
+	uint32_t tx_gpd_cam_mask_1;
+	/* [0x10] Tx Generic protocol detect Cam compare mask_1 (high ... */
+	uint32_t tx_gpd_cam_mask_2;
+	/* [0x14] Tx Generic protocol detect Cam compare control */
+	uint32_t tx_gpd_cam_ctrl;
+	/* [0x18] Tx Generic crc parameters legacy */
+	uint32_t tx_gcp_legacy;
+	/* [0x1c] Tx Generic crc prameters table address */
+	uint32_t tx_gcp_table_addr;
+	/* [0x20] Tx Generic crc prameters table general */
+	uint32_t tx_gcp_table_gen;
+	/* [0x24] Tx Generic crc parametrs tabel mask word 1 */
+	uint32_t tx_gcp_table_mask_1;
+	/* [0x28] Tx Generic crc parametrs tabel mask word 2 */
+	uint32_t tx_gcp_table_mask_2;
+	/* [0x2c] Tx Generic crc parametrs tabel mask word 3 */
+	uint32_t tx_gcp_table_mask_3;
+	/* [0x30] Tx Generic crc parametrs tabel mask word 4 */
+	uint32_t tx_gcp_table_mask_4;
+	/* [0x34] Tx Generic crc parametrs tabel mask word 5 */
+	uint32_t tx_gcp_table_mask_5;
+	/* [0x38] Tx Generic crc parametrs tabel mask word 6 */
+	uint32_t tx_gcp_table_mask_6;
+	/* [0x3c] Tx Generic crc parametrs tabel crc init */
+	uint32_t tx_gcp_table_crc_init;
+	/* [0x40] Tx Generic crc parametrs tabel result configuration ... */
+	uint32_t tx_gcp_table_res;
+	/* [0x44] Tx Generic crc parameters table alu opcode */
+	uint32_t tx_gcp_table_alu_opcode;
+	/* [0x48] Tx Generic crc parameters table alu opsel */
+	uint32_t tx_gcp_table_alu_opsel;
+	/* [0x4c] Tx Generic crc parameters table alu constant value */
+	uint32_t tx_gcp_table_alu_val;
+	/* [0x50] Tx CRC/Checksum replace */
+	uint32_t crc_csum_replace;
+	/* [0x54] CRC/Checksum replace table address */
+	uint32_t crc_csum_replace_table_addr;
+	/* [0x58] CRC/Checksum replace table */
+	uint32_t crc_csum_replace_table;
+	uint32_t rsrvd[9];
+};
+
+struct al_ec_rfw_v3 {
+	/* [0x0] Rx Generic protocol detect Cam compare table addres ... */
+	uint32_t rx_gpd_cam_addr;
+	/* [0x4] Rx Generic protocol detect Cam compare data_1 (low) ... */
+	uint32_t rx_gpd_cam_data_1;
+	/* [0x8] Rx Generic protocol detect Cam compare data_2 (high ... */
+	uint32_t rx_gpd_cam_data_2;
+	/* [0xc] Rx Generic protocol detect Cam compare mask_1 (low) ... */
+	uint32_t rx_gpd_cam_mask_1;
+	/* [0x10] Rx Generic protocol detect Cam compare mask_1 (high ... */
+	uint32_t rx_gpd_cam_mask_2;
+	/* [0x14] Rx Generic protocol detect Cam compare control */
+	uint32_t rx_gpd_cam_ctrl;
+	/* [0x18] Generic protocol detect Parser result vector pointe ... */
+	uint32_t gpd_p1;
+	/* [0x1c] Generic protocol detect Parser result vector pointe ... */
+	uint32_t gpd_p2;
+	/* [0x20] Generic protocol detect Parser result vector pointe ... */
+	uint32_t gpd_p3;
+	/* [0x24] Generic protocol detect Parser result vector pointe ... */
+	uint32_t gpd_p4;
+	/* [0x28] Generic protocol detect Parser result vector pointe ... */
+	uint32_t gpd_p5;
+	/* [0x2c] Generic protocol detect Parser result vector pointe ... */
+	uint32_t gpd_p6;
+	/* [0x30] Generic protocol detect Parser result vector pointe ... */
+	uint32_t gpd_p7;
+	/* [0x34] Generic protocol detect Parser result vector pointe ... */
+	uint32_t gpd_p8;
+	/* [0x38] Rx Generic crc parameters legacy */
+	uint32_t rx_gcp_legacy;
+	/* [0x3c] Rx Generic crc prameters table address */
+	uint32_t rx_gcp_table_addr;
+	/* [0x40] Rx Generic crc prameters table general */
+	uint32_t rx_gcp_table_gen;
+	/* [0x44] Rx Generic crc parametrs tabel mask word 1 */
+	uint32_t rx_gcp_table_mask_1;
+	/* [0x48] Rx Generic crc parametrs tabel mask word 2 */
+	uint32_t rx_gcp_table_mask_2;
+	/* [0x4c] Rx Generic crc parametrs tabel mask word 3 */
+	uint32_t rx_gcp_table_mask_3;
+	/* [0x50] Rx Generic crc parametrs tabel mask word 4 */
+	uint32_t rx_gcp_table_mask_4;
+	/* [0x54] Rx Generic crc parametrs tabel mask word 5 */
+	uint32_t rx_gcp_table_mask_5;
+	/* [0x58] Rx Generic crc parametrs tabel mask word 6 */
+	uint32_t rx_gcp_table_mask_6;
+	/* [0x5c] Rx Generic crc parametrs tabel crc init */
+	uint32_t rx_gcp_table_crc_init;
+	/* [0x60] Rx Generic crc parametrs tabel result configuration ... */
+	uint32_t rx_gcp_table_res;
+	/* [0x64] Rx Generic crc  parameters table alu opcode */
+	uint32_t rx_gcp_table_alu_opcode;
+	/* [0x68] Rx Generic crc  parameters table alu opsel */
+	uint32_t rx_gcp_table_alu_opsel;
+	/* [0x6c] Rx Generic crc  parameters table alu constant value ... */
+	uint32_t rx_gcp_table_alu_val;
+	/* [0x70] Generic crc engin parameters alu Parser result vect ... */
+	uint32_t rx_gcp_alu_p1;
+	/* [0x74] Generic crc engine parameters alu Parser result vec ... */
+	uint32_t rx_gcp_alu_p2;
+	/* [0x78] Header split control table address */
+	uint32_t hs_ctrl_table_addr;
+	/* [0x7c] Header split control table */
+	uint32_t hs_ctrl_table;
+	/* [0x80] Header split control alu opcode */
+	uint32_t hs_ctrl_table_alu_opcode;
+	/* [0x84] Header split control alu opsel */
+	uint32_t hs_ctrl_table_alu_opsel;
+	/* [0x88] Header split control alu constant value */
+	uint32_t hs_ctrl_table_alu_val;
+	/* [0x8c] Header split control configuration */
+	uint32_t hs_ctrl_cfg;
+	/* [0x90] Header split control alu Parser result vector point ... */
+	uint32_t hs_ctrl_alu_p1;
+	/* [0x94] Header split control alu Parser result vector point ... */
+	uint32_t hs_ctrl_alu_p2;
+	uint32_t rsrvd[26];
+};
+struct al_ec_crypto {
+	/* [0x0] Tx inline crypto configuration */
+	uint32_t tx_config;
+	/* [0x4] Rx inline crypto configuration */
+	uint32_t rx_config;
+	/* [0x8] reserved FFU */
+	uint32_t tx_override;
+	/* [0xc] reserved FFU */
+	uint32_t rx_override;
+	/* [0x10] inline XTS alpha [31:0] */
+	uint32_t xts_alpha_1;
+	/* [0x14] inline XTS alpha [63:32] */
+	uint32_t xts_alpha_2;
+	/* [0x18] inline XTS alpha [95:64] */
+	uint32_t xts_alpha_3;
+	/* [0x1c] inline XTS alpha [127:96] */
+	uint32_t xts_alpha_4;
+	/* [0x20] inline XTS sector ID increment [31:0] */
+	uint32_t xts_sector_id_1;
+	/* [0x24] inline XTS sector ID increment [63:32] */
+	uint32_t xts_sector_id_2;
+	/* [0x28] inline XTS sector ID increment [95:64] */
+	uint32_t xts_sector_id_3;
+	/* [0x2c] inline XTS sector ID increment [127:96] */
+	uint32_t xts_sector_id_4;
+	/* [0x30] IV formation configuration */
+	uint32_t tx_enc_iv_construction;
+	/* [0x34] IV formation configuration */
+	uint32_t rx_enc_iv_construction;
+	/* [0x38] IV formation configuration */
+	uint32_t rx_enc_iv_map;
+	/*
+	[0x3c] effectively shorten shift-registers used for
+	eop-pkt-trim, in order to improve performance.
+	Each value must be built of consecutive 1's (bypassed regs),
+	and then consecutive 0's (non-bypassed regs)
+	*/
+	uint32_t tx_pkt_trim_len;
+	/*
+	[0x40] effectively shorten shift-registers used for
+	eop-pkt-trim, in order to improve performance.
+	Each value must be built of consecutive 1's (bypassed regs),
+	and then consecutive 0's (non-bypassed regs)
+	*/
+	uint32_t rx_pkt_trim_len;
+	/* [0x44] reserved FFU */
+	uint32_t tx_reserved;
+	/* [0x48] reserved FFU */
+	uint32_t rx_reserved;
+	uint32_t rsrvd[13];
+};
+struct al_ec_crypto_perf_cntr {
+	/* [0x0]  */
+	uint32_t total_tx_pkts;
+	/* [0x4]  */
+	uint32_t total_rx_pkts;
+	/* [0x8]  */
+	uint32_t total_tx_secured_pkts;
+	/* [0xc]  */
+	uint32_t total_rx_secured_pkts;
+	/* [0x10]  */
+	uint32_t total_tx_secured_pkts_cipher_mode;
+	/* [0x14]  */
+	uint32_t total_tx_secured_pkts_cipher_mode_cmpr;
+	/* [0x18]  */
+	uint32_t total_rx_secured_pkts_cipher_mode;
+	/* [0x1c]  */
+	uint32_t total_rx_secured_pkts_cipher_mode_cmpr;
+	/* [0x20]  */
+	uint32_t total_tx_secured_bytes_low;
+	/* [0x24]  */
+	uint32_t total_tx_secured_bytes_high;
+	/* [0x28]  */
+	uint32_t total_rx_secured_bytes_low;
+	/* [0x2c]  */
+	uint32_t total_rx_secured_bytes_high;
+	/* [0x30]  */
+	uint32_t total_tx_sign_calcs;
+	/* [0x34]  */
+	uint32_t total_rx_sign_calcs;
+	/* [0x38]  */
+	uint32_t total_tx_sign_errs;
+	/* [0x3c]  */
+	uint32_t total_rx_sign_errs;
+};
+struct al_ec_crypto_tx_tid {
+	/* [0x0] tid_default_entry */
+	uint32_t def_val;
+};
+
+struct al_ec_regs {
+	uint32_t rsrvd_0[32];
+	struct al_ec_gen gen;                                /* [0x80] */
+	struct al_ec_mac mac;                                /* [0xc0] */
+	struct al_ec_rxf rxf;                                /* [0x100] */
+	struct al_ec_epe epe[2];                             /* [0x180] */
+	struct al_ec_epe_res epe_res;                        /* [0x200] */
+	struct al_ec_epe_h epe_h[32];                        /* [0x280] */
+	struct al_ec_epe_p epe_p[32];                        /* [0x300] */
+	struct al_ec_epe_a epe_a[32];                        /* [0x680] */
+	struct al_ec_rfw rfw;                                /* [0x700] */
+	struct al_ec_rfw_udma rfw_udma[4];                   /* [0x7f0] */
+	struct al_ec_rfw_hash rfw_hash[10];                  /* [0x800] */
+	struct al_ec_rfw_priority rfw_priority[8];           /* [0x828] */
+	struct al_ec_rfw_default rfw_default[8];             /* [0x848] */
+	struct al_ec_fwd_mac fwd_mac[32];                    /* [0x868] */
+	struct al_ec_msw msw;                                /* [0xae8] */
+	struct al_ec_tso tso;                                /* [0xb00] */
+	struct al_ec_tso_sel tso_sel[8];                     /* [0xb60] */
+	struct al_ec_tpe tpe;                                /* [0xb80] */
+	struct al_ec_tpm_udma tpm_udma[4];                   /* [0xbc0] */
+	struct al_ec_tpm_sel tpm_sel[4];                     /* [0xbf0] */
+	struct al_ec_tfw tfw;                                /* [0xc00] */
+	struct al_ec_tfw_udma tfw_udma[4];                   /* [0xc60] */
+	struct al_ec_tmi tmi;                                /* [0xcc0] */
+	struct al_ec_efc efc;                                /* [0xcd0] */
+	struct al_ec_fc_udma fc_udma[4];                     /* [0xd00] */
+	struct al_ec_tpg_rpa_res tpg_rpa_res;                /* [0xf00] */
+	struct al_ec_eee eee;                                /* [0x1000] */
+	struct al_ec_stat stat;                              /* [0x1100] */
+	struct al_ec_stat_udma stat_udma[4];                 /* [0x1300] */
+	struct al_ec_msp msp;                                /* [0x1700] */
+	struct al_ec_msp_p msp_p[32];                        /* [0x1740] */
+	struct al_ec_msp_c msp_c[32];                        /* [0x17c0] */
+	uint32_t rsrvd_1[16];
+	struct al_ec_wol wol;                                /* [0x1b80] */
+	uint32_t rsrvd_2[80];
+	struct al_ec_pth pth;                                /* [0x1d00] */
+	struct al_ec_pth_egress pth_egress[8];               /* [0x1d80] */
+	struct al_ec_pth_db pth_db[16];                      /* [0x1e80] */
+	uint32_t rsrvd_3[416];
+	struct al_ec_gen_v3 gen_v3;                             /* [0x2680] */
+	struct al_ec_tfw_v3 tfw_v3;                             /* [0x26c0] */
+	struct al_ec_rfw_v3 rfw_v3;                             /* [0x2740] */
+	struct al_ec_crypto crypto;                             /* [0x2840] */
+	struct al_ec_crypto_perf_cntr crypto_perf_cntr[2];      /* [0x28c0] */
+	uint32_t rsrvd_4[48];
+	struct al_ec_crypto_tx_tid crypto_tx_tid[8];            /* [0x2a00] */
+};
+
+
+/*
+* Registers Fields
+*/
+
+
+/**** version register ****/
+/* Revision number (Minor) */
+#define EC_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
+#define EC_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
+/* Revision number (Major) */
+#define EC_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
+#define EC_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
+/* Day of release */
+#define EC_GEN_VERSION_DATE_DAY_MASK     0x001F0000
+#define EC_GEN_VERSION_DATE_DAY_SHIFT    16
+/* Month of release */
+#define EC_GEN_VERSION_DATA_MONTH_MASK   0x01E00000
+#define EC_GEN_VERSION_DATA_MONTH_SHIFT  21
+/* Year of release (starting from 2000) */
+#define EC_GEN_VERSION_DATE_YEAR_MASK    0x3E000000
+#define EC_GEN_VERSION_DATE_YEAR_SHIFT   25
+/* Reserved */
+#define EC_GEN_VERSION_RESERVED_MASK     0xC0000000
+#define EC_GEN_VERSION_RESERVED_SHIFT    30
+
+/**** en register ****/
+/* Enable Frequency adjust FIFO input controller operation. */
+#define EC_GEN_EN_FAF_IN                 (1 << 0)
+/* Enable Frequency adjust FIFO output controller operation. */
+#define EC_GEN_EN_FAF_OUT                (1 << 1)
+/* Enable Rx FIFO input controller 1 operation. */
+#define EC_GEN_EN_RXF_IN                 (1 << 2)
+/* Enable Rx FIFO output controller  operation. */
+#define EC_GEN_EN_RXF_OUT                (1 << 3)
+/* Enable Rx forwarding input controller operation. */
+#define EC_GEN_EN_RFW_IN                 (1 << 4)
+/* Enable Rx forwarding output controller operation. */
+#define EC_GEN_EN_RFW_OUT                (1 << 5)
+/* Enable Rx multi-stream write controller operation. */
+#define EC_GEN_EN_MSW_IN                 (1 << 6)
+/* Enable Rx first parsing engine output operation. */
+#define EC_GEN_EN_RPE_1_OUT              (1 << 7)
+/* Enable Rx first parsing engine input operation. */
+#define EC_GEN_EN_RPE_1_IN               (1 << 8)
+/* Enable Rx second parsing engine output operation. */
+#define EC_GEN_EN_RPE_2_OUT              (1 << 9)
+/* Enable Rx second parsing engine input operation. */
+#define EC_GEN_EN_RPE_2_IN               (1 << 10)
+/* Enable Rx MACsec parsing engine output operation. */
+#define EC_GEN_EN_RPE_3_OUT              (1 << 11)
+/* Enable Rx MACsec parsing engine input operation. */
+#define EC_GEN_EN_RPE_3_IN               (1 << 12)
+/* Enable Loopback FIFO input controller 1 operation. */
+#define EC_GEN_EN_LBF_IN                 (1 << 13)
+/* Enable Rx packet analyzer operation. */
+#define EC_GEN_EN_RPA                    (1 << 14)
+
+#define EC_GEN_EN_RESERVED_15            (1 << 15)
+/* Enable Tx stream interface operation. */
+#define EC_GEN_EN_TSO                    (1 << 16)
+/* Enable Tx parser input controller operation. */
+#define EC_GEN_EN_TPE_IN                 (1 << 17)
+/* Enable Tx parser output controller operation. */
+#define EC_GEN_EN_TPE_OUT                (1 << 18)
+/* Enable Tx packet modification operation. */
+#define EC_GEN_EN_TPM                    (1 << 19)
+/* Enable Tx forwarding input controller operation. */
+#define EC_GEN_EN_TFW_IN                 (1 << 20)
+/* Enable Tx forwarding output controller operation. */
+#define EC_GEN_EN_TFW_OUT                (1 << 21)
+/* Enable Tx MAC interface controller operation. */
+#define EC_GEN_EN_TMI                    (1 << 22)
+/* Enable Tx packet generator operation. */
+#define EC_GEN_EN_TPG                    (1 << 23)
+
+#define EC_GEN_EN_RESERVED_31_MASK       0xFF000000
+#define EC_GEN_EN_RESERVED_31_SHIFT      24
+
+/**** fifo_en register ****/
+/* Enable Frequency adjust FIFO operation (input). */
+#define EC_GEN_FIFO_EN_FAF_IN            (1 << 0)
+/* Enable Frequency adjust FIFO operation (output). */
+#define EC_GEN_FIFO_EN_FAF_OUT           (1 << 1)
+/* Enable Rx FIFO operation. */
+#define EC_GEN_FIFO_EN_RX_FIFO           (1 << 2)
+/* Enable Rx forwarding FIFO operation. */
+#define EC_GEN_FIFO_EN_RFW_FIFO          (1 << 3)
+/* Enable Rx multi-stream write FIFO operation */
+#define EC_GEN_FIFO_EN_MSW_FIFO          (1 << 4)
+/* Enable Rx first parser FIFO operation. */
+#define EC_GEN_FIFO_EN_RPE_1_FIFO        (1 << 5)
+/* Enable Rx second parser FIFO operation. */
+#define EC_GEN_FIFO_EN_RPE_2_FIFO        (1 << 6)
+/* Enable Rx MACsec parser FIFO operation. */
+#define EC_GEN_FIFO_EN_RPE_3_FIFO        (1 << 7)
+/* Enable Loopback FIFO operation. */
+#define EC_GEN_FIFO_EN_LB_FIFO           (1 << 8)
+
+#define EC_GEN_FIFO_EN_RESERVED_15_9_MASK 0x0000FE00
+#define EC_GEN_FIFO_EN_RESERVED_15_9_SHIFT 9
+/* Enable Tx parser FIFO operation. */
+#define EC_GEN_FIFO_EN_TPE_FIFO          (1 << 16)
+/* Enable Tx forwarding FIFO operation. */
+#define EC_GEN_FIFO_EN_TFW_FIFO          (1 << 17)
+
+#define EC_GEN_FIFO_EN_RESERVED_31_18_MASK 0xFFFC0000
+#define EC_GEN_FIFO_EN_RESERVED_31_18_SHIFT 18
+
+/**** l2 register ****/
+/* Size of a 802.3 Ethernet header (DA+SA) */
+#define EC_GEN_L2_SIZE_802_3_MASK        0x0000003F
+#define EC_GEN_L2_SIZE_802_3_SHIFT       0
+/* Size of a 802.3 + MACsec 8 byte header */
+#define EC_GEN_L2_SIZE_802_3_MS_8_MASK   0x00003F00
+#define EC_GEN_L2_SIZE_802_3_MS_8_SHIFT  8
+/* Offset of the L2 header from the beginning of the packet. */
+#define EC_GEN_L2_OFFSET_MASK            0x7F000000
+#define EC_GEN_L2_OFFSET_SHIFT           24
+
+/**** cfg_i register ****/
+/* IPv4 protocol index */
+#define EC_GEN_CFG_I_IPV4_INDEX_MASK     0x0000001F
+#define EC_GEN_CFG_I_IPV4_INDEX_SHIFT    0
+/* IPv6 protocol index */
+#define EC_GEN_CFG_I_IPV6_INDEX_MASK     0x000003E0
+#define EC_GEN_CFG_I_IPV6_INDEX_SHIFT    5
+/* TCP protocol index */
+#define EC_GEN_CFG_I_TCP_INDEX_MASK      0x00007C00
+#define EC_GEN_CFG_I_TCP_INDEX_SHIFT     10
+/* UDP protocol index */
+#define EC_GEN_CFG_I_UDP_INDEX_MASK      0x000F8000
+#define EC_GEN_CFG_I_UDP_INDEX_SHIFT     15
+/* MACsec with 8 bytes SecTAG */
+#define EC_GEN_CFG_I_MACSEC_8_INDEX_MASK 0x01F00000
+#define EC_GEN_CFG_I_MACSEC_8_INDEX_SHIFT 20
+/* MACsec with 16 bytes SecTAG */
+#define EC_GEN_CFG_I_MACSEC_16_INDEX_MASK 0x3E000000
+#define EC_GEN_CFG_I_MACSEC_16_INDEX_SHIFT 25
+
+/**** cfg_i_ext register ****/
+/* FcoE protocol index */
+#define EC_GEN_CFG_I_EXT_FCOE_INDEX_MASK 0x0000001F
+#define EC_GEN_CFG_I_EXT_FCOE_INDEX_SHIFT 0
+/* RoCE protocol index */
+#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_1_MASK 0x000003E0
+#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_1_SHIFT 5
+/* RoCE protocol index */
+#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_2_MASK 0x00007C00
+#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L3_2_SHIFT 10
+/* RoCE protocol index */
+#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L4_MASK 0x000F8000
+#define EC_GEN_CFG_I_EXT_ROCE_INDEX_L4_SHIFT 15
+
+/**** en_ext register ****/
+/* Enable Usage of Ethernet port memories for testing */
+#define EC_GEN_EN_EXT_MEM_FOR_TEST_MASK  0x0000000F
+#define EC_GEN_EN_EXT_MEM_FOR_TEST_SHIFT 0
+#define EC_GEN_EN_EXT_MEM_FOR_TEST_VAL_EN	\
+	(0xa << EC_GEN_EN_EXT_MEM_FOR_TEST_SHIFT)
+#define EC_GEN_EN_EXT_MEM_FOR_TEST_VAL_DIS	\
+	(0x0 << EC_GEN_EN_EXT_MEM_FOR_TEST_SHIFT)
+/* Enable MAC loop back (Rx --> Tx, after MAC layer) for 802 */
+#define EC_GEN_EN_EXT_MAC_LB             (1 << 4)
+/* CRC forward value for the MAC Tx when working in loopback mod ... */
+#define EC_GEN_EN_EXT_MAC_LB_CRC_FWD     (1 << 5)
+/* Ready signal configuration when in loopback mode:00 - Ready f ... */
+#define EC_GEN_EN_EXT_MAC_LB_READY_CFG_MASK 0x000000C0
+#define EC_GEN_EN_EXT_MAC_LB_READY_CFG_SHIFT 6
+/* Bypass the PTH completion update. */
+#define EC_GEN_EN_EXT_PTH_COMPLETION_BYPASS (1 << 16)
+/* Selection between the 1G and 10G MAC:
+0 - 1G
+1 - 10G */
+#define EC_GEN_EN_EXT_PTH_1_10_SEL       (1 << 17)
+/* avoid timestamping every pkt in 1G */
+#define EC_GEN_EN_EXT_PTH_CFG_1G_TIMESTAMP_OPT (1 << 18)
+/* Selection between descriptor caching options (WORD selection) ... */
+#define EC_GEN_EN_EXT_CACHE_WORD_SPLIT   (1 << 20)
+
+/**** gen register ****/
+/* Enable swap of input byte order */
+#define EC_MAC_GEN_SWAP_IN_BYTE          (1 << 0)
+
+/**** min_pkt register ****/
+/* Minimum packet size  */
+#define EC_MAC_MIN_PKT_SIZE_MASK         0x000FFFFF
+#define EC_MAC_MIN_PKT_SIZE_SHIFT        0
+
+/**** max_pkt register ****/
+/* Maximum packet size  */
+#define EC_MAC_MAX_PKT_SIZE_MASK         0x000FFFFF
+#define EC_MAC_MAX_PKT_SIZE_SHIFT        0
+
+/**** cfg_1 register ****/
+/* Drop packet at the ingress0 - Packets are not dropped at the  ... */
+#define EC_RXF_CFG_1_DROP_AT_INGRESS     (1 << 0)
+/* Accept packet criteria at start of packet indication */
+#define EC_RXF_CFG_1_SOP_ACCEPT          (1 << 1)
+/* Select the arbiter between Rx packets and Tx packets (packets ... */
+#define EC_RXF_CFG_1_ARB_SEL             (1 << 2)
+/* Arbiter priority when strict priority is selected in arb_sel0 ... */
+#define EC_RXF_CFG_1_ARB_P               (1 << 3)
+/* Force loopback operation */
+#define EC_RXF_CFG_1_FORCE_LB            (1 << 4)
+/* Forwarding selection between Rx path and/or packet analyzer */
+#define EC_RXF_CFG_1_FWD_SEL_MASK        0x00000300
+#define EC_RXF_CFG_1_FWD_SEL_SHIFT       8
+
+/**** cfg_2 register ****/
+/* FIFO USED threshold for accepting new packets, low threshold  ... */
+#define EC_RXF_CFG_2_FIFO_USED_TH_L_MASK 0x0000FFFF
+#define EC_RXF_CFG_2_FIFO_USED_TH_L_SHIFT 0
+/* FIFO USED threshold for accepting new packets, high threshold ... */
+#define EC_RXF_CFG_2_FIFO_USED_TH_H_MASK 0xFFFF0000
+#define EC_RXF_CFG_2_FIFO_USED_TH_H_SHIFT 16
+
+/**** rd_fifo register ****/
+/* Minimum number of entries in the data FIFO to start reading p ... */
+#define EC_RXF_RD_FIFO_TH_DATA_MASK      0x0000FFFF
+#define EC_RXF_RD_FIFO_TH_DATA_SHIFT     0
+/* Enable cut through operation */
+#define EC_RXF_RD_FIFO_EN_CUT_TH         (1 << 16)
+
+/**** wr_fifo register ****/
+
+#define EC_RXF_WR_FIFO_TH_DATA_MASK      0x0000FFFF
+#define EC_RXF_WR_FIFO_TH_DATA_SHIFT     0
+
+#define EC_RXF_WR_FIFO_TH_INFO_MASK      0xFFFF0000
+#define EC_RXF_WR_FIFO_TH_INFO_SHIFT     16
+
+/**** lb_fifo register ****/
+
+#define EC_RXF_LB_FIFO_TH_DATA_MASK      0x0000FFFF
+#define EC_RXF_LB_FIFO_TH_DATA_SHIFT     0
+
+#define EC_RXF_LB_FIFO_TH_INFO_MASK      0xFFFF0000
+#define EC_RXF_LB_FIFO_TH_INFO_SHIFT     16
+
+/**** cfg_lb register ****/
+/* FIFO USED threshold for accepting new packets */
+#define EC_RXF_CFG_LB_FIFO_USED_TH_INT_MASK 0x0000FFFF
+#define EC_RXF_CFG_LB_FIFO_USED_TH_INT_SHIFT 0
+/* FIFO USED threshold for generating ready for the Tx path */
+#define EC_RXF_CFG_LB_FIFO_USED_TH_EXT_MASK 0xFFFF0000
+#define EC_RXF_CFG_LB_FIFO_USED_TH_EXT_SHIFT 16
+
+/**** out_drop register ****/
+
+#define EC_RXF_OUT_DROP_MAC_ERR          (1 << 0)
+
+#define EC_RXF_OUT_DROP_MAC_COL          (1 << 1)
+
+#define EC_RXF_OUT_DROP_MAC_DEC          (1 << 2)
+
+#define EC_RXF_OUT_DROP_MAC_LEN          (1 << 3)
+
+#define EC_RXF_OUT_DROP_MAC_PHY          (1 << 4)
+
+#define EC_RXF_OUT_DROP_MAC_FIFO         (1 << 5)
+
+#define EC_RXF_OUT_DROP_MAC_FCS          (1 << 6)
+
+#define EC_RXF_OUT_DROP_MAC_ETYPE        (1 << 7)
+
+#define EC_RXF_OUT_DROP_EC_LEN           (1 << 8)
+
+#define EC_RXF_OUT_DROP_EC_FIFO          (1 << 9)
+
+/**** parse_cfg register ****/
+/* MAX number of beats for packet parsing */
+#define EC_EPE_PARSE_CFG_MAX_BEATS_MASK  0x000000FF
+#define EC_EPE_PARSE_CFG_MAX_BEATS_SHIFT 0
+/* MAX number of parsing iterations for packet parsing */
+#define EC_EPE_PARSE_CFG_MAX_ITER_MASK   0x0000FF00
+#define EC_EPE_PARSE_CFG_MAX_ITER_SHIFT  8
+
+/**** act_table_addr register ****/
+/* Address for accessing the table */
+#define EC_EPE_ACT_TABLE_ADDR_VAL_MASK   0x0000001F
+#define EC_EPE_ACT_TABLE_ADDR_VAL_SHIFT  0
+
+/**** act_table_data_1 register ****/
+/* Table data[5:0] - Offset to next protocol [bytes][6] - Next p ... */
+#define EC_EPE_ACT_TABLE_DATA_1_VAL_MASK 0x03FFFFFF
+#define EC_EPE_ACT_TABLE_DATA_1_VAL_SHIFT 0
+
+/**** act_table_data_2 register ****/
+/* Table Data [8:0] - Offset to data in the packet [bits][17:9]  ... */
+#define EC_EPE_ACT_TABLE_DATA_2_VAL_MASK 0x1FFFFFFF
+#define EC_EPE_ACT_TABLE_DATA_2_VAL_SHIFT 0
+
+/**** act_table_data_3 register ****/
+/* Table Data  [8:0] - Offset to data in the packet [bits] [17:9 ... */
+#define EC_EPE_ACT_TABLE_DATA_3_VAL_MASK 0x1FFFFFFF
+#define EC_EPE_ACT_TABLE_DATA_3_VAL_SHIFT 0
+
+/**** act_table_data_4 register ****/
+/* Table data[7:0] - Offset to header length location in the pac ... */
+#define EC_EPE_ACT_TABLE_DATA_4_VAL_MASK 0x0FFFFFFF
+#define EC_EPE_ACT_TABLE_DATA_4_VAL_SHIFT 0
+
+/**** act_table_data_6 register ****/
+/* Table data[0] - WR header length[10:1] - Write header length  ... */
+#define EC_EPE_ACT_TABLE_DATA_6_VAL_MASK 0x007FFFFF
+#define EC_EPE_ACT_TABLE_DATA_6_VAL_SHIFT 0
+
+/**** res_in register ****/
+/* Selector for input parse_en0 - Input vector1 - Default value  ... */
+#define EC_EPE_RES_IN_SEL_PARSE_EN       (1 << 0)
+/* Selector for input protocol_index 0 - Input vector 1 - Defaul ... */
+#define EC_EPE_RES_IN_SEL_PROT_INDEX     (1 << 1)
+/* Selector for input hdr_offset 0 - Input vector 1 - Default va ... */
+#define EC_EPE_RES_IN_SEL_HDR_OFFSET     (1 << 2)
+
+/**** p1 register ****/
+/* Location of the input protocol index in the parser result vec ... */
+#define EC_EPE_RES_P1_IN_PROT_INDEX_MASK 0x000003FF
+#define EC_EPE_RES_P1_IN_PROT_INDEX_SHIFT 0
+
+/**** p2 register ****/
+/* Location of the input offset in the parser result vector */
+#define EC_EPE_RES_P2_IN_OFFSET_MASK     0x000003FF
+#define EC_EPE_RES_P2_IN_OFFSET_SHIFT    0
+
+/**** p3 register ****/
+/* Location of the input parse enable in the parser result vecto ... */
+#define EC_EPE_RES_P3_IN_PARSE_EN_MASK   0x000003FF
+#define EC_EPE_RES_P3_IN_PARSE_EN_SHIFT  0
+
+/**** p4 register ****/
+/* Location of the control bits in the parser result vector */
+#define EC_EPE_RES_P4_CTRL_BITS_MASK     0x000003FF
+#define EC_EPE_RES_P4_CTRL_BITS_SHIFT    0
+
+/**** p5 register ****/
+/* Location of the MAC DA in the parser result vector */
+#define EC_EPE_RES_P5_DA_MASK            0x000003FF
+#define EC_EPE_RES_P5_DA_SHIFT           0
+
+/**** p6 register ****/
+/* Location of the MAC SA in the parser result vector */
+#define EC_EPE_RES_P6_SA_MASK            0x000003FF
+#define EC_EPE_RES_P6_SA_SHIFT           0
+
+/**** p7 register ****/
+/* Location of the first VLAN in the parser result vector */
+#define EC_EPE_RES_P7_VLAN_1_MASK        0x000003FF
+#define EC_EPE_RES_P7_VLAN_1_SHIFT       0
+
+/**** p8 register ****/
+/* Location of the second VLAN in the parser result vector */
+#define EC_EPE_RES_P8_VLAN_2_MASK        0x000003FF
+#define EC_EPE_RES_P8_VLAN_2_SHIFT       0
+
+/**** p9 register ****/
+/* Location of the L3 protocol index in the parser result vector ... */
+#define EC_EPE_RES_P9_L3_PROT_INDEX_MASK 0x000003FF
+#define EC_EPE_RES_P9_L3_PROT_INDEX_SHIFT 0
+
+/**** p10 register ****/
+/* Location of the L3 offset in the parser result vector */
+#define EC_EPE_RES_P10_L3_OFFSET_MASK    0x000003FF
+#define EC_EPE_RES_P10_L3_OFFSET_SHIFT   0
+
+/**** p11 register ****/
+/* Location of the L3 SIP in the parser result vector */
+#define EC_EPE_RES_P11_L3_SIP_MASK       0x000003FF
+#define EC_EPE_RES_P11_L3_SIP_SHIFT      0
+
+/**** p12 register ****/
+/* Location of the L3 DIP in the parser result vector */
+#define EC_EPE_RES_P12_L3_DIP_MASK       0x000003FF
+#define EC_EPE_RES_P12_L3_DIP_SHIFT      0
+
+/**** p13 register ****/
+/* Location of the L3 priority in the parser result vector */
+#define EC_EPE_RES_P13_L3_PRIORITY_MASK  0x000003FF
+#define EC_EPE_RES_P13_L3_PRIORITY_SHIFT 0
+
+/**** p14 register ****/
+/* Location of the L3 header length in the parser result vector */
+#define EC_EPE_RES_P14_L3_HDR_LEN_MASK   0x000003FF
+#define EC_EPE_RES_P14_L3_HDR_LEN_SHIFT  0
+
+/**** p15 register ****/
+/* Location of the L4 protocol index in the parser result vector ... */
+#define EC_EPE_RES_P15_L4_PROT_INDEX_MASK 0x000003FF
+#define EC_EPE_RES_P15_L4_PROT_INDEX_SHIFT 0
+
+/**** p16 register ****/
+/* Location of the L4 source port in the parser result vector */
+#define EC_EPE_RES_P16_L4_SRC_PORT_MASK  0x000003FF
+#define EC_EPE_RES_P16_L4_SRC_PORT_SHIFT 0
+
+/**** p17 register ****/
+/* Location of the L4 destination port in the parser result vect ... */
+#define EC_EPE_RES_P17_L4_DST_PORT_MASK  0x000003FF
+#define EC_EPE_RES_P17_L4_DST_PORT_SHIFT 0
+
+/**** p18 register ****/
+/* Location of the L4 offset in the parser result vector */
+#define EC_EPE_RES_P18_L4_OFFSET_MASK    0x000003FF
+#define EC_EPE_RES_P18_L4_OFFSET_SHIFT   0
+
+/**** p19 register ****/
+/* Location of the Ether type in the parser result vector when w ... */
+#define EC_EPE_RES_P19_WOL_ETYPE_MASK    0x000003FF
+#define EC_EPE_RES_P19_WOL_ETYPE_SHIFT   0
+
+/**** p20 register ****/
+/* Location of the RoCE QP number field in the parser result vec ... */
+#define EC_EPE_RES_P20_ROCE_QPN_MASK     0x000003FF
+#define EC_EPE_RES_P20_ROCE_QPN_SHIFT    0
+
+/**** hdr_len register ****/
+/* Value for selecting table 1 */
+#define EC_EPE_H_HDR_LEN_TABLE_1_MASK    0x000000FF
+#define EC_EPE_H_HDR_LEN_TABLE_1_SHIFT   0
+/* Value for selecting table 2 */
+#define EC_EPE_H_HDR_LEN_TABLE_2_MASK    0x00FF0000
+#define EC_EPE_H_HDR_LEN_TABLE_2_SHIFT   16
+
+/**** comp_data register ****/
+/* Data 1 for comparison */
+#define EC_EPE_P_COMP_DATA_DATA_1_MASK   0x0000FFFF
+#define EC_EPE_P_COMP_DATA_DATA_1_SHIFT  0
+/* Data 2 for comparison
+[18:16] - Stage
+[24:19] - Branch ID */
+#define EC_EPE_P_COMP_DATA_DATA_2_MASK   0x01FF0000
+#define EC_EPE_P_COMP_DATA_DATA_2_SHIFT  16
+
+/**** comp_mask register ****/
+/* Data 1 for comparison */
+#define EC_EPE_P_COMP_MASK_DATA_1_MASK   0x0000FFFF
+#define EC_EPE_P_COMP_MASK_DATA_1_SHIFT  0
+/* Data 2 for comparison
+[18:16] - Stage
+[24:19] - Branch ID */
+#define EC_EPE_P_COMP_MASK_DATA_2_MASK   0x01FF0000
+#define EC_EPE_P_COMP_MASK_DATA_2_SHIFT  16
+
+/**** comp_ctrl register ****/
+/* Output result value */
+#define EC_EPE_P_COMP_CTRL_RES_MASK      0x0000001F
+#define EC_EPE_P_COMP_CTRL_RES_SHIFT     0
+/* Compare command for the data_1 field00 - Compare01 - <=10 - > ... */
+#define EC_EPE_P_COMP_CTRL_CMD_1_MASK    0x00030000
+#define EC_EPE_P_COMP_CTRL_CMD_1_SHIFT   16
+/* Compare command for the data_2 field 00 - Compare 01 - <= 10  ... */
+#define EC_EPE_P_COMP_CTRL_CMD_2_MASK    0x000C0000
+#define EC_EPE_P_COMP_CTRL_CMD_2_SHIFT   18
+/* Entry is valid */
+#define EC_EPE_P_COMP_CTRL_VALID         (1 << 31)
+
+/**** prot_act register ****/
+/* Drop indication for the selected protocol index */
+#define EC_EPE_A_PROT_ACT_DROP           (1 << 0)
+/* Mapping value Used when mapping the entire protocol index ran ... */
+#define EC_EPE_A_PROT_ACT_MAP_MASK       0x00000F00
+#define EC_EPE_A_PROT_ACT_MAP_SHIFT      8
+
+/**** thash_cfg_1 register ****/
+/* Hash function output selection:000 - [7:0]001 - [15:8]010 - [ ... */
+#define EC_RFW_THASH_CFG_1_OUT_SEL_MASK  0x00000007
+#define EC_RFW_THASH_CFG_1_OUT_SEL_SHIFT 0
+/* Selects between hash functions00 - toeplitz01 - CRC-3210 - 0x ... */
+#define EC_RFW_THASH_CFG_1_FUNC_SEL_MASK 0x00000300
+#define EC_RFW_THASH_CFG_1_FUNC_SEL_SHIFT 8
+/* Enable SIP/DIP swap if SIP<DIP */
+#define EC_RFW_THASH_CFG_1_ENABLE_IP_SWAP (1 << 16)
+/* Enable PORT swap if SPORT<DPORT */
+#define EC_RFW_THASH_CFG_1_ENABLE_PORT_SWAP (1 << 17)
+
+/**** mhash_cfg_1 register ****/
+/* Hash function output selection:000 - [7:0]001 - [15:8]010 - [ ... */
+#define EC_RFW_MHASH_CFG_1_OUT_SEL_MASK  0x00000007
+#define EC_RFW_MHASH_CFG_1_OUT_SEL_SHIFT 0
+/* Selects the input to the MAC hash function0 - DA1 - DA + SA ... */
+#define EC_RFW_MHASH_CFG_1_INPUT_SEL     (1 << 4)
+/* Selects between hash functions00 - toeplitz01 - CRC-3210 - 0x ... */
+#define EC_RFW_MHASH_CFG_1_FUNC_SEL_MASK 0x00000300
+#define EC_RFW_MHASH_CFG_1_FUNC_SEL_SHIFT 8
+
+/**** hdr_split register ****/
+/* Default header length for header split */
+#define EC_RFW_HDR_SPLIT_DEF_LEN_MASK    0x0000FFFF
+#define EC_RFW_HDR_SPLIT_DEF_LEN_SHIFT   0
+/* Enable header split operation */
+#define EC_RFW_HDR_SPLIT_EN              (1 << 16)
+
+/**** meta_err register ****/
+/* Mask for error 1 in the Rx descriptor */
+#define EC_RFW_META_ERR_MASK_1_MASK      0x000003FF
+#define EC_RFW_META_ERR_MASK_1_SHIFT     0
+/* Mask for error 2 in the Rx descriptor */
+#define EC_RFW_META_ERR_MASK_2_MASK      0x03FF0000
+#define EC_RFW_META_ERR_MASK_2_SHIFT     16
+
+/**** meta register ****/
+/* Selection of the L3 offset source: 1 - Inner packet 0 - Outer ... */
+#define EC_RFW_META_L3_LEN_SEL           (1 << 0)
+/* Selection of the L3 offset source:1 - Inner packet0 - Outer p ... */
+#define EC_RFW_META_L3_OFFSET_SEL        (1 << 1)
+/* Selection of the l3 protocol index source: 1 - Inner packet 0 ... */
+#define EC_RFW_META_L3_PROT_SEL          (1 << 2)
+/* Selection of the l4 protocol index source:  1 - Inner packet  ... */
+#define EC_RFW_META_L4_PROT_SEL          (1 << 3)
+/* Selects how to calculate the L3 header length when L3 is IpPv ... */
+#define EC_RFW_META_L3_LEN_CALC          (1 << 4)
+/* Selection of the IPv4 fragment indication source:  1 - Inner  ... */
+#define EC_RFW_META_FRAG_SEL             (1 << 5)
+/* Selection of the L4 offset source:1 - Inner packet0 - Outer p ... */
+#define EC_RFW_META_L4_OFFSET_SEL        (1 << 6)
+
+/**** filter register ****/
+/* Filter undetected MAC DA */
+#define EC_RFW_FILTER_UNDET_MAC          (1 << 0)
+/* Filter specific MAC DA based on MAC table output. */
+#define EC_RFW_FILTER_DET_MAC            (1 << 1)
+/* Filter all tagged. */
+#define EC_RFW_FILTER_TAGGED             (1 << 2)
+/* Filter all untagged. */
+#define EC_RFW_FILTER_UNTAGGED           (1 << 3)
+/* Filter all broadcast. */
+#define EC_RFW_FILTER_BC                 (1 << 4)
+/* Filter all multicast. */
+#define EC_RFW_FILTER_MC                 (1 << 5)
+/* Filter based on parsing output (used to drop selected protoco ... */
+#define EC_RFW_FILTER_PARSE              (1 << 6)
+/* Filter packet based on VLAN table output. */
+#define EC_RFW_FILTER_VLAN_VID           (1 << 7)
+/* Filter packet based on control table output. */
+#define EC_RFW_FILTER_CTRL_TABLE         (1 << 8)
+/* Filter packet based on protocol index action register. */
+#define EC_RFW_FILTER_PROT_INDEX         (1 << 9)
+/* Filter packet based on WoL decision */
+#define EC_RFW_FILTER_WOL                (1 << 10)
+/* Override filter decision and forward to default UDMA/queue;dr ... */
+#define EC_RFW_FILTER_OR_UNDET_MAC       (1 << 16)
+/* Override filter decision and forward to default UDMA/queue;Dr ... */
+#define EC_RFW_FILTER_OR_DET_MAC         (1 << 17)
+/* Override filter decision and forward to default UDMA/queue;Dr ... */
+#define EC_RFW_FILTER_OR_TAGGED          (1 << 18)
+/* Override filter decision and forward to default UDMA/queue;Dr ... */
+#define EC_RFW_FILTER_OR_UNTAGGED        (1 << 19)
+/* Override filter decision and forward to default UDMA/queue;Dr ... */
+#define EC_RFW_FILTER_OR_BC              (1 << 20)
+/* Override filter decision and forward to default UDMA/queue;Dr ... */
+#define EC_RFW_FILTER_OR_MC              (1 << 21)
+/* Override filter decision and forward to default UDMA/queue;Dr ... */
+#define EC_RFW_FILTER_OR_PARSE           (1 << 22)
+/* Override filter decision and forward to default UDMA/queue;Dr ... */
+#define EC_RFW_FILTER_OR_VLAN_VID        (1 << 23)
+/* Override filter decision and forward to default UDMA/queue;Dr ... */
+#define EC_RFW_FILTER_OR_CTRL_TABLE      (1 << 24)
+/* Override filter decision and forward to default UDMA/queue;Dr ... */
+#define EC_RFW_FILTER_OR_PROT_INDEX      (1 << 25)
+/* Override filter decision and forward to default UDMA/queue;Dr ... */
+#define EC_RFW_FILTER_OR_WOL             (1 << 26)
+
+/**** thash_table_addr register ****/
+/* Address for accessing the table */
+#define EC_RFW_THASH_TABLE_ADDR_VAL_MASK 0x000000FF
+#define EC_RFW_THASH_TABLE_ADDR_VAL_SHIFT 0
+
+/**** thash_table_data register ****/
+/* Table data (valid only after configuring the table address re ... */
+#define EC_RFW_THASH_TABLE_DATA_VAL_MASK 0x00003FFF
+#define EC_RFW_THASH_TABLE_DATA_VAL_SHIFT 0
+
+/**** mhash_table_addr register ****/
+/* Address for accessing the table */
+#define EC_RFW_MHASH_TABLE_ADDR_VAL_MASK 0x000000FF
+#define EC_RFW_MHASH_TABLE_ADDR_VAL_SHIFT 0
+
+/**** mhash_table_data register ****/
+/* Table data (valid only after configuring the table address re ... */
+#define EC_RFW_MHASH_TABLE_DATA_VAL_MASK 0x0000003F
+#define EC_RFW_MHASH_TABLE_DATA_VAL_SHIFT 0
+
+/**** vid_table_addr register ****/
+/* Address for accessing the table */
+#define EC_RFW_VID_TABLE_ADDR_VAL_MASK   0x00000FFF
+#define EC_RFW_VID_TABLE_ADDR_VAL_SHIFT  0
+
+/**** vid_table_data register ****/
+/* Table data (valid only after configuring the table address re ... */
+#define EC_RFW_VID_TABLE_DATA_VAL_MASK   0x0000003F
+#define EC_RFW_VID_TABLE_DATA_VAL_SHIFT  0
+
+/**** pbits_table_addr register ****/
+/* Address for accessing the table */
+#define EC_RFW_PBITS_TABLE_ADDR_VAL_MASK 0x00000007
+#define EC_RFW_PBITS_TABLE_ADDR_VAL_SHIFT 0
+
+/**** pbits_table_data register ****/
+/* VLAN P-bits to internal priority mapping */
+#define EC_RFW_PBITS_TABLE_DATA_VAL_MASK 0x00000007
+#define EC_RFW_PBITS_TABLE_DATA_VAL_SHIFT 0
+
+/**** dscp_table_addr register ****/
+/* Address for accessing the table */
+#define EC_RFW_DSCP_TABLE_ADDR_VAL_MASK  0x000000FF
+#define EC_RFW_DSCP_TABLE_ADDR_VAL_SHIFT 0
+
+/**** dscp_table_data register ****/
+/* IPv4 DSCP to internal priority mapping */
+#define EC_RFW_DSCP_TABLE_DATA_VAL_MASK  0x00000007
+#define EC_RFW_DSCP_TABLE_DATA_VAL_SHIFT 0
+
+/**** tc_table_addr register ****/
+/* Address for accessing the table */
+#define EC_RFW_TC_TABLE_ADDR_VAL_MASK    0x000000FF
+#define EC_RFW_TC_TABLE_ADDR_VAL_SHIFT   0
+
+/**** tc_table_data register ****/
+/* IPv6 TC to internal priority mapping */
+#define EC_RFW_TC_TABLE_DATA_VAL_MASK    0x00000007
+#define EC_RFW_TC_TABLE_DATA_VAL_SHIFT   0
+
+/**** ctrl_table_addr register ****/
+/* Address for accessing the table[0] - VLAN table control out[1 ... */
+#define EC_RFW_CTRL_TABLE_ADDR_VAL_MASK  0x000007FF
+#define EC_RFW_CTRL_TABLE_ADDR_VAL_SHIFT 0
+
+/**** ctrl_table_data register ****/
+/* Control table output for selecting the forwarding MUXs[3:0] - ... */
+#define EC_RFW_CTRL_TABLE_DATA_VAL_MASK  0x000FFFFF
+#define EC_RFW_CTRL_TABLE_DATA_VAL_SHIFT 0
+
+/**** out_cfg register ****/
+/* Number of MetaData at the end of the packet1 - One MetaData b ... */
+#define EC_RFW_OUT_CFG_META_CNT_MASK     0x00000003
+#define EC_RFW_OUT_CFG_META_CNT_SHIFT    0
+/* Enable packet drop */
+#define EC_RFW_OUT_CFG_DROP_EN           (1 << 2)
+/* Swap output byte order */
+#define EC_RFW_OUT_CFG_SWAP_OUT_BYTE     (1 << 3)
+/* Enable the insertion of the MACsec decoding result into the M ... */
+#define EC_RFW_OUT_CFG_EN_MACSEC_DEC     (1 << 4)
+/* Sample time of the time stamp:0 - SOP (for 10G MAC)1 - EOP (f ... */
+#define EC_RFW_OUT_CFG_TIMESTAMP_SAMPLE  (1 << 5)
+/* Determines which queue to write into the packet header0 - Ori ... */
+#define EC_RFW_OUT_CFG_QUEUE_OR_SEL   (1 << 6)
+/* Determines the logic of the drop indication:0 - Sample the dr ... */
+#define EC_RFW_OUT_CFG_DROP_LOGIC_SEL (1 << 7)
+/* Determines the logic of the drop indication:0 - Sample the dr ... */
+#define EC_RFW_OUT_CFG_PKT_TYPE_DEF   (1 << 8)
+
+/**** fsm_table_addr register ****/
+/* Address for accessing the table :[2:0] - Outer header control ... */
+#define EC_RFW_FSM_TABLE_ADDR_VAL_MASK   0x0000007F
+#define EC_RFW_FSM_TABLE_ADDR_VAL_SHIFT  0
+
+/**** fsm_table_data register ****/
+/* Flow steering mechanism output selectors:[1:0] - Input select ... */
+#define EC_RFW_FSM_TABLE_DATA_VAL_MASK   0x00000007
+#define EC_RFW_FSM_TABLE_DATA_VAL_SHIFT  0
+
+/**** ctrl_sel register ****/
+/* Packet type (UC/MC/BC) for the control table */
+#define EC_RFW_CTRL_SEL_PKT_TYPE         (1 << 0)
+/* L3 protocol index for the control table */
+#define EC_RFW_CTRL_SEL_L3_PROTOCOL      (1 << 1)
+/* Selects the content and structure of the control table addres ... */
+#define EC_RFW_CTRL_SEL_ADDR_MASK        0x0000000C
+#define EC_RFW_CTRL_SEL_ADDR_SHIFT       2
+
+/**** default_vlan register ****/
+/* Default VLAN data, used for untagged packets */
+#define EC_RFW_DEFAULT_VLAN_DATA_MASK    0x0000FFFF
+#define EC_RFW_DEFAULT_VLAN_DATA_SHIFT   0
+
+/**** default_hash register ****/
+/* Default UDMA */
+#define EC_RFW_DEFAULT_HASH_UDMA_MASK    0x0000000F
+#define EC_RFW_DEFAULT_HASH_UDMA_SHIFT   0
+/* Default queue */
+#define EC_RFW_DEFAULT_HASH_QUEUE_MASK   0x00030000
+#define EC_RFW_DEFAULT_HASH_QUEUE_SHIFT  16
+
+/**** default_or register ****/
+/* Default UDMA */
+#define EC_RFW_DEFAULT_OR_UDMA_MASK      0x0000000F
+#define EC_RFW_DEFAULT_OR_UDMA_SHIFT     0
+/* Default queue */
+#define EC_RFW_DEFAULT_OR_QUEUE_MASK     0x00030000
+#define EC_RFW_DEFAULT_OR_QUEUE_SHIFT    16
+
+/**** checksum register ****/
+/* Check that the length in the UDP header matches the length in ... */
+#define EC_RFW_CHECKSUM_UDP_LEN          (1 << 0)
+/* Select the header that will be used for the checksum when a t ... */
+#define EC_RFW_CHECKSUM_HDR_SEL          (1 << 1)
+/* Enable L4 checksum when L3 fragmentation is detected */
+#define EC_RFW_CHECKSUM_L4_FRAG_EN       (1 << 2)
+/* L3 Checksum result selection for the Metadata descriptor0 - O ... */
+#define EC_RFW_CHECKSUM_L3_CKS_SEL       (1 << 4)
+/* L4 Checksum result selection for the Metadata descriptor0 - O ... */
+#define EC_RFW_CHECKSUM_L4_CKS_SEL       (1 << 5)
+
+/**** lro_cfg_1 register ****/
+/* Select the header that will be used for the LRO offload engin ... */
+#define EC_RFW_LRO_CFG_1_HDR_SEL         (1 << 0)
+/* Select the L2 header that will be used for the LRO offload en ... */
+#define EC_RFW_LRO_CFG_1_HDR_L2_SEL      (1 << 1)
+
+/**** lro_check_ipv4 register ****/
+/* Check version field. */
+#define EC_RFW_LRO_CHECK_IPV4_VER        (1 << 0)
+/* Check IHL field == 5. */
+#define EC_RFW_LRO_CHECK_IPV4_IHL_0      (1 << 1)
+/* Check IHL field >= 5. */
+#define EC_RFW_LRO_CHECK_IPV4_IHL_1      (1 << 2)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_IPV4_IHL_2      (1 << 3)
+/* Compare DSCP to previous packet. */
+#define EC_RFW_LRO_CHECK_IPV4_DSCP       (1 << 4)
+/* Check that Total length >= lro_ipv4_tlen_val. */
+#define EC_RFW_LRO_CHECK_IPV4_TLEN       (1 << 5)
+/* Compare to previous packet value +1. */
+#define EC_RFW_LRO_CHECK_IPV4_ID         (1 << 6)
+/* Compare to lro_ipv4_flags_val with lro_ipv4_flags_mask_0. */
+#define EC_RFW_LRO_CHECK_IPV4_FLAGS_0    (1 << 7)
+/* Compare to previous packet flags with lro_ipv4_flags_mask_1. */
+#define EC_RFW_LRO_CHECK_IPV4_FLAGS_1    (1 << 8)
+/* Verify that the fragment offset field is 0. */
+#define EC_RFW_LRO_CHECK_IPV4_FRAG       (1 << 9)
+/* Verify that the TTL value >0. */
+#define EC_RFW_LRO_CHECK_IPV4_TTL_0      (1 << 10)
+/* Compare TTL value to previous packet. */
+#define EC_RFW_LRO_CHECK_IPV4_TTL_1      (1 << 11)
+/* Compare to previous packet protocol field. */
+#define EC_RFW_LRO_CHECK_IPV4_PROT_0     (1 << 12)
+/* Verify that the protocol is TCP or UDP. */
+#define EC_RFW_LRO_CHECK_IPV4_PROT_1     (1 << 13)
+/* Verify that the check sum is correct. */
+#define EC_RFW_LRO_CHECK_IPV4_CHECKSUM   (1 << 14)
+/* Compare SIP to previous packet. */
+#define EC_RFW_LRO_CHECK_IPV4_SIP        (1 << 15)
+/* Compare DIP to previous packet. */
+#define EC_RFW_LRO_CHECK_IPV4_DIP        (1 << 16)
+
+/**** lro_ipv4 register ****/
+/* Total length minimum value */
+#define EC_RFW_LRO_IPV4_TLEN_VAL_MASK    0x0000FFFF
+#define EC_RFW_LRO_IPV4_TLEN_VAL_SHIFT   0
+/* Flags value  */
+#define EC_RFW_LRO_IPV4_FLAGS_VAL_MASK   0x00070000
+#define EC_RFW_LRO_IPV4_FLAGS_VAL_SHIFT  16
+/* Flags mask */
+#define EC_RFW_LRO_IPV4_FLAGS_MASK_0_MASK 0x00380000
+#define EC_RFW_LRO_IPV4_FLAGS_MASK_0_SHIFT 19
+/* Flags mask */
+#define EC_RFW_LRO_IPV4_FLAGS_MASK_1_MASK 0x01C00000
+#define EC_RFW_LRO_IPV4_FLAGS_MASK_1_SHIFT 22
+/* Version value */
+#define EC_RFW_LRO_IPV4_VER_MASK         0xF0000000
+#define EC_RFW_LRO_IPV4_VER_SHIFT        28
+
+/**** lro_check_ipv6 register ****/
+/* Check version field */
+#define EC_RFW_LRO_CHECK_IPV6_VER        (1 << 0)
+/* Compare TC to previous packet. */
+#define EC_RFW_LRO_CHECK_IPV6_TC         (1 << 1)
+/* Compare flow label field to previous packet. */
+#define EC_RFW_LRO_CHECK_IPV6_FLOW       (1 << 2)
+/* Check that Total length >= lro_ipv6_pen_val. */
+#define EC_RFW_LRO_CHECK_IPV6_PLEN       (1 << 3)
+/* Compare to previous packet next header field. */
+#define EC_RFW_LRO_CHECK_IPV6_NEXT_0     (1 << 4)
+/* Verify that the next header is TCP or UDP. */
+#define EC_RFW_LRO_CHECK_IPV6_NEXT_1     (1 << 5)
+/* Verify that hop limit is >0. */
+#define EC_RFW_LRO_CHECK_IPV6_HOP_0      (1 << 6)
+/* Compare hop limit to previous packet. */
+#define EC_RFW_LRO_CHECK_IPV6_HOP_1      (1 << 7)
+/* Compare SIP to previous packet. */
+#define EC_RFW_LRO_CHECK_IPV6_SIP        (1 << 8)
+/* Compare DIP to previous packet. */
+#define EC_RFW_LRO_CHECK_IPV6_DIP        (1 << 9)
+
+/**** lro_ipv6 register ****/
+/* Payload length minimum value */
+#define EC_RFW_LRO_IPV6_PLEN_VAL_MASK    0x0000FFFF
+#define EC_RFW_LRO_IPV6_PLEN_VAL_SHIFT   0
+/* Version value */
+#define EC_RFW_LRO_IPV6_VER_MASK         0x0F000000
+#define EC_RFW_LRO_IPV6_VER_SHIFT        24
+
+/**** lro_check_tcp register ****/
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_TCP_SRC_PORT    (1 << 0)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_TCP_DST_PORT    (1 << 1)
+/* If (SYN == 1), don't check  */
+#define EC_RFW_LRO_CHECK_TCP_SN          (1 << 2)
+/* Check data offset field == 5. */
+#define EC_RFW_LRO_CHECK_TCP_OFFSET_0    (1 << 3)
+/* Check data offset field >= 5. */
+#define EC_RFW_LRO_CHECK_TCP_OFFSET_1    (1 << 4)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_TCP_OFFSET_2    (1 << 5)
+/* Compare reserved field to lro_tcp_res. */
+#define EC_RFW_LRO_CHECK_TCP_RES         (1 << 6)
+/* Compare to lro_tcp_ecn_val and lro_tcp_ecn_mask_0. */
+#define EC_RFW_LRO_CHECK_TCP_ECN_0       (1 << 7)
+/* Compare to previous packet ECN field with lro_tcp_ecn_mask_1 */
+#define EC_RFW_LRO_CHECK_TCP_ECN_1       (1 << 8)
+/* Compare to lro_tcp_ctrl_val and lro_tcp_ctrl_mask_0. */
+#define EC_RFW_LRO_CHECK_TCP_CTRL_0      (1 << 9)
+/* Compare to previous packet ECN field with lro_tcp_ctrl_mask_1 */
+#define EC_RFW_LRO_CHECK_TCP_CTRL_1      (1 << 10)
+/* Verify that check sum is correct. */
+#define EC_RFW_LRO_CHECK_TCP_CHECKSUM    (1 << 11)
+
+/**** lro_tcp register ****/
+/* Reserved field default value */
+#define EC_RFW_LRO_TCP_RES_MASK          0x00000007
+#define EC_RFW_LRO_TCP_RES_SHIFT         0
+/* ECN field value */
+#define EC_RFW_LRO_TCP_ECN_VAL_MASK      0x00000038
+#define EC_RFW_LRO_TCP_ECN_VAL_SHIFT     3
+/* ECN field mask */
+#define EC_RFW_LRO_TCP_ECN_MASK_0_MASK   0x000001C0
+#define EC_RFW_LRO_TCP_ECN_MASK_0_SHIFT  6
+/* ECN field mask */
+#define EC_RFW_LRO_TCP_ECN_MASK_1_MASK   0x00000E00
+#define EC_RFW_LRO_TCP_ECN_MASK_1_SHIFT  9
+/* Control field value */
+#define EC_RFW_LRO_TCP_CTRL_VAL_MASK     0x0003F000
+#define EC_RFW_LRO_TCP_CTRL_VAL_SHIFT    12
+/* Control field mask */
+#define EC_RFW_LRO_TCP_CTRL_MASK_0_MASK  0x00FC0000
+#define EC_RFW_LRO_TCP_CTRL_MASK_0_SHIFT 18
+/* Control field mask */
+#define EC_RFW_LRO_TCP_CTRL_MASK_1_MASK  0x3F000000
+#define EC_RFW_LRO_TCP_CTRL_MASK_1_SHIFT 24
+
+/**** lro_check_udp register ****/
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_UDP_SRC_PORT    (1 << 0)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_UDP_DST_PORT    (1 << 1)
+/* Verify that check sum is correct. */
+#define EC_RFW_LRO_CHECK_UDP_CHECKSUM    (1 << 2)
+
+/**** lro_check_l2 register ****/
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_L2_MAC_DA       (1 << 0)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_L2_MAC_SA       (1 << 1)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_L2_VLAN_1_EXIST (1 << 2)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_L2_VLAN_1_VID   (1 << 3)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_L2_VLAN_1_CFI   (1 << 4)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_L2_VLAN_1_PBITS (1 << 5)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_L2_VLAN_2_EXIST (1 << 6)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_L2_VLAN_2_VID   (1 << 7)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_L2_VLAN_2_CFI   (1 << 8)
+/* Compare to previous packet. */
+#define EC_RFW_LRO_CHECK_L2_VLAN_2_PBITS (1 << 9)
+/* Verify that the FCS is correct. */
+#define EC_RFW_LRO_CHECK_L2_FCS          (1 << 10)
+
+/**** lro_check_gen register ****/
+/* Compare to previous packet */
+#define EC_RFW_LRO_CHECK_GEN_UDMA        (1 << 0)
+/* Compare to previous packet */
+#define EC_RFW_LRO_CHECK_GEN_QUEUE       (1 << 1)
+
+/**** lro_store register ****/
+/* Store packet information if protocol match. */
+#define EC_RFW_LRO_STORE_IPV4            (1 << 0)
+/* Store packet information if protocol match. */
+#define EC_RFW_LRO_STORE_IPV6            (1 << 1)
+/* Store packet information if protocol match. */
+#define EC_RFW_LRO_STORE_TCP             (1 << 2)
+/* Store packet information if protocol match. */
+#define EC_RFW_LRO_STORE_UDP             (1 << 3)
+/* Store packet if IPv4 flags match the register value with mask */
+#define EC_RFW_LRO_STORE_IPV4_FLAGS_VAL_MASK 0x00000070
+#define EC_RFW_LRO_STORE_IPV4_FLAGS_VAL_SHIFT 4
+/* Mask for IPv4 flags */
+#define EC_RFW_LRO_STORE_IPV4_FLAGS_MASK_MASK 0x00000380
+#define EC_RFW_LRO_STORE_IPV4_FLAGS_MASK_SHIFT 7
+/* Store packet if TCP control and ECN match the register value  ... */
+#define EC_RFW_LRO_STORE_TCP_CTRL_VAL_MASK 0x0007FC00
+#define EC_RFW_LRO_STORE_TCP_CTRL_VAL_SHIFT 10
+/* Mask for TCP control */
+#define EC_RFW_LRO_STORE_TCP_CTRL_MASK_MASK 0x0FF80000
+#define EC_RFW_LRO_STORE_TCP_CTRL_MASK_SHIFT 19
+
+/**** vid_table_def register ****/
+/* Table default data (valid only after configuring the table ad ... */
+#define EC_RFW_VID_TABLE_DEF_VAL_MASK    0x0000003F
+#define EC_RFW_VID_TABLE_DEF_VAL_SHIFT   0
+/* Default data selection
+0 - Default value
+1 - Table data out */
+#define EC_RFW_VID_TABLE_DEF_SEL         (1 << 6)
+
+/**** ctrl_table_def register ****/
+/* Control table output for selecting the forwarding MUXs [3:0]  ... */
+#define EC_RFW_CTRL_TABLE_DEF_VAL_MASK   0x000FFFFF
+#define EC_RFW_CTRL_TABLE_DEF_VAL_SHIFT  0
+/* Default data selection 0 - Default value 1 - Table data out ... */
+#define EC_RFW_CTRL_TABLE_DEF_SEL        (1 << 20)
+
+/**** cfg_a_0 register ****/
+/* Selection of the L3 checksum result in the Metadata00 - L3 ch ... */
+#define EC_RFW_CFG_A_0_META_L3_CHK_RES_SEL_MASK 0x00000003
+#define EC_RFW_CFG_A_0_META_L3_CHK_RES_SEL_SHIFT 0
+/* Selection of the L4 checksum result in the Metadata0 - L4 che ... */
+#define EC_RFW_CFG_A_0_META_L4_CHK_RES_SEL (1 << 2)
+/* Selection of the LRO_context_value result in the Metadata0 -  ... */
+#define EC_RFW_CFG_A_0_LRO_CONTEXT_SEL   (1 << 4)
+
+/**** thash_cfg_3 register ****/
+/* Enable Hash value for RoCE packets in outer packet. */
+#define EC_RFW_THASH_CFG_3_ENABLE_OUTER_ROCE (1 << 0)
+/* Enable Hash value for RoCE packets in inner packet. */
+#define EC_RFW_THASH_CFG_3_ENABLE_INNER_ROCE (1 << 1)
+/* Enable Hash value for FcoE packets in outer packet. */
+#define EC_RFW_THASH_CFG_3_ENABLE_OUTER_FCOE (1 << 2)
+/* Enable Hash value for FcoE packets in inner packet. */
+#define EC_RFW_THASH_CFG_3_ENABLE_INNER_FCOE (1 << 3)
+
+/**** thash_mask_outer_ipv6 register ****/
+/* IPv6 source IP address */
+#define EC_RFW_THASH_MASK_OUTER_IPV6_SRC_MASK 0x0000FFFF
+#define EC_RFW_THASH_MASK_OUTER_IPV6_SRC_SHIFT 0
+/* IPv6 destination IP address */
+#define EC_RFW_THASH_MASK_OUTER_IPV6_DST_MASK 0xFFFF0000
+#define EC_RFW_THASH_MASK_OUTER_IPV6_DST_SHIFT 16
+
+/**** thash_mask_outer register ****/
+/* IPv4 source IP address */
+#define EC_RFW_THASH_MASK_OUTER_IPV4_SRC_MASK 0x0000000F
+#define EC_RFW_THASH_MASK_OUTER_IPV4_SRC_SHIFT 0
+/* IPv4 destination IP address */
+#define EC_RFW_THASH_MASK_OUTER_IPV4_DST_MASK 0x000000F0
+#define EC_RFW_THASH_MASK_OUTER_IPV4_DST_SHIFT 4
+/* TCP source port */
+#define EC_RFW_THASH_MASK_OUTER_TCP_SRC_PORT_MASK 0x00000300
+#define EC_RFW_THASH_MASK_OUTER_TCP_SRC_PORT_SHIFT 8
+/* TCP destination port */
+#define EC_RFW_THASH_MASK_OUTER_TCP_DST_PORT_MASK 0x00000C00
+#define EC_RFW_THASH_MASK_OUTER_TCP_DST_PORT_SHIFT 10
+/* UDP source port */
+#define EC_RFW_THASH_MASK_OUTER_UDP_SRC_PORT_MASK 0x00003000
+#define EC_RFW_THASH_MASK_OUTER_UDP_SRC_PORT_SHIFT 12
+/* UDP destination port */
+#define EC_RFW_THASH_MASK_OUTER_UDP_DST_PORT_MASK 0x0000C000
+#define EC_RFW_THASH_MASK_OUTER_UDP_DST_PORT_SHIFT 14
+
+/**** thash_mask_inner_ipv6 register ****/
+/* IPv6 source IP address */
+#define EC_RFW_THASH_MASK_INNER_IPV6_SRC_MASK 0x0000FFFF
+#define EC_RFW_THASH_MASK_INNER_IPV6_SRC_SHIFT 0
+/* IPv6 destination IP address */
+#define EC_RFW_THASH_MASK_INNER_IPV6_DST_MASK 0xFFFF0000
+#define EC_RFW_THASH_MASK_INNER_IPV6_DST_SHIFT 16
+
+/**** thash_mask_inner register ****/
+/* IPv4 source IP address */
+#define EC_RFW_THASH_MASK_INNER_IPV4_SRC_MASK 0x0000000F
+#define EC_RFW_THASH_MASK_INNER_IPV4_SRC_SHIFT 0
+/* IPv4 destination IP address */
+#define EC_RFW_THASH_MASK_INNER_IPV4_DST_MASK 0x000000F0
+#define EC_RFW_THASH_MASK_INNER_IPV4_DST_SHIFT 4
+/* TCP source port */
+#define EC_RFW_THASH_MASK_INNER_TCP_SRC_PORT_MASK 0x00000300
+#define EC_RFW_THASH_MASK_INNER_TCP_SRC_PORT_SHIFT 8
+/* TCP destination port */
+#define EC_RFW_THASH_MASK_INNER_TCP_DST_PORT_MASK 0x00000C00
+#define EC_RFW_THASH_MASK_INNER_TCP_DST_PORT_SHIFT 10
+/* UDP source port */
+#define EC_RFW_THASH_MASK_INNER_UDP_SRC_PORT_MASK 0x00003000
+#define EC_RFW_THASH_MASK_INNER_UDP_SRC_PORT_SHIFT 12
+/* UDP destination port */
+#define EC_RFW_THASH_MASK_INNER_UDP_DST_PORT_MASK 0x0000C000
+#define EC_RFW_THASH_MASK_INNER_UDP_DST_PORT_SHIFT 14
+
+/**** def_cfg register ****/
+/* Number of padding bytes to add at the beginning of each Ether ... */
+#define EC_RFW_UDMA_DEF_CFG_RX_PAD_MASK  0x0000003F
+#define EC_RFW_UDMA_DEF_CFG_RX_PAD_SHIFT 0
+
+/**** queue register ****/
+/* Mapping between priority and queue number */
+#define EC_RFW_PRIORITY_QUEUE_MAP_MASK   0x00000003
+#define EC_RFW_PRIORITY_QUEUE_MAP_SHIFT  0
+
+/**** opt_1 register ****/
+/* Default UDMA for forwarding  */
+#define EC_RFW_DEFAULT_OPT_1_UDMA_MASK   0x0000000F
+#define EC_RFW_DEFAULT_OPT_1_UDMA_SHIFT  0
+/* Default priority for forwarding */
+#define EC_RFW_DEFAULT_OPT_1_PRIORITY_MASK 0x00000700
+#define EC_RFW_DEFAULT_OPT_1_PRIORITY_SHIFT 8
+/* Default queue for forwarding */
+#define EC_RFW_DEFAULT_OPT_1_QUEUE_MASK  0x00030000
+#define EC_RFW_DEFAULT_OPT_1_QUEUE_SHIFT 16
+
+/**** data_h register ****/
+/* MAC address data  */
+#define EC_FWD_MAC_DATA_H_VAL_MASK       0x0000FFFF
+#define EC_FWD_MAC_DATA_H_VAL_SHIFT      0
+
+/**** mask_h register ****/
+/* MAC address mask  */
+#define EC_FWD_MAC_MASK_H_VAL_MASK       0x0000FFFF
+#define EC_FWD_MAC_MASK_H_VAL_SHIFT      0
+
+/**** ctrl register ****/
+/* Control value for Rx forwarding engine[0] - Drop indication[2 ... */
+#define EC_FWD_MAC_CTRL_RX_VAL_MASK      0x000001FF
+#define EC_FWD_MAC_CTRL_RX_VAL_SHIFT     0
+
+/* Drop indication */
+#define EC_FWD_MAC_CTRL_RX_VAL_DROP		(1 << 0)
+
+/* control table command input */
+#define EC_FWD_MAC_CTRL_RX_VAL_CTRL_CMD_MASK	0x00000006
+#define EC_FWD_MAC_CTRL_RX_VAL_CTRL_CMD_SHIFT	1
+
+/* UDMA selection */
+#define EC_FWD_MAC_CTRL_RX_VAL_UDMA_MASK	0x000000078
+#define EC_FWD_MAC_CTRL_RX_VAL_UDMA_SHIFT	3
+
+/* queue number */
+#define EC_FWD_MAC_CTRL_RX_VAL_QID_MASK		0x00000180
+#define EC_FWD_MAC_CTRL_RX_VAL_QID_SHIFT	7
+
+/* Entry is valid for Rx forwarding engine. */
+#define EC_FWD_MAC_CTRL_RX_VALID         (1 << 15)
+/* Control value for Tx forwarding engine */
+#define EC_FWD_MAC_CTRL_TX_VAL_MASK      0x001F0000
+#define EC_FWD_MAC_CTRL_TX_VAL_SHIFT     16
+/* Entry is valid for Tx forwarding engine. */
+#define EC_FWD_MAC_CTRL_TX_VALID         (1 << 31)
+
+/**** uc register ****/
+/* timer max value for waiting for a stream to be ready to accep ... */
+#define EC_MSW_UC_TIMER_MASK             0x0000FFFF
+#define EC_MSW_UC_TIMER_SHIFT            0
+/* Drop packet if target queue in the UDMA is full */
+#define EC_MSW_UC_Q_FULL_DROP_MASK       0x000F0000
+#define EC_MSW_UC_Q_FULL_DROP_SHIFT      16
+/* Drop packet if timer expires. */
+#define EC_MSW_UC_TIMER_DROP_MASK        0x0F000000
+#define EC_MSW_UC_TIMER_DROP_SHIFT       24
+
+/**** mc register ****/
+/* Timer max value for waiting for a stream to be ready to accep ... */
+#define EC_MSW_MC_TIMER_MASK             0x0000FFFF
+#define EC_MSW_MC_TIMER_SHIFT            0
+/* Drop packet if target queue in UDMA is full. */
+#define EC_MSW_MC_Q_FULL_DROP_MASK       0x000F0000
+#define EC_MSW_MC_Q_FULL_DROP_SHIFT      16
+/* Drop packet if timer expires. */
+#define EC_MSW_MC_TIMER_DROP_MASK        0x0F000000
+#define EC_MSW_MC_TIMER_DROP_SHIFT       24
+
+/**** bc register ****/
+/* Timer max value for waiting for a stream to be ready to accep ... */
+#define EC_MSW_BC_TIMER_MASK             0x0000FFFF
+#define EC_MSW_BC_TIMER_SHIFT            0
+/* Drop packet if target queue in UDMA is full. */
+#define EC_MSW_BC_Q_FULL_DROP_MASK       0x000F0000
+#define EC_MSW_BC_Q_FULL_DROP_SHIFT      16
+/* Drop packet if timer expires. */
+#define EC_MSW_BC_TIMER_DROP_MASK        0x0F000000
+#define EC_MSW_BC_TIMER_DROP_SHIFT       24
+
+/**** in_cfg register ****/
+/* Swap input bytes order */
+#define EC_TSO_IN_CFG_SWAP_BYTES         (1 << 0)
+/* Selects strict priority or round robin scheduling between GDM ... */
+#define EC_TSO_IN_CFG_SEL_SP_RR          (1 << 1)
+/* Selects scheduler numbering direction */
+#define EC_TSO_IN_CFG_SEL_SCH_DIR        (1 << 2)
+/* Minimum L2 packet size (not including FCS) */
+#define EC_TSO_IN_CFG_L2_MIN_SIZE_MASK   0x00007F00
+#define EC_TSO_IN_CFG_L2_MIN_SIZE_SHIFT  8
+/* Swap input bytes order */
+#define EC_TSO_IN_CFG_SP_INIT_VAL_MASK   0x000F0000
+#define EC_TSO_IN_CFG_SP_INIT_VAL_SHIFT  16
+
+/**** cache_table_addr register ****/
+/* Address for accessing the table */
+#define EC_TSO_CACHE_TABLE_ADDR_VAL_MASK 0x0000000F
+#define EC_TSO_CACHE_TABLE_ADDR_VAL_SHIFT 0
+
+/**** ctrl_first register ****/
+/* Data to be written into the control BIS. */
+#define EC_TSO_CTRL_FIRST_DATA_MASK      0x000001FF
+#define EC_TSO_CTRL_FIRST_DATA_SHIFT     0
+/* Mask for control bits */
+#define EC_TSO_CTRL_FIRST_MASK_MASK      0x01FF0000
+#define EC_TSO_CTRL_FIRST_MASK_SHIFT     16
+
+/**** ctrl_middle register ****/
+/* Data to be written into the control BIS. */
+#define EC_TSO_CTRL_MIDDLE_DATA_MASK     0x000001FF
+#define EC_TSO_CTRL_MIDDLE_DATA_SHIFT    0
+/* Mask for the control bits */
+#define EC_TSO_CTRL_MIDDLE_MASK_MASK     0x01FF0000
+#define EC_TSO_CTRL_MIDDLE_MASK_SHIFT    16
+
+/**** ctrl_last register ****/
+/* Data to be written into the control BIS. */
+#define EC_TSO_CTRL_LAST_DATA_MASK       0x000001FF
+#define EC_TSO_CTRL_LAST_DATA_SHIFT      0
+/* Mask for the control bits */
+#define EC_TSO_CTRL_LAST_MASK_MASK       0x01FF0000
+#define EC_TSO_CTRL_LAST_MASK_SHIFT      16
+
+/**** cfg_add_0 register ****/
+/* MSS selection option:0 - MSS value is selected using MSS_sel  ... */
+#define EC_TSO_CFG_ADD_0_MSS_SEL         (1 << 0)
+
+/**** cfg_tunnel register ****/
+/* Enable TSO with tunnelling */
+#define EC_TSO_CFG_TUNNEL_EN_TUNNEL_TSO  (1 << 0)
+/* Enable outer UDP checksum update */
+#define EC_TSO_CFG_TUNNEL_EN_UDP_CHKSUM  (1 << 8)
+/* Enable outer UDP length update */
+#define EC_TSO_CFG_TUNNEL_EN_UDP_LEN     (1 << 9)
+/* Enable outer Ip6  length update */
+#define EC_TSO_CFG_TUNNEL_EN_IPV6_PLEN   (1 << 10)
+/* Enable outer IPv4 checksum update */
+#define EC_TSO_CFG_TUNNEL_EN_IPV4_CHKSUM (1 << 11)
+/* Enable outer IPv4 Identification update */
+#define EC_TSO_CFG_TUNNEL_EN_IPV4_IDEN   (1 << 12)
+/* Enable outer IPv4 length update */
+#define EC_TSO_CFG_TUNNEL_EN_IPV4_TLEN   (1 << 13)
+
+/**** mss register ****/
+/* MSS value */
+#define EC_TSO_SEL_MSS_VAL_MASK          0x000FFFFF
+#define EC_TSO_SEL_MSS_VAL_SHIFT         0
+
+/**** parse register ****/
+/* Max number of bus beats for parsing */
+#define EC_TPE_PARSE_MAX_BEATS_MASK      0x0000FFFF
+#define EC_TPE_PARSE_MAX_BEATS_SHIFT     0
+
+/**** vlan_data register ****/
+/* UDMA default VLAN 1 data */
+#define EC_TPM_UDMA_VLAN_DATA_DEF_1_MASK 0x0000FFFF
+#define EC_TPM_UDMA_VLAN_DATA_DEF_1_SHIFT 0
+/* UDMA default VLAN 2 data */
+#define EC_TPM_UDMA_VLAN_DATA_DEF_2_MASK 0xFFFF0000
+#define EC_TPM_UDMA_VLAN_DATA_DEF_2_SHIFT 16
+
+/**** mac_sa_2 register ****/
+/* MAC source address data [47:32] */
+#define EC_TPM_UDMA_MAC_SA_2_H_VAL_MASK  0x0000FFFF
+#define EC_TPM_UDMA_MAC_SA_2_H_VAL_SHIFT 0
+/* Drop indication for MAC SA spoofing0 – Don't drop */
+#define EC_TPM_UDMA_MAC_SA_2_DROP        (1 << 16)
+/* Replace indication for MAC SA spoofing 0 - Don't replace */
+#define EC_TPM_UDMA_MAC_SA_2_REPLACE     (1 << 17)
+
+/**** etype register ****/
+/* Ether type value  */
+#define EC_TPM_SEL_ETYPE_VAL_MASK        0x0000FFFF
+#define EC_TPM_SEL_ETYPE_VAL_SHIFT       0
+
+/**** tx_wr_fifo register ****/
+/* Max data beats that can be used in the Tx FIFO */
+#define EC_TFW_TX_WR_FIFO_DATA_TH_MASK   0x0000FFFF
+#define EC_TFW_TX_WR_FIFO_DATA_TH_SHIFT  0
+/* Max packets that can be stored in the Tx FIFO */
+#define EC_TFW_TX_WR_FIFO_INFO_TH_MASK   0xFFFF0000
+#define EC_TFW_TX_WR_FIFO_INFO_TH_SHIFT  16
+
+/**** tx_vid_table_addr register ****/
+/* Address for accessing the table */
+#define EC_TFW_TX_VID_TABLE_ADDR_VAL_MASK 0x00000FFF
+#define EC_TFW_TX_VID_TABLE_ADDR_VAL_SHIFT 0
+
+/**** tx_vid_table_data register ****/
+/* Table data (valid only after configuring the table address re ... */
+#define EC_TFW_TX_VID_TABLE_DATA_VAL_MASK 0x0000001F
+#define EC_TFW_TX_VID_TABLE_DATA_VAL_SHIFT 0
+
+/**** tx_rd_fifo register ****/
+/* Read data threshold when cut through mode is enabled. */
+#define EC_TFW_TX_RD_FIFO_READ_TH_MASK   0x0000FFFF
+#define EC_TFW_TX_RD_FIFO_READ_TH_SHIFT  0
+/* Enable cut through operation of the Tx FIFO. */
+#define EC_TFW_TX_RD_FIFO_EN_CUT_THROUGH (1 << 16)
+
+/**** tx_checksum register ****/
+/* Enable L3 checksum insertion. */
+#define EC_TFW_TX_CHECKSUM_L3_EN         (1 << 0)
+/* Enable L4 checksum insertion. */
+#define EC_TFW_TX_CHECKSUM_L4_EN         (1 << 1)
+/* Enable L4 checksum when L3 fragmentation is detected. */
+#define EC_TFW_TX_CHECKSUM_L4_FRAG_EN    (1 << 2)
+
+/**** tx_gen register ****/
+/* Force forward of all Tx packets to MAC. */
+#define EC_TFW_TX_GEN_FWD_ALL_TO_MAC     (1 << 0)
+/* Select the Packet generator as the source of Tx packets0 - Tx ... */
+#define EC_TFW_TX_GEN_SELECT_PKT_GEN     (1 << 1)
+
+/**** tx_spf register ****/
+/* Select the VID for spoofing check:[0] - Packet VID[1] - Forwa ... */
+#define EC_TFW_TX_SPF_VID_SEL            (1 << 0)
+
+/**** data_fifo register ****/
+/* FIFO used value (number of entries) */
+#define EC_TFW_DATA_FIFO_USED_MASK       0x0000FFFF
+#define EC_TFW_DATA_FIFO_USED_SHIFT      0
+/* FIFO FULL status */
+#define EC_TFW_DATA_FIFO_FULL            (1 << 16)
+/* FIFO EMPTY status */
+#define EC_TFW_DATA_FIFO_EMPTY           (1 << 17)
+
+/**** ctrl_fifo register ****/
+/* FIFO used value (number of entries) */
+#define EC_TFW_CTRL_FIFO_USED_MASK       0x0000FFFF
+#define EC_TFW_CTRL_FIFO_USED_SHIFT      0
+/* FIFO FULL status */
+#define EC_TFW_CTRL_FIFO_FULL            (1 << 16)
+/* FIFO EMPTY status */
+#define EC_TFW_CTRL_FIFO_EMPTY           (1 << 17)
+
+/**** hdr_fifo register ****/
+/* FIFO used value (number of entries) */
+#define EC_TFW_HDR_FIFO_USED_MASK        0x0000FFFF
+#define EC_TFW_HDR_FIFO_USED_SHIFT       0
+/* FIFO FULL status */
+#define EC_TFW_HDR_FIFO_FULL             (1 << 16)
+/* FIFO EMPTY status */
+#define EC_TFW_HDR_FIFO_EMPTY            (1 << 17)
+
+/**** uc_udma register ****/
+/* Default UDMA bitmap
+(MSB represents physical port) */
+#define EC_TFW_UDMA_UC_UDMA_DEF_MASK     0x0000001F
+#define EC_TFW_UDMA_UC_UDMA_DEF_SHIFT    0
+
+/**** mc_udma register ****/
+/* Default UDMA bitmap (MSB represents physical port.) */
+#define EC_TFW_UDMA_MC_UDMA_DEF_MASK     0x0000001F
+#define EC_TFW_UDMA_MC_UDMA_DEF_SHIFT    0
+
+/**** bc_udma register ****/
+/* Default UDMA bitmap (MSB represents physical port.) */
+#define EC_TFW_UDMA_BC_UDMA_DEF_MASK     0x0000001F
+#define EC_TFW_UDMA_BC_UDMA_DEF_SHIFT    0
+
+/**** spf_cmd register ****/
+/* Command for the VLAN spoofing00 – Ignore  mismatch */
+#define EC_TFW_UDMA_SPF_CMD_VID_MASK     0x00000003
+#define EC_TFW_UDMA_SPF_CMD_VID_SHIFT    0
+/* Command for VLAN spoofing 00 - Ignore  mismatch */
+#define EC_TFW_UDMA_SPF_CMD_MAC_MASK     0x0000000C
+#define EC_TFW_UDMA_SPF_CMD_MAC_SHIFT    2
+
+/**** fwd_dec register ****/
+/* Forwarding decision control:[0] – Enable internal switch */
+#define EC_TFW_UDMA_FWD_DEC_CTRL_MASK    0x000003FF
+#define EC_TFW_UDMA_FWD_DEC_CTRL_SHIFT   0
+
+/**** tx_cfg register ****/
+/* Swap output byte order */
+#define EC_TMI_TX_CFG_SWAP_BYTES         (1 << 0)
+/* Enable forwarding to the Rx data path. */
+#define EC_TMI_TX_CFG_EN_FWD_TO_RX       (1 << 1)
+/* Force forwarding all packets to the MAC. */
+#define EC_TMI_TX_CFG_FORCE_FWD_MAC      (1 << 2)
+/* Force forwarding all packets to the MAC. */
+#define EC_TMI_TX_CFG_FORCE_FWD_RX       (1 << 3)
+/* Force loop back operation */
+#define EC_TMI_TX_CFG_FORCE_LB           (1 << 4)
+
+/**** ec_pause register ****/
+/* Mask of pause_on [7:0] */
+#define EC_EFC_EC_PAUSE_MASK_MAC_MASK    0x000000FF
+#define EC_EFC_EC_PAUSE_MASK_MAC_SHIFT   0
+/* Mask of GPIO input [7:0] */
+#define EC_EFC_EC_PAUSE_MASK_GPIO_MASK   0x0000FF00
+#define EC_EFC_EC_PAUSE_MASK_GPIO_SHIFT  8
+
+/**** ec_xoff register ****/
+/* Mask 1 for XOFF [7:0]
+Mask 1 for Almost Full indication, */
+#define EC_EFC_EC_XOFF_MASK_1_MASK       0x000000FF
+#define EC_EFC_EC_XOFF_MASK_1_SHIFT      0
+/* Mask 2 for XOFF [7:0] Mask 2 for sampled Almost Full indicati ... */
+#define EC_EFC_EC_XOFF_MASK_2_MASK       0x0000FF00
+#define EC_EFC_EC_XOFF_MASK_2_SHIFT      8
+
+/**** xon register ****/
+/* Mask 1 for generating XON pulse, masking XOFF [0] */
+#define EC_EFC_XON_MASK_1                (1 << 0)
+/* Mask 2 for generating XON pulse, masking Almost Full indicati ... */
+#define EC_EFC_XON_MASK_2                (1 << 1)
+
+/**** gpio register ****/
+/* Mask for generating GPIO output XOFF indication from XOFF[0] */
+#define EC_EFC_GPIO_MASK_1               (1 << 0)
+
+/**** rx_fifo_af register ****/
+/* Threshold */
+#define EC_EFC_RX_FIFO_AF_TH_MASK        0x0000FFFF
+#define EC_EFC_RX_FIFO_AF_TH_SHIFT       0
+
+/**** rx_fifo_hyst register ****/
+/* Threshold low */
+#define EC_EFC_RX_FIFO_HYST_TH_LOW_MASK  0x0000FFFF
+#define EC_EFC_RX_FIFO_HYST_TH_LOW_SHIFT 0
+/* Threshold high */
+#define EC_EFC_RX_FIFO_HYST_TH_HIGH_MASK 0xFFFF0000
+#define EC_EFC_RX_FIFO_HYST_TH_HIGH_SHIFT 16
+
+/**** stat register ****/
+/* 10G MAC PFC mode, input from the 10 MAC */
+#define EC_EFC_STAT_PFC_MODE             (1 << 0)
+
+/**** ec_pfc register ****/
+/* Force PFC flow control */
+#define EC_EFC_EC_PFC_FORCE_MASK         0x000000FF
+#define EC_EFC_EC_PFC_FORCE_SHIFT        0
+
+/**** q_pause_0 register ****/
+/* [i] – Mask for Q[i] */
+#define EC_FC_UDMA_Q_PAUSE_0_MASK_MASK   0x0000000F
+#define EC_FC_UDMA_Q_PAUSE_0_MASK_SHIFT  0
+
+/**** q_pause_1 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_PAUSE_1_MASK_MASK   0x0000000F
+#define EC_FC_UDMA_Q_PAUSE_1_MASK_SHIFT  0
+
+/**** q_pause_2 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_PAUSE_2_MASK_MASK   0x0000000F
+#define EC_FC_UDMA_Q_PAUSE_2_MASK_SHIFT  0
+
+/**** q_pause_3 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_PAUSE_3_MASK_MASK   0x0000000F
+#define EC_FC_UDMA_Q_PAUSE_3_MASK_SHIFT  0
+
+/**** q_pause_4 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_PAUSE_4_MASK_MASK   0x0000000F
+#define EC_FC_UDMA_Q_PAUSE_4_MASK_SHIFT  0
+
+/**** q_pause_5 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_PAUSE_5_MASK_MASK   0x0000000F
+#define EC_FC_UDMA_Q_PAUSE_5_MASK_SHIFT  0
+
+/**** q_pause_6 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_PAUSE_6_MASK_MASK   0x0000000F
+#define EC_FC_UDMA_Q_PAUSE_6_MASK_SHIFT  0
+
+/**** q_pause_7 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_PAUSE_7_MASK_MASK   0x0000000F
+#define EC_FC_UDMA_Q_PAUSE_7_MASK_SHIFT  0
+
+/**** q_gpio_0 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_GPIO_0_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_GPIO_0_MASK_SHIFT   0
+
+/**** q_gpio_1 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_GPIO_1_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_GPIO_1_MASK_SHIFT   0
+
+/**** q_gpio_2 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_GPIO_2_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_GPIO_2_MASK_SHIFT   0
+
+/**** q_gpio_3 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_GPIO_3_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_GPIO_3_MASK_SHIFT   0
+
+/**** q_gpio_4 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_GPIO_4_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_GPIO_4_MASK_SHIFT   0
+
+/**** q_gpio_5 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_GPIO_5_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_GPIO_5_MASK_SHIFT   0
+
+/**** q_gpio_6 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_GPIO_6_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_GPIO_6_MASK_SHIFT   0
+
+/**** q_gpio_7 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_GPIO_7_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_GPIO_7_MASK_SHIFT   0
+
+/**** s_pause register ****/
+/* Mask of pause_on [7:0] */
+#define EC_FC_UDMA_S_PAUSE_MASK_MAC_MASK 0x000000FF
+#define EC_FC_UDMA_S_PAUSE_MASK_MAC_SHIFT 0
+/* Mask of GPIO input  [7:0] */
+#define EC_FC_UDMA_S_PAUSE_MASK_GPIO_MASK 0x0000FF00
+#define EC_FC_UDMA_S_PAUSE_MASK_GPIO_SHIFT 8
+
+/**** q_xoff_0 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_XOFF_0_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_XOFF_0_MASK_SHIFT   0
+
+/**** q_xoff_1 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_XOFF_1_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_XOFF_1_MASK_SHIFT   0
+
+/**** q_xoff_2 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_XOFF_2_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_XOFF_2_MASK_SHIFT   0
+
+/**** q_xoff_3 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_XOFF_3_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_XOFF_3_MASK_SHIFT   0
+
+/**** q_xoff_4 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_XOFF_4_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_XOFF_4_MASK_SHIFT   0
+
+/**** q_xoff_5 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_XOFF_5_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_XOFF_5_MASK_SHIFT   0
+
+/**** q_xoff_6 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_XOFF_6_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_XOFF_6_MASK_SHIFT   0
+
+/**** q_xoff_7 register ****/
+/* [i] - Mask for Q[i] */
+#define EC_FC_UDMA_Q_XOFF_7_MASK_MASK    0x0000000F
+#define EC_FC_UDMA_Q_XOFF_7_MASK_SHIFT   0
+
+/**** cfg_e register ****/
+/* Use MAC Tx FIFO empty status for EEE control. */
+#define EC_EEE_CFG_E_USE_MAC_TX_FIFO     (1 << 0)
+/* Use MAC Rx FIFO empty status for EEE control. */
+#define EC_EEE_CFG_E_USE_MAC_RX_FIFO     (1 << 1)
+/* Use Ethernet controller Tx FIFO empty status for EEE control */
+#define EC_EEE_CFG_E_USE_EC_TX_FIFO      (1 << 2)
+/* Use Ethernet controller Rx FIFO empty status for EEE control */
+#define EC_EEE_CFG_E_USE_EC_RX_FIFO      (1 << 3)
+/* Enable Low power signalling. */
+#define EC_EEE_CFG_E_ENABLE              (1 << 4)
+/* Mask output to MAC.  */
+#define EC_EEE_CFG_E_MASK_MAC_EEE        (1 << 8)
+/* Mask output to stop MAC interface. */
+#define EC_EEE_CFG_E_MASK_EC_TMI_STOP    (1 << 9)
+
+/**** stat_eee register ****/
+/* EEE state */
+#define EC_EEE_STAT_EEE_STATE_MASK       0x0000000F
+#define EC_EEE_STAT_EEE_STATE_SHIFT      0
+/* EEE detected */
+#define EC_EEE_STAT_EEE_DET              (1 << 4)
+
+/**** p_parse_cfg register ****/
+/* MAX number of beats for packet parsing */
+#define EC_MSP_P_PARSE_CFG_MAX_BEATS_MASK 0x000000FF
+#define EC_MSP_P_PARSE_CFG_MAX_BEATS_SHIFT 0
+/* MAX number of parsing iterations for packet parsing */
+#define EC_MSP_P_PARSE_CFG_MAX_ITER_MASK 0x0000FF00
+#define EC_MSP_P_PARSE_CFG_MAX_ITER_SHIFT 8
+
+/**** p_act_table_addr register ****/
+/* Address for accessing the table */
+#define EC_MSP_P_ACT_TABLE_ADDR_VAL_MASK 0x0000001F
+#define EC_MSP_P_ACT_TABLE_ADDR_VAL_SHIFT 0
+
+/**** p_act_table_data_1 register ****/
+/* Table data[5:0] - Offset to next protocol [bytes] [6] - Next  ... */
+#define EC_MSP_P_ACT_TABLE_DATA_1_VAL_MASK 0x03FFFFFF
+#define EC_MSP_P_ACT_TABLE_DATA_1_VAL_SHIFT 0
+
+/**** p_act_table_data_2 register ****/
+/* Table data  [8:0] - Offset to data in the packet [bits][17:9] ... */
+#define EC_MSP_P_ACT_TABLE_DATA_2_VAL_MASK 0x1FFFFFFF
+#define EC_MSP_P_ACT_TABLE_DATA_2_VAL_SHIFT 0
+
+/**** p_act_table_data_3 register ****/
+/* Table data   [8:0] - Offset to data in the packet [bits]  [17 ... */
+#define EC_MSP_P_ACT_TABLE_DATA_3_VAL_MASK 0x1FFFFFFF
+#define EC_MSP_P_ACT_TABLE_DATA_3_VAL_SHIFT 0
+
+/**** p_act_table_data_4 register ****/
+/* Table data [7:0] - Offset to the header length location in th ... */
+#define EC_MSP_P_ACT_TABLE_DATA_4_VAL_MASK 0x0FFFFFFF
+#define EC_MSP_P_ACT_TABLE_DATA_4_VAL_SHIFT 0
+
+/**** p_act_table_data_6 register ****/
+/* Table data [0] - Wr header length [10:1] - Write header lengt ... */
+#define EC_MSP_P_ACT_TABLE_DATA_6_VAL_MASK 0x007FFFFF
+#define EC_MSP_P_ACT_TABLE_DATA_6_VAL_SHIFT 0
+
+/**** p_res_in register ****/
+/* Selector for input parse_en 0 - Input vector 1 - Default valu ... */
+#define EC_MSP_P_RES_IN_SEL_PARSE_EN     (1 << 0)
+/* Selector for input protocol_index  0 - Input vector  1 - Defa ... */
+#define EC_MSP_P_RES_IN_SEL_PROT_INDEX   (1 << 1)
+/* Selector for input hdr_offset  0 - Input vector 1 - Default v ... */
+#define EC_MSP_P_RES_IN_SEL_HDR_OFFSET   (1 << 2)
+
+/**** h_hdr_len register ****/
+/* Value for selecting table 1 */
+#define EC_MSP_P_H_HDR_LEN_TABLE_1_MASK  0x000000FF
+#define EC_MSP_P_H_HDR_LEN_TABLE_1_SHIFT 0
+/* Value for selecting table 2 */
+#define EC_MSP_P_H_HDR_LEN_TABLE_2_MASK  0x00FF0000
+#define EC_MSP_P_H_HDR_LEN_TABLE_2_SHIFT 16
+
+/**** p_comp_data register ****/
+/* Data 1 for comparison */
+#define EC_MSP_C_P_COMP_DATA_DATA_1_MASK 0x0000FFFF
+#define EC_MSP_C_P_COMP_DATA_DATA_1_SHIFT 0
+/* Data 2 for comparison
+[18:16] - Stage
+[24:19] - Branch ID */
+#define EC_MSP_C_P_COMP_DATA_DATA_2_MASK 0x01FF0000
+#define EC_MSP_C_P_COMP_DATA_DATA_2_SHIFT 16
+
+/**** p_comp_mask register ****/
+/* Data 1 for comparison */
+#define EC_MSP_C_P_COMP_MASK_DATA_1_MASK 0x0000FFFF
+#define EC_MSP_C_P_COMP_MASK_DATA_1_SHIFT 0
+/* Data 2 for comparison
+[18:16] - Stage
+[24:19] - Branch ID */
+#define EC_MSP_C_P_COMP_MASK_DATA_2_MASK 0x01FF0000
+#define EC_MSP_C_P_COMP_MASK_DATA_2_SHIFT 16
+
+/**** p_comp_ctrl register ****/
+/* Output result value */
+#define EC_MSP_C_P_COMP_CTRL_RES_MASK    0x0000001F
+#define EC_MSP_C_P_COMP_CTRL_RES_SHIFT   0
+/* Compare command for the data_1 field 00 - Compare 01 - <= 10  ... */
+#define EC_MSP_C_P_COMP_CTRL_CMD_1_MASK  0x00030000
+#define EC_MSP_C_P_COMP_CTRL_CMD_1_SHIFT 16
+/* Compare command for the data_2 field 00 - Compare 01 - <= 10  ... */
+#define EC_MSP_C_P_COMP_CTRL_CMD_2_MASK  0x000C0000
+#define EC_MSP_C_P_COMP_CTRL_CMD_2_SHIFT 18
+/* Entry is valid */
+#define EC_MSP_C_P_COMP_CTRL_VALID       (1 << 31)
+
+/**** wol_en register ****/
+/* Interrupt enable WoL MAC DA Unicast detected  packet */
+#define EC_WOL_WOL_EN_INTRPT_EN_UNICAST  (1 << 0)
+/* Interrupt enable WoL L2 Multicast detected  packet */
+#define EC_WOL_WOL_EN_INTRPT_EN_MULTICAST (1 << 1)
+/* Interrupt enable WoL L2 Broadcast detected  packet */
+#define EC_WOL_WOL_EN_INTRPT_EN_BROADCAST (1 << 2)
+/* Interrupt enable WoL IPv4 detected  packet */
+#define EC_WOL_WOL_EN_INTRPT_EN_IPV4     (1 << 3)
+/* Interrupt enable WoL IPv6 detected  packet */
+#define EC_WOL_WOL_EN_INTRPT_EN_IPV6     (1 << 4)
+/* Interrupt enable WoL EtherType+MAC DA detected  packet */
+#define EC_WOL_WOL_EN_INTRPT_EN_ETHERTYPE_DA (1 << 5)
+/* Interrupt enable WoL EtherType+L2 Broadcast detected  packet */
+#define EC_WOL_WOL_EN_INTRPT_EN_ETHERTYPE_BC (1 << 6)
+/* Interrupt enable WoL parser detected  packet */
+#define EC_WOL_WOL_EN_INTRPT_EN_PARSER   (1 << 7)
+/* Interrupt enable WoL magic detected  packet */
+#define EC_WOL_WOL_EN_INTRPT_EN_MAGIC    (1 << 8)
+/* Interrupt enable WoL magic+password detected  packet */
+#define EC_WOL_WOL_EN_INTRPT_EN_MAGIC_PSWD (1 << 9)
+/* Forward enable WoL MAC DA Unicast detected  packet */
+#define EC_WOL_WOL_EN_FWRD_EN_UNICAST    (1 << 16)
+/* Forward enable WoL L2 Multicast detected  packet */
+#define EC_WOL_WOL_EN_FWRD_EN_MULTICAST  (1 << 17)
+/* Forward enable WoL L2 Broadcast detected  packet */
+#define EC_WOL_WOL_EN_FWRD_EN_BROADCAST  (1 << 18)
+/* Forward enable WoL IPv4 detected  packet */
+#define EC_WOL_WOL_EN_FWRD_EN_IPV4       (1 << 19)
+/* Forward enable WoL IPv6 detected  packet */
+#define EC_WOL_WOL_EN_FWRD_EN_IPV6       (1 << 20)
+/* Forward enable WoL EtherType+MAC DA detected  packet */
+#define EC_WOL_WOL_EN_FWRD_EN_ETHERTYPE_DA (1 << 21)
+/* Forward enable WoL EtherType+L2 Broadcast detected  packet */
+#define EC_WOL_WOL_EN_FWRD_EN_ETHERTYPE_BC (1 << 22)
+/* Forward enable WoL parser detected  packet */
+#define EC_WOL_WOL_EN_FWRD_EN_PARSER     (1 << 23)
+
+/**** magic_pswd_h register ****/
+/* Password for magic_password packet detection - bits 47:32 */
+#define EC_WOL_MAGIC_PSWD_H_VAL_MASK     0x0000FFFF
+#define EC_WOL_MAGIC_PSWD_H_VAL_SHIFT    0
+
+/**** ethertype register ****/
+/* Configured EtherType 1 for WoL EtherType_da/EtherType_bc pack ... */
+#define EC_WOL_ETHERTYPE_VAL_1_MASK      0x0000FFFF
+#define EC_WOL_ETHERTYPE_VAL_1_SHIFT     0
+/* Configured EtherType 2 for WoL EtherType_da/EtherType_bc pack ... */
+#define EC_WOL_ETHERTYPE_VAL_2_MASK      0xFFFF0000
+#define EC_WOL_ETHERTYPE_VAL_2_SHIFT     16
+
+#define EC_PTH_SYSTEM_TIME_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
+#define EC_PTH_SYSTEM_TIME_SUBSECONDS_LSB_VAL_SHIFT 14
+
+#define EC_PTH_CLOCK_PERIOD_LSB_VAL_MASK 0xFFFFC000
+#define EC_PTH_CLOCK_PERIOD_LSB_VAL_SHIFT 14
+
+/**** int_update_ctrl register ****/
+/* This field chooses between two methods for SW to update the s ... */
+#define EC_PTH_INT_UPDATE_CTRL_UPDATE_TRIG (1 << 0)
+/* 3'b000 - Set system time according to the value in {int_updat ... */
+#define EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_MASK 0x0000000E
+#define EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_SHIFT 1
+/* 1'b1 - Next update writes to system_time_subseconds1'b0 - Nex ... */
+#define EC_PTH_INT_UPDATE_CTRL_SUBSECOND_MASK (1 << 4)
+/* 1'b1 - Next update writes to system_time_seconds1'b0 - Next u ... */
+#define EC_PTH_INT_UPDATE_CTRL_SECOND_MASK (1 << 5)
+/* Enabling / disabling the internal ingress trigger (ingress_tr ... */
+#define EC_PTH_INT_UPDATE_CTRL_INT_TRIG_EN (1 << 16)
+/* Determines if internal ingress trigger (ingress_trigger #0) s ... */
+#define EC_PTH_INT_UPDATE_CTRL_PULSE_LEVEL_N (1 << 17)
+/* Internal ingress trigger polarity (ingress_trigger #0)1'b0 -  ... */
+#define EC_PTH_INT_UPDATE_CTRL_POLARITY  (1 << 18)
+
+/**** int_update_subseconds_lsb register ****/
+
+#define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF
+#define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0
+
+#define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
+#define EC_PTH_INT_UPDATE_SUBSECONDS_LSB_VAL_SHIFT 14
+/* 3'b000 - Set system time according to the value in {int_updat ... */
+#define EC_PTH_EXT_UPDATE_CTRL_UPDATE_METHOD_MASK 0x0000000E
+#define EC_PTH_EXT_UPDATE_CTRL_UPDATE_METHOD_SHIFT 1
+/* 1'b1 - next update writes to system_time_subseconds1'b0 - nex ... */
+#define EC_PTH_EXT_UPDATE_CTRL_SUBSECOND_MASK (1 << 4)
+/* 1'b1 - Next update writes to system_time_seconds1'b0 - Next u ... */
+#define EC_PTH_EXT_UPDATE_CTRL_SECOND_MASK (1 << 5)
+/* Enabling / disabling the external ingress triggers (ingress_t ... */
+#define EC_PTH_EXT_UPDATE_CTRL_EXT_TRIG_EN_MASK 0x00001F00
+#define EC_PTH_EXT_UPDATE_CTRL_EXT_TRIG_EN_SHIFT 8
+/* Determines if external ingress triggers (ingress_triggers #1- ... */
+#define EC_PTH_EXT_UPDATE_CTRL_PULSE_LEVEL_N_MASK 0x001F0000
+#define EC_PTH_EXT_UPDATE_CTRL_PULSE_LEVEL_N_SHIFT 16
+/* bit-field configurations of external ingress trigger polarity ... */
+#define EC_PTH_EXT_UPDATE_CTRL_POLARITY_MASK 0x1F000000
+#define EC_PTH_EXT_UPDATE_CTRL_POLARITY_SHIFT 24
+
+/**** ext_update_subseconds_lsb register ****/
+
+#define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF
+#define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0
+
+#define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
+#define EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_VAL_SHIFT 14
+
+#define EC_PTH_READ_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
+#define EC_PTH_READ_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14
+
+#define EC_PTH_INT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
+#define EC_PTH_INT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14
+
+#define EC_PTH_EXT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
+#define EC_PTH_EXT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14
+
+#define EC_PTH_SYNC_COMPENSATION_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
+#define EC_PTH_SYNC_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT 14
+
+/**** trigger_ctrl register ****/
+/* Enabling / disabling the egress trigger1'b1 - Enabled1'b0 - D ... */
+#define EC_PTH_EGRESS_TRIGGER_CTRL_EN    (1 << 0)
+/* Configuration that determines if the egress trigger is a peri ... */
+#define EC_PTH_EGRESS_TRIGGER_CTRL_PERIODIC (1 << 1)
+/* Configuration of egress trigger polarity */
+#define EC_PTH_EGRESS_TRIGGER_CTRL_POLARITY (1 << 2)
+/* If the pulse is marked as periodic (see periodic field), this ... */
+#define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SUBSEC_MASK 0x00FFFFF0
+#define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SUBSEC_SHIFT 4
+/* If the pulse is marked as periodic (see periodic field), this ... */
+#define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SEC_MASK 0xFF000000
+#define EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SEC_SHIFT 24
+
+/**** trigger_subseconds_lsb register ****/
+
+#define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF
+#define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0
+
+#define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
+#define EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_VAL_SHIFT 14
+
+/**** pulse_width_subseconds_lsb register ****/
+
+#define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_RESERVED_13_0_MASK 0x00003FFF
+#define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_RESERVED_13_0_SHIFT 0
+
+#define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_VAL_MASK 0xFFFFC000
+#define EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_VAL_SHIFT 14
+
+/**** qual register ****/
+
+#define EC_PTH_DB_QUAL_TS_VALID       (1 << 0)
+
+#define EC_PTH_DB_QUAL_RESERVED_31_1_MASK 0xFFFFFFFE
+#define EC_PTH_DB_QUAL_RESERVED_31_1_SHIFT 1
+
+/**** rx_comp_desc register ****/
+/* Selection for word0[13]:0- legacy SR-A01- per generic protoco ... */
+#define EC_GEN_V3_RX_COMP_DESC_W0_L3_CKS_RES_SEL (1 << 0)
+/* Selection for word0[14]:0- legacy SR-A01- per generic protoco ... */
+#define EC_GEN_V3_RX_COMP_DESC_W0_L4_CKS_RES_SEL (1 << 1)
+/* Selection for word3[29]:0-macsec decryption status[13] (legac ... */
+#define EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_13_L4_CKS_RES_SEL (1 << 8)
+/* Selection for word3[30]:0-macsec decryption status[14] (legac ... */
+#define EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_14_L3_CKS_RES_SEL (1 << 9)
+/* Selection for word3[31]:0-macsec decryption status[15] (legac ... */
+#define EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_15_CRC_RES_SEL (1 << 10)
+/* Selection for word 0 [6:5], source VLAN count0- source vlan c ... */
+#define EC_GEN_V3_RX_COMP_DESC_W0_SRC_VLAN_CNT (1 << 12)
+/* Selection for word 0 [4:0], l3 protocol index0-  l3 protocol  ... */
+#define EC_GEN_V3_RX_COMP_DESC_W0_L3_PROT_INDEX (1 << 13)
+/* Selection for word 1 [31:16], lP fragment checksum0-  IP frag ... */
+#define EC_GEN_V3_RX_COMP_DESC_W1_IP_FRAG_CHECKSUM (1 << 14)
+/* Selection for word 2 [15:9], L3 offset0-  LL3 offset1- CRC re ... */
+#define EC_GEN_V3_RX_COMP_DESC_W2_L3_OFFSET (1 << 15)
+/* Selection for word 2 [8:0], tunnel offset0-  tunnel offset1-  ... */
+#define EC_GEN_V3_RX_COMP_DESC_W2_TUNNEL_OFFSET (1 << 16)
+
+/**** conf register ****/
+/* Valid signal configuration when in loopback mode:00 - valid f ... */
+#define EC_GEN_V3_CONF_MAC_LB_EC_OUT_S_VALID_CFG_MASK 0x00000003
+#define EC_GEN_V3_CONF_MAC_LB_EC_OUT_S_VALID_CFG_SHIFT 0
+/* Valid signal configuration when in loopback mode:00 – valid f ... */
+#define EC_GEN_V3_CONF_MAC_LB_EC_IN_S_VALID_CFG_MASK 0x0000000C
+#define EC_GEN_V3_CONF_MAC_LB_EC_IN_S_VALID_CFG_SHIFT 2
+
+/**** tx_gpd_cam_addr register ****/
+/* Cam compare table address */
+#define EC_TFW_V3_TX_GPD_CAM_ADDR_VAL_MASK 0x0000001F
+#define EC_TFW_V3_TX_GPD_CAM_ADDR_VAL_SHIFT 0
+/* cam entry is valid */
+#define EC_TFW_V3_TX_GPD_CAM_CTRL_VALID  (1 << 31)
+
+/**** tx_gcp_legacy register ****/
+/* 0-choose parameters from table1- choose legacy crce roce para ... */
+#define EC_TFW_V3_TX_GCP_LEGACY_PARAM_SEL (1 << 0)
+
+/**** tx_gcp_table_addr register ****/
+/* parametrs table address */
+#define EC_TFW_V3_TX_GCP_TABLE_ADDR_VAL_MASK 0x0000001F
+#define EC_TFW_V3_TX_GCP_TABLE_ADDR_VAL_SHIFT 0
+
+/**** tx_gcp_table_gen register ****/
+/* polynomial selcet
+0-crc32(0x104C11DB7)
+1-crc32c(0x11EDC6F41) */
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_POLY_SEL (1 << 0)
+/* Enable bit complement on crc result */
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_CRC32_BIT_COMP (1 << 1)
+/* Enable bit swap on crc result */
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_CRC32_BIT_SWAP (1 << 2)
+/* Enable byte swap on crc result */
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_CRC32_BYTE_SWAP (1 << 3)
+/* Enable bit swap on input data */
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_DATA_BIT_SWAP (1 << 4)
+/* Enable byte swap on input data */
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_DATA_BYTE_SWAP (1 << 5)
+/* Number of bytes in trailer which are not part of crc calculat ... */
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_TRAIL_SIZE_MASK 0x000003C0
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_TRAIL_SIZE_SHIFT 6
+/* Number of bytes in header which are not part of crc calculati ... */
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_HEAD_SIZE_MASK 0x00FF0000
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_HEAD_SIZE_SHIFT 16
+/* corrected offset calculation0- subtract head_size (roce)1- ad ... */
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_HEAD_CALC (1 << 24)
+/* 0-replace masked bits with 01-replace masked bits with 1 (roc ... */
+#define EC_TFW_V3_TX_GCP_TABLE_GEN_MASK_POLARITY (1 << 25)
+
+/**** tx_gcp_table_res register ****/
+/* Not in use */
+#define EC_TFW_V3_TX_GCP_TABLE_RES_SEL_MASK 0x0000001F
+#define EC_TFW_V3_TX_GCP_TABLE_RES_SEL_SHIFT 0
+/* Not in use */
+#define EC_TFW_V3_TX_GCP_TABLE_RES_EN    (1 << 5)
+/* Not in use */
+#define EC_TFW_V3_TX_GCP_TABLE_RES_DEF   (1 << 6)
+
+/**** tx_gcp_table_alu_opcode register ****/
+/* first opcode
+e.g. (A op1 B) op3 (C op2 D) */
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_1_MASK 0x0000003F
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_1_SHIFT 0
+/* second opcode
+e.g. (A op1 B) op3 (C op2 D) */
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_2_MASK 0x00000FC0
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_2_SHIFT 6
+/* third opcode
+e.g. (A op1 B) op3 (C op2 D) */
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_3_MASK 0x0003F000
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPCODE_OPCODE_3_SHIFT 12
+
+/**** tx_gcp_table_alu_opsel register ****/
+/* frst opsel, input selection */
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_1_MASK 0x0000000F
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_1_SHIFT 0
+/* second opsel, input selection */
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_2_MASK 0x000000F0
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_2_SHIFT 4
+/* third opsel, input selction */
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_3_MASK 0x00000F00
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_3_SHIFT 8
+/* fourth opsel, input selction */
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_4_MASK 0x0000F000
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_OPSEL_OPSEL_4_SHIFT 12
+
+/**** tx_gcp_table_alu_val register ****/
+/* value for alu input */
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_VAL_VAL_MASK 0x000001FF
+#define EC_TFW_V3_TX_GCP_TABLE_ALU_VAL_VAL_SHIFT 0
+
+/**** crc_csum_replace register ****/
+/* 0- use table
+1- legacy SR-A0 */
+#define EC_TFW_V3_CRC_CSUM_REPLACE_L3_CSUM_LEGACY_SEL (1 << 0)
+/* 0- use table
+1- legacy SR-A0 */
+#define EC_TFW_V3_CRC_CSUM_REPLACE_L4_CSUM_LEGACY_SEL (1 << 1)
+/* 0- use table
+1- legacy SR-A0 */
+#define EC_TFW_V3_CRC_CSUM_REPLACE_CRC_LEGACY_SEL (1 << 2)
+
+/**** crc_csum_replace_table_addr register ****/
+/* parametrs table address */
+#define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_ADDR_VAL_MASK 0x0000007F
+#define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_ADDR_VAL_SHIFT 0
+
+/**** crc_csum_replace_table register ****/
+/* L3 Checksum replace enable */
+#define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_L3_CSUM_EN (1 << 0)
+/* L4 Checksum replace enable */
+#define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_L4_CSUM_EN (1 << 1)
+/* CRC replace enable */
+#define EC_TFW_V3_CRC_CSUM_REPLACE_TABLE_CRC_EN (1 << 2)
+
+/**** rx_gpd_cam_addr register ****/
+/* Cam compare table address */
+#define EC_RFW_V3_RX_GPD_CAM_ADDR_VAL_MASK 0x0000001F
+#define EC_RFW_V3_RX_GPD_CAM_ADDR_VAL_SHIFT 0
+/* cam entry is valid */
+#define EC_RFW_V3_RX_GPD_CAM_CTRL_VALID  (1 << 31)
+
+/**** gpd_p1 register ****/
+/* Location in bytes of the gpd cam data1 in the parser result v ... */
+#define EC_RFW_V3_GPD_P1_OFFSET_MASK     0x000003FF
+#define EC_RFW_V3_GPD_P1_OFFSET_SHIFT    0
+
+/**** gpd_p2 register ****/
+/* Location in bytes of the gpd cam data2 in the parser result v ... */
+#define EC_RFW_V3_GPD_P2_OFFSET_MASK     0x000003FF
+#define EC_RFW_V3_GPD_P2_OFFSET_SHIFT    0
+
+/**** gpd_p3 register ****/
+/* Location in bytes of the gpd cam data3 in the parser result v ... */
+#define EC_RFW_V3_GPD_P3_OFFSET_MASK     0x000003FF
+#define EC_RFW_V3_GPD_P3_OFFSET_SHIFT    0
+
+/**** gpd_p4 register ****/
+/* Location in bytes of the gpd cam data4 in the parser result v ... */
+#define EC_RFW_V3_GPD_P4_OFFSET_MASK     0x000003FF
+#define EC_RFW_V3_GPD_P4_OFFSET_SHIFT    0
+
+/**** gpd_p5 register ****/
+/* Location in bytes of the gpd cam data5 in the parser result v ... */
+#define EC_RFW_V3_GPD_P5_OFFSET_MASK     0x000003FF
+#define EC_RFW_V3_GPD_P5_OFFSET_SHIFT    0
+
+/**** gpd_p6 register ****/
+/* Location in bytes of the gpd cam data6 in the parser result v ... */
+#define EC_RFW_V3_GPD_P6_OFFSET_MASK     0x000003FF
+#define EC_RFW_V3_GPD_P6_OFFSET_SHIFT    0
+
+/**** gpd_p7 register ****/
+/* Location in bytes of the gpd cam data7 in the parser result v ... */
+#define EC_RFW_V3_GPD_P7_OFFSET_MASK     0x000003FF
+#define EC_RFW_V3_GPD_P7_OFFSET_SHIFT    0
+
+/**** gpd_p8 register ****/
+/* Location in bytes of the gpd cam data8 in the parser result v ... */
+#define EC_RFW_V3_GPD_P8_OFFSET_MASK     0x000003FF
+#define EC_RFW_V3_GPD_P8_OFFSET_SHIFT    0
+
+/**** rx_gcp_legacy register ****/
+/* 0-choose parameters from table1- choose legacy crce roce para ... */
+#define EC_RFW_V3_RX_GCP_LEGACY_PARAM_SEL (1 << 0)
+
+/**** rx_gcp_table_addr register ****/
+/* parametrs table address */
+#define EC_RFW_V3_RX_GCP_TABLE_ADDR_VAL_MASK 0x0000001F
+#define EC_RFW_V3_RX_GCP_TABLE_ADDR_VAL_SHIFT 0
+
+/**** rx_gcp_table_gen register ****/
+/* polynomial selcet
+0-crc32(0x104C11DB7)
+1-crc32c(0x11EDC6F41) */
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_POLY_SEL (1 << 0)
+/* Enable bit complement on crc result */
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_CRC32_BIT_COMP (1 << 1)
+/* Enable bit swap on crc result */
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_CRC32_BIT_SWAP (1 << 2)
+/* Enable byte swap on crc result */
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_CRC32_BYTE_SWAP (1 << 3)
+/* Enable bit swap on input data */
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_DATA_BIT_SWAP (1 << 4)
+/* Enable byte swap on input data */
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_DATA_BYTE_SWAP (1 << 5)
+/* Number of bytes in trailer which are not part of crc calculat ... */
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_TRAIL_SIZE_MASK 0x000003C0
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_TRAIL_SIZE_SHIFT 6
+/* Number of bytes in header which are not part of crc calculati ... */
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_HEAD_SIZE_MASK 0x00FF0000
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_HEAD_SIZE_SHIFT 16
+/* corrected offset calculation0- subtract head_size (roce)1- ad ... */
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_HEAD_CALC (1 << 24)
+/* 0-replace masked bits with 01-replace masked bits with 1 (roc ... */
+#define EC_RFW_V3_RX_GCP_TABLE_GEN_MASK_POLARITY (1 << 25)
+
+/**** rx_gcp_table_res register ****/
+/* Bit mask for crc/checksum result options for metadata W0[13][ ... */
+#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_0_MASK 0x0000001F
+#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_0_SHIFT 0
+/* Bit mask for crc/checksum result options for metadata W0[14][ ... */
+#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_1_MASK 0x000003E0
+#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_1_SHIFT 5
+/* Bit mask for crc/checksum result options for metadata W3[29][ ... */
+#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_2_MASK 0x00007C00
+#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_2_SHIFT 10
+/* Bit mask for crc/checksum result options for metadata W3[30][ ... */
+#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_3_MASK 0x000F8000
+#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_3_SHIFT 15
+/* Bit mask for crc/checksum result options for metadata W3[31][ ... */
+#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_4_MASK 0x01F00000
+#define EC_RFW_V3_RX_GCP_TABLE_RES_SEL_4_SHIFT 20
+/* enable crc result check */
+#define EC_RFW_V3_RX_GCP_TABLE_RES_EN    (1 << 25)
+/* default value for crc check for non-crc protocol */
+#define EC_RFW_V3_RX_GCP_TABLE_RES_DEF   (1 << 26)
+
+/**** rx_gcp_table_alu_opcode register ****/
+/* first opcode
+e.g. (A op1 B) op3 (C op2 D) */
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_1_MASK 0x0000003F
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_1_SHIFT 0
+/* second opcode
+e.g. (A op1 B) op3 (C op2 D) */
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_2_MASK 0x00000FC0
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_2_SHIFT 6
+/* third opcode
+e.g. (A op1 B) op3 (C op2 D) */
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_3_MASK 0x0003F000
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPCODE_OPCODE_3_SHIFT 12
+
+/**** rx_gcp_table_alu_opsel register ****/
+/* frst opsel, input selection */
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_1_MASK 0x0000000F
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_1_SHIFT 0
+/* second opsel, input selection */
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_2_MASK 0x000000F0
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_2_SHIFT 4
+/* third opsel, input selction */
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_3_MASK 0x00000F00
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_3_SHIFT 8
+/* fourth opsel, input selction */
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_4_MASK 0x0000F000
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_OPSEL_OPSEL_4_SHIFT 12
+
+/**** rx_gcp_table_alu_val register ****/
+/* value for alu input */
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_VAL_VAL_MASK 0x000001FF
+#define EC_RFW_V3_RX_GCP_TABLE_ALU_VAL_VAL_SHIFT 0
+
+/**** rx_gcp_alu_p1 register ****/
+/* Location in bytes of field 1 in the parser result vector */
+#define EC_RFW_V3_RX_GCP_ALU_P1_OFFSET_MASK 0x000003FF
+#define EC_RFW_V3_RX_GCP_ALU_P1_OFFSET_SHIFT 0
+/* Right shift for field 1 in the parser result vector */
+#define EC_RFW_V3_RX_GCP_ALU_P1_SHIFT_MASK 0x000F0000
+#define EC_RFW_V3_RX_GCP_ALU_P1_SHIFT_SHIFT 16
+
+/**** rx_gcp_alu_p2 register ****/
+/* Location in bytes of field 2 in the parser result vector */
+#define EC_RFW_V3_RX_GCP_ALU_P2_OFFSET_MASK 0x000003FF
+#define EC_RFW_V3_RX_GCP_ALU_P2_OFFSET_SHIFT 0
+/* Right shift for field 2 in the parser result vector */
+#define EC_RFW_V3_RX_GCP_ALU_P2_SHIFT_MASK 0x000F0000
+#define EC_RFW_V3_RX_GCP_ALU_P2_SHIFT_SHIFT 16
+
+/**** hs_ctrl_table_addr register ****/
+/* Header split control table address */
+#define EC_RFW_V3_HS_CTRL_TABLE_ADDR_VAL_MASK 0x000000FF
+#define EC_RFW_V3_HS_CTRL_TABLE_ADDR_VAL_SHIFT 0
+
+/**** hs_ctrl_table register ****/
+/* Header split length select */
+#define EC_RFW_V3_HS_CTRL_TABLE_SEL_MASK 0x00000003
+#define EC_RFW_V3_HS_CTRL_TABLE_SEL_SHIFT 0
+/* enable header split */
+#define EC_RFW_V3_HS_CTRL_TABLE_ENABLE   (1 << 2)
+
+/**** hs_ctrl_table_alu_opcode register ****/
+/* first opcode
+e.g. (A op1 B) op3 (C op2 D) */
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_1_MASK 0x0000003F
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_1_SHIFT 0
+/* second opcode
+e.g. (A op1 B) op3 (C op2 D) */
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_2_MASK 0x00000FC0
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_2_SHIFT 6
+/* third opcode
+e.g. (A op1 B) op3 (C op2 D) */
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_3_MASK 0x0003F000
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPCODE_OPCODE_3_SHIFT 12
+
+/**** hs_ctrl_table_alu_opsel register ****/
+/* frst opsel, input selection */
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_1_MASK 0x0000000F
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_1_SHIFT 0
+/* second opsel, input selection */
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_2_MASK 0x000000F0
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_2_SHIFT 4
+/* third opsel, input selction */
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_3_MASK 0x00000F00
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_3_SHIFT 8
+/* fourth opsel, input selction */
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_4_MASK 0x0000F000
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_OPSEL_OPSEL_4_SHIFT 12
+
+/**** hs_ctrl_table_alu_val register ****/
+/* value for alu input */
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_VAL_VAL_MASK 0x0000FFFF
+#define EC_RFW_V3_HS_CTRL_TABLE_ALU_VAL_VAL_SHIFT 0
+
+/**** hs_ctrl_cfg register ****/
+/* Header split enable static selction0 – legacy1 – header split ... */
+#define EC_RFW_V3_HS_CTRL_CFG_ENABLE_SEL (1 << 0)
+/* Header split length static selction0 – legacy1 – header split ... */
+#define EC_RFW_V3_HS_CTRL_CFG_LENGTH_SEL (1 << 1)
+
+/**** hs_ctrl_alu_p1 register ****/
+/* Location in bytes of field 1 in the parser result vector */
+#define EC_RFW_V3_HS_CTRL_ALU_P1_OFFSET_MASK 0x000003FF
+#define EC_RFW_V3_HS_CTRL_ALU_P1_OFFSET_SHIFT 0
+/* Right shift for field 1 in the parser result vector */
+#define EC_RFW_V3_HS_CTRL_ALU_P1_SHIFT_MASK 0x000F0000
+#define EC_RFW_V3_HS_CTRL_ALU_P1_SHIFT_SHIFT 16
+
+/**** hs_ctrl_alu_p2 register ****/
+/* Location in bytes of field 2 in the parser result vector */
+#define EC_RFW_V3_HS_CTRL_ALU_P2_OFFSET_MASK 0x000003FF
+#define EC_RFW_V3_HS_CTRL_ALU_P2_OFFSET_SHIFT 0
+/* Right shift for field 2 in the parser result vector */
+#define EC_RFW_V3_HS_CTRL_ALU_P2_SHIFT_MASK 0x000F0000
+#define EC_RFW_V3_HS_CTRL_ALU_P2_SHIFT_SHIFT 16
+
+/**** tx_config register ****/
+/* [0] pre increment word swap[1] pre increment byte swap[2] pre ... */
+#define EC_CRYPTO_TX_CONFIG_TWEAK_ENDIANITY_SWAP_MASK 0x0000003F
+#define EC_CRYPTO_TX_CONFIG_TWEAK_ENDIANITY_SWAP_SHIFT 0
+/* [0] pre encryption word swap[1] pre encryption byte swap[2] p ... */
+#define EC_CRYPTO_TX_CONFIG_DATA_ENDIANITY_SWAP_MASK 0x00003F00
+#define EC_CRYPTO_TX_CONFIG_DATA_ENDIANITY_SWAP_SHIFT 8
+/* direction flip, used in order to use same TID entry for both TX & RX traffic */
+#define EC_CRYPTO_TX_CONFIG_CRYPTO_DIR_FLIP (1 << 14)
+/* Enabling pipe line optimization */
+#define EC_CRYPTO_TX_CONFIG_PIPE_CALC_EN (1 << 16)
+/* enable performance counters */
+#define EC_CRYPTO_TX_CONFIG_PERF_CNT_EN  (1 << 17)
+/* [0] pre aes word swap[1] pre aes byte swap[2] pre aes bit swa ... */
+#define EC_CRYPTO_TX_CONFIG_AES_ENDIANITY_SWAP_MASK 0x03F00000
+#define EC_CRYPTO_TX_CONFIG_AES_ENDIANITY_SWAP_SHIFT 20
+/* [0] pre aes key word swap[1] pre aes key byte swap[2] pre aes ... */
+#define EC_CRYPTO_TX_CONFIG_AES_KEY_ENDIANITY_SWAP_MASK 0xFC000000
+#define EC_CRYPTO_TX_CONFIG_AES_KEY_ENDIANITY_SWAP_SHIFT 26
+
+/**** rx_config register ****/
+/* [0] pre increment word swap[1] pre increment byte swap[2] pre ... */
+#define EC_CRYPTO_RX_CONFIG_TWEAK_ENDIANITY_SWAP_MASK 0x0000003F
+#define EC_CRYPTO_RX_CONFIG_TWEAK_ENDIANITY_SWAP_SHIFT 0
+/* [0] pre encryption word swap[1] pre encryption byte swap[2] p ... */
+#define EC_CRYPTO_RX_CONFIG_DATA_ENDIANITY_SWAP_MASK 0x00003F00
+#define EC_CRYPTO_RX_CONFIG_DATA_ENDIANITY_SWAP_SHIFT 8
+/* direction flip, used in order to use same TID entry for both TX & RX traffic */
+#define EC_CRYPTO_RX_CONFIG_CRYPTO_DIR_FLIP (1 << 14)
+/* Enabling pipe line optimization */
+#define EC_CRYPTO_RX_CONFIG_PIPE_CALC_EN (1 << 16)
+/* enable performance counters */
+#define EC_CRYPTO_RX_CONFIG_PERF_CNT_EN  (1 << 17)
+/* [0] pre aes word swap[1] pre aes byte swap[2] pre aes bit swa ... */
+#define EC_CRYPTO_RX_CONFIG_AES_ENDIANITY_SWAP_MASK 0x03F00000
+#define EC_CRYPTO_RX_CONFIG_AES_ENDIANITY_SWAP_SHIFT 20
+/* [0] data aes key word swap[1] data aes key byte swap[2] data  ... */
+#define EC_CRYPTO_RX_CONFIG_AES_KEY_ENDIANITY_SWAP_MASK 0xFC000000
+#define EC_CRYPTO_RX_CONFIG_AES_KEY_ENDIANITY_SWAP_SHIFT 26
+
+/**** tx_override register ****/
+/* all transactions are encrypted */
+#define EC_CRYPTO_TX_OVERRIDE_ENCRYPT_ONLY (1 << 0)
+/* all transactions are decrypted */
+#define EC_CRYPTO_TX_OVERRIDE_DECRYPT_ONLY (1 << 1)
+/* all pkts use IV */
+#define EC_CRYPTO_TX_OVERRIDE_ALWAYS_DRIVE_IV (1 << 2)
+/* no pkt uses IV */
+#define EC_CRYPTO_TX_OVERRIDE_NEVER_DRIVE_IV (1 << 3)
+/* all pkts perform authentication calculation */
+#define EC_CRYPTO_TX_OVERRIDE_ALWAYS_PERFORM_SIGN (1 << 4)
+/* no pkt performs authentication calculation */
+#define EC_CRYPTO_TX_OVERRIDE_NEVER_PERFORM_SIGN (1 << 5)
+/* all pkts perform encryption calculation */
+#define EC_CRYPTO_TX_OVERRIDE_ALWAYS_PERFORM_ENC (1 << 6)
+/* no pkt performs encryption calculation */
+#define EC_CRYPTO_TX_OVERRIDE_NEVER_PERFORM_ENC (1 << 7)
+/* Enforce pkt trimming
+bit[0] relates to metadata_pkt_trim
+bit[1] relates to trailer_pkt_trime
+bit[2] relates to sign_trim
+bit[3] relates to aes_padding_trim */
+#define EC_CRYPTO_TX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_MASK 0x00000F00
+#define EC_CRYPTO_TX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_SHIFT 8
+/* Enforce no pkt trimming
+bit[0] relates to metadata_pkt_trim
+bit[1] relates to trailer_pkt_trime
+bit[2] relates to sign_trim
+bit[3] relates to aes_padding_trim */
+#define EC_CRYPTO_TX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_MASK 0x0000F000
+#define EC_CRYPTO_TX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_SHIFT 12
+/* chicken bit to disable metadata handling optimization */
+#define EC_CRYPTO_TX_OVERRIDE_EXPLICIT_METADATA_STAGE (1 << 16)
+
+/**** rx_override register ****/
+/* all transactions are encrypted */
+#define EC_CRYPTO_RX_OVERRIDE_ENCRYPT_ONLY (1 << 0)
+/* all transactions are decrypted */
+#define EC_CRYPTO_RX_OVERRIDE_DECRYPT_ONLY (1 << 1)
+/* all pkts use IV */
+#define EC_CRYPTO_RX_OVERRIDE_ALWAYS_DRIVE_IV (1 << 2)
+/* no pkt uses IV */
+#define EC_CRYPTO_RX_OVERRIDE_NEVER_DRIVE_IV (1 << 3)
+/* all pkts perform authentication calculation */
+#define EC_CRYPTO_RX_OVERRIDE_ALWAYS_PERFORM_SIGN (1 << 4)
+/* no pkt performs authentication calculation */
+#define EC_CRYPTO_RX_OVERRIDE_NEVER_PERFORM_SIGN (1 << 5)
+/* all pkts perform encryption calculation */
+#define EC_CRYPTO_RX_OVERRIDE_ALWAYS_PERFORM_ENC (1 << 6)
+/* no pkt performs encryption calculation */
+#define EC_CRYPTO_RX_OVERRIDE_NEVER_PERFORM_ENC (1 << 7)
+/* Enforce pkt trimming
+bit[0] relates to metadata_pkt_trim
+bit[1] relates to trailer_pkt_trime
+bit[2] relates to sign_trim
+bit[3] relates to aes_padding_trim */
+#define EC_CRYPTO_RX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_MASK 0x00000F00
+#define EC_CRYPTO_RX_OVERRIDE_ALWAYS_BYPASS_PKT_TRIM_SHIFT 8
+/* Enforce no pkt trimming
+bit[0] relates to metadata_pkt_trim
+bit[1] relates to trailer_pkt_trime
+bit[2] relates to sign_trim
+bit[3] relates to aes_padding_trim */
+#define EC_CRYPTO_RX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_MASK 0x0000F000
+#define EC_CRYPTO_RX_OVERRIDE_NEVER_BYPASS_PKT_TRIM_SHIFT 12
+/* bit enable for writing to rx_cmpl metadata info */
+#define EC_CRYPTO_RX_OVERRIDE_META_DATA_WRITE_EN_MASK 0x00070000
+#define EC_CRYPTO_RX_OVERRIDE_META_DATA_WRITE_EN_SHIFT 16
+/* chicken bit to disable metadata handling optimization */
+#define EC_CRYPTO_RX_OVERRIDE_EXPLICIT_METADATA_STAGE (1 << 19)
+/* crypto metadata offset in the rx cmpl_desc */
+#define EC_CRYPTO_RX_OVERRIDE_META_DATA_BASE_MASK 0x07F00000
+#define EC_CRYPTO_RX_OVERRIDE_META_DATA_BASE_SHIFT 20
+
+/**** tx_enc_iv_construction register ****/
+/* for each IV byte, select between src1 & src2. Src1 & src2 ... */
+#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MUX_SEL_MASK 0x0000FFFF
+#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MUX_SEL_SHIFT 0
+/* configure meaning of mux_sel=1'b0 (2'b00 – zeros, 2'b01 f...  */
+#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_0_MASK 0x00030000
+#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_0_SHIFT 16
+/* configure meaning of mux_sel=1'b1 (2'b00 – zeros, 2'b01 ...  */
+#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_1_MASK 0x000C0000
+#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_MAP_1_SHIFT 18
+/* Per-byte mux select taken from Crypto table (otherwise ...  */
+#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_SEL_FROM_TABLE (1 << 20)
+/* [0] word swap en
+[1] byte swap en
+[2] bit swap en */
+#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_MASK 0x00E00000
+#define EC_CRYPTO_TX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_SHIFT 21
+
+/**** rx_enc_iv_construction register ****/
+/* for each IV byte, select between src1 & src2. Src1 & src2 ...  */
+#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MUX_SEL_MASK 0x0000FFFF
+#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MUX_SEL_SHIFT 0
+/* configure meaning of mux_sel=1'b0 (2'b00 – zeros, 2'b01 – ...  */
+#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_0_MASK 0x00030000
+#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_0_SHIFT 16
+/* configure meaning of mux_sel=1'b1 (2'b00 – zeros, 2'b01 – ...  */
+#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_1_MASK 0x000C0000
+#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_MAP_1_SHIFT 18
+/* Per-byte mux select taken from Crypto table (otherwise from ...  */
+#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_SEL_FROM_TABLE (1 << 20)
+/* [0] word swap en
+[1] byte swap en
+[2] bit swap en */
+#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_MASK 0x00E00000
+#define EC_CRYPTO_RX_ENC_IV_CONSTRUCTION_ENDIANITY_SWAP_SHIFT 21
+
+/**** rx_enc_iv_map register ****/
+/* [0] word swap en
+[1] byte swap en
+[2] bit swap en */
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_OFFSET_MASK 0x0000001F
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_OFFSET_SHIFT 0
+/* number of valid bytes in word, as generated by field extract ... */
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_LENGTH_MASK 0x000000E0
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_0_LENGTH_SHIFT 5
+/* [0] word swap en
+[1] byte swap en
+[2] bit swap en */
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_OFFSET_MASK 0x00001F00
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_OFFSET_SHIFT 8
+/* number of valid bytes in word, as generated by field extract ... */
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_LENGTH_MASK 0x0000E000
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_1_LENGTH_SHIFT 13
+/* [0] word swap en
+[1] byte swap en
+[2] bit swap en */
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_OFFSET_MASK 0x001F0000
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_OFFSET_SHIFT 16
+/* number of valid bytes in word, as generated by field extract ... */
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_LENGTH_MASK 0x00E00000
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_2_LENGTH_SHIFT 21
+/* [0] word swap en
+[1] byte swap en
+[2] bit swap en */
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_OFFSET_MASK 0x1F000000
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_OFFSET_SHIFT 24
+/* number of valid bytes in word, as generated by field extract ... */
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_LENGTH_MASK 0xE0000000
+#define EC_CRYPTO_RX_ENC_IV_MAP_FIELD_EXTRACT_3_LENGTH_SHIFT 29
+
+/**** tx_pkt_trim_len register ****/
+/* metadata shift-reg length */
+#define EC_CRYPTO_TX_PKT_TRIM_LEN_META_MASK 0x00000007
+#define EC_CRYPTO_TX_PKT_TRIM_LEN_META_SHIFT 0
+/* pkt trailer shift-reg length */
+#define EC_CRYPTO_TX_PKT_TRIM_LEN_TRAIL_MASK 0x000000F0
+#define EC_CRYPTO_TX_PKT_TRIM_LEN_TRAIL_SHIFT 4
+/* sign shift-reg length */
+#define EC_CRYPTO_TX_PKT_TRIM_LEN_SIGN_MASK 0x00000300
+#define EC_CRYPTO_TX_PKT_TRIM_LEN_SIGN_SHIFT 8
+/* crypto padding shift-reg length */
+#define EC_CRYPTO_TX_PKT_TRIM_LEN_CRYPTO_PADDING_MASK 0x00003000
+#define EC_CRYPTO_TX_PKT_TRIM_LEN_CRYPTO_PADDING_SHIFT 12
+/* hardware chooses shift-registers configurations automatically – no need for sw configuration */
+#define EC_CRYPTO_TX_PKT_TRIM_LEN_AUTO_MODE (1 << 16)
+
+/**** rx_pkt_trim_len register ****/
+/* metadata shift-reg length */
+#define EC_CRYPTO_RX_PKT_TRIM_LEN_META_MASK 0x00000007
+#define EC_CRYPTO_RX_PKT_TRIM_LEN_META_SHIFT 0
+/* pkt trailer shift-reg length */
+#define EC_CRYPTO_RX_PKT_TRIM_LEN_TRAIL_MASK 0x000000F0
+#define EC_CRYPTO_RX_PKT_TRIM_LEN_TRAIL_SHIFT 4
+/* sign shift-reg length */
+#define EC_CRYPTO_RX_PKT_TRIM_LEN_SIGN_MASK 0x00000300
+#define EC_CRYPTO_RX_PKT_TRIM_LEN_SIGN_SHIFT 8
+/* crypto padding shift-reg length */
+#define EC_CRYPTO_RX_PKT_TRIM_LEN_CRYPTO_PADDING_MASK 0x00003000
+#define EC_CRYPTO_RX_PKT_TRIM_LEN_CRYPTO_PADDING_SHIFT 12
+/* hardware chooses shift-registers configurations automatically – no need for sw configuration */
+#define EC_CRYPTO_RX_PKT_TRIM_LEN_AUTO_MODE (1 << 16)
+
+/**** total_tx_secured_pkts_cipher_mode_cmpr register ****/
+
+#define EC_CRYPTO_PERF_CNTR_TOTAL_TX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_MASK 0x0000000F
+#define EC_CRYPTO_PERF_CNTR_TOTAL_TX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_SHIFT 0
+
+/**** total_rx_secured_pkts_cipher_mode_cmpr register ****/
+
+#define EC_CRYPTO_PERF_CNTR_TOTAL_RX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_MASK 0x0000000F
+#define EC_CRYPTO_PERF_CNTR_TOTAL_RX_SECURED_PKTS_CIPHER_MODE_CMPR_MODE_SHIFT 0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_EC_REG_H */
+
+/** @} end of ... group */
+
+
diff --git a/sys/contrib/alpine-hal/eth/al_hal_eth_kr.c b/sys/contrib/alpine-hal/eth/al_hal_eth_kr.c
new file mode 100644
index 000000000000..14ef797eb00c
--- /dev/null
+++ b/sys/contrib/alpine-hal/eth/al_hal_eth_kr.c
@@ -0,0 +1,1030 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+/**
+ *  Ethernet
+ *  @{
+ * @file   al_hal_eth_kr.c
+ *
+ * @brief  KR HAL driver for main functions (auto-neg, Link Training)
+ *
+ */
+
+#include "al_hal_eth_kr.h"
+#include "al_hal_eth_mac_regs.h"
+#include "al_hal_an_lt_wrapper_regs.h"
+
+enum al_eth_lt_unit_rev {
+	AL_ETH_LT_UNIT_REV_1 = 0,
+	AL_ETH_LT_UNIT_REV_2,
+
+	AL_ETH_LT_UNIT_REV_MAX
+};
+
+enum al_eth_an_lt_regs_ids {
+	AL_ETH_KR_AN_CONTROL = 0,
+	AL_ETH_KR_AN_STATUS,
+	AL_ETH_KR_AN_ADV0,
+	AL_ETH_KR_AN_ADV1,
+	AL_ETH_KR_AN_ADV2,
+	AL_ETH_KR_AN_REM_ADV0,
+	AL_ETH_KR_AN_REM_ADV1,
+	AL_ETH_KR_AN_REM_ADV2,
+	AL_ETH_KR_PMD_CONTROL,
+	AL_ETH_KR_PMD_STATUS,
+	AL_ETH_KR_PMD_LP_COEF_UP,
+	AL_ETH_KR_PMD_LP_STATUS_REPORT,
+	AL_ETH_KR_PMD_LD_COEF_UP,
+	AL_ETH_KR_PMD_LD_STATUS_REPORT,
+	AL_ETH_KR_AN_XNP_ADV0,
+	AL_ETH_KR_AN_XNP_ADV1,
+	AL_ETH_KR_AN_XNP_ADV2,
+	AL_ETH_KR_AN_REM_XNP_ADV0,
+	AL_ETH_KR_AN_REM_XNP_ADV1,
+	AL_ETH_KR_AN_REM_XNP_ADV2,
+};
+
+static uint32_t al_eth_an_lt_regs_addr[][AL_ETH_LT_UNIT_REV_MAX] = {
+	[AL_ETH_KR_AN_CONTROL]			=	{0  ,	0x0},
+	[AL_ETH_KR_AN_STATUS]			=	{1  ,	0x4},
+	[AL_ETH_KR_AN_ADV0]			=	{16 ,	0x8},
+	[AL_ETH_KR_AN_ADV1]			=	{17 ,	0xc},
+	[AL_ETH_KR_AN_ADV2]			=	{18 ,	0x10},
+	[AL_ETH_KR_AN_REM_ADV0]			=	{19 ,	0x14},
+	[AL_ETH_KR_AN_REM_ADV1]			=	{20 ,	0x18},
+	[AL_ETH_KR_AN_REM_ADV2]			=	{21 ,	0x1c},
+	[AL_ETH_KR_PMD_CONTROL]			=	{150,	0x400},
+	[AL_ETH_KR_PMD_STATUS]			=	{151,	0x404},
+	[AL_ETH_KR_PMD_LP_COEF_UP]		=	{152,	0x408},
+	[AL_ETH_KR_PMD_LP_STATUS_REPORT]	=	{153,	0x40c},
+	[AL_ETH_KR_PMD_LD_COEF_UP]		=	{154,	0x410},
+	[AL_ETH_KR_PMD_LD_STATUS_REPORT]	=	{155,	0x414},
+	[AL_ETH_KR_AN_XNP_ADV0]			=	{22 ,   0x24},
+	[AL_ETH_KR_AN_XNP_ADV1]			=	{23 ,   0x28},
+	[AL_ETH_KR_AN_XNP_ADV2]			=	{24 ,   0x2c},
+	[AL_ETH_KR_AN_REM_XNP_ADV0]		=	{25 ,   0x30},
+	[AL_ETH_KR_AN_REM_XNP_ADV1]		=	{26 ,   0x34},
+	[AL_ETH_KR_AN_REM_XNP_ADV2]		=	{27 ,   0x38},
+};
+
+
+/*
+ * AN(Auto Negotiation) registers
+ * (read / write indirect with al_eth_an_reg_read/write)
+ */
+#define AL_ETH_KR_AN_CONTROL_RESTART				AL_BIT(9)
+#define AL_ETH_KR_AN_CONTROL_ENABLE				AL_BIT(12)
+#define AL_ETH_KR_AN_CONTROL_NP_ENABLE				AL_BIT(13)
+
+#define AL_ETH_KR_AN_STATUS_COMPLETED				AL_BIT(5)
+#define AL_ETH_KR_AN_STATUS_BASE_PAGE_RECEIVED			AL_BIT(6)
+#define AL_ETH_KR_AN_STATUS_CHECK_MASK				0xFF0A
+#define AL_ETH_KR_AN_STATUS_CHECK_NO_ERROR			0x0008
+
+/* AN advertising registers parsing */
+/* register 1 */
+#define AL_ETH_KR_AN_ADV1_SEL_FIELD_MASK			0x001f
+#define AL_ETH_KR_AN_ADV1_SEL_FIELD_SHIFT			0
+#define AL_ETH_KR_AN_ADV1_ECHOED_NONCE_MASK			0x03e0
+#define AL_ETH_KR_AN_ADV1_ECHOED_NONCE_SHIFT			5
+#define AL_ETH_KR_AN_ADV1_CAPABILITY_MASK			0x1c00
+#define AL_ETH_KR_AN_ADV1_CAPABILITY_SHIFT			10
+#define AL_ETH_KR_AN_ADV1_REM_FAULT_MASK			0x2000
+#define AL_ETH_KR_AN_ADV1_REM_FAULT_SHIFT			13
+#define AL_ETH_KR_AN_ADV1_ACK_MASK				0x4000
+#define AL_ETH_KR_AN_ADV1_ACK_SHIFT				14
+#define AL_ETH_KR_AN_ADV1_NEXT_PAGE_MASK			0x8000
+#define AL_ETH_KR_AN_ADV1_NEXT_PAGE_SHIFT			15
+/* register 2 */
+#define AL_ETH_KR_AN_ADV2_TX_NONCE_MASK				0x001f
+#define AL_ETH_KR_AN_ADV2_TX_NONCE_SHIFT			0
+#define AL_ETH_KR_AN_ADV2_TECH_MASK				0xffe0
+#define AL_ETH_KR_AN_ADV2_TECH_SHIFT				5
+/* register 3 */
+/* TECH field in the third register is extended to the field in the second
+ * register and it is currently reserved (should be always 0) */
+#define AL_ETH_KR_AN_ADV3_TECH_MASK				0x1fff
+#define AL_ETH_KR_AN_ADV3_TECH_SHIFT				0
+#define AL_ETH_KR_AN_ADV3_FEC_MASK				0xc000
+#define AL_ETH_KR_AN_ADV3_FEC_SHIFT				14
+
+/* Next Page Fields */
+/* register 1 */
+#define AL_ETH_KR_AN_NP_ADV1_DATA1_MASK				0x07ff
+#define AL_ETH_KR_AN_NP_ADV1_DATA1_SHIFT			0
+#define AL_ETH_KR_AN_NP_ADV1_TOGGLE_MASK			0x0800
+#define AL_ETH_KR_AN_NP_ADV1_TOGGLE_SHIFT			11
+#define AL_ETH_KR_AN_NP_ADV1_ACK2_MASK				0x1000
+#define AL_ETH_KR_AN_NP_ADV1_ACK2_SHIFT				12
+#define AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_MASK			0x2000
+#define AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_SHIFT			13
+#define AL_ETH_KR_AN_NP_ADV1_NP_MASK				0x8000
+#define AL_ETH_KR_AN_NP_ADV1_NP_SHIFT				15
+
+/*
+ * LT(Link Training) registers
+ * (read / write indirect with al_eth_pma_reg_read/write)
+ */
+#define AL_ETH_KR_PMD_CONTROL_RESTART				0
+#define AL_ETH_KR_PMD_CONTROL_ENABLE				1
+
+#define AL_ETH_KR_PMD_STATUS_RECEIVER_COMPLETED_SHIFT		0
+#define AL_ETH_KR_PMD_STATUS_RECEIVER_FRAME_LOCK_SHIFT		1
+#define AL_ETH_KR_PMD_STATUS_RECEIVER_START_UP_PROTO_PROG_SHIFT	2
+#define AL_ETH_KR_PMD_STATUS_FAILURE_SHIFT			3
+
+#define AL_ETH_KR_PMD_LP_COEF_UP_MINUS_MASK			0x0003
+#define AL_ETH_KR_PMD_LP_COEF_UP_MINUS_SHIFT			0
+#define AL_ETH_KR_PMD_LP_COEF_UP_ZERO_MASK			0x000C
+#define AL_ETH_KR_PMD_LP_COEF_UP_ZERO_SHIFT			2
+#define AL_ETH_KR_PMD_LP_COEF_UP_PLUS_MASK			0x0030
+#define AL_ETH_KR_PMD_LP_COEF_UP_PLUS_SHIFT			4
+#define AL_ETH_KR_PMD_LP_COEF_UP_INITIALIZE_SHIFT		12
+#define AL_ETH_KR_PMD_LP_COEF_UP_PRESET_SHIFT			13
+
+#define AL_ETH_KR_PMD_LP_STATUS_REPORT_MINUS_MASK		0x0003
+#define AL_ETH_KR_PMD_LP_STATUS_REPORT_MINUS_SHIFT		0
+#define AL_ETH_KR_PMD_LP_STATUS_REPORT_ZERO_MASK		0x000C
+#define AL_ETH_KR_PMD_LP_STATUS_REPORT_ZERO_SHIFT		2
+#define AL_ETH_KR_PMD_LP_STATUS_REPORT_PLUS_MASK		0x0030
+#define AL_ETH_KR_PMD_LP_STATUS_REPORT_PLUS_SHIFT		4
+#define AL_ETH_KR_PMD_LP_STATUS_RECEIVER_READY_SHIFT		15
+
+#define AL_ETH_KR_PMD_LD_COEF_UP_MINUS_MASK			0x0003
+#define AL_ETH_KR_PMD_LD_COEF_UP_MINUS_SHIFT			0
+#define AL_ETH_KR_PMD_LD_COEF_UP_ZERO_MASK			0x000C
+#define AL_ETH_KR_PMD_LD_COEF_UP_ZERO_SHIFT			2
+#define AL_ETH_KR_PMD_LD_COEF_UP_PLUS_MASK			0x0030
+#define AL_ETH_KR_PMD_LD_COEF_UP_PLUS_SHIFT			4
+#define AL_ETH_KR_PMD_LD_COEF_UP_INITIALIZE_SHIFT		12
+#define AL_ETH_KR_PMD_LD_COEF_UP_PRESET_SHIFT			13
+
+#define AL_ETH_KR_PMD_LD_STATUS_REPORT_MINUS_MASK		0x0003
+#define AL_ETH_KR_PMD_LD_STATUS_REPORT_MINUS_SHIFT		0
+#define AL_ETH_KR_PMD_LD_STATUS_REPORT_ZERO_MASK		0x000C
+#define AL_ETH_KR_PMD_LD_STATUS_REPORT_ZERO_SHIFT		2
+#define AL_ETH_KR_PMD_LD_STATUS_REPORT_PLUS_MASK		0x0030
+#define AL_ETH_KR_PMD_LD_STATUS_REPORT_PLUS_SHIFT		4
+#define AL_ETH_KR_PMD_LD_STATUS_REPORT_RECEIVER_READY_SHIFT	15
+
+
+enum al_eth_an_lt_regs {
+	AL_ETH_AN_REGS,
+	AL_ETH_LT_REGS,
+};
+
+static uint16_t al_eth_an_lt_reg_read(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_an_lt_regs_ids reg_id,
+			enum al_eth_an_lt_regs an_lt,
+			enum al_eth_an_lt_lane lane)
+{
+	uint32_t val;
+	uint16_t reg_addr;
+
+	if (adapter->rev_id < AL_ETH_REV_ID_3) {
+		al_assert(lane == AL_ETH_AN__LT_LANE_0);
+
+		reg_addr = al_eth_an_lt_regs_addr[reg_id][AL_ETH_LT_UNIT_REV_1];
+		if (an_lt == AL_ETH_AN_REGS) {
+			al_reg_write32(&adapter->mac_regs_base->kr.an_addr, reg_addr);
+			val = al_reg_read32(&adapter->mac_regs_base->kr.an_data);
+		} else {
+			al_reg_write32(&adapter->mac_regs_base->kr.pma_addr, reg_addr);
+			val = al_reg_read32(&adapter->mac_regs_base->kr.pma_data);
+		}
+	} else {
+		struct al_an_lt_wrapper_regs *regs = NULL;
+
+		reg_addr = al_eth_an_lt_regs_addr[reg_id][AL_ETH_LT_UNIT_REV_2];
+
+		switch (lane) {
+		case AL_ETH_AN__LT_LANE_0:
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_data,
+				       reg_addr);
+
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
+			val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_0_data);
+			break;
+		case AL_ETH_AN__LT_LANE_1:
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_data,
+				       reg_addr);
+
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
+			val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_1_data);
+			break;
+		case AL_ETH_AN__LT_LANE_2:
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_data,
+				       reg_addr);
+
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
+			val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_2_data);
+			break;
+		case AL_ETH_AN__LT_LANE_3:
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_data,
+				       reg_addr);
+
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
+			val = al_reg_read32(&adapter->mac_regs_base->gen_v3.an_lt_3_data);
+			break;
+		default:
+			al_err("%s: Unknown Lane %d\n", __func__, lane);
+			return 0;
+		}
+	}
+
+
+	al_dbg("[%s]: %s - (%s) lane %d, reg %d, val 0x%x", adapter->name, __func__,
+	       (an_lt == AL_ETH_AN_REGS) ? "AN" : "LT", lane, reg_addr, val);
+
+	return (uint16_t)val;
+}
+
+static void al_eth_an_lt_reg_write(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_an_lt_regs_ids reg_id,
+			enum al_eth_an_lt_regs an_lt,
+			enum al_eth_an_lt_lane lane,
+			uint16_t val)
+{
+	uint16_t reg_addr;
+
+	if (adapter->rev_id < AL_ETH_REV_ID_3) {
+		reg_addr = al_eth_an_lt_regs_addr[reg_id][AL_ETH_LT_UNIT_REV_1];
+		if (an_lt == AL_ETH_AN_REGS) {
+			al_reg_write32(&adapter->mac_regs_base->kr.an_addr, reg_addr);
+			al_reg_write32(&adapter->mac_regs_base->kr.an_data, val);
+		} else {
+			al_reg_write32(&adapter->mac_regs_base->kr.pma_addr, reg_addr);
+			al_reg_write32(&adapter->mac_regs_base->kr.pma_data, val);
+		}
+	} else {
+		struct al_an_lt_wrapper_regs *regs = NULL;
+
+		reg_addr = al_eth_an_lt_regs_addr[reg_id][AL_ETH_LT_UNIT_REV_2];
+
+		switch (lane) {
+		case AL_ETH_AN__LT_LANE_0:
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_data,
+				       reg_addr);
+
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_data,
+				       val);
+			break;
+		case AL_ETH_AN__LT_LANE_1:
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_data,
+				       reg_addr);
+
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_data,
+				       val);
+			break;
+		case AL_ETH_AN__LT_LANE_2:
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_data,
+				       reg_addr);
+
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_data,
+				       val);
+			break;
+		case AL_ETH_AN__LT_LANE_3:
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].addr);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_data,
+				       reg_addr);
+
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_addr,
+				       (uintptr_t)&regs->an_lt[adapter->curr_lt_unit].data);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_data,
+				       val);
+			break;
+		default:
+			al_err("%s: Unknown Lane %d\n", __func__, lane);
+			return;
+		}
+	}
+
+
+	al_dbg("[%s]: %s - (%s) lane %d, reg %d, val 0x%x", adapter->name, __func__,
+	       (an_lt == AL_ETH_AN_REGS) ? "AN" : "LT", lane, reg_addr, val);
+}
+
+static void al_eth_an_lt_unit_config(struct al_hal_eth_adapter *adapter)
+{
+	struct al_an_lt_wrapper_regs *regs = NULL;
+	uint32_t cfg_lane_0 = (AN_LT_WRAPPER_GEN_CFG_BYPASS_RX | AN_LT_WRAPPER_GEN_CFG_BYPASS_TX);
+	uint32_t cfg_lane_1 = (AN_LT_WRAPPER_GEN_CFG_BYPASS_RX | AN_LT_WRAPPER_GEN_CFG_BYPASS_TX);
+	uint32_t cfg_lane_2 = (AN_LT_WRAPPER_GEN_CFG_BYPASS_RX | AN_LT_WRAPPER_GEN_CFG_BYPASS_TX);
+	uint32_t cfg_lane_3 = (AN_LT_WRAPPER_GEN_CFG_BYPASS_RX | AN_LT_WRAPPER_GEN_CFG_BYPASS_TX);
+
+	switch (adapter->mac_mode) {
+	case AL_ETH_MAC_MODE_10GbE_Serial:
+		cfg_lane_0 = 0;
+		AL_REG_FIELD_SET(cfg_lane_0,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_20_BIT);
+		AL_REG_FIELD_SET(cfg_lane_0,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_20_BIT);
+
+		adapter->curr_lt_unit = AL_ETH_AN_LT_UNIT_20_BIT;
+
+		break;
+	case AL_ETH_MAC_MODE_KR_LL_25G:
+		cfg_lane_0 = 0;
+		AL_REG_FIELD_SET(cfg_lane_0,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_32_BIT);
+		AL_REG_FIELD_SET(cfg_lane_0,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_32_BIT);
+
+		adapter->curr_lt_unit = AL_ETH_AN_LT_UNIT_32_BIT;
+
+		break;
+	case AL_ETH_MAC_MODE_XLG_LL_40G:
+		cfg_lane_0 = 0;
+		AL_REG_FIELD_SET(cfg_lane_0,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_16_BIT);
+		AL_REG_FIELD_SET(cfg_lane_0,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_16_BIT);
+
+		cfg_lane_1 = 0;
+		AL_REG_FIELD_SET(cfg_lane_1,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_16_BIT);
+		AL_REG_FIELD_SET(cfg_lane_1,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_16_BIT);
+
+		cfg_lane_2 = 0;
+		AL_REG_FIELD_SET(cfg_lane_2,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_16_BIT);
+		AL_REG_FIELD_SET(cfg_lane_2,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_16_BIT);
+
+		cfg_lane_3 = 0;
+		AL_REG_FIELD_SET(cfg_lane_3,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_16_BIT);
+		AL_REG_FIELD_SET(cfg_lane_3,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_16_BIT);
+
+		adapter->curr_lt_unit = AL_ETH_AN_LT_UNIT_16_BIT;
+
+		break;
+	case AL_ETH_MAC_MODE_XLG_LL_50G:
+		cfg_lane_0 = 0;
+		AL_REG_FIELD_SET(cfg_lane_0,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_32_BIT);
+		AL_REG_FIELD_SET(cfg_lane_0,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_32_BIT);
+
+		cfg_lane_1 = 0;
+		AL_REG_FIELD_SET(cfg_lane_1,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_32_BIT);
+		AL_REG_FIELD_SET(cfg_lane_1,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK,
+				 AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT,
+				 AL_ETH_AN_LT_UNIT_32_BIT);
+
+		adapter->curr_lt_unit = AL_ETH_AN_LT_UNIT_32_BIT;
+
+		break;
+	default:
+		al_err("%s: Unknown mac_mode\n", __func__);
+		return;
+	}
+
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_addr,
+		       (uintptr_t)&regs->gen.cfg);
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_0_data,
+		       cfg_lane_0);
+
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_addr,
+		       (uintptr_t)&regs->gen.cfg);
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_1_data,
+		       cfg_lane_1);
+
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_addr,
+		       (uintptr_t)&regs->gen.cfg);
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_2_data,
+		       cfg_lane_2);
+
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_addr,
+		       (uintptr_t)&regs->gen.cfg);
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.an_lt_3_data,
+		       cfg_lane_3);
+}
+
+void al_eth_lp_coeff_up_get(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_an_lt_lane lane,
+			struct al_eth_kr_coef_up_data *lpcoeff)
+{
+	uint16_t reg;
+
+	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_LP_COEF_UP, AL_ETH_LT_REGS, lane);
+
+	lpcoeff->preset =
+		(AL_REG_BIT_GET(
+			reg, AL_ETH_KR_PMD_LP_COEF_UP_PRESET_SHIFT) != 0);
+
+	lpcoeff->initialize =
+		(AL_REG_BIT_GET(
+			reg, AL_ETH_KR_PMD_LP_COEF_UP_INITIALIZE_SHIFT) != 0);
+
+	lpcoeff->c_minus = AL_REG_FIELD_GET(reg,
+					AL_ETH_KR_PMD_LP_COEF_UP_MINUS_MASK,
+					AL_ETH_KR_PMD_LP_COEF_UP_MINUS_SHIFT);
+
+	lpcoeff->c_zero = AL_REG_FIELD_GET(reg,
+					AL_ETH_KR_PMD_LP_COEF_UP_ZERO_MASK,
+					AL_ETH_KR_PMD_LP_COEF_UP_ZERO_SHIFT);
+
+	lpcoeff->c_plus = AL_REG_FIELD_GET(reg,
+					AL_ETH_KR_PMD_LP_COEF_UP_PLUS_MASK,
+					AL_ETH_KR_PMD_LP_COEF_UP_PLUS_SHIFT);
+}
+
+void al_eth_lp_status_report_get(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_an_lt_lane lane,
+			struct al_eth_kr_status_report_data *status)
+{
+	uint16_t reg;
+
+	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_LP_STATUS_REPORT, AL_ETH_LT_REGS, lane);
+
+	status->c_minus = AL_REG_FIELD_GET(reg,
+				    AL_ETH_KR_PMD_LP_STATUS_REPORT_MINUS_MASK,
+				    AL_ETH_KR_PMD_LP_STATUS_REPORT_MINUS_SHIFT);
+
+	status->c_zero = AL_REG_FIELD_GET(reg,
+				   AL_ETH_KR_PMD_LP_STATUS_REPORT_ZERO_MASK,
+				   AL_ETH_KR_PMD_LP_STATUS_REPORT_ZERO_SHIFT);
+
+	status->c_plus = AL_REG_FIELD_GET(reg,
+				   AL_ETH_KR_PMD_LP_STATUS_REPORT_PLUS_MASK,
+				   AL_ETH_KR_PMD_LP_STATUS_REPORT_PLUS_SHIFT);
+
+	status->receiver_ready =
+		(AL_REG_BIT_GET(
+			reg, AL_ETH_KR_PMD_LP_STATUS_RECEIVER_READY_SHIFT) != 0);
+
+}
+
+void al_eth_ld_coeff_up_set(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_an_lt_lane lane,
+			struct al_eth_kr_coef_up_data *ldcoeff)
+{
+	uint16_t reg = 0;
+
+	if (ldcoeff->preset)
+		AL_REG_BIT_SET(reg, AL_ETH_KR_PMD_LD_COEF_UP_PRESET_SHIFT);
+
+	if (ldcoeff->initialize)
+		AL_REG_BIT_SET(reg, AL_ETH_KR_PMD_LD_COEF_UP_INITIALIZE_SHIFT);
+
+	AL_REG_FIELD_SET(reg,
+			 AL_ETH_KR_PMD_LD_COEF_UP_MINUS_MASK,
+			 AL_ETH_KR_PMD_LD_COEF_UP_MINUS_SHIFT,
+			 ldcoeff->c_minus);
+
+	AL_REG_FIELD_SET(reg,
+			 AL_ETH_KR_PMD_LD_COEF_UP_ZERO_MASK,
+			 AL_ETH_KR_PMD_LD_COEF_UP_ZERO_SHIFT,
+			 ldcoeff->c_zero);
+
+	AL_REG_FIELD_SET(reg,
+			 AL_ETH_KR_PMD_LD_COEF_UP_PLUS_MASK,
+			 AL_ETH_KR_PMD_LD_COEF_UP_PLUS_SHIFT,
+			 ldcoeff->c_plus);
+
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_LD_COEF_UP, AL_ETH_LT_REGS, lane, reg);
+}
+
+void al_eth_ld_status_report_set(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_an_lt_lane lane,
+			struct al_eth_kr_status_report_data *status)
+{
+	uint16_t reg = 0;
+
+	AL_REG_FIELD_SET(reg,
+			 AL_ETH_KR_PMD_LD_STATUS_REPORT_MINUS_MASK,
+			 AL_ETH_KR_PMD_LD_STATUS_REPORT_MINUS_SHIFT,
+			 status->c_minus);
+
+	AL_REG_FIELD_SET(reg,
+			 AL_ETH_KR_PMD_LD_STATUS_REPORT_ZERO_MASK,
+			 AL_ETH_KR_PMD_LD_STATUS_REPORT_ZERO_SHIFT,
+			 status->c_zero);
+
+	AL_REG_FIELD_SET(reg,
+			 AL_ETH_KR_PMD_LD_STATUS_REPORT_PLUS_MASK,
+			 AL_ETH_KR_PMD_LD_STATUS_REPORT_PLUS_SHIFT,
+			 status->c_plus);
+
+	if (status->receiver_ready)
+		AL_REG_BIT_SET(reg,
+			AL_ETH_KR_PMD_LD_STATUS_REPORT_RECEIVER_READY_SHIFT);
+
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_LD_STATUS_REPORT, AL_ETH_LT_REGS, lane, reg);
+}
+
+al_bool al_eth_kr_receiver_frame_lock_get(struct al_hal_eth_adapter *adapter,
+					  enum al_eth_an_lt_lane lane)
+{
+	uint16_t reg;
+
+	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane);
+
+	return (AL_REG_BIT_GET(reg,
+			AL_ETH_KR_PMD_STATUS_RECEIVER_FRAME_LOCK_SHIFT) != 0);
+}
+
+al_bool al_eth_kr_startup_proto_prog_get(struct al_hal_eth_adapter *adapter,
+					 enum al_eth_an_lt_lane lane)
+{
+	uint16_t reg;
+
+	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane);
+
+	return (AL_REG_BIT_GET(
+		reg, AL_ETH_KR_PMD_STATUS_RECEIVER_START_UP_PROTO_PROG_SHIFT) != 0);
+}
+
+al_bool al_eth_kr_training_status_fail_get(struct al_hal_eth_adapter *adapter,
+					   enum al_eth_an_lt_lane lane)
+{
+	uint16_t reg;
+
+	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane);
+
+	return (AL_REG_BIT_GET(reg, AL_ETH_KR_PMD_STATUS_FAILURE_SHIFT) != 0);
+}
+
+void al_eth_receiver_ready_set(struct al_hal_eth_adapter *adapter,
+			       enum al_eth_an_lt_lane lane)
+{
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane, 1);
+}
+
+/*************************** auto negotiation *********************************/
+static int al_eth_kr_an_validate_adv(struct al_hal_eth_adapter *adapter,
+				     struct al_eth_an_adv *an_adv)
+{
+	al_assert(adapter);
+
+	if (an_adv == NULL)
+		return 0;
+
+	if (an_adv->selector_field != 1) {
+		al_err("[%s]: %s failed on selector_field (%d)\n",
+			adapter->name, __func__, an_adv->selector_field);
+		return -EINVAL;
+	}
+
+	if (an_adv->capability & AL_BIT(2)) {
+		al_err("[%s]: %s failed on capability bit 2 (%d)\n",
+			adapter->name, __func__, an_adv->capability);
+		return -EINVAL;
+	}
+
+	if (an_adv->remote_fault) {
+		al_err("[%s]: %s failed on remote_fault (%d)\n",
+			adapter->name, __func__, an_adv->remote_fault);
+		return -EINVAL;
+	}
+
+	if (an_adv->acknowledge) {
+		al_err("[%s]: %s failed on acknowledge (%d)\n",
+			adapter->name, __func__, an_adv->acknowledge);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int al_eth_kr_an_write_adv(struct al_hal_eth_adapter *adapter,
+			       struct al_eth_an_adv *an_adv)
+{
+	uint16_t	reg;
+
+	if(an_adv == NULL)
+		return 0;
+
+	reg = 0;
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV1_SEL_FIELD_MASK,
+			 AL_ETH_KR_AN_ADV1_SEL_FIELD_SHIFT,
+			 an_adv->selector_field);
+
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV1_ECHOED_NONCE_MASK,
+			 AL_ETH_KR_AN_ADV1_ECHOED_NONCE_SHIFT,
+			 an_adv->echoed_nonce);
+
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV1_CAPABILITY_MASK,
+			 AL_ETH_KR_AN_ADV1_CAPABILITY_SHIFT,
+			 an_adv->capability);
+
+	AL_REG_BIT_VAL_SET(reg, AL_ETH_KR_AN_ADV1_REM_FAULT_SHIFT,
+			   an_adv->remote_fault);
+
+	AL_REG_BIT_VAL_SET(reg, AL_ETH_KR_AN_ADV1_ACK_SHIFT,
+			   an_adv->acknowledge);
+
+	AL_REG_BIT_VAL_SET(reg, AL_ETH_KR_AN_ADV1_NEXT_PAGE_SHIFT,
+			   an_adv->next_page);
+
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_ADV0, AL_ETH_AN_REGS,
+			       AL_ETH_AN__LT_LANE_0, reg);
+
+	reg = 0;
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV2_TX_NONCE_MASK,
+			 AL_ETH_KR_AN_ADV2_TX_NONCE_SHIFT,
+			 an_adv->transmitted_nonce);
+
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV2_TECH_MASK,
+			 AL_ETH_KR_AN_ADV2_TECH_SHIFT,
+			 an_adv->technology);
+
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_ADV1, AL_ETH_AN_REGS,
+			       AL_ETH_AN__LT_LANE_0, reg);
+
+	reg = 0;
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV3_TECH_MASK,
+			 AL_ETH_KR_AN_ADV3_TECH_SHIFT,
+			 an_adv->technology >> 11);
+
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_ADV3_FEC_MASK,
+			 AL_ETH_KR_AN_ADV3_FEC_SHIFT,
+			 an_adv->fec_capability);
+
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_ADV2, AL_ETH_AN_REGS,
+			       AL_ETH_AN__LT_LANE_0, reg);
+
+	return 0;
+}
+
+void al_eth_kr_an_read_adv(struct al_hal_eth_adapter *adapter,
+			   struct al_eth_an_adv *an_adv)
+{
+	int16_t	reg;
+
+	al_assert(an_adv != NULL);
+
+
+	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_AN_REM_ADV0,
+				    AL_ETH_AN_REGS, AL_ETH_AN__LT_LANE_0);
+
+	an_adv->selector_field = AL_REG_FIELD_GET(reg,
+					AL_ETH_KR_AN_ADV1_SEL_FIELD_MASK,
+					AL_ETH_KR_AN_ADV1_SEL_FIELD_SHIFT);
+
+	an_adv->echoed_nonce = AL_REG_FIELD_GET(reg,
+					AL_ETH_KR_AN_ADV1_ECHOED_NONCE_MASK,
+					AL_ETH_KR_AN_ADV1_ECHOED_NONCE_SHIFT);
+
+	an_adv->capability = AL_REG_FIELD_GET(reg,
+					AL_ETH_KR_AN_ADV1_CAPABILITY_MASK,
+					AL_ETH_KR_AN_ADV1_CAPABILITY_SHIFT);
+
+	an_adv->remote_fault = AL_REG_BIT_GET(reg,
+					AL_ETH_KR_AN_ADV1_REM_FAULT_SHIFT);
+
+	an_adv->acknowledge = AL_REG_BIT_GET(reg,
+					AL_ETH_KR_AN_ADV1_ACK_SHIFT);
+
+	an_adv->next_page = AL_REG_BIT_GET(reg,
+					AL_ETH_KR_AN_ADV1_NEXT_PAGE_SHIFT);
+
+
+	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_AN_REM_ADV1,
+				    AL_ETH_AN_REGS, AL_ETH_AN__LT_LANE_0);
+
+	an_adv->transmitted_nonce = AL_REG_FIELD_GET(reg,
+					 AL_ETH_KR_AN_ADV2_TX_NONCE_MASK,
+					 AL_ETH_KR_AN_ADV2_TX_NONCE_SHIFT);
+
+	an_adv->technology = AL_REG_FIELD_GET(reg,
+					 AL_ETH_KR_AN_ADV2_TECH_MASK,
+					 AL_ETH_KR_AN_ADV2_TECH_SHIFT);
+
+
+	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_AN_REM_ADV2,
+				    AL_ETH_AN_REGS, AL_ETH_AN__LT_LANE_0);
+
+	an_adv->technology |= (AL_REG_FIELD_GET(reg,
+					AL_ETH_KR_AN_ADV3_TECH_MASK,
+					AL_ETH_KR_AN_ADV3_TECH_SHIFT)  << 11);
+
+	an_adv->fec_capability = AL_REG_FIELD_GET(reg,
+					 AL_ETH_KR_AN_ADV3_FEC_MASK,
+					 AL_ETH_KR_AN_ADV3_FEC_SHIFT);
+}
+
+int al_eth_kr_next_page_read(struct al_hal_eth_adapter *adapter,
+			     struct al_eth_an_np *np)
+{
+	uint16_t reg;
+
+	reg = al_eth_an_lt_reg_read(adapter,
+				    AL_ETH_KR_AN_REM_XNP_ADV0,
+				    AL_ETH_AN_REGS,
+				    AL_ETH_AN__LT_LANE_0);
+
+	np->unformatted_code_field = AL_REG_FIELD_GET(reg, AL_ETH_KR_AN_NP_ADV1_DATA1_MASK,
+					 AL_ETH_KR_AN_NP_ADV1_DATA1_SHIFT);
+
+	np->toggle = AL_REG_FIELD_GET(reg, AL_ETH_KR_AN_NP_ADV1_TOGGLE_MASK,
+					 AL_ETH_KR_AN_NP_ADV1_TOGGLE_SHIFT);
+
+	np->ack2 = AL_REG_FIELD_GET(reg, AL_ETH_KR_AN_NP_ADV1_ACK2_MASK,
+					 AL_ETH_KR_AN_NP_ADV1_ACK2_SHIFT);
+
+	np->msg_page = AL_REG_FIELD_GET(reg, AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_MASK,
+					 AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_SHIFT);
+
+	np->next_page = AL_REG_FIELD_GET(reg, AL_ETH_KR_AN_NP_ADV1_NP_MASK,
+					 AL_ETH_KR_AN_NP_ADV1_NP_SHIFT);
+
+	np->unformatted_code_field1 = al_eth_an_lt_reg_read(adapter,
+							    AL_ETH_KR_AN_REM_XNP_ADV1,
+							    AL_ETH_AN_REGS,
+							    AL_ETH_AN__LT_LANE_0);
+	np->unformatted_code_field2 = al_eth_an_lt_reg_read(adapter,
+							    AL_ETH_KR_AN_REM_XNP_ADV2,
+							    AL_ETH_AN_REGS,
+							    AL_ETH_AN__LT_LANE_0);
+
+	return 0;
+}
+
+int al_eth_kr_next_page_write(struct al_hal_eth_adapter *adapter,
+			      struct al_eth_an_np *np)
+{
+	uint16_t reg = 0;
+
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_NP_ADV1_DATA1_MASK,
+			 AL_ETH_KR_AN_NP_ADV1_DATA1_SHIFT,
+			 np->unformatted_code_field);
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_NP_ADV1_TOGGLE_MASK,
+			 AL_ETH_KR_AN_NP_ADV1_TOGGLE_SHIFT,
+			 np->toggle);
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_NP_ADV1_ACK2_MASK,
+			 AL_ETH_KR_AN_NP_ADV1_ACK2_SHIFT,
+			 np->ack2);
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_MASK,
+			 AL_ETH_KR_AN_NP_ADV1_MSG_PAGE_SHIFT,
+			 np->msg_page);
+	AL_REG_FIELD_SET(reg, AL_ETH_KR_AN_NP_ADV1_NP_MASK,
+			 AL_ETH_KR_AN_NP_ADV1_NP_SHIFT,
+			 np->next_page);
+
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_XNP_ADV0, AL_ETH_AN_REGS,
+			       AL_ETH_AN__LT_LANE_0, reg);
+
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_XNP_ADV1, AL_ETH_AN_REGS,
+			       AL_ETH_AN__LT_LANE_0, np->unformatted_code_field1);
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_XNP_ADV2, AL_ETH_AN_REGS,
+			       AL_ETH_AN__LT_LANE_0, np->unformatted_code_field2);
+
+	return 0;
+}
+
+int al_eth_kr_an_init(struct al_hal_eth_adapter *adapter,
+		      struct al_eth_an_adv *an_adv)
+{
+	int		rc;
+
+	if (adapter->rev_id > AL_ETH_REV_ID_2)
+		al_eth_an_lt_unit_config(adapter);
+
+	rc = al_eth_kr_an_validate_adv(adapter, an_adv);
+	if (rc)
+		return rc;
+
+	rc = al_eth_kr_an_write_adv(adapter, an_adv);
+	if (rc)
+		return rc;
+
+	/* clear status */
+	al_eth_an_lt_reg_read(adapter, AL_ETH_KR_AN_STATUS, AL_ETH_AN_REGS, AL_ETH_AN__LT_LANE_0);
+
+	al_dbg("[%s]: autonegotiation initialized successfully", adapter->name);
+	return 0;
+}
+
+int al_eth_kr_an_start(struct al_hal_eth_adapter *adapter,
+		       enum al_eth_an_lt_lane lane,
+		       al_bool next_page_enable,
+		       al_bool lt_enable)
+{
+	uint16_t control = AL_ETH_KR_AN_CONTROL_ENABLE | AL_ETH_KR_AN_CONTROL_RESTART;
+
+	al_dbg("Eth [%s]: enable autonegotiation. lt_en %s",
+		adapter->name, (lt_enable == AL_TRUE) ? "yes" : "no");
+
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_CONTROL, AL_ETH_LT_REGS,
+			       lane, AL_BIT(AL_ETH_KR_PMD_CONTROL_RESTART));
+
+	if (next_page_enable == AL_TRUE)
+		control |= AL_ETH_KR_AN_CONTROL_NP_ENABLE;
+
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_CONTROL, AL_ETH_AN_REGS,
+			       lane, control);
+
+	if (lt_enable == AL_TRUE) {
+		al_eth_kr_lt_initialize(adapter, lane);
+	}
+
+	return 0;
+}
+
+void al_eth_kr_an_stop(struct al_hal_eth_adapter *adapter)
+{
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_AN_CONTROL, AL_ETH_AN_REGS,
+			       AL_ETH_AN__LT_LANE_0, 0);
+}
+
+void al_eth_kr_an_status_check(struct al_hal_eth_adapter *adapter,
+			      al_bool *page_received,
+			      al_bool *an_completed,
+			      al_bool *error)
+{
+	uint16_t	reg;
+
+	reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_AN_STATUS,
+				    AL_ETH_AN_REGS, AL_ETH_AN__LT_LANE_0);
+
+	if ((reg & AL_ETH_KR_AN_STATUS_CHECK_MASK) !=
+				AL_ETH_KR_AN_STATUS_CHECK_NO_ERROR) {
+		al_err("[%s]: %s AN_STATUS (0x%x) indicated error\n",
+			adapter->name, __func__, reg);
+
+		*error = AL_TRUE;
+	}
+
+	if (reg & AL_ETH_KR_AN_STATUS_BASE_PAGE_RECEIVED)
+		*page_received = AL_TRUE;
+	else
+		*page_received = AL_FALSE;
+
+	if (reg & AL_ETH_KR_AN_STATUS_COMPLETED)
+		*an_completed = AL_TRUE;
+	else
+		*an_completed = AL_FALSE;
+}
+
+
+/****************************** KR Link Training *****************************/
+void al_eth_kr_lt_restart(struct al_hal_eth_adapter *adapter,
+			  enum al_eth_an_lt_lane lane)
+{
+	al_dbg("[%s]: KR LT Restart Link Training.\n", adapter->name);
+
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_CONTROL, AL_ETH_LT_REGS,
+			       lane, (AL_BIT(AL_ETH_KR_PMD_CONTROL_ENABLE) |
+				      AL_BIT(AL_ETH_KR_PMD_CONTROL_RESTART)));
+}
+
+void al_eth_kr_lt_stop(struct al_hal_eth_adapter *adapter,
+		       enum al_eth_an_lt_lane lane)
+{
+	al_dbg("[%s]: KR LT Stop Link Training.\n", adapter->name);
+
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_CONTROL, AL_ETH_LT_REGS,
+			       lane, AL_BIT(AL_ETH_KR_PMD_CONTROL_RESTART));
+}
+
+void al_eth_kr_lt_initialize(struct al_hal_eth_adapter *adapter,
+			     enum al_eth_an_lt_lane lane)
+{
+	al_dbg("[%s]: KR LT Initialize.\n", adapter->name);
+
+	/* Reset LT state machine */
+	al_eth_kr_lt_stop(adapter, lane);
+
+	/* clear receiver status */
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane, 0);
+
+	/* Coefficient Update to all zero (no command, hold) */
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_LD_COEF_UP, AL_ETH_LT_REGS, lane, 0);
+	/* Coefficient Status to all zero (not_updated) */
+	al_eth_an_lt_reg_write(adapter, AL_ETH_KR_PMD_LD_STATUS_REPORT, AL_ETH_LT_REGS, lane, 0);
+
+	/* start */
+	al_eth_kr_lt_restart(adapter, lane);
+}
+
+al_bool al_eth_kr_lt_frame_lock_wait(struct al_hal_eth_adapter *adapter,
+				     enum al_eth_an_lt_lane lane,
+				     uint32_t timeout)
+{
+	uint32_t loop;
+	uint16_t reg = 0;
+
+	for (loop = 0; loop < timeout; loop++) {
+		reg = al_eth_an_lt_reg_read(adapter, AL_ETH_KR_PMD_STATUS, AL_ETH_LT_REGS, lane);
+
+		if (AL_REG_BIT_GET(reg, AL_ETH_KR_PMD_STATUS_FAILURE_SHIFT)) {
+			al_info("[%s]: Failed on Training Failure."
+			       " loops %d PMD STATUS 0x%04x\n",
+			       adapter->name, loop, reg);
+
+			return AL_FALSE;
+		}
+		if (AL_REG_BIT_GET(reg,
+			AL_ETH_KR_PMD_STATUS_RECEIVER_FRAME_LOCK_SHIFT)) {
+			al_dbg("[%s]: Frame lock received."
+			       " loops %d PMD STATUS 0x%04x\n",
+			       adapter->name, loop, reg);
+
+			return AL_TRUE;
+		}
+		al_udelay(1);
+	}
+	al_info("[%s]: Failed on timeout. PMD STATUS 0x%04x\n",
+			adapter->name, reg);
+
+	return AL_FALSE;
+}
diff --git a/sys/contrib/alpine-hal/eth/al_hal_eth_kr.h b/sys/contrib/alpine-hal/eth/al_hal_eth_kr.h
new file mode 100644
index 000000000000..c8b69460aaa7
--- /dev/null
+++ b/sys/contrib/alpine-hal/eth/al_hal_eth_kr.h
@@ -0,0 +1,372 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+/**
+ * @defgroup group_eth_kr_api API
+ * Ethernet KR auto-neg and link-training driver API
+ * @ingroup group_eth
+ * @{
+ * @file   al_hal_eth_kr.h
+ *
+ * @brief Header file for KR driver
+ *
+ *
+ */
+
+#ifndef __AL_HAL_ETH_KR_H__
+#define __AL_HAL_ETH_KR_H__
+
+#include "al_hal_eth.h"
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/* AN (Auto-negotiation) Advertisement Registers */
+struct al_eth_an_adv {
+	/* constant value defining 802.3ap support.
+	 * The suggested value is 0x01.*/
+	uint8_t   selector_field;
+	/* Contains arbitrary data. */
+	uint8_t   echoed_nonce;
+	/* pause capability. */
+	uint8_t   capability;
+	/* Set to 1 to indicate a Remote Fault condition.
+	 * Set to 0 to indicate normal operation.*/
+	uint8_t   remote_fault;
+	/* Should always be set to 0. */
+	uint8_t   acknowledge;
+	/* Set to 1 to indicate that the device has next pages to send.
+	 * Set to 0 to indicate that that device has no next pages to send. */
+	uint8_t   next_page;
+	/* Must be set to an arbitrary value.
+	 * Two devices must have a different nonce for autonegotiation to
+	 * operate (a loopback will not allow autonegotiation to complete). */
+	uint8_t   transmitted_nonce;
+	uint32_t  technology;
+#define AL_ETH_AN_TECH_1000BASE_KX  AL_BIT(0)
+#define AL_ETH_AN_TECH_10GBASE_KX4  AL_BIT(1)
+#define AL_ETH_AN_TECH_10GBASE_KR   AL_BIT(2)
+#define AL_ETH_AN_TECH_40GBASE_KR4  AL_BIT(3)
+#define AL_ETH_AN_TECH_40GBASE_CR4  AL_BIT(4)
+#define AL_ETH_AN_TECH_100GBASE_CR  AL_BIT(5)
+	uint8_t   fec_capability;
+};
+
+/* AN next page fields */
+struct al_eth_an_np {
+	/* These bits can be used as message code field or unformatted code field.
+	 * When msg_page is true, these bits represent message code field.
+	 * Predefined message code field Code Field should be used as specified in the standard
+	 * 802.3ap.
+	 * For the null message code the value is 0x01.
+	 */
+	uint16_t	unformatted_code_field;
+	/* Flag to keep track of the state of the local device's Toggle bit.
+	 * Initial value is taken from base page. Set to 0.
+	 */
+	al_bool		toggle;
+	/* Acknowledge 2 is used to indicate that the receiver is able to act on the information
+	 * (or perform the task) defined in the message.
+	 */
+	al_bool		ack2;
+	al_bool		msg_page;
+	/* If the device does not have any more Next Pages to send, set to AL_FALSE */
+	al_bool		next_page;
+	uint16_t	unformatted_code_field1;
+	uint16_t	unformatted_code_field2;
+};
+
+enum al_eth_kr_cl72_cstate {
+	C72_CSTATE_NOT_UPDATED = 0,
+	C72_CSTATE_UPDATED = 1,
+	C72_CSTATE_MIN = 2,
+	C72_CSTATE_MAX = 3,
+};
+
+enum al_eth_kr_cl72_coef_op {
+	AL_PHY_KR_COEF_UP_HOLD = 0,
+	AL_PHY_KR_COEF_UP_INC = 1,
+	AL_PHY_KR_COEF_UP_DEC = 2,
+	AL_PHY_KR_COEF_UP_RESERVED = 3
+};
+
+struct al_eth_kr_coef_up_data {
+	enum al_eth_kr_cl72_coef_op c_zero;
+	enum al_eth_kr_cl72_coef_op c_plus;
+	enum al_eth_kr_cl72_coef_op c_minus;
+	al_bool preset;
+	al_bool initialize;
+};
+
+struct al_eth_kr_status_report_data {
+	enum al_eth_kr_cl72_cstate c_zero;
+	enum al_eth_kr_cl72_cstate c_plus;
+	enum al_eth_kr_cl72_cstate c_minus;
+	al_bool receiver_ready;
+};
+
+enum al_eth_an_lt_lane {
+	AL_ETH_AN__LT_LANE_0,
+	AL_ETH_AN__LT_LANE_1,
+	AL_ETH_AN__LT_LANE_2,
+	AL_ETH_AN__LT_LANE_3,
+};
+
+/**
+ * get the last received coefficient update message from the link partner
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ * @param lpcoeff coeff update received
+ *
+ */
+void al_eth_lp_coeff_up_get(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_an_lt_lane lane,
+			struct al_eth_kr_coef_up_data *lpcoeff);
+
+/**
+ * get the last received status report message from the link partner
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ * @param status status report received
+ *
+ */
+void al_eth_lp_status_report_get(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_an_lt_lane lane,
+			struct al_eth_kr_status_report_data *status);
+
+/**
+ * set the coefficient data for the next message that will be sent to lp
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ * @param ldcoeff coeff update to send
+ *
+ */
+void al_eth_ld_coeff_up_set(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_an_lt_lane lane,
+			struct al_eth_kr_coef_up_data *ldcoeff);
+
+/**
+ * set the status report message for the next message that will be sent to lp
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ * @param status status report to send
+ *
+ */
+void al_eth_ld_status_report_set(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_an_lt_lane lane,
+			struct al_eth_kr_status_report_data *status);
+
+/**
+ * get the receiver frame lock status
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ *
+ * @return true if Training frame delineation is detected, otherwise false.
+ */
+al_bool al_eth_kr_receiver_frame_lock_get(struct al_hal_eth_adapter *adapter,
+					  enum al_eth_an_lt_lane lane);
+
+/**
+ * get the start up protocol progress status
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ *
+ * @return true if the startup protocol is in progress.
+ */
+al_bool al_eth_kr_startup_proto_prog_get(struct al_hal_eth_adapter *adapter,
+					 enum al_eth_an_lt_lane lane);
+
+/**
+ * indicate the receiver is ready (the link training is completed)
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ *
+ */
+void al_eth_receiver_ready_set(struct al_hal_eth_adapter *adapter,
+			       enum al_eth_an_lt_lane lane);
+
+/**
+ * read Training failure status.
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ *
+ *@return true if Training failure has been detected.
+ */
+al_bool al_eth_kr_training_status_fail_get(struct al_hal_eth_adapter *adapter,
+					   enum al_eth_an_lt_lane lane);
+
+/****************************** auto negotiation *******************************/
+/**
+ * Initialize Auto-negotiation
+ * - Program Ability Registers (Advertisement Registers)
+ * - Clear Status latches
+ * @param adapter pointer to the private structure
+ * @param an_adv pointer to the AN Advertisement Registers structure
+ *        when NULL, the registers will not be updated.
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_kr_an_init(struct al_hal_eth_adapter *adapter,
+		      struct al_eth_an_adv *an_adv);
+
+/**
+ * Enable/Restart Auto-negotiation
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ * @param lt_enable initialize link training as well
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_kr_an_start(struct al_hal_eth_adapter *adapter,
+		       enum al_eth_an_lt_lane lane,
+		       al_bool next_page_enable,
+		       al_bool lt_enable);
+
+
+int al_eth_kr_next_page_write(struct al_hal_eth_adapter *adapter,
+			      struct al_eth_an_np *np);
+
+int al_eth_kr_next_page_read(struct al_hal_eth_adapter *adapter,
+			     struct al_eth_an_np *np);
+
+/**
+ * Stop Auto-negotiation
+ *
+ * Stopping the auto-negotiation will prevent the mac from sending the last page
+ * to the link partner in case it start the AN again. It must be called after
+ * link training is completed or the software will lose sync with the HW state
+ * machine
+ *
+ * @param adapter pointer to the private structure
+ *
+ */
+void al_eth_kr_an_stop(struct al_hal_eth_adapter *adapter);
+
+/**
+ *  Check Auto-negotiation event done
+ *
+ * @param adapter pointer to the private structure
+ * @param page_received	Set to true if the AN page received indication is set.
+ *			Set to false otherwise.
+ * @param an_completed	Set to true of the AN completed indication is set.
+ *			Set to false otherwise.
+ * @param error	Set to true if any error encountered
+ *
+ */
+void al_eth_kr_an_status_check(struct al_hal_eth_adapter *adapter,
+			      al_bool *page_received,
+			      al_bool *an_completed,
+			      al_bool *error);
+
+/**
+ *  Read the remote auto-negotiation advertising.
+ *  This function is safe to called after al_eth_kr_an_status_check returned
+ *  with page_received set.
+ *
+ * @param adapter pointer to the private structure
+ * @param an_adv pointer to the AN Advertisement Registers structure
+ *
+ */
+void al_eth_kr_an_read_adv(struct al_hal_eth_adapter *adapter,
+			   struct al_eth_an_adv *an_adv);
+
+/****************************** link training **********************************/
+/**
+ *  Initialize Link-training.
+ *  Clear the status register and set the local coefficient update and status
+ *  to zero.
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ *
+ */
+void al_eth_kr_lt_initialize(struct al_hal_eth_adapter *adapter,
+			     enum al_eth_an_lt_lane lane);
+
+/**
+ * Wait for frame lock.
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ * @param timeout timeout in usec.
+ *
+ * @return true if frame lock received. false otherwise.
+ */
+al_bool al_eth_kr_lt_frame_lock_wait(struct al_hal_eth_adapter *adapter,
+				     enum al_eth_an_lt_lane lane,
+				     uint32_t timeout);
+
+/**
+ * reset the 10GBase- KR startup protocol and begin its operation
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ *
+ */
+void al_eth_kr_lt_restart(struct al_hal_eth_adapter *adapter,
+			  enum al_eth_an_lt_lane lane);
+
+/**
+ * reset the 10GBase- KR startup protocol and end its operation
+ *
+ * @param adapter pointer to the private structure
+ * @param lane lane number
+ *
+ */
+void al_eth_kr_lt_stop(struct al_hal_eth_adapter *adapter,
+		       enum al_eth_an_lt_lane lane);
+
+#ifdef __cplusplus
+}
+#endif
+/* *INDENT-ON* */
+#endif /*__AL_HAL_ETH_KR_H__*/
+/** @} end of Ethernet kr group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_eth_mac_regs.h b/sys/contrib/alpine-hal/eth/al_hal_eth_mac_regs.h
new file mode 100644
index 000000000000..a2dc745ffde9
--- /dev/null
+++ b/sys/contrib/alpine-hal/eth/al_hal_eth_mac_regs.h
@@ -0,0 +1,1809 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ *  @{
+ * @file   al_hal_eth_mac_regs.h
+ *
+ * @brief Ethernet MAC registers
+ *
+ */
+
+#ifndef __AL_HAL_ETH_MAC_REGS_H__
+#define __AL_HAL_ETH_MAC_REGS_H__
+
+#include "al_hal_plat_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+* Unit Registers
+*/
+
+struct al_eth_mac_1g {
+	/* [0x0] */
+	uint32_t rev;
+	uint32_t scratch;
+	uint32_t cmd_cfg;
+	uint32_t mac_0;
+	/* [0x10] */
+	uint32_t mac_1;
+	uint32_t frm_len;
+	uint32_t pause_quant;
+	uint32_t rx_section_empty;
+	/* [0x20] */
+	uint32_t rx_section_full;
+	uint32_t tx_section_empty;
+	uint32_t tx_section_full;
+	uint32_t rx_almost_empty;
+	/* [0x30] */
+	uint32_t rx_almost_full;
+	uint32_t tx_almost_empty;
+	uint32_t tx_almost_full;
+	uint32_t mdio_addr0;
+	/* [0x40] */
+	uint32_t mdio_addr1;
+	uint32_t Reserved[5];
+	/* [0x58] */
+	uint32_t reg_stat;
+	uint32_t tx_ipg_len;
+	/* [0x60] */
+	uint32_t Reserved1[104];
+	/* [0x200] */
+	uint32_t phy_regs_base;
+	uint32_t Reserved2[127];
+};
+
+struct al_eth_mac_10g {
+	/* [0x0] */
+	uint32_t rev;
+	uint32_t scratch;
+	uint32_t cmd_cfg;
+	uint32_t mac_0;
+	/* [0x10] */
+	uint32_t mac_1;
+	uint32_t frm_len;
+	uint32_t Reserved;
+	uint32_t rx_fifo_sections;
+	/* [0x20] */
+	uint32_t tx_fifo_sections;
+	uint32_t rx_fifo_almost_f_e;
+	uint32_t tx_fifo_almost_f_e;
+	uint32_t hashtable_load;
+	/* [0x30] */
+	uint32_t mdio_cfg_status;
+	uint16_t mdio_cmd;
+	uint16_t reserved1;
+	uint16_t mdio_data;
+	uint16_t reserved2;
+	uint16_t mdio_regaddr;
+	uint16_t reserved3;
+	/* [0x40] */
+	uint32_t status;
+	uint32_t tx_ipg_len;
+	uint32_t Reserved1[3];
+	/* [0x54] */
+	uint32_t cl01_pause_quanta;
+	uint32_t cl23_pause_quanta;
+	uint32_t cl45_pause_quanta;
+	/* [0x60] */
+	uint32_t cl67_pause_quanta;
+	uint32_t cl01_quanta_thresh;
+	uint32_t cl23_quanta_thresh;
+	uint32_t cl45_quanta_thresh;
+	/* [0x70] */
+	uint32_t cl67_quanta_thresh;
+	uint32_t rx_pause_status;
+	uint32_t Reserved2;
+	uint32_t ts_timestamp;
+	/* [0x80] */
+
+	uint32_t Reserved3[160];
+
+	/* [0x300] */
+	uint32_t control;
+	uint32_t status_reg;
+	uint32_t phy_id[2];
+	/* [0x310] */
+	uint32_t dev_ability;
+	uint32_t partner_ability;
+	uint32_t an_expansion;
+	uint32_t device_np;
+	/* [0x320] */
+	uint32_t partner_np;
+	uint32_t Reserved4[9];
+
+	/* [0x348] */
+	uint32_t link_timer_lo;
+	uint32_t link_timer_hi;
+	/* [0x350] */
+	uint32_t if_mode;
+
+	uint32_t Reserved5[43];
+};
+
+struct al_eth_mac_gen {
+	/* [0x0]  Ethernet Controller Version */
+	uint32_t version;
+	uint32_t rsrvd_0[2];
+	/* [0xc] MAC selection configuration */
+	uint32_t cfg;
+	/* [0x10] 10/100/1000 MAC external configuration */
+	uint32_t mac_1g_cfg;
+	/* [0x14] 10/100/1000 MAC status */
+	uint32_t mac_1g_stat;
+	/* [0x18] RGMII external configuration */
+	uint32_t rgmii_cfg;
+	/* [0x1c] RGMII status */
+	uint32_t rgmii_stat;
+	/* [0x20] 1/2.5/10G MAC external configuration */
+	uint32_t mac_10g_cfg;
+	/* [0x24] 1/2.5/10G MAC status */
+	uint32_t mac_10g_stat;
+	/* [0x28] XAUI PCS configuration */
+	uint32_t xaui_cfg;
+	/* [0x2c] XAUI PCS status */
+	uint32_t xaui_stat;
+	/* [0x30] RXAUI PCS configuration */
+	uint32_t rxaui_cfg;
+	/* [0x34] RXAUI PCS status */
+	uint32_t rxaui_stat;
+	/* [0x38] Signal detect configuration */
+	uint32_t sd_cfg;
+	/* [0x3c] MDIO control register for MDIO interface 1 */
+	uint32_t mdio_ctrl_1;
+	/* [0x40] MDIO information register for MDIO interface 1 */
+	uint32_t mdio_1;
+	/* [0x44] MDIO control register for MDIO interface 2 */
+	uint32_t mdio_ctrl_2;
+	/* [0x48] MDIO information register for MDIO interface 2 */
+	uint32_t mdio_2;
+	/* [0x4c] XGMII 32 to 64 data FIFO control */
+	uint32_t xgmii_dfifo_32_64;
+	/* [0x50] Reserved 1 out */
+	uint32_t mac_res_1_out;
+	/* [0x54] XGMII 64 to 32 data FIFO control */
+	uint32_t xgmii_dfifo_64_32;
+	/* [0x58] Reserved 1 in */
+	uint32_t mac_res_1_in;
+	/* [0x5c] SerDes TX FIFO control */
+	uint32_t sd_fifo_ctrl;
+	/* [0x60] SerDes TX FIFO status */
+	uint32_t sd_fifo_stat;
+	/* [0x64] SerDes in/out selection */
+	uint32_t mux_sel;
+	/* [0x68] Clock configuration */
+	uint32_t clk_cfg;
+	uint32_t rsrvd_1;
+	/* [0x70] LOS and SD selection */
+	uint32_t los_sel;
+	/* [0x74] RGMII selection configuration */
+	uint32_t rgmii_sel;
+	/* [0x78] Ethernet LED configuration */
+	uint32_t led_cfg;
+	uint32_t rsrvd[33];
+};
+struct al_eth_mac_kr {
+	/* [0x0] PCS register file address */
+	uint32_t pcs_addr;
+	/* [0x4] PCS register file data */
+	uint32_t pcs_data;
+	/* [0x8] AN register file address */
+	uint32_t an_addr;
+	/* [0xc] AN register file data */
+	uint32_t an_data;
+	/* [0x10] PMA register file address */
+	uint32_t pma_addr;
+	/* [0x14] PMA register file data */
+	uint32_t pma_data;
+	/* [0x18] MTIP register file address */
+	uint32_t mtip_addr;
+	/* [0x1c] MTIP register file data */
+	uint32_t mtip_data;
+	/* [0x20] KR PCS config  */
+	uint32_t pcs_cfg;
+	/* [0x24] KR PCS status  */
+	uint32_t pcs_stat;
+	uint32_t rsrvd[54];
+};
+struct al_eth_mac_sgmii {
+	/* [0x0] PCS register file address */
+	uint32_t reg_addr;
+	/* [0x4] PCS register file data */
+	uint32_t reg_data;
+	/* [0x8] PCS clock divider configuration */
+	uint32_t clk_div;
+	/* [0xc] PCS Status */
+	uint32_t link_stat;
+	uint32_t rsrvd[60];
+};
+struct al_eth_mac_stat {
+	/* [0x0] Receive rate matching error */
+	uint32_t match_fault;
+	/* [0x4] EEE, number of times the MAC went into low power mode */
+	uint32_t eee_in;
+	/* [0x8] EEE, number of times the MAC went out of low power mode */
+	uint32_t eee_out;
+	/*
+	 * [0xc] 40G PCS,
+	 * FEC corrected error indication
+	 */
+	uint32_t v3_pcs_40g_ll_cerr_0;
+	/*
+	 * [0x10] 40G PCS,
+	 * FEC corrected error indication
+	 */
+	uint32_t v3_pcs_40g_ll_cerr_1;
+	/*
+	 * [0x14] 40G PCS,
+	 * FEC corrected error indication
+	 */
+	uint32_t v3_pcs_40g_ll_cerr_2;
+	/*
+	 * [0x18] 40G PCS,
+	 * FEC corrected error indication
+	 */
+	uint32_t v3_pcs_40g_ll_cerr_3;
+	/*
+	 * [0x1c] 40G PCS,
+	 * FEC uncorrectable error indication
+	 */
+	uint32_t v3_pcs_40g_ll_ncerr_0;
+	/*
+	 * [0x20] 40G PCS,
+	 * FEC uncorrectable error indication
+	 */
+	uint32_t v3_pcs_40g_ll_ncerr_1;
+	/*
+	 * [0x24] 40G PCS,
+	 * FEC uncorrectable error indication
+	 */
+	uint32_t v3_pcs_40g_ll_ncerr_2;
+	/*
+	 * [0x28] 40G PCS,
+	 * FEC uncorrectable error indication
+	 */
+	uint32_t v3_pcs_40g_ll_ncerr_3;
+	/*
+	 * [0x2c] 10G_LL PCS,
+	 * FEC corrected error indication
+	 */
+	uint32_t v3_pcs_10g_ll_cerr;
+	/*
+	 * [0x30] 10G_LL PCS,
+	 * FEC uncorrectable error indication
+	 */
+	uint32_t v3_pcs_10g_ll_ncerr;
+	uint32_t rsrvd[51];
+};
+struct al_eth_mac_stat_lane {
+	/* [0x0] Character error */
+	uint32_t char_err;
+	/* [0x4] Disparity error */
+	uint32_t disp_err;
+	/* [0x8] Comma detection */
+	uint32_t pat;
+	uint32_t rsrvd[13];
+};
+struct al_eth_mac_gen_v3 {
+	/* [0x0] ASYNC FIFOs control */
+	uint32_t afifo_ctrl;
+	/* [0x4] TX ASYNC FIFO configuration */
+	uint32_t tx_afifo_cfg_1;
+	/* [0x8] TX ASYNC FIFO configuration */
+	uint32_t tx_afifo_cfg_2;
+	/* [0xc] TX ASYNC FIFO configuration */
+	uint32_t tx_afifo_cfg_3;
+	/* [0x10] TX ASYNC FIFO configuration */
+	uint32_t tx_afifo_cfg_4;
+	/* [0x14] TX ASYNC FIFO configuration */
+	uint32_t tx_afifo_cfg_5;
+	/* [0x18] RX ASYNC FIFO configuration */
+	uint32_t rx_afifo_cfg_1;
+	/* [0x1c] RX ASYNC FIFO configuration */
+	uint32_t rx_afifo_cfg_2;
+	/* [0x20] RX ASYNC FIFO configuration */
+	uint32_t rx_afifo_cfg_3;
+	/* [0x24] RX ASYNC FIFO configuration */
+	uint32_t rx_afifo_cfg_4;
+	/* [0x28] RX ASYNC FIFO configuration */
+	uint32_t rx_afifo_cfg_5;
+	/* [0x2c] MAC selection configuration */
+	uint32_t mac_sel;
+	/* [0x30] 10G LL MAC configuration */
+	uint32_t mac_10g_ll_cfg;
+	/* [0x34] 10G LL MAC control */
+	uint32_t mac_10g_ll_ctrl;
+	/* [0x38] 10G LL PCS configuration */
+	uint32_t pcs_10g_ll_cfg;
+	/* [0x3c] 10G LL PCS status */
+	uint32_t pcs_10g_ll_status;
+	/* [0x40] 40G LL PCS configuration */
+	uint32_t pcs_40g_ll_cfg;
+	/* [0x44] 40G LL PCS status */
+	uint32_t pcs_40g_ll_status;
+	/* [0x48] PCS 40G  register file address */
+	uint32_t pcs_40g_ll_addr;
+	/* [0x4c] PCS 40G register file data */
+	uint32_t pcs_40g_ll_data;
+	/* [0x50] 40G LL MAC configuration */
+	uint32_t mac_40g_ll_cfg;
+	/* [0x54] 40G LL MAC status */
+	uint32_t mac_40g_ll_status;
+	/* [0x58] Preamble configuration (high [55:32]) */
+	uint32_t preamble_cfg_high;
+	/* [0x5c] Preamble configuration (low [31:0]) */
+	uint32_t preamble_cfg_low;
+	/* [0x60] MAC 40G register file address */
+	uint32_t mac_40g_ll_addr;
+	/* [0x64] MAC 40G register file data */
+	uint32_t mac_40g_ll_data;
+	/* [0x68] 40G LL MAC control */
+	uint32_t mac_40g_ll_ctrl;
+	/* [0x6c] PCS 40G  register file address */
+	uint32_t pcs_40g_fec_91_ll_addr;
+	/* [0x70] PCS 40G register file data */
+	uint32_t pcs_40g_fec_91_ll_data;
+	/* [0x74] 40G LL PCS EEE configuration */
+	uint32_t pcs_40g_ll_eee_cfg;
+	/* [0x78] 40G LL PCS EEE status */
+	uint32_t pcs_40g_ll_eee_status;
+	/*
+	 * [0x7c] SERDES 32-bit interface shift configuration (when swap is
+	 * enabled)
+	 */
+	uint32_t serdes_32_tx_shift;
+	/*
+	 * [0x80] SERDES 32-bit interface shift configuration (when swap is
+	 * enabled)
+	 */
+	uint32_t serdes_32_rx_shift;
+	/*
+	 * [0x84] SERDES 32-bit interface bit selection
+	 */
+	uint32_t serdes_32_tx_sel;
+	/*
+	 * [0x88] SERDES 32-bit interface bit selection
+	 */
+	uint32_t serdes_32_rx_sel;
+	/* [0x8c] AN/LT wrapper  control */
+	uint32_t an_lt_ctrl;
+	/* [0x90] AN/LT wrapper  register file address */
+	uint32_t an_lt_0_addr;
+	/* [0x94] AN/LT wrapper register file data */
+	uint32_t an_lt_0_data;
+	/* [0x98] AN/LT wrapper  register file address */
+	uint32_t an_lt_1_addr;
+	/* [0x9c] AN/LT wrapper register file data */
+	uint32_t an_lt_1_data;
+	/* [0xa0] AN/LT wrapper  register file address */
+	uint32_t an_lt_2_addr;
+	/* [0xa4] AN/LT wrapper register file data */
+	uint32_t an_lt_2_data;
+	/* [0xa8] AN/LT wrapper  register file address */
+	uint32_t an_lt_3_addr;
+	/* [0xac] AN/LT wrapper register file data */
+	uint32_t an_lt_3_data;
+	/* [0xb0] External SERDES control */
+	uint32_t ext_serdes_ctrl;
+	/* [0xb4] spare bits */
+	uint32_t spare;
+	uint32_t rsrvd[18];
+};
+
+struct al_eth_mac_regs {
+	struct al_eth_mac_1g mac_1g;				/* [0x000] */
+	struct al_eth_mac_10g mac_10g;				/* [0x400] */
+	uint32_t rsrvd_0[64];					/* [0x800] */
+	struct al_eth_mac_gen gen;                              /* [0x900] */
+	struct al_eth_mac_kr kr;                                /* [0xa00] */
+	struct al_eth_mac_sgmii sgmii;                          /* [0xb00] */
+	struct al_eth_mac_stat stat;                            /* [0xc00] */
+	struct al_eth_mac_stat_lane stat_lane[4];               /* [0xd00] */
+	struct al_eth_mac_gen_v3 gen_v3;                        /* [0xe00] */
+};
+
+
+/*
+* Registers Fields
+*/
+
+/**** control register (1G mac) ****/
+/* enable Half Duplex */
+#define AL_ETH_1G_MAC_CTRL_HD_EN		(1 << 10)
+/* enable 1G speed */
+#define AL_ETH_1G_MAC_CTRL_1G_SPD		(1 << 3)
+/* enable 10M speed */
+#define AL_ETH_1G_MAC_CTRL_10M_SPD		(1 << 25)
+
+
+/**** 10G MAC register ****/
+/* mdio_cfg_status */
+#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_MASK	0x0000001c
+#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_SHIFT	2
+
+#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_1_CLK	0
+#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_3_CLK	1
+#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_5_CLK	2
+#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_7_CLK	3
+#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_9_CLK	4
+#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_11_CLK	5
+#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_13_CLK	6
+#define ETH_10G_MAC_MDIO_CFG_HOLD_TIME_15_CLK	7
+
+/**** version register ****/
+/*  Revision number (Minor) */
+#define ETH_MAC_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
+#define ETH_MAC_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
+/*  Revision number (Major) */
+#define ETH_MAC_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
+#define ETH_MAC_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
+/*  Date of release */
+#define ETH_MAC_GEN_VERSION_DATE_DAY_MASK 0x001F0000
+#define ETH_MAC_GEN_VERSION_DATE_DAY_SHIFT 16
+/*  Month of release */
+#define ETH_MAC_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
+#define ETH_MAC_GEN_VERSION_DATA_MONTH_SHIFT 21
+/*  Year of release (starting from 2000) */
+#define ETH_MAC_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
+#define ETH_MAC_GEN_VERSION_DATE_YEAR_SHIFT 25
+/*  Reserved */
+#define ETH_MAC_GEN_VERSION_RESERVED_MASK 0xC0000000
+#define ETH_MAC_GEN_VERSION_RESERVED_SHIFT 30
+
+/**** cfg register ****/
+/*
+ * Selects between the 10/100/1000 MAC and the 1/2.5/10G MAC:
+ * 0 - 10/100/1000
+ * 1 - 1/2.5/10G
+ */
+#define ETH_MAC_GEN_CFG_MAC_1_10         (1 << 0)
+/*
+ * Selects the operation mode of the 1/2.5/10G MAC:
+ * 00 - 1/2.5G SGMII
+ * 01 - 10G XAUI/RXAUI
+ * 10 – 10G KR
+ * 11 – Reserved
+ */
+#define ETH_MAC_GEN_CFG_XGMII_SGMII_MASK 0x00000006
+#define ETH_MAC_GEN_CFG_XGMII_SGMII_SHIFT 1
+/*
+ * Selects the operation mode of the PCS:
+ * 0 - XAUI
+ * 1 - RXAUI
+ */
+#define ETH_MAC_GEN_CFG_XAUI_RXAUI       (1 << 3)
+/* Swap bits of TBI (SGMII mode) interface */
+#define ETH_MAC_GEN_CFG_SWAP_TBI_RX      (1 << 4)
+/*
+ * Determines the offset of the TBI bus on the SerDes interface:
+ * 0 - LSB
+ * 1 - MSB
+ */
+#define ETH_MAC_GEN_CFG_TBI_MSB_RX       (1 << 5)
+/*
+ * Selects the SGMII PCS/MAC:
+ * 0 – 10G MAC with SGMII
+ * 1 – 1G MAC with SGMII
+ */
+#define ETH_MAC_GEN_CFG_SGMII_SEL        (1 << 6)
+/*
+ * Selects between RGMII and SGMII for the 1G MAC:
+ * 0 – RGMII
+ * 1 – SGMII
+ */
+#define ETH_MAC_GEN_CFG_RGMII_SGMII_SEL  (1 << 7)
+/* Swap bits of TBI (SGMII mode) interface */
+#define ETH_MAC_GEN_CFG_SWAP_TBI_TX      (1 << 8)
+/*
+ * Determines the offset of the TBI bus on the SerDes interface:
+ *  0 - LSB
+ * 1 - MSB
+ */
+#define ETH_MAC_GEN_CFG_TBI_MSB_TX       (1 << 9)
+/*
+ * Selection between the MDIO from 10/100/1000 MAC or the 1/2.5/10G MAC
+ * 0 - 10/100/1000
+ * 1 - 1/2.5/10G
+ */
+#define ETH_MAC_GEN_CFG_MDIO_1_10        (1 << 10)
+/*
+ * Swap MDC output
+ * 0 – Normal
+ * 1 – Flipped
+ */
+#define ETH_MAC_GEN_CFG_MDIO_POL         (1 << 11)
+/* Swap bits on SerDes interface */
+#define ETH_MAC_GEN_CFG_SWAP_SERDES_RX_MASK 0x000F0000
+#define ETH_MAC_GEN_CFG_SWAP_SERDES_RX_SHIFT 16
+/* Swap bits on SerDes interface */
+#define ETH_MAC_GEN_CFG_SWAP_SERDES_TX_MASK 0x0F000000
+#define ETH_MAC_GEN_CFG_SWAP_SERDES_TX_SHIFT 24
+
+/**** mac_1g_cfg register ****/
+/*
+ * Selection of the input for the "set_1000" input of the Ethernet 10/100/1000
+ * MAC:
+ * 0 - From RGMII converter (automatic speed selection)
+ * 1 - From register set_1000_def
+ */
+#define ETH_MAC_GEN_MAC_1G_CFG_SET_1000_SEL (1 << 0)
+/* Default value for the 10/100/1000 MAC "set_1000" input */
+#define ETH_MAC_GEN_MAC_1G_CFG_SET_1000_DEF (1 << 1)
+/*
+ * Selection of the input for the "set_10" input of the Ethernet 10/100/1000
+ * MAC:
+ * 0 - From RGMII converter (automatic speed selection)
+ * 1 - From register set_10_def
+ */
+#define ETH_MAC_GEN_MAC_1G_CFG_SET_10_SEL (1 << 4)
+/* Default value for the 10/100/1000 MAC "set_10" input */
+#define ETH_MAC_GEN_MAC_1G_CFG_SET_10_DEF (1 << 5)
+/* Transmit low power enable */
+#define ETH_MAC_GEN_MAC_1G_CFG_LOWP_ENA  (1 << 8)
+/*
+ * Enable magic packet mode:
+ * 0 - Sleep mode
+ * 1 - Normal operation
+ */
+#define ETH_MAC_GEN_MAC_1G_CFG_SLEEPN    (1 << 9)
+/* Swap ff_tx_crc input */
+#define ETH_MAC_GEN_MAC_1G_CFG_SWAP_FF_TX_CRC (1 << 12)
+
+/**** mac_1g_stat register ****/
+/* Status of the en_10 output form the 10/100/1000 MAC */
+#define ETH_MAC_GEN_MAC_1G_STAT_EN_10    (1 << 0)
+/* Status of the eth_mode output from th 10/100/1000 MAC */
+#define ETH_MAC_GEN_MAC_1G_STAT_ETH_MODE (1 << 1)
+/* Status of the lowp output from the 10/100/1000 MAC */
+#define ETH_MAC_GEN_MAC_1G_STAT_LOWP     (1 << 4)
+/* Status of the wakeup output from the 10/100/1000 MAC */
+#define ETH_MAC_GEN_MAC_1G_STAT_WAKEUP   (1 << 5)
+
+/**** rgmii_cfg register ****/
+/*
+ * Selection of the input for the "set_1000" input of the RGMII converter
+ * 0 - From MAC
+ * 1 - From register set_1000_def (automatic speed selection)
+ */
+#define ETH_MAC_GEN_RGMII_CFG_SET_1000_SEL (1 << 0)
+/* Default value for the RGMII converter "set_1000" input */
+#define ETH_MAC_GEN_RGMII_CFG_SET_1000_DEF (1 << 1)
+/*
+ * Selection of the input for the "set_10" input of the RGMII converter:
+ * 0 - From MAC
+ * 1 - From register set_10_def (automatic speed selection)
+ */
+#define ETH_MAC_GEN_RGMII_CFG_SET_10_SEL (1 << 4)
+/* Default value for the 10/100/1000 MAC "set_10" input  */
+#define ETH_MAC_GEN_RGMII_CFG_SET_10_DEF (1 << 5)
+/* Enable automatic speed selection (based on PHY in-band status information) */
+#define ETH_MAC_GEN_RGMII_CFG_ENA_AUTO   (1 << 8)
+/* Force full duplex, only valid when ena_auto is '1'. */
+#define ETH_MAC_GEN_RGMII_CFG_SET_FD     (1 << 9)
+
+/**** rgmii_stat register ****/
+/*
+ * Status of the speed output form the RGMII converter
+ * 00 - 10 Mbps
+ * 01 - 100 Mbps
+ * 10 - 1000 Mbps
+ * 11 - Reserved
+ */
+#define ETH_MAC_GEN_RGMII_STAT_SPEED_MASK 0x00000003
+#define ETH_MAC_GEN_RGMII_STAT_SPEED_SHIFT 0
+/*
+ * Link indication from the RGMII converter (valid only if the external PHY
+ * supports in-band status signaling)
+ */
+#define ETH_MAC_GEN_RGMII_STAT_LINK      (1 << 4)
+/*
+ * Full duplex indication from the RGMII converter (valid only if the external
+ * PHY supports in-band status signaling)
+ */
+#define ETH_MAC_GEN_RGMII_STAT_DUP       (1 << 5)
+
+/**** mac_10g_cfg register ****/
+/* Instruct the XGMII to transmit local fault. */
+#define ETH_MAC_GEN_MAC_10G_CFG_TX_LOC_FAULT (1 << 0)
+/* Instruct the XGMII to transmit remote fault. */
+#define ETH_MAC_GEN_MAC_10G_CFG_TX_REM_FAULT (1 << 1)
+/* Instruct the XGMII to transmit link fault. */
+#define ETH_MAC_GEN_MAC_10G_CFG_TX_LI_FAULT (1 << 2)
+/*
+ * Synchronous reset for the PCS layer. Can be used after SerDes lock assertion
+ * to reset the PCS state machine.
+ */
+#define ETH_MAC_GEN_MAC_10G_CFG_SG_SRESET (1 << 3)
+/*
+ * PHY LOS indication selection
+ * 00 - Select register value from phy_los_def
+ * 01 - Select input from the SerDes
+ * 10 - Select input from GPIO
+ * 11 - Select inverted input from GPIO
+ */
+#define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_SEL_MASK 0x00000030
+#define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_SEL_SHIFT 4
+/*
+ * Default value for PHY LOS indication. Reflects the LOS indication from the
+ * SerDes. ('0' if not used)
+ */
+#define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_DEF (1 << 6)
+/* Reverse polarity of the LOS signal from the SerDes */
+#define ETH_MAC_GEN_MAC_10G_CFG_PHY_LOS_POL (1 << 7)
+/* Transmit low power enable */
+#define ETH_MAC_GEN_MAC_10G_CFG_LOWP_ENA (1 << 8)
+/* Swap ff_tx_crc input */
+#define ETH_MAC_GEN_MAC_10G_CFG_SWAP_FF_TX_CRC (1 << 12)
+
+/**** mac_10g_stat register ****/
+/* XGMII RS detects local fault */
+#define ETH_MAC_GEN_MAC_10G_STAT_LOC_FAULT (1 << 0)
+/* XGMII RS detects remote fault */
+#define ETH_MAC_GEN_MAC_10G_STAT_REM_FAULT (1 << 1)
+/* XGMII RS detects link fault */
+#define ETH_MAC_GEN_MAC_10G_STAT_LI_FAULT (1 << 2)
+/* PFC mode */
+#define ETH_MAC_GEN_MAC_10G_STAT_PFC_MODE (1 << 3)
+
+#define ETH_MAC_GEN_MAC_10G_STAT_SG_ENA  (1 << 4)
+
+#define ETH_MAC_GEN_MAC_10G_STAT_SG_ANDONE (1 << 5)
+
+#define ETH_MAC_GEN_MAC_10G_STAT_SG_SYNC (1 << 6)
+
+#define ETH_MAC_GEN_MAC_10G_STAT_SG_SPEED_MASK 0x00000180
+#define ETH_MAC_GEN_MAC_10G_STAT_SG_SPEED_SHIFT 7
+/* Status of the lowp output form the 1/2.5/10G MAC */
+#define ETH_MAC_GEN_MAC_10G_STAT_LOWP    (1 << 9)
+/* Status of the ts_avail output from th 1/2.5/10G MAC */
+#define ETH_MAC_GEN_MAC_10G_STAT_TS_AVAIL (1 << 10)
+/* Transmit pause indication */
+#define ETH_MAC_GEN_MAC_10G_STAT_PAUSE_ON_MASK 0xFF000000
+#define ETH_MAC_GEN_MAC_10G_STAT_PAUSE_ON_SHIFT 24
+
+/**** xaui_cfg register ****/
+/* Increase rate matching FIFO threshold */
+#define ETH_MAC_GEN_XAUI_CFG_JUMBO_EN    (1 << 0)
+
+/**** xaui_stat register ****/
+/* Lane alignment status */
+#define ETH_MAC_GEN_XAUI_STAT_ALIGN_DONE (1 << 0)
+/* Lane synchronization */
+#define ETH_MAC_GEN_XAUI_STAT_SYNC_MASK  0x000000F0
+#define ETH_MAC_GEN_XAUI_STAT_SYNC_SHIFT 4
+/* Code group alignment indication */
+#define ETH_MAC_GEN_XAUI_STAT_CG_ALIGN_MASK 0x00000F00
+#define ETH_MAC_GEN_XAUI_STAT_CG_ALIGN_SHIFT 8
+
+/**** rxaui_cfg register ****/
+/* Increase rate matching FIFO threshold */
+#define ETH_MAC_GEN_RXAUI_CFG_JUMBO_EN   (1 << 0)
+/* Scrambler enable */
+#define ETH_MAC_GEN_RXAUI_CFG_SRBL_EN    (1 << 1)
+/* Disparity calculation across lanes enabled */
+#define ETH_MAC_GEN_RXAUI_CFG_DISP_ACROSS_LANE (1 << 2)
+
+/**** rxaui_stat register ****/
+/* Lane alignment status */
+#define ETH_MAC_GEN_RXAUI_STAT_ALIGN_DONE (1 << 0)
+/* Lane synchronization */
+#define ETH_MAC_GEN_RXAUI_STAT_SYNC_MASK 0x000000F0
+#define ETH_MAC_GEN_RXAUI_STAT_SYNC_SHIFT 4
+/* Code group alignment indication */
+#define ETH_MAC_GEN_RXAUI_STAT_CG_ALIGN_MASK 0x00000F00
+#define ETH_MAC_GEN_RXAUI_STAT_CG_ALIGN_SHIFT 8
+
+/**** sd_cfg register ****/
+/*
+ * Signal detect selection
+ * 0 - from register
+ * 1 - from SerDes
+ */
+#define ETH_MAC_GEN_SD_CFG_SEL_MASK      0x0000000F
+#define ETH_MAC_GEN_SD_CFG_SEL_SHIFT     0
+/* Signal detect value */
+#define ETH_MAC_GEN_SD_CFG_VAL_MASK      0x000000F0
+#define ETH_MAC_GEN_SD_CFG_VAL_SHIFT     4
+/* Signal detect revers polarity (reverse polarity of signal from the SerDes */
+#define ETH_MAC_GEN_SD_CFG_POL_MASK      0x00000F00
+#define ETH_MAC_GEN_SD_CFG_POL_SHIFT     8
+
+/**** mdio_ctrl_1 register ****/
+/*
+ * Available indication
+ * 0 - The port was available and it is captured by this Ethernet controller.
+ * 1 - The port is used by another Ethernet controller.
+ */
+#define ETH_MAC_GEN_MDIO_CTRL_1_AVAIL    (1 << 0)
+
+/**** mdio_1 register ****/
+/* Current Ethernet interface number that controls the MDIO port */
+#define ETH_MAC_GEN_MDIO_1_INFO_MASK     0x000000FF
+#define ETH_MAC_GEN_MDIO_1_INFO_SHIFT    0
+
+/**** mdio_ctrl_2 register ****/
+/*
+ * Available indication
+ * 0 - The port was available and it is captured by this Ethernet controller.
+ * 1 - The port is used by another Ethernet controller.
+ */
+#define ETH_MAC_GEN_MDIO_CTRL_2_AVAIL    (1 << 0)
+
+/**** mdio_2 register ****/
+/* Current Ethernet interface number that controls the MDIO port */
+#define ETH_MAC_GEN_MDIO_2_INFO_MASK     0x000000FF
+#define ETH_MAC_GEN_MDIO_2_INFO_SHIFT    0
+
+/**** xgmii_dfifo_32_64 register ****/
+/* FIFO enable */
+#define ETH_MAC_GEN_XGMII_DFIFO_32_64_ENABLE (1 << 0)
+/* Read Write command every 2 cycles */
+#define ETH_MAC_GEN_XGMII_DFIFO_32_64_RW_2_CYCLES (1 << 1)
+/* Swap LSB MSB when creating wider bus */
+#define ETH_MAC_GEN_XGMII_DFIFO_32_64_SWAP_LSB_MSB (1 << 2)
+/* Software reset */
+#define ETH_MAC_GEN_XGMII_DFIFO_32_64_SW_RESET (1 << 4)
+/* Read threshold */
+#define ETH_MAC_GEN_XGMII_DFIFO_32_64_READ_TH_MASK 0x0000FF00
+#define ETH_MAC_GEN_XGMII_DFIFO_32_64_READ_TH_SHIFT 8
+/* FIFO used */
+#define ETH_MAC_GEN_XGMII_DFIFO_32_64_USED_MASK 0x00FF0000
+#define ETH_MAC_GEN_XGMII_DFIFO_32_64_USED_SHIFT 16
+
+/**** xgmii_dfifo_64_32 register ****/
+/* FIFO enable */
+#define ETH_MAC_GEN_XGMII_DFIFO_64_32_ENABLE (1 << 0)
+/* Read Write command every 2 cycles */
+#define ETH_MAC_GEN_XGMII_DFIFO_64_32_RW_2_CYCLES (1 << 1)
+/* Swap LSB MSB when creating wider bus */
+#define ETH_MAC_GEN_XGMII_DFIFO_64_32_SWAP_LSB_MSB (1 << 2)
+/* Software reset */
+#define ETH_MAC_GEN_XGMII_DFIFO_64_32_SW_RESET (1 << 4)
+/* Read threshold */
+#define ETH_MAC_GEN_XGMII_DFIFO_64_32_READ_TH_MASK 0x0000FF00
+#define ETH_MAC_GEN_XGMII_DFIFO_64_32_READ_TH_SHIFT 8
+/* FIFO used */
+#define ETH_MAC_GEN_XGMII_DFIFO_64_32_USED_MASK 0x00FF0000
+#define ETH_MAC_GEN_XGMII_DFIFO_64_32_USED_SHIFT 16
+
+/**** sd_fifo_ctrl register ****/
+/* FIFO enable */
+#define ETH_MAC_GEN_SD_FIFO_CTRL_ENABLE_MASK 0x0000000F
+#define ETH_MAC_GEN_SD_FIFO_CTRL_ENABLE_SHIFT 0
+/* Software reset */
+#define ETH_MAC_GEN_SD_FIFO_CTRL_SW_RESET_MASK 0x000000F0
+#define ETH_MAC_GEN_SD_FIFO_CTRL_SW_RESET_SHIFT 4
+/* Read threshold */
+#define ETH_MAC_GEN_SD_FIFO_CTRL_READ_TH_MASK 0x0000FF00
+#define ETH_MAC_GEN_SD_FIFO_CTRL_READ_TH_SHIFT 8
+
+/**** sd_fifo_stat register ****/
+/* FIFO 0 used */
+#define ETH_MAC_GEN_SD_FIFO_STAT_USED_0_MASK 0x000000FF
+#define ETH_MAC_GEN_SD_FIFO_STAT_USED_0_SHIFT 0
+/* FIFO 1 used */
+#define ETH_MAC_GEN_SD_FIFO_STAT_USED_1_MASK 0x0000FF00
+#define ETH_MAC_GEN_SD_FIFO_STAT_USED_1_SHIFT 8
+/* FIFO 2 used */
+#define ETH_MAC_GEN_SD_FIFO_STAT_USED_2_MASK 0x00FF0000
+#define ETH_MAC_GEN_SD_FIFO_STAT_USED_2_SHIFT 16
+/* FIFO 3 used */
+#define ETH_MAC_GEN_SD_FIFO_STAT_USED_3_MASK 0xFF000000
+#define ETH_MAC_GEN_SD_FIFO_STAT_USED_3_SHIFT 24
+
+/**** mux_sel register ****/
+/*
+ * SGMII input selection selector
+ * 00 – SerDes 0
+ * 01 – SerDes 1
+ * 10 – SerDes 2
+ * 11 – SerDes 3
+ */
+#define ETH_MAC_GEN_MUX_SEL_SGMII_IN_MASK 0x00000003
+#define ETH_MAC_GEN_MUX_SEL_SGMII_IN_SHIFT 0
+/*
+ * RXAUI Lane 0 Input
+ * 00 – SerDes 0
+ * 01 – SerDes 1
+ * 10 – SerDes 2
+ * 11 – SerDes 3
+ */
+#define ETH_MAC_GEN_MUX_SEL_RXAUI_0_IN_MASK 0x0000000C
+#define ETH_MAC_GEN_MUX_SEL_RXAUI_0_IN_SHIFT 2
+/*
+ * RXAUI Lane 1 Input
+ * 00 – SERDES 0
+ * 01 – SERDES 1
+ * 10 – SERDES 2
+ * 11 – SERDES 3
+ */
+#define ETH_MAC_GEN_MUX_SEL_RXAUI_1_IN_MASK 0x00000030
+#define ETH_MAC_GEN_MUX_SEL_RXAUI_1_IN_SHIFT 4
+/*
+ * XAUI Lane 0 Input
+ * 00 – SERDES 0
+ * 01 – SERDES 1
+ * 10 – SERDES 2
+ * 11 – SERDES 3
+ */
+#define ETH_MAC_GEN_MUX_SEL_XAUI_0_IN_MASK 0x000000C0
+#define ETH_MAC_GEN_MUX_SEL_XAUI_0_IN_SHIFT 6
+/*
+ * XAUI Lane 1 Input
+ * 00 – SERDES 0
+ * 01 – SERDES 1
+ * 10 – SERDES 2
+ * 11 – SERDES 3
+ */
+#define ETH_MAC_GEN_MUX_SEL_XAUI_1_IN_MASK 0x00000300
+#define ETH_MAC_GEN_MUX_SEL_XAUI_1_IN_SHIFT 8
+/*
+ * XAUI Lane 2 Input
+ * 00 – SERDES 0
+ * 01 – SERDES 1
+ * 10 – SERDES 2
+ * 11 – SERDES 3
+ */
+#define ETH_MAC_GEN_MUX_SEL_XAUI_2_IN_MASK 0x00000C00
+#define ETH_MAC_GEN_MUX_SEL_XAUI_2_IN_SHIFT 10
+/*
+ * XAUI Lane 3 Input
+ * 00 – SERDES 0
+ * 01 – SERDES 1
+ * 10 – SERDES 2
+ * 11 – SERDES 3
+ */
+#define ETH_MAC_GEN_MUX_SEL_XAUI_3_IN_MASK 0x00003000
+#define ETH_MAC_GEN_MUX_SEL_XAUI_3_IN_SHIFT 12
+/*
+ * KR PCS Input
+ * 00 - SERDES 0
+ * 01 - SERDES 1
+ * 10 - SERDES 2
+ * 11 - SERDES 3
+ */
+#define ETH_MAC_GEN_MUX_SEL_KR_IN_MASK   0x0000C000
+#define ETH_MAC_GEN_MUX_SEL_KR_IN_SHIFT  14
+/*
+ * SerDes 0 input selection (TX)
+ * 000 – XAUI lane 0
+ * 001 – XAUI lane 1
+ * 010 – XAUI lane 2
+ * 011 – XAUI lane 3
+ * 100 – RXAUI lane 0
+ * 101 – RXAUI lane 1
+ * 110 – SGMII
+ * 111 – KR
+ */
+#define ETH_MAC_GEN_MUX_SEL_SERDES_0_TX_MASK 0x00070000
+#define ETH_MAC_GEN_MUX_SEL_SERDES_0_TX_SHIFT 16
+/*
+ * SERDES 1 input selection (Tx)
+ * 000 – XAUI lane 0
+ * 001 – XAUI lane 1
+ * 010 – XAUI lane 2
+ * 011 – XAUI lane 3
+ * 100 – RXAUI lane 0
+ * 101 – RXAUI lane 1
+ * 110 – SGMII
+ * 111 – KR
+ */
+#define ETH_MAC_GEN_MUX_SEL_SERDES_1_TX_MASK 0x00380000
+#define ETH_MAC_GEN_MUX_SEL_SERDES_1_TX_SHIFT 19
+/*
+ * SerDes 2 input selection (Tx)
+ * 000 – XAUI lane 0
+ * 001 – XAUI lane 1
+ * 010 – XAUI lane 2
+ * 011 – XAUI lane 3
+ * 100 – RXAUI lane 0
+ * 101 – RXAUI lane 1
+ * 110 – SGMII
+ * 111 – KR
+ */
+#define ETH_MAC_GEN_MUX_SEL_SERDES_2_TX_MASK 0x01C00000
+#define ETH_MAC_GEN_MUX_SEL_SERDES_2_TX_SHIFT 22
+/*
+ * SerDes 3 input selection (Tx)
+ * 000 – XAUI lane 0
+ * 001 – XAUI lane 1
+ * 010 – XAUI lane 2
+ * 011 – XAUI lane 3
+ * 100 – RXAUI lane 0
+ * 101 – RXAUI lane 1
+ * 110 – SGMII
+ * 111 – KR
+ */
+#define ETH_MAC_GEN_MUX_SEL_SERDES_3_TX_MASK 0x0E000000
+#define ETH_MAC_GEN_MUX_SEL_SERDES_3_TX_SHIFT 25
+
+/**** clk_cfg register ****/
+/*
+ * Rx/Tx lane 0 clock MUX select
+ * must be aligned with data selector MUXs)
+ * 0 – SerDes 0 clock
+ * 0 – SerDes 1 clock
+ * 2 – SerDes 2 clock
+ * 3 – SerDes 3 clock
+ */
+#define ETH_MAC_GEN_CLK_CFG_LANE_0_CLK_SEL_MASK 0x00000003
+#define ETH_MAC_GEN_CLK_CFG_LANE_0_CLK_SEL_SHIFT 0
+/*
+ * Rx/Tx lane 0 clock MUX select must be aligned with data selector MUXs)
+ * 0 - SerDes 0 clock
+ * 1 - SerDes 1 clock
+ * 2 - SerDes 2 clock
+ * 3 - SerDes 3 clock
+ */
+#define ETH_MAC_GEN_CLK_CFG_LANE_1_CLK_SEL_MASK 0x00000030
+#define ETH_MAC_GEN_CLK_CFG_LANE_1_CLK_SEL_SHIFT 4
+/*
+ * RX/TX lane 0 clock MUX select (should be aligned with data selector MUXs)
+ * 0 - SERDES 0 clock
+ * 1 - SERDES 1 clock
+ * 2 - SERDES 2 clock
+ * 3 - SERDES 3 clock
+ */
+#define ETH_MAC_GEN_CLK_CFG_LANE_2_CLK_SEL_MASK 0x00000300
+#define ETH_MAC_GEN_CLK_CFG_LANE_2_CLK_SEL_SHIFT 8
+/*
+ * Rx/Tx lane 0 clock MUX select must be aligned with data selector MUXs)
+ * 0 - SerDes 0 clock
+ * 1 - SerDes 1 clock
+ * 2 - SerDes 2 clock
+ * 3 - SerDes 3 clock
+ */
+#define ETH_MAC_GEN_CLK_CFG_LANE_3_CLK_SEL_MASK 0x00003000
+#define ETH_MAC_GEN_CLK_CFG_LANE_3_CLK_SEL_SHIFT 12
+/*
+ * MAC GMII Rx clock MUX select must be aligned with data selector MUXs)
+ * 0 – RGMII
+ * 1 – SGMII
+ */
+#define ETH_MAC_GEN_CLK_CFG_GMII_RX_CLK_SEL (1 << 16)
+/*
+ * MAC GMII Tx clock MUX select (should be aligned with data selector MUXs)
+ * 0 - RGMII
+ * 1 - SGMII
+ */
+#define ETH_MAC_GEN_CLK_CFG_GMII_TX_CLK_SEL (1 << 18)
+/*
+ * Tx clock MUX select,
+ * Selects the internal clock for the Tx data path
+ * 0 – SerDes[0] TX DWORD CLK REF (for RXAUI and SGMII)
+ * 1 – SerDes[0] TX WORD CLK REF (for XAUI and KR)
+ */
+#define ETH_MAC_GEN_CLK_CFG_TX_CLK_SEL   (1 << 28)
+/*
+ * Rxclock MUX select
+ * Selects the internal clock for the Rx data path
+ * 0 – XGMII TX CLK 32 LOCAL (for XAUI and RXAUI and KR)
+ * 1 – SerDes[0] RX DWORD CLK GENERATED (125M)
+ * (for SGMII)
+ */
+#define ETH_MAC_GEN_CLK_CFG_RX_CLK_SEL   (1 << 30)
+
+/**** los_sel register ****/
+/*
+ * Selected LOS/SD select
+ * 00 – SerDes 0
+ * 01 – SerDes 1
+ * 10 – SerDes 2
+ * 11 – SerDes 3
+ */
+#define ETH_MAC_GEN_LOS_SEL_LANE_0_SEL_MASK 0x00000003
+#define ETH_MAC_GEN_LOS_SEL_LANE_0_SEL_SHIFT 0
+/*
+ * Selected LOS/SD select
+ * 00 - SerDes 0
+ * 01 - SerDes 1
+ * 10 - SerDes 2
+ * 11 - SerDes 3
+ */
+#define ETH_MAC_GEN_LOS_SEL_LANE_1_SEL_MASK 0x00000030
+#define ETH_MAC_GEN_LOS_SEL_LANE_1_SEL_SHIFT 4
+/*
+ * Selected LOS/SD select
+ * 00 - SerDes 0
+ * 01 - SerDes 1
+ * 10 - SerDes 2
+ * 11 - SerDes 3
+ */
+#define ETH_MAC_GEN_LOS_SEL_LANE_2_SEL_MASK 0x00000300
+#define ETH_MAC_GEN_LOS_SEL_LANE_2_SEL_SHIFT 8
+/*
+ * Selected LOS/SD select
+ * 00 - SerDes 0
+ * 01 - SerDes 1
+ * 10 - SerDes 2
+ * 11 - SerDes 3
+ */
+#define ETH_MAC_GEN_LOS_SEL_LANE_3_SEL_MASK 0x00003000
+#define ETH_MAC_GEN_LOS_SEL_LANE_3_SEL_SHIFT 12
+
+/**** rgmii_sel register ****/
+/* Swap [3:0] input with [7:4] */
+#define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_3_0 (1 << 0)
+/* Swap [4] input with [9] */
+#define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_4  (1 << 1)
+/* Swap [7:4] input with [3:0] */
+#define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_7_3 (1 << 2)
+/* Swap [9] input with [4] */
+#define ETH_MAC_GEN_RGMII_SEL_RX_SWAP_9  (1 << 3)
+/* Swap [3:0] input with [7:4] */
+#define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_3_0 (1 << 4)
+/* Swap [4] input with [9] */
+#define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_4  (1 << 5)
+/* Swap [7:4] input with [3:0] */
+#define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_7_3 (1 << 6)
+/* Swap [9] input with [4] */
+#define ETH_MAC_GEN_RGMII_SEL_TX_SWAP_9  (1 << 7)
+
+/**** led_cfg register ****/
+/*
+ * LED source selection:
+ * 0 – Default reg
+ * 1 – Rx activity
+ * 2 – Tx activity
+ * 3 – Rx | Tx activity
+ * 4-9 – SGMII LEDs
+ */
+#define ETH_MAC_GEN_LED_CFG_SEL_MASK     0x0000000F
+#define ETH_MAC_GEN_LED_CFG_SEL_SHIFT    0
+
+/* turn the led on/off based on default value field (ETH_MAC_GEN_LED_CFG_DEF) */
+#define ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG	0
+#define ETH_MAC_GEN_LED_CFG_SEL_RX_ACTIVITY_DEPRECIATED	1
+#define ETH_MAC_GEN_LED_CFG_SEL_TX_ACTIVITY_DEPRECIATED	2
+#define ETH_MAC_GEN_LED_CFG_SEL_RX_TX_ACTIVITY_DEPRECIATED 3
+#define ETH_MAC_GEN_LED_CFG_SEL_LINK_ACTIVITY 10
+
+/* LED default value */
+#define ETH_MAC_GEN_LED_CFG_DEF          (1 << 4)
+/* LED signal polarity */
+#define ETH_MAC_GEN_LED_CFG_POL          (1 << 5)
+/*
+ * activity timer (MSB)
+ * 32 bit timer @SB clock
+ */
+#define ETH_MAC_GEN_LED_CFG_ACT_TIMER_MASK 0x00FF0000
+#define ETH_MAC_GEN_LED_CFG_ACT_TIMER_SHIFT 16
+/*
+ * activity timer (MSB)
+ * 32 bit timer @SB clock
+ */
+#define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_MASK 0xFF000000
+#define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_SHIFT 24
+
+/**** pcs_addr register ****/
+/* Address value */
+#define ETH_MAC_KR_PCS_ADDR_VAL_MASK     0x0000FFFF
+#define ETH_MAC_KR_PCS_ADDR_VAL_SHIFT    0
+
+/**** pcs_data register ****/
+/* Data value */
+#define ETH_MAC_KR_PCS_DATA_VAL_MASK     0x0000FFFF
+#define ETH_MAC_KR_PCS_DATA_VAL_SHIFT    0
+
+/**** an_addr register ****/
+/* Address value */
+#define ETH_MAC_KR_AN_ADDR_VAL_MASK      0x0000FFFF
+#define ETH_MAC_KR_AN_ADDR_VAL_SHIFT     0
+
+/**** an_data register ****/
+/* Data value */
+#define ETH_MAC_KR_AN_DATA_VAL_MASK      0x0000FFFF
+#define ETH_MAC_KR_AN_DATA_VAL_SHIFT     0
+
+/**** pma_addr register ****/
+/* Dddress value */
+#define ETH_MAC_KR_PMA_ADDR_VAL_MASK     0x0000FFFF
+#define ETH_MAC_KR_PMA_ADDR_VAL_SHIFT    0
+
+/**** pma_data register ****/
+/* Data value */
+#define ETH_MAC_KR_PMA_DATA_VAL_MASK     0x0000FFFF
+#define ETH_MAC_KR_PMA_DATA_VAL_SHIFT    0
+
+/**** mtip_addr register ****/
+/* Address value */
+#define ETH_MAC_KR_MTIP_ADDR_VAL_MASK    0x0000FFFF
+#define ETH_MAC_KR_MTIP_ADDR_VAL_SHIFT   0
+
+/**** mtip_data register ****/
+/* Data value */
+#define ETH_MAC_KR_MTIP_DATA_VAL_MASK    0x0000FFFF
+#define ETH_MAC_KR_MTIP_DATA_VAL_SHIFT   0
+
+/**** pcs_cfg register ****/
+/* Enable Auto-Negotiation after Reset */
+#define ETH_MAC_KR_PCS_CFG_STRAP_AN_ENA  (1 << 0)
+/*
+ * Signal detect selector for the EEE
+ * 0 – Register default value
+ * 1 – SerDes value
+ */
+#define ETH_MAC_KR_PCS_CFG_EEE_SD_SEL    (1 << 4)
+/* Signal detect default value for the EEE */
+#define ETH_MAC_KR_PCS_CFG_EEE_DEF_VAL   (1 << 5)
+/* Signal detect polarity reversal for the EEE */
+#define ETH_MAC_KR_PCS_CFG_EEE_SD_POL    (1 << 6)
+/* EEE timer value  */
+#define ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_MASK 0x0000FF00
+#define ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_SHIFT 8
+/*
+ * Selects source for the enable SerDes DME signal
+ * 0 – Register value
+ * 1 – PCS output
+ */
+#define ETH_MAC_KR_PCS_CFG_DME_SEL       (1 << 16)
+/* DME default value */
+#define ETH_MAC_KR_PCS_CFG_DME_VAL       (1 << 17)
+/* DME default polarity reversal when selecting PCS output */
+#define ETH_MAC_KR_PCS_CFG_DME_POL       (1 << 18)
+
+/**** pcs_stat register ****/
+/* Link enable by the Auto-Negotiation */
+#define ETH_MAC_KR_PCS_STAT_AN_LINK_CONTROL_MASK 0x0000003F
+#define ETH_MAC_KR_PCS_STAT_AN_LINK_CONTROL_SHIFT 0
+/* Block lock */
+#define ETH_MAC_KR_PCS_STAT_BLOCK_LOCK   (1 << 8)
+/* hi BER */
+#define ETH_MAC_KR_PCS_STAT_HI_BER       (1 << 9)
+
+#define ETH_MAC_KR_PCS_STAT_RX_WAKE_ERR  (1 << 16)
+
+#define ETH_MAC_KR_PCS_STAT_PMA_TXMODE_ALERT (1 << 17)
+
+#define ETH_MAC_KR_PCS_STAT_PMA_TXMODE_QUIET (1 << 18)
+
+#define ETH_MAC_KR_PCS_STAT_PMA_RXMODE_QUIET (1 << 19)
+
+#define ETH_MAC_KR_PCS_STAT_RX_LPI_ACTIVE (1 << 20)
+
+#define ETH_MAC_KR_PCS_STAT_TX_LPI_ACTIVE (1 << 21)
+
+/**** reg_addr register ****/
+/* Address value */
+#define ETH_MAC_SGMII_REG_ADDR_VAL_MASK  0x0000001F
+#define ETH_MAC_SGMII_REG_ADDR_VAL_SHIFT 0
+
+#define ETH_MAC_SGMII_REG_ADDR_CTRL_REG	0x0
+#define ETH_MAC_SGMII_REG_ADDR_IF_MODE_REG 0x14
+
+/**** reg_data register ****/
+/* Data value */
+#define ETH_MAC_SGMII_REG_DATA_VAL_MASK  0x0000FFFF
+#define ETH_MAC_SGMII_REG_DATA_VAL_SHIFT 0
+
+#define ETH_MAC_SGMII_REG_DATA_CTRL_AN_ENABLE			(1 << 12)
+#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_EN			(1 << 0)
+#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_AN			(1 << 1)
+#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_MASK		0xC
+#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_SHIFT	2
+#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_10		0x0
+#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_100		0x1
+#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_1000		0x2
+#define ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_DUPLEX		(1 << 4)
+
+/**** clk_div register ****/
+/* Value for 1000M selection */
+#define ETH_MAC_SGMII_CLK_DIV_VAL_1000_MASK 0x000000FF
+#define ETH_MAC_SGMII_CLK_DIV_VAL_1000_SHIFT 0
+/* Value for 100M selection */
+#define ETH_MAC_SGMII_CLK_DIV_VAL_100_MASK 0x0000FF00
+#define ETH_MAC_SGMII_CLK_DIV_VAL_100_SHIFT 8
+/* Value for 10M selection */
+#define ETH_MAC_SGMII_CLK_DIV_VAL_10_MASK 0x00FF0000
+#define ETH_MAC_SGMII_CLK_DIV_VAL_10_SHIFT 16
+/* Bypass PCS selection */
+#define ETH_MAC_SGMII_CLK_DIV_BYPASS     (1 << 24)
+/*
+ * Divider selection when bypass field is '1', one hot
+ * 001 – 1000M
+ * 010 – 100M
+ * 100 – 10M
+ */
+#define ETH_MAC_SGMII_CLK_DIV_SEL_MASK   0x0E000000
+#define ETH_MAC_SGMII_CLK_DIV_SEL_SHIFT  25
+
+/**** link_stat register ****/
+
+#define ETH_MAC_SGMII_LINK_STAT_SET_1000 (1 << 0)
+
+#define ETH_MAC_SGMII_LINK_STAT_SET_100  (1 << 1)
+
+#define ETH_MAC_SGMII_LINK_STAT_SET_10   (1 << 2)
+
+#define ETH_MAC_SGMII_LINK_STAT_LED_AN   (1 << 3)
+
+#define ETH_MAC_SGMII_LINK_STAT_HD_ENA   (1 << 4)
+
+#define ETH_MAC_SGMII_LINK_STAT_LED_LINK (1 << 5)
+
+/**** afifo_ctrl register ****/
+/* enable tx input operation */
+#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_IN (1 << 0)
+/* enable tx output operation */
+#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_OUT (1 << 1)
+/* enable rx input operation */
+#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_IN (1 << 4)
+/* enable rx output operation */
+#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_OUT (1 << 5)
+/* enable tx FIFO input operation */
+#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_FIFO_IN (1 << 8)
+/* enable tx FIFO output operation */
+#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_TX_FIFO_OUT (1 << 9)
+/* enable rx FIFO input operation */
+#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_FIFO_IN (1 << 12)
+/* enable rx FIFO output operation */
+#define ETH_MAC_GEN_V3_AFIFO_CTRL_EN_RX_FIFO_OUT (1 << 13)
+
+/**** tx_afifo_cfg_1 register ****/
+/* minimum packet size configuration */
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_1_MIN_PKT_SIZE_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_1_MIN_PKT_SIZE_SHIFT 0
+
+/**** tx_afifo_cfg_2 register ****/
+/* maximum packet size configuration */
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_2_MAX_PKT_SIZE_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_2_MAX_PKT_SIZE_SHIFT 0
+
+/**** tx_afifo_cfg_3 register ****/
+/* input bus width */
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_SHIFT 0
+/* input bus width divide factor */
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_F_MASK 0xFFFF0000
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_3_INPUT_BUS_W_F_SHIFT 16
+
+/**** tx_afifo_cfg_4 register ****/
+/* output bus width */
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_SHIFT 0
+/* output bus width divide factor */
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_F_MASK 0xFFFF0000
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_4_OUTPUT_BUS_W_F_SHIFT 16
+
+/**** tx_afifo_cfg_5 register ****/
+/*
+ * determines if the input bus is valid/read or “write enable”.
+ * 0 – write enable
+ * 1 – valid/ready
+ */
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_INPUT_BUS_VALID_RDY (1 << 0)
+/*
+ * determines if the output bus is valid/read or “write enable”.
+ * 0 – write enable
+ * 1 – valid/ready
+ */
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_BUS_VALID_RDY (1 << 1)
+/* Swap input bus bytes */
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_INPUT_BUS_SWAP_BYTES (1 << 4)
+/* Swap output bus bytes */
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_BUS_SWAP_BYTES (1 << 5)
+/*
+ * output clock select
+ * 0 – mac_ll_tx_clk
+ * 1 – clk_mac_sys_clk
+ */
+#define ETH_MAC_GEN_V3_TX_AFIFO_CFG_5_OUTPUT_CLK_SEL (1 << 8)
+
+/**** rx_afifo_cfg_1 register ****/
+/* minimum packet size configuration */
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_1_MIN_PKT_SIZE_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_1_MIN_PKT_SIZE_SHIFT 0
+
+/**** rx_afifo_cfg_2 register ****/
+/* maximum packet size configuration */
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_2_MAX_PKT_SIZE_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_2_MAX_PKT_SIZE_SHIFT 0
+
+/**** rx_afifo_cfg_3 register ****/
+/* input bus width */
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_SHIFT 0
+/* input bus width divide factor */
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_F_MASK 0xFFFF0000
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_3_INPUT_BUS_W_F_SHIFT 16
+
+/**** rx_afifo_cfg_4 register ****/
+/* output bus width */
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_SHIFT 0
+/* output bus width divide factor */
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_F_MASK 0xFFFF0000
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_4_OUTPUT_BUS_W_F_SHIFT 16
+
+/**** rx_afifo_cfg_5 register ****/
+/*
+ * determines if the input bus is valid/read or “write enable”.
+ * 0 – write enable
+ * 1 – valid/ready
+ */
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_BUS_VALID_RDY (1 << 0)
+/*
+ * determines if the output bus is valid/read or “write enable”.
+ * 0 – write enable
+ * 1 – valid/ready
+ */
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_OUTPUT_BUS_VALID_RDY (1 << 1)
+/* Swap input bus bytes */
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_BUS_SWAP_BYTES (1 << 4)
+/* Swap output bus bytes */
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_OUTPUT_BUS_SWAP_BYTES (1 << 5)
+/*
+ * input clock select
+ * 0 – mac_ll_rx_clk
+ * 1 – clk_serdes_int_0_tx_dword_ref
+ * 2 – clk_mac_sys_clk
+ * 3 – mac_ll_tx_clk
+ */
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_CLK_SEL_MASK 0x00000300
+#define ETH_MAC_GEN_V3_RX_AFIFO_CFG_5_INPUT_CLK_SEL_SHIFT 8
+
+/**** mac_sel register ****/
+/*
+ * Select the MAC that is connected to the SGMII PCS.
+ * 0 – 1G MAC
+ * 1 – 10G MAC
+ */
+#define ETH_MAC_GEN_V3_MAC_SEL_MAC_10G_SGMII (1 << 0)
+/*
+ * Select between the 10G and 40G MAC
+ * 0 – 10G MAC
+ * 1 – 40G MAC
+ */
+#define ETH_MAC_GEN_V3_MAC_SEL_MAC_10G_40G (1 << 4)
+
+/**** mac_10g_ll_cfg register ****/
+/*
+ * select between 10G (KR PCS) and 1G (SGMII) mode.
+ * 0 – 10G
+ * 1 – 1G
+ */
+#define ETH_MAC_GEN_V3_MAC_10G_LL_CFG_MODE_1G (1 << 0)
+/* enable Magic packet detection in the MAC (all other packets are dropped) */
+#define ETH_MAC_GEN_V3_MAC_10G_LL_CFG_MAGIC_ENA (1 << 5)
+
+/**** mac_10g_ll_ctrl register ****/
+/* Force the MAC to stop TX transmission after low power mode. */
+#define ETH_MAC_GEN_V3_MAC_10G_LL_CTRL_LPI_TXHOLD (1 << 0)
+
+/**** pcs_10g_ll_cfg register ****/
+/* RX FEC Enable */
+#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_RX (1 << 0)
+/* TX FEC enable */
+#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_EN_TX (1 << 1)
+/*
+ * RX FEC error propagation enable,
+ * (debug, always 0)
+ */
+#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_FEC_ERR_ENA (1 << 2)
+/*
+ * Gearbox configuration:
+ * 00 -16
+ * 01 – 20
+ * 10 – 32
+ * 11 – reserved
+ */
+#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_TX_GB_CFG_MASK 0x00000030
+#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_TX_GB_CFG_SHIFT 4
+/*
+ * Gearbox configuration:
+ * 00 -16
+ * 01 – 20
+ * 10 – 32
+ * 11 – reserved
+ */
+#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_RX_GB_CFG_MASK 0x000000C0
+#define ETH_MAC_GEN_V3_PCS_10G_LL_CFG_RX_GB_CFG_SHIFT 6
+
+/**** pcs_10g_ll_status register ****/
+/* FEC locked indication */
+#define ETH_MAC_GEN_V3_PCS_10G_LL_STATUS_FEC_LOCKED (1 << 0)
+
+/**** pcs_40g_ll_cfg register ****/
+/* RX FEC Enable */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_RX_MASK 0x0000000F
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_RX_SHIFT 0
+/* TX FEC enable */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_TX_MASK 0x000000F0
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_EN_TX_SHIFT 4
+/*
+ * RX FEC error propagation enable,
+ * (debug, always 0)
+ */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_ERR_EN_MASK 0x00000F00
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC_ERR_EN_SHIFT 8
+/*
+ * SERDES width, 16 bit enable
+ * 1 – 16
+ * 2 – 32
+ */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_SD_16B (1 << 12)
+/* FEC 91 enable */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_FEC91_ENA (1 << 13)
+/*
+ * PHY LOS indication selection
+ * 00 - Select register value from phy_los_def
+ * 01 - Select input from the SerDes
+ * 10 - Select input from GPIO
+ * 11 - Select inverted input from GPIO
+ */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_SEL_MASK 0x00030000
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_SEL_SHIFT 16
+/* PHY LOS default value */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_DEF (1 << 18)
+/* PHY LOS polarity */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_PHY_LOS_POL (1 << 19)
+/*
+ * Energy detect  indication selection
+ * 00 - Select register value from phy_los_def
+ * 01 - Select input from the SerDes
+ * 10 - Select input from GPIO
+ * 11 - Select inverted input from GPIO
+ */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_SEL_MASK 0x00300000
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_SEL_SHIFT 20
+/* Energy detect default value */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_DEF (1 << 22)
+/* Energy detect polarity */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_CFG_ENERGY_DETECT_POL (1 << 23)
+
+/**** pcs_40g_ll_status register ****/
+/* Block lock */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_BLOCK_LOCK_MASK 0x0000000F
+#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_BLOCK_LOCK_SHIFT 0
+/* align done */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_ALIGN_DONE (1 << 4)
+/* high BER */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_HIGH_BER (1 << 8)
+/* FEC locked indication */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_FEC_LOCKED_MASK 0x0000F000
+#define ETH_MAC_GEN_V3_PCS_40G_LL_STATUS_FEC_LOCKED_SHIFT 12
+
+/**** pcs_40g_ll_addr register ****/
+/* Address value */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_ADDR_VAL_MASK 0x0001FFFF
+#define ETH_MAC_GEN_V3_PCS_40G_LL_ADDR_VAL_SHIFT 0
+
+/**** pcs_40g_ll_data register ****/
+/* Data value */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_DATA_VAL_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_PCS_40G_LL_DATA_VAL_SHIFT 0
+
+/**** mac_40g_ll_cfg register ****/
+/* change TX CRC polarity */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_SWAP_FF_TX_CRC (1 << 0)
+/* force TX remote fault */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_REM_FAULT (1 << 4)
+/* force TX local fault */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_LOC_FAULT (1 << 5)
+/* force TX Link fault */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_TX_LI_FAULT (1 << 6)
+/*
+ * PHY LOS indication selection
+ * 00 - Select register value from phy_los_def
+ * 01 - Select input from the SerDes
+ * 10 - Select input from GPIO
+ * 11 - Select inverted input from GPIO
+ */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_SEL_MASK 0x00000300
+#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_SEL_SHIFT 8
+/* PHY LOS default value */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_DEF (1 << 10)
+/* PHY LOS polarity */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_CFG_PHY_LOS_POL (1 << 11)
+
+/**** mac_40g_ll_status register ****/
+/* pause on indication */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_PAUSE_ON_MASK 0x000000FF
+#define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_PAUSE_ON_SHIFT 0
+/* local fault indication received */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LOC_FAULT (1 << 8)
+/* remote fault indication received */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_REM_FAULT (1 << 9)
+/* Link fault indication */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LI_FAULT (1 << 10)
+
+/**** preamble_cfg_high register ****/
+/* preamble value */
+#define ETH_MAC_GEN_V3_PREAMBLE_CFG_HIGH_VAL_MASK 0x00FFFFFF
+#define ETH_MAC_GEN_V3_PREAMBLE_CFG_HIGH_VAL_SHIFT 0
+
+/**** mac_40g_ll_addr register ****/
+/* Address value */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_ADDR_VAL_MASK 0x000003FF
+#define ETH_MAC_GEN_V3_MAC_40G_LL_ADDR_VAL_SHIFT 0
+
+/**** mac_40g_ll_ctrl register ****/
+/* Force the MAC to stop TX transmission after low power mode. */
+#define ETH_MAC_GEN_V3_MAC_40G_LL_CTRL_LPI_TXHOLD (1 << 0)
+
+#define ETH_MAC_GEN_V3_MAC_40G_LL_CTRL_REG_LOWP_ENA (1 << 1)
+
+/**** pcs_40g_fec_91_ll_addr register ****/
+/* Address value */
+#define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_ADDR_VAL_MASK 0x000001FF
+#define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_ADDR_VAL_SHIFT 0
+
+/**** pcs_40g_fec_91_ll_data register ****/
+/* Data value */
+#define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_DATA_VAL_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_PCS_40G_FEC_91_LL_DATA_VAL_SHIFT 0
+
+/**** pcs_40g_ll_eee_cfg register ****/
+/* Low power timer configuration */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_MASK 0x000000FF
+#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_TIMER_VAL_SHIFT 0
+/* Low power Fast wake */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_CFG_LPI_FW (1 << 8)
+
+/**** pcs_40g_ll_eee_status register ****/
+/* TX LPI mode */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_MODE_MASK 0x00000003
+#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_MODE_SHIFT 0
+/* TX LPI state */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_STATE_MASK 0x00000070
+#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_TX_LPI_STATE_SHIFT 4
+/* TX LPI mode */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_MODE (1 << 8)
+/* TX LPI state */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_STATE_MASK 0x00007000
+#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_STATE_SHIFT 12
+/* TX LPI active */
+#define ETH_MAC_GEN_V3_PCS_40G_LL_EEE_STATUS_RX_LPI_ACTIVE (1 << 15)
+
+/**** serdes_32_tx_shift register ****/
+/* bit shift */
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_0_MASK 0x0000001F
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_0_SHIFT 0
+/* bit shift */
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_1_MASK 0x000003E0
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_1_SHIFT 5
+/* bit shift */
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_2_MASK 0x00007C00
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_2_SHIFT 10
+/* bit shift */
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_3_MASK 0x000F8000
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SHIFT_SERDES_3_SHIFT 15
+
+/**** serdes_32_rx_shift register ****/
+/* bit shift */
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_0_MASK 0x0000001F
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_0_SHIFT 0
+/* bit shift */
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_1_MASK 0x000003E0
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_1_SHIFT 5
+/* bit shift */
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_2_MASK 0x00007C00
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_2_SHIFT 10
+/* bit shift */
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_3_MASK 0x000F8000
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SHIFT_SERDES_3_SHIFT 15
+
+/**** serdes_32_tx_sel register ****/
+/*
+ * 0 – directly from serdes
+ * 1 – swapped
+ * 2 – swapped with shift
+ * 3 - legacy (based on gen cfg register)
+ */
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_0_MASK 0x00000003
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_0_SHIFT 0
+/*
+ * 0 – directly from serdes
+ * 1 – swapped
+ * 2 – swapped with shift
+ * 3 - legacy (based on gen cfg register)
+ */
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_1_MASK 0x00000030
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_1_SHIFT 4
+/*
+ * 0 – directly from serdes
+ * 1 – swapped
+ * 2 – swapped with shift
+ * 3 - legacy (based on gen cfg register)
+ */
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_2_MASK 0x00000300
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_2_SHIFT 8
+/*
+ * 0 – directly from serdes
+ * 1 – swapped
+ * 2 – swapped with shift
+ * 3 - legacy (based on gen cfg register)
+ */
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_3_MASK 0x00003000
+#define ETH_MAC_GEN_V3_SERDES_32_TX_SEL_SERDES_3_SHIFT 12
+
+/**** serdes_32_rx_sel register ****/
+/*
+ * 0 – directly from serdes
+ * 1 – swapped
+ * 2 – swapped with shift
+ * 3 - legacy (based on gen cfg register)
+ */
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_0_MASK 0x00000003
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_0_SHIFT 0
+/*
+ * 0 – directly from serdes
+ * 1 – swapped
+ * 2 – swapped with shift
+ * 3 - legacy (based on gen cfg register)
+ */
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_1_MASK 0x00000030
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_1_SHIFT 4
+/*
+ * 0 – directly from serdes
+ * 1 – swapped
+ * 2 – swapped with shift
+ * 3 - legacy (based on gen cfg register)
+ */
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_2_MASK 0x00000300
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_2_SHIFT 8
+/*
+ * 0 – directly from serdes
+ * 1 – swapped
+ * 2 – swapped with shift
+ * 3 - legacy (based on gen cfg register)
+ */
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_3_MASK 0x00003000
+#define ETH_MAC_GEN_V3_SERDES_32_RX_SEL_SERDES_3_SHIFT 12
+
+/**** an_lt_ctrl register ****/
+/* reset lane [3:0] */
+#define ETH_MAC_GEN_V3_AN_LT_CTRL_SW_RESET_MASK 0x0000000F
+#define ETH_MAC_GEN_V3_AN_LT_CTRL_SW_RESET_SHIFT 0
+
+/* PHY LOS indication input selection
+ * 0 - from serdes
+ * 1 - from an_lt
+ */
+#define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_0 (1 << 8)
+/* PHY LOS indication input selection
+ * 0 - from serdes
+ * 1 - from an_lt
+ */
+#define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_1 (1 << 9)
+/* PHY LOS indication input selection
+ * 0 - from serdes
+ * 1 - from an_lt
+ */
+#define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_2 (1 << 10)
+/* PHY LOS indication input selection
+ * 0 - from serdes
+ * 1 - from an_lt
+ */
+#define ETH_MAC_GEN_V3_AN_LT_CTRL_PHY_LOS_SEL_LANE_3 (1 << 11)
+
+/**** an_lt_0_addr register ****/
+/* Address value */
+#define ETH_MAC_GEN_V3_AN_LT_0_ADDR_VAL_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_AN_LT_0_ADDR_VAL_SHIFT 0
+
+/**** an_lt_1_addr register ****/
+/* Address value */
+#define ETH_MAC_GEN_V3_AN_LT_1_ADDR_VAL_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_AN_LT_1_ADDR_VAL_SHIFT 0
+
+/**** an_lt_2_addr register ****/
+/* Address value */
+#define ETH_MAC_GEN_V3_AN_LT_2_ADDR_VAL_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_AN_LT_2_ADDR_VAL_SHIFT 0
+
+/**** an_lt_3_addr register ****/
+/* Address value */
+#define ETH_MAC_GEN_V3_AN_LT_3_ADDR_VAL_MASK 0x0000FFFF
+#define ETH_MAC_GEN_V3_AN_LT_3_ADDR_VAL_SHIFT 0
+
+/**** ext_serdes_ctrl register ****/
+/*
+ * Lane 0, SERDES selection:
+ * 0 – 10G SERDES, lane 0
+ * 1 – 25G SERDES, lane 0
+ */
+#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_SEL_25_10 (1 << 0)
+/*
+ * Lane 1, SERDES selection:
+ * 0 – 10G SERDES, lane 1
+ * 1 – 25G SERDES, lane 1
+ */
+#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_SEL_25_10 (1 << 1)
+/*
+ * Lane 2, SERDES selection:
+ * 0 – 10G SERDES, lane 2
+ * 1 – 25G SERDES, lane 0
+ */
+#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_2_SEL_25_10 (1 << 2)
+/*
+ * Lane 3, SERDES selection:
+ * 0 – 10G SERDES, lane 3
+ * 1 – 25G SERDES, lane 1
+ */
+#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_3_SEL_25_10 (1 << 3)
+
+/* Lane 0 Rx, 25G 40bit-32bit gearshitf sw reset */
+#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_RX_25_GS_SW_RESET (1 << 4)
+/* Lane 0 Tx, 25G 40bit-32bit gearshitf sw reset */
+#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_0_TX_25_GS_SW_RESET (1 << 5)
+/* Lane 1 Rx, 25G 40bit-32bit gearshitf sw reset */
+#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_RX_25_GS_SW_RESET (1 << 6)
+/* Lane 1 Tx, 25G 40bit-32bit gearshitf sw reset */
+#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_LANE_1_TX_25_GS_SW_RESET (1 << 7)
+/* SerDes 25G gear shift Tx lane selector */
+#define ETH_MAC_GEN_V3_EXT_SERDES_CTRL_SRDS25_GS_TX_LANE_CLK_SEL (1 << 8)
+
+/*** MAC Core registers addresses ***/
+/* command config */
+#define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR	0x00000008
+#define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_TX_ENA	(1 << 0)
+#define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_RX_ENA	(1 << 1)
+#define ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_PFC_MODE	(1 << 19)
+
+/* frame length */
+#define ETH_MAC_GEN_V3_MAC_40G_FRM_LENGTH_ADDR		0x00000014
+
+#define ETH_MAC_GEN_V3_MAC_40G_CL01_PAUSE_QUANTA_ADDR	0x00000054
+#define ETH_MAC_GEN_V3_MAC_40G_CL23_PAUSE_QUANTA_ADDR	0x00000058
+#define ETH_MAC_GEN_V3_MAC_40G_CL45_PAUSE_QUANTA_ADDR	0x0000005C
+#define ETH_MAC_GEN_V3_MAC_40G_CL67_PAUSE_QUANTA_ADDR	0x00000060
+#define ETH_MAC_GEN_V3_MAC_40G_CL01_QUANTA_THRESH_ADDR	0x00000064
+#define ETH_MAC_GEN_V3_MAC_40G_CL23_QUANTA_THRESH_ADDR	0x00000068
+#define ETH_MAC_GEN_V3_MAC_40G_CL45_QUANTA_THRESH_ADDR	0x0000006C
+#define ETH_MAC_GEN_V3_MAC_40G_CL67_QUANTA_THRESH_ADDR	0x00000070
+
+/* spare */
+#define ETH_MAC_GEN_V3_SPARE_CHICKEN_DISABLE_TIMESTAMP_STRETCH (1 << 0)
+
+/*** PCS Core registers addresses ***/
+/* 40g control/status */
+#define ETH_MAC_GEN_V3_PCS_40G_CONTROL_STATUS_ADDR      0x00000000
+/* 10g control_1 */
+#define ETH_MAC_KR_PCS_CONTROL_1_ADDR                   0x00000000
+
+#define ETH_MAC_KR_AN_MILLISECONDS_COUNTER_ADDR         0x00008000
+#define ETH_MAC_AN_LT_MILLISECONDS_COUNTER_ADDR         0x00000020
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __AL_HAL_ETH_MAC_REGS_H__ */
+
+/** @} end of Ethernet group */
diff --git a/sys/contrib/alpine-hal/eth/al_hal_eth_main.c b/sys/contrib/alpine-hal/eth/al_hal_eth_main.c
new file mode 100644
index 000000000000..b3a5c70b1f04
--- /dev/null
+++ b/sys/contrib/alpine-hal/eth/al_hal_eth_main.c
@@ -0,0 +1,5260 @@
+/*-
+*******************************************************************************
+Copyright (C) 2015 Annapurna Labs Ltd.
+
+This file may be licensed under the terms of the Annapurna Labs Commercial
+License Agreement.
+
+Alternatively, this file can be distributed under the terms of the GNU General
+Public License V2 as published by the Free Software Foundation and can be
+found at http://www.gnu.org/licenses/gpl-2.0.html
+
+Alternatively, redistribution and use in source and binary forms, with or
+without modification, are permitted provided that the following conditions are
+met:
+
+    *     Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
+    *     Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/**
+ *  @{
+ * @file   al_hal_eth_main.c
+ *
+ * @brief  XG Ethernet unit HAL driver for main functions (initialization, data path)
+ *
+ */
+
+#include "al_hal_eth.h"
+#include <al_hal_udma_iofic.h>
+#include <al_hal_udma_config.h>
+#include <al_hal_udma.h>
+#include "al_hal_eth_ec_regs.h"
+#include "al_hal_eth_mac_regs.h"
+#include <al_hal_unit_adapter_regs.h>
+#ifdef AL_ETH_EX
+#include "al_hal_eth_ex_internal.h"
+#endif
+
+/* Number of xfi_txclk cycles that accumulate into 100ns */
+#define ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL 52
+
+#define AL_ETH_TX_PKT_UDMA_FLAGS	(AL_ETH_TX_FLAGS_NO_SNOOP | \
+					 AL_ETH_TX_FLAGS_INT)
+
+#define AL_ETH_TX_PKT_META_FLAGS	(AL_ETH_TX_FLAGS_IPV4_L3_CSUM | \
+					 AL_ETH_TX_FLAGS_L4_CSUM |	\
+					 AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM |	\
+					 AL_ETH_TX_FLAGS_L2_MACSEC_PKT | \
+					 AL_ETH_TX_FLAGS_L2_DIS_FCS |\
+					 AL_ETH_TX_FLAGS_TSO |\
+					 AL_ETH_TX_FLAGS_TS)
+
+#define AL_ETH_TX_SRC_VLAN_CNT_MASK	3
+#define AL_ETH_TX_SRC_VLAN_CNT_SHIFT	5
+#define AL_ETH_TX_L4_PROTO_IDX_MASK	0x1F
+#define AL_ETH_TX_L4_PROTO_IDX_SHIFT	8
+#define AL_ETH_TX_TUNNEL_MODE_SHIFT		18
+#define AL_ETH_TX_OUTER_L3_PROTO_SHIFT		20
+#define AL_ETH_TX_VLAN_MOD_ADD_SHIFT		22
+#define AL_ETH_TX_VLAN_MOD_DEL_SHIFT		24
+#define AL_ETH_TX_VLAN_MOD_E_SEL_SHIFT		26
+#define AL_ETH_TX_VLAN_MOD_VID_SEL_SHIFT	28
+#define AL_ETH_TX_VLAN_MOD_PBIT_SEL_SHIFT	30
+
+/* tx Meta Descriptor defines */
+#define AL_ETH_TX_META_STORE			(1 << 21)
+#define AL_ETH_TX_META_L3_LEN_MASK		0xff
+#define AL_ETH_TX_META_L3_OFF_MASK		0xff
+#define AL_ETH_TX_META_L3_OFF_SHIFT		8
+#define AL_ETH_TX_META_MSS_LSB_VAL_SHIFT	22
+#define AL_ETH_TX_META_MSS_MSB_TS_VAL_SHIFT	16
+#define AL_ETH_TX_META_OUTER_L3_LEN_MASK	0x1f
+#define AL_ETH_TX_META_OUTER_L3_LEN_SHIFT	24
+#define AL_ETH_TX_META_OUTER_L3_OFF_HIGH_MASK	0x18
+#define AL_ETH_TX_META_OUTER_L3_OFF_HIGH_SHIFT	10
+#define AL_ETH_TX_META_OUTER_L3_OFF_LOW_MASK	0x07
+#define AL_ETH_TX_META_OUTER_L3_OFF_LOW_SHIFT	29
+
+/* tx Meta Descriptor defines - MacSec */
+#define AL_ETH_TX_MACSEC_SIGN_SHIFT			  0		/* Sign TX pkt */
+#define AL_ETH_TX_MACSEC_ENCRYPT_SHIFT			  1		/* Encrypt TX pkt */
+#define AL_ETH_TX_MACSEC_AN_LSB_SHIFT			  2		/* Association Number */
+#define AL_ETH_TX_MACSEC_AN_MSB_SHIFT			  3
+#define AL_ETH_TX_MACSEC_SC_LSB_SHIFT			  4		/* Secured Channel */
+#define AL_ETH_TX_MACSEC_SC_MSB_SHIFT			  9
+#define AL_ETH_TX_MACSEC_SECURED_PYLD_LEN_LSB_SHIFT	 10		/* Secure Payload Length (0x3FFF for non-SL packets) */
+#define AL_ETH_TX_MACSEC_SECURED_PYLD_LEN_MSB_SHIFT	 23
+
+/* Rx Descriptor defines */
+#define AL_ETH_RX_L3_PROTO_IDX_MASK	0x1F
+#define AL_ETH_RX_SRC_VLAN_CNT_MASK	3
+#define AL_ETH_RX_SRC_VLAN_CNT_SHIFT	5
+#define AL_ETH_RX_L4_PROTO_IDX_MASK	0x1F
+#define AL_ETH_RX_L4_PROTO_IDX_SHIFT	8
+
+#define AL_ETH_RX_L3_OFFSET_SHIFT	9
+#define AL_ETH_RX_L3_OFFSET_MASK	(0x7f << AL_ETH_RX_L3_OFFSET_SHIFT)
+#define AL_ETH_RX_HASH_SHIFT		16
+#define AL_ETH_RX_HASH_MASK		(0xffff 	<< AL_ETH_RX_HASH_SHIFT)
+
+#define ETH_MAC_GEN_LED_CFG_BLINK_TIMER_VAL 5
+#define ETH_MAC_GEN_LED_CFG_ACT_TIMER_VAL 7
+
+/* Tx VID Table*/
+#define AL_ETH_TX_VLAN_TABLE_UDMA_MASK		0xF
+#define AL_ETH_TX_VLAN_TABLE_FWD_TO_MAC		(1 << 4)
+
+/* tx gpd defines */
+#define AL_ETH_TX_GPD_L3_PROTO_MASK		0x1f
+#define AL_ETH_TX_GPD_L3_PROTO_SHIFT		0
+#define AL_ETH_TX_GPD_L4_PROTO_MASK		0x1f
+#define AL_ETH_TX_GPD_L4_PROTO_SHIFT		5
+#define AL_ETH_TX_GPD_TUNNEL_CTRL_MASK		0x7
+#define AL_ETH_TX_GPD_TUNNEL_CTRL_SHIFT		10
+#define AL_ETH_TX_GPD_SRC_VLAN_CNT_MASK		0x3
+#define AL_ETH_TX_GPD_SRC_VLAN_CNT_SHIFT	13
+#define AL_ETH_TX_GPD_CAM_DATA_2_SHIFT		32
+#define AL_ETH_TX_GPD_CAM_MASK_2_SHIFT		32
+#define AL_ETH_TX_GPD_CAM_CTRL_VALID_SHIFT	31
+
+/* tx gcp defines */
+#define AL_ETH_TX_GCP_POLY_SEL_MASK		0x1
+#define AL_ETH_TX_GCP_POLY_SEL_SHIFT		0
+#define AL_ETH_TX_GCP_CRC32_BIT_COMP_MASK	0x1
+#define AL_ETH_TX_GCP_CRC32_BIT_COMP_SHIFT	1
+#define AL_ETH_TX_GCP_CRC32_BIT_SWAP_MASK	0x1
+#define AL_ETH_TX_GCP_CRC32_BIT_SWAP_SHIFT	2
+#define AL_ETH_TX_GCP_CRC32_BYTE_SWAP_MASK	0x1
+#define AL_ETH_TX_GCP_CRC32_BYTE_SWAP_SHIFT	3
+#define AL_ETH_TX_GCP_DATA_BIT_SWAP_MASK	0x1
+#define AL_ETH_TX_GCP_DATA_BIT_SWAP_SHIFT	4
+#define AL_ETH_TX_GCP_DATA_BYTE_SWAP_MASK	0x1
+#define AL_ETH_TX_GCP_DATA_BYTE_SWAP_SHIFT	5
+#define AL_ETH_TX_GCP_TRAIL_SIZE_MASK		0xF
+#define AL_ETH_TX_GCP_TRAIL_SIZE_SHIFT		6
+#define AL_ETH_TX_GCP_HEAD_SIZE_MASK		0xFF
+#define AL_ETH_TX_GCP_HEAD_SIZE_SHIFT		16
+#define AL_ETH_TX_GCP_HEAD_CALC_MASK		0x1
+#define AL_ETH_TX_GCP_HEAD_CALC_SHIFT		24
+#define AL_ETH_TX_GCP_MASK_POLARITY_MASK	0x1
+#define AL_ETH_TX_GCP_MASK_POLARITY_SHIFT	25
+
+#define AL_ETH_TX_GCP_OPCODE_1_MASK		0x3F
+#define AL_ETH_TX_GCP_OPCODE_1_SHIFT		0
+#define AL_ETH_TX_GCP_OPCODE_2_MASK		0x3F
+#define AL_ETH_TX_GCP_OPCODE_2_SHIFT		6
+#define AL_ETH_TX_GCP_OPCODE_3_MASK		0x3F
+#define AL_ETH_TX_GCP_OPCODE_3_SHIFT		12
+#define AL_ETH_TX_GCP_OPSEL_1_MASK		0xF
+#define AL_ETH_TX_GCP_OPSEL_1_SHIFT		0
+#define AL_ETH_TX_GCP_OPSEL_2_MASK		0xF
+#define AL_ETH_TX_GCP_OPSEL_2_SHIFT		4
+#define AL_ETH_TX_GCP_OPSEL_3_MASK		0xF
+#define AL_ETH_TX_GCP_OPSEL_3_SHIFT		8
+#define AL_ETH_TX_GCP_OPSEL_4_MASK		0xF
+#define AL_ETH_TX_GCP_OPSEL_4_SHIFT		12
+
+/*  Tx crc_chksum_replace defines */
+#define L4_CHECKSUM_DIS_AND_L3_CHECKSUM_DIS     0x00
+#define L4_CHECKSUM_DIS_AND_L3_CHECKSUM_EN      0x20
+#define L4_CHECKSUM_EN_AND_L3_CHECKSUM_DIS      0x40
+#define L4_CHECKSUM_EN_AND_L3_CHECKSUM_EN       0x60
+
+/* rx gpd defines */
+#define AL_ETH_RX_GPD_OUTER_L3_PROTO_MASK		0x1f
+#define AL_ETH_RX_GPD_OUTER_L3_PROTO_SHIFT		(3 + 0)
+#define AL_ETH_RX_GPD_OUTER_L4_PROTO_MASK		0x1f
+#define AL_ETH_RX_GPD_OUTER_L4_PROTO_SHIFT		(3 + 8)
+#define AL_ETH_RX_GPD_INNER_L3_PROTO_MASK		0x1f
+#define AL_ETH_RX_GPD_INNER_L3_PROTO_SHIFT		(3 + 16)
+#define AL_ETH_RX_GPD_INNER_L4_PROTO_MASK		0x1f
+#define AL_ETH_RX_GPD_INNER_L4_PROTO_SHIFT		(3 + 24)
+#define AL_ETH_RX_GPD_OUTER_PARSE_CTRL_MASK		0xFF
+#define AL_ETH_RX_GPD_OUTER_PARSE_CTRL_SHIFT	32
+#define AL_ETH_RX_GPD_INNER_PARSE_CTRL_MASK		0xFF
+#define AL_ETH_RX_GPD_INNER_PARSE_CTRL_SHIFT	40
+#define AL_ETH_RX_GPD_L3_PRIORITY_MASK			0xFF
+#define AL_ETH_RX_GPD_L3_PRIORITY_SHIFT			48
+#define AL_ETH_RX_GPD_L4_DST_PORT_LSB_MASK		0xFF
+#define AL_ETH_RX_GPD_L4_DST_PORT_LSB_SHIFT		56
+#define AL_ETH_RX_GPD_CAM_DATA_2_SHIFT			32
+#define AL_ETH_RX_GPD_CAM_MASK_2_SHIFT			32
+#define AL_ETH_RX_GPD_CAM_CTRL_VALID_SHIFT		31
+
+#define AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L3_PROTO_IDX_OFFSET	(106 + 5)
+#define AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L4_PROTO_IDX_OFFSET	(106 + 10)
+#define AL_ETH_RX_GPD_PARSE_RESULT_INNER_L3_PROTO_IDX_OFFSET	(0 + 5)
+#define AL_ETH_RX_GPD_PARSE_RESULT_INNER_L4_PROTO_IDX_OFFSET	(0 + 10)
+#define AL_ETH_RX_GPD_PARSE_RESULT_OUTER_PARSE_CTRL			(106 + 4)
+#define AL_ETH_RX_GPD_PARSE_RESULT_INNER_PARSE_CTRL			4
+#define AL_ETH_RX_GPD_PARSE_RESULT_L3_PRIORITY			(106 + 13)
+#define AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L4_DST_PORT_LSB	(106 + 65)
+
+/* rx gcp defines */
+#define AL_ETH_RX_GCP_POLY_SEL_MASK		0x1
+#define AL_ETH_RX_GCP_POLY_SEL_SHIFT		0
+#define AL_ETH_RX_GCP_CRC32_BIT_COMP_MASK	0x1
+#define AL_ETH_RX_GCP_CRC32_BIT_COMP_SHIFT	1
+#define AL_ETH_RX_GCP_CRC32_BIT_SWAP_MASK	0x1
+#define AL_ETH_RX_GCP_CRC32_BIT_SWAP_SHIFT	2
+#define AL_ETH_RX_GCP_CRC32_BYTE_SWAP_MASK      0x1
+#define AL_ETH_RX_GCP_CRC32_BYTE_SWAP_SHIFT	3
+#define AL_ETH_RX_GCP_DATA_BIT_SWAP_MASK	0x1
+#define AL_ETH_RX_GCP_DATA_BIT_SWAP_SHIFT	4
+#define AL_ETH_RX_GCP_DATA_BYTE_SWAP_MASK       0x1
+#define AL_ETH_RX_GCP_DATA_BYTE_SWAP_SHIFT	5
+#define AL_ETH_RX_GCP_TRAIL_SIZE_MASK		0xF
+#define AL_ETH_RX_GCP_TRAIL_SIZE_SHIFT		6
+#define AL_ETH_RX_GCP_HEAD_SIZE_MASK		0xFF
+#define AL_ETH_RX_GCP_HEAD_SIZE_SHIFT		16
+#define AL_ETH_RX_GCP_HEAD_CALC_MASK		0x1
+#define AL_ETH_RX_GCP_HEAD_CALC_SHIFT		24
+#define AL_ETH_RX_GCP_MASK_POLARITY_MASK	0x1
+#define AL_ETH_RX_GCP_MASK_POLARITY_SHIFT	25
+
+#define AL_ETH_RX_GCP_OPCODE_1_MASK		0x3F
+#define AL_ETH_RX_GCP_OPCODE_1_SHIFT		0
+#define AL_ETH_RX_GCP_OPCODE_2_MASK		0x3F
+#define AL_ETH_RX_GCP_OPCODE_2_SHIFT		6
+#define AL_ETH_RX_GCP_OPCODE_3_MASK		0x3F
+#define AL_ETH_RX_GCP_OPCODE_3_SHIFT		12
+#define AL_ETH_RX_GCP_OPSEL_1_MASK		0xF
+#define AL_ETH_RX_GCP_OPSEL_1_SHIFT		0
+#define AL_ETH_RX_GCP_OPSEL_2_MASK		0xF
+#define AL_ETH_RX_GCP_OPSEL_2_SHIFT		4
+#define AL_ETH_RX_GCP_OPSEL_3_MASK		0xF
+#define AL_ETH_RX_GCP_OPSEL_3_SHIFT		8
+#define AL_ETH_RX_GCP_OPSEL_4_MASK		0xF
+#define AL_ETH_RX_GCP_OPSEL_4_SHIFT		12
+
+#define AL_ETH_MDIO_DELAY_PERIOD	1 /* micro seconds to wait when polling mdio status */
+#define AL_ETH_MDIO_DELAY_COUNT		150 /* number of times to poll */
+#define AL_ETH_S2M_UDMA_COMP_COAL_TIMEOUT	200 /* Rx descriptors coalescing timeout in SB clocks */
+
+#define AL_ETH_EPE_ENTRIES_NUM 26
+static struct al_eth_epe_p_reg_entry al_eth_epe_p_regs[AL_ETH_EPE_ENTRIES_NUM] = {
+	{ 0x0, 0x0, 0x0 },
+	{ 0x0, 0x0, 0x1 },
+	{ 0x0, 0x0, 0x2 },
+	{ 0x0, 0x0, 0x3 },
+	{ 0x18100, 0xFFFFF, 0x80000004 },
+	{ 0x188A8, 0xFFFFF, 0x80000005 },
+	{ 0x99100, 0xFFFFF, 0x80000006 },
+	{ 0x98100, 0xFFFFF, 0x80000007 },
+	{ 0x10800, 0x7FFFF, 0x80000008 },
+	{ 0x20000, 0x73FFF, 0x80000009 },
+	{ 0x20000, 0x70000, 0x8000000A },
+	{ 0x186DD, 0x7FFFF, 0x8000000B },
+	{ 0x30600, 0x7FF00, 0x8000000C },
+	{ 0x31100, 0x7FF00, 0x8000000D },
+	{ 0x32F00, 0x7FF00, 0x8000000E },
+	{ 0x32900, 0x7FF00, 0x8000000F },
+	{ 0x105DC, 0x7FFFF, 0x80010010 },
+	{ 0x188E5, 0x7FFFF, 0x80000011 },
+	{ 0x72000, 0x72000, 0x80000012 },
+	{ 0x70000, 0x72000, 0x80000013 },
+	{ 0x46558, 0x7FFFF, 0x80000001 },
+	{ 0x18906, 0x7FFFF, 0x80000015 },
+	{ 0x18915, 0x7FFFF, 0x80000016 },
+	{ 0x31B00, 0x7FF00, 0x80000017 },
+	{ 0x30400, 0x7FF00, 0x80000018 },
+	{ 0x0, 0x0, 0x8000001F }
+};
+
+
+static struct al_eth_epe_control_entry al_eth_epe_control_table[AL_ETH_EPE_ENTRIES_NUM] = {
+	{{ 0x2800000, 0x0, 0x0, 0x0, 0x1, 0x400000 }},
+	{{ 0x280004C, 0x746000, 0xA46030, 0xE00000, 0x2, 0x400000 }},
+	{{ 0x2800054, 0x746000, 0xA46030, 0x1600000, 0x2, 0x400000 }},
+	{{ 0x280005C, 0x746000, 0xA46030, 0x1E00000, 0x2, 0x400000 }},
+	{{ 0x2800042, 0xD42000, 0x0, 0x400000, 0x1010412, 0x400000 }},
+	{{ 0x2800042, 0xD42000, 0x0, 0x400000, 0x1010412, 0x400000 }},
+	{{ 0x2800042, 0xE42000, 0x0, 0x400000, 0x2020002, 0x400000 }},
+	{{ 0x2800042, 0xE42000, 0x0, 0x400000, 0x2020002, 0x400000 }},
+	{{ 0x280B046, 0x0, 0x6C1008, 0x0, 0x4, 0x406800 }},
+	{{ 0x2800049, 0xF44060, 0x1744080, 0x14404, 0x6, 0x400011 }},
+	{{ 0x2015049, 0xF44060, 0x1744080, 0x14404, 0x8080007, 0x400011 }},
+	{{ 0x280B046, 0xF60040, 0x6C1004, 0x2800000, 0x6, 0x406811 }},
+	{{ 0x2815042, 0x1F42000, 0x2042010, 0x1414460, 0x10100009, 0x40B800 }},
+	{{ 0x2815042, 0x1F42000, 0x2042010, 0x800000, 0x10100009, 0x40B800 }},
+	{{ 0x280B042, 0x0, 0x0, 0x430400, 0x4040009, 0x0 }},
+	{{ 0x2815580, 0x0, 0x0, 0x0, 0x4040005, 0x0 }},
+	{{ 0x280B000, 0x0, 0x0, 0x0, 0x1, 0x400000 }},
+	{{ 0x2800040, 0x174E000, 0x0, 0x0, 0xE, 0x406800 }},
+	{{ 0x280B000, 0x0, 0x0, 0x600000, 0x1, 0x406800 }},
+	{{ 0x280B000, 0x0, 0x0, 0xE00000, 0x1, 0x406800 }},
+	{{ 0x2800000, 0x0, 0x0, 0x0, 0x1, 0x400000 }},
+	{{ 0x280B046, 0x0, 0x0, 0x2800000, 0x7, 0x400000 }},
+	{{ 0x280B046, 0xF60040, 0x6C1004, 0x2800000, 0x6, 0x406811 }},
+	{{ 0x2815042, 0x1F43028, 0x2000000, 0xC00000, 0x10100009, 0x40B800 }},
+	{{ 0x2815400, 0x0, 0x0, 0x0, 0x4040005, 0x0 }},
+	{{ 0x2800000, 0x0, 0x0, 0x0, 0x1, 0x400000 }}
+};
+
+
+#define AL_ETH_IS_1G_MAC(mac_mode) (((mac_mode) == AL_ETH_MAC_MODE_RGMII) || ((mac_mode) == AL_ETH_MAC_MODE_SGMII))
+#define AL_ETH_IS_10G_MAC(mac_mode)	(((mac_mode) == AL_ETH_MAC_MODE_10GbE_Serial) ||	\
+					((mac_mode) == AL_ETH_MAC_MODE_10G_SGMII) ||		\
+					((mac_mode) == AL_ETH_MAC_MODE_SGMII_2_5G))
+#define AL_ETH_IS_25G_MAC(mac_mode) ((mac_mode) == AL_ETH_MAC_MODE_KR_LL_25G)
+
+static const char *al_eth_mac_mode_str(enum al_eth_mac_mode mode)
+{
+	switch(mode) {
+	case AL_ETH_MAC_MODE_RGMII:
+		return "RGMII";
+	case AL_ETH_MAC_MODE_SGMII:
+		return "SGMII";
+	case AL_ETH_MAC_MODE_SGMII_2_5G:
+		return "SGMII_2_5G";
+	case AL_ETH_MAC_MODE_10GbE_Serial:
+		return "KR";
+        case AL_ETH_MAC_MODE_KR_LL_25G:
+		return "KR_LL_25G";
+	case AL_ETH_MAC_MODE_10G_SGMII:
+		return "10G_SGMII";
+	case AL_ETH_MAC_MODE_XLG_LL_40G:
+		return "40G_LL";
+	case AL_ETH_MAC_MODE_XLG_LL_50G:
+		return "50G_LL";
+	default:
+		return "N/A";
+	}
+}
+
+/**
+ * change and wait udma state
+ *
+ * @param dma the udma to change its state
+ * @param new_state
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+static int al_udma_state_set_wait(struct al_udma *dma, enum al_udma_state new_state)
+{
+	enum al_udma_state state;
+	enum al_udma_state expected_state = new_state;
+	int count = 1000;
+	int rc;
+
+	rc = al_udma_state_set(dma, new_state);
+	if (rc != 0) {
+		al_warn("[%s] warn: failed to change state, error %d\n", dma->name, rc);
+		return rc;
+	}
+
+	if ((new_state == UDMA_NORMAL) || (new_state == UDMA_DISABLE))
+		expected_state = UDMA_IDLE;
+
+	do {
+		state = al_udma_state_get(dma);
+		if (state == expected_state)
+			break;
+		al_udelay(1);
+		if (count-- == 0) {
+			al_warn("[%s] warn: dma state didn't change to %s\n",
+				 dma->name, al_udma_states_name[new_state]);
+			return -ETIMEDOUT;
+		}
+	} while (1);
+	return 0;
+}
+
+static void al_eth_epe_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_epe_p_reg_entry *reg_entry,
+		struct al_eth_epe_control_entry *control_entry)
+{
+	al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_data, reg_entry->data);
+	al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_mask, reg_entry->mask);
+	al_reg_write32(&adapter->ec_regs_base->epe_p[idx].comp_ctrl, reg_entry->ctrl);
+
+	al_reg_write32(&adapter->ec_regs_base->msp_c[idx].p_comp_data, reg_entry->data);
+	al_reg_write32(&adapter->ec_regs_base->msp_c[idx].p_comp_mask, reg_entry->mask);
+	al_reg_write32(&adapter->ec_regs_base->msp_c[idx].p_comp_ctrl, reg_entry->ctrl);
+
+	/*control table  0*/
+	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_6,
+			control_entry->data[5]);
+	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_2,
+			control_entry->data[1]);
+	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_3,
+			control_entry->data[2]);
+	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_4,
+			control_entry->data[3]);
+	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_5,
+			control_entry->data[4]);
+	al_reg_write32(&adapter->ec_regs_base->epe[0].act_table_data_1,
+			control_entry->data[0]);
+
+	/*control table 1*/
+	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_6,
+			control_entry->data[5]);
+	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_2,
+			control_entry->data[1]);
+	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_3,
+			control_entry->data[2]);
+	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_4,
+			control_entry->data[3]);
+	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_5,
+			control_entry->data[4]);
+	al_reg_write32(&adapter->ec_regs_base->epe[1].act_table_data_1,
+			control_entry->data[0]);
+}
+
+static void al_eth_epe_init(struct al_hal_eth_adapter *adapter)
+{
+	int idx;
+
+	if (adapter->enable_rx_parser == 0) {
+		al_dbg("eth [%s]: disable rx parser\n", adapter->name);
+
+		al_reg_write32(&adapter->ec_regs_base->epe[0].res_def, 0x08000000);
+		al_reg_write32(&adapter->ec_regs_base->epe[0].res_in, 0x7);
+
+		al_reg_write32(&adapter->ec_regs_base->epe[1].res_def, 0x08000000);
+		al_reg_write32(&adapter->ec_regs_base->epe[1].res_in, 0x7);
+
+		return;
+	}
+	al_dbg("eth [%s]: enable rx parser\n", adapter->name);
+	for (idx = 0; idx < AL_ETH_EPE_ENTRIES_NUM; idx++)
+		al_eth_epe_entry_set(adapter, idx, &al_eth_epe_p_regs[idx], &al_eth_epe_control_table[idx]);
+
+	al_reg_write32(&adapter->ec_regs_base->epe[0].res_def, 0x08000080);
+	al_reg_write32(&adapter->ec_regs_base->epe[0].res_in, 0x7);
+
+	al_reg_write32(&adapter->ec_regs_base->epe[1].res_def, 0x08000080);
+	al_reg_write32(&adapter->ec_regs_base->epe[1].res_in, 0);
+
+	/* header length as function of 4 bits value, for GRE, when C bit is set, the header len should be increase by 4*/
+	al_reg_write32(&adapter->ec_regs_base->epe_h[8].hdr_len, (4 << 16) | 4);
+
+	/* select the outer information when writing the rx descriptor (l3 protocol index etc) */
+	al_reg_write32(&adapter->ec_regs_base->rfw.meta, EC_RFW_META_L3_LEN_CALC);
+
+	al_reg_write32(&adapter->ec_regs_base->rfw.checksum, EC_RFW_CHECKSUM_HDR_SEL);
+}
+
+/**
+ * read 40G MAC registers (indirect access)
+ *
+ * @param adapter pointer to the private structure
+ * @param reg_addr address in the an registers
+ *
+ * @return the register value
+ */
+static uint32_t al_eth_40g_mac_reg_read(
+			struct al_hal_eth_adapter *adapter,
+			uint32_t reg_addr)
+{
+	uint32_t val;
+
+	/* indirect access */
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, reg_addr);
+	val = al_reg_read32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data);
+
+	al_dbg("[%s]: %s - reg %d. val 0x%x",
+	       adapter->name, __func__, reg_addr, val);
+
+	return val;
+}
+
+/**
+ * write 40G MAC registers (indirect access)
+ *
+ * @param adapter pointer to the private structure
+ * @param reg_addr address in the an registers
+ * @param reg_data value to write to the register
+ *
+ */
+static void al_eth_40g_mac_reg_write(
+			struct al_hal_eth_adapter *adapter,
+			uint32_t reg_addr,
+			uint32_t reg_data)
+{
+	/* indirect access */
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, reg_addr);
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, reg_data);
+
+	al_dbg("[%s]: %s - reg %d. val 0x%x",
+	       adapter->name, __func__, reg_addr, reg_data);
+}
+
+/**
+ * read 40G PCS registers (indirect access)
+ *
+ * @param adapter pointer to the private structure
+ * @param reg_addr address in the an registers
+ *
+ * @return the register value
+ */
+static uint32_t al_eth_40g_pcs_reg_read(
+			struct al_hal_eth_adapter *adapter,
+			uint32_t reg_addr)
+{
+	uint32_t val;
+
+	/* indirect access */
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, reg_addr);
+	val = al_reg_read32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data);
+
+	al_dbg("[%s]: %s - reg %d. val 0x%x",
+	       adapter->name, __func__, reg_addr, val);
+
+	return val;
+}
+
+/**
+ * write 40G PCS registers (indirect access)
+ *
+ * @param adapter pointer to the private structure
+ * @param reg_addr address in the an registers
+ * @param reg_data value to write to the register
+ *
+ */
+static void al_eth_40g_pcs_reg_write(
+			struct al_hal_eth_adapter *adapter,
+			uint32_t reg_addr,
+			uint32_t reg_data)
+{
+	/* indirect access */
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, reg_addr);
+	al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, reg_data);
+
+	al_dbg("[%s]: %s - reg %d. val 0x%x",
+	       adapter->name, __func__, reg_addr, reg_data);
+}
+
+/*****************************API Functions  **********************************/
+/*adapter management */
+/**
+ * initialize the ethernet adapter's DMA
+ */
+int al_eth_adapter_init(struct al_hal_eth_adapter *adapter, struct al_eth_adapter_params *params)
+{
+	struct al_udma_params udma_params;
+	struct al_udma_m2s_pkt_len_conf conf;
+	int i;
+	uint32_t reg;
+	int rc;
+
+	al_dbg("eth [%s]: initialize controller's UDMA. id = %d\n", params->name, params->udma_id);
+	al_dbg("eth [%s]: UDMA base regs: %p\n", params->name, params->udma_regs_base);
+	al_dbg("eth [%s]: EC base regs: %p\n", params->name, params->ec_regs_base);
+	al_dbg("eth [%s]: MAC base regs: %p\n", params->name, params->mac_regs_base);
+	al_dbg("eth [%s]: enable_rx_parser: %x\n", params->name, params->enable_rx_parser);
+
+	adapter->name = params->name;
+	adapter->rev_id = params->rev_id;
+	adapter->udma_id = params->udma_id;
+	adapter->udma_regs_base = params->udma_regs_base;
+	adapter->ec_regs_base = (struct al_ec_regs __iomem*)params->ec_regs_base;
+	adapter->mac_regs_base = (struct al_eth_mac_regs __iomem*)params->mac_regs_base;
+	adapter->unit_regs = (struct unit_regs __iomem *)params->udma_regs_base;
+	adapter->enable_rx_parser = params->enable_rx_parser;
+	adapter->ec_ints_base = (void __iomem *)((uint32_t)adapter->ec_regs_base + 0x1c00);
+	adapter->mac_ints_base = (void __iomem *)((uint32_t)adapter->mac_regs_base + 0x800);
+
+	/* initialize Tx udma */
+	udma_params.udma_regs_base = adapter->unit_regs;
+	udma_params.type = UDMA_TX;
+	udma_params.num_of_queues = AL_ETH_UDMA_TX_QUEUES;
+	udma_params.name = "eth tx";
+	rc = al_udma_init(&adapter->tx_udma, &udma_params);
+
+	if (rc != 0) {
+		al_err("failed to initialize %s, error %d\n",
+			 udma_params.name, rc);
+		return rc;
+	}
+	rc = al_udma_state_set_wait(&adapter->tx_udma, UDMA_NORMAL);
+	if (rc != 0) {
+		al_err("[%s]: failed to change state, error %d\n",
+			 udma_params.name, rc);
+		return rc;
+	}
+	/* initialize Rx udma */
+	udma_params.udma_regs_base = adapter->unit_regs;
+	udma_params.type = UDMA_RX;
+	udma_params.num_of_queues = AL_ETH_UDMA_RX_QUEUES;
+	udma_params.name = "eth rx";
+	rc = al_udma_init(&adapter->rx_udma, &udma_params);
+
+	if (rc != 0) {
+		al_err("failed to initialize %s, error %d\n",
+			 udma_params.name, rc);
+		return rc;
+	}
+
+	rc = al_udma_state_set_wait(&adapter->rx_udma, UDMA_NORMAL);
+	if (rc != 0) {
+		al_err("[%s]: failed to change state, error %d\n",
+			 udma_params.name, rc);
+		return rc;
+	}
+	al_dbg("eth [%s]: controller's UDMA successfully initialized\n",
+		 params->name);
+
+	/* set max packet size to 1M (for TSO) */
+	conf.encode_64k_as_zero = AL_TRUE;
+	conf.max_pkt_size = 0xfffff;
+	al_udma_m2s_packet_size_cfg_set(&adapter->tx_udma, &conf);
+
+	/* set m2s (tx) max descriptors to max data buffers number and one for
+	 * meta descriptor
+	 */
+	al_udma_m2s_max_descs_set(&adapter->tx_udma, AL_ETH_PKT_MAX_BUFS + 1);
+
+	/* set s2m (rx) max descriptors to max data buffers */
+	al_udma_s2m_max_descs_set(&adapter->rx_udma, AL_ETH_PKT_MAX_BUFS);
+
+	/* set s2m burst lenght when writing completion descriptors to 64 bytes
+	 */
+	al_udma_s2m_compl_desc_burst_config(&adapter->rx_udma, 64);
+
+	/* if pointer to ec regs provided, then init the tx meta cache of this udma*/
+	if (adapter->ec_regs_base != NULL) {
+		// INIT TX CACHE TABLE:
+		for (i = 0; i < 4; i++) {
+			al_reg_write32(&adapter->ec_regs_base->tso.cache_table_addr, i + (adapter->udma_id * 4));
+			al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_1, 0x00000000);
+			al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_2, 0x00000000);
+			al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_3, 0x00000000);
+			al_reg_write32(&adapter->ec_regs_base->tso.cache_table_data_4, 0x00000000);
+		}
+	}
+	// only udma 0 allowed to init ec
+	if (adapter->udma_id != 0) {
+		return 0;
+	}
+	/* enable Ethernet controller: */
+	/* enable internal machines*/
+	al_reg_write32(&adapter->ec_regs_base->gen.en, 0xffffffff);
+	al_reg_write32(&adapter->ec_regs_base->gen.fifo_en, 0xffffffff);
+
+	if (adapter->rev_id > AL_ETH_REV_ID_0) {
+		/* enable A0 descriptor structure */
+		al_reg_write32_masked(&adapter->ec_regs_base->gen.en_ext,
+				      EC_GEN_EN_EXT_CACHE_WORD_SPLIT,
+				      EC_GEN_EN_EXT_CACHE_WORD_SPLIT);
+
+		/* use mss value in the descriptor */
+		al_reg_write32(&adapter->ec_regs_base->tso.cfg_add_0,
+						EC_TSO_CFG_ADD_0_MSS_SEL);
+
+		/* enable tunnel TSO */
+		al_reg_write32(&adapter->ec_regs_base->tso.cfg_tunnel,
+						(EC_TSO_CFG_TUNNEL_EN_TUNNEL_TSO |
+						 EC_TSO_CFG_TUNNEL_EN_UDP_CHKSUM |
+						 EC_TSO_CFG_TUNNEL_EN_UDP_LEN |
+						 EC_TSO_CFG_TUNNEL_EN_IPV6_PLEN |
+						 EC_TSO_CFG_TUNNEL_EN_IPV4_CHKSUM |
+						 EC_TSO_CFG_TUNNEL_EN_IPV4_IDEN |
+						 EC_TSO_CFG_TUNNEL_EN_IPV4_TLEN));
+	}
+
+	/* swap input byts from MAC RX */
+	al_reg_write32(&adapter->ec_regs_base->mac.gen, 0x00000001);
+	/* swap output bytes to MAC TX*/
+	al_reg_write32(&adapter->ec_regs_base->tmi.tx_cfg, EC_TMI_TX_CFG_EN_FWD_TO_RX|EC_TMI_TX_CFG_SWAP_BYTES);
+
+	/* TODO: check if we need this line*/
+	al_reg_write32(&adapter->ec_regs_base->tfw_udma[0].fwd_dec, 0x000003fb);
+
+	/* RFW configuration: default 0 */
+	al_reg_write32(&adapter->ec_regs_base->rfw_default[0].opt_1, 0x00000001);
+
+	/* VLAN table address*/
+	al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_addr, 0x00000000);
+	/* VLAN table data*/
+	al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_data, 0x00000000);
+	/* HASH config (select toeplitz and bits 7:0 of the thash result, enable
+	 * symmetric hash) */
+	al_reg_write32(&adapter->ec_regs_base->rfw.thash_cfg_1,
+			EC_RFW_THASH_CFG_1_ENABLE_IP_SWAP |
+			EC_RFW_THASH_CFG_1_ENABLE_PORT_SWAP);
+
+	al_eth_epe_init(adapter);
+
+	/* disable TSO padding and use mac padding instead */
+	reg = al_reg_read32(&adapter->ec_regs_base->tso.in_cfg);
+	reg &= ~0x7F00; /*clear bits 14:8 */
+	al_reg_write32(&adapter->ec_regs_base->tso.in_cfg, reg);
+
+	return 0;
+}
+
+/*****************************API Functions  **********************************/
+/*adapter management */
+/**
+ * enable the ec and mac interrupts
+ */
+int al_eth_ec_mac_ints_config(struct al_hal_eth_adapter *adapter)
+{
+
+	al_dbg("eth [%s]: enable ethernet and mac interrupts\n", adapter->name);
+
+	// only udma 0 allowed to init ec
+	if (adapter->udma_id != 0)
+		return -EPERM;
+
+	/* enable mac ints */
+	al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_A,
+		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
+	al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_B,
+		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
+	al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_C,
+		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
+	al_iofic_config(adapter->ec_ints_base, AL_INT_GROUP_D,
+		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
+
+	/* unmask MAC int */
+	al_iofic_unmask(adapter->ec_ints_base, AL_INT_GROUP_A, 8);
+
+	/* enable ec interrupts */
+	al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_A,
+		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
+	al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_B,
+		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
+	al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_C,
+		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
+	al_iofic_config(adapter->mac_ints_base, AL_INT_GROUP_D,
+		INT_CONTROL_GRP_SET_ON_POSEDGE | INT_CONTROL_GRP_CLEAR_ON_READ);
+
+	/* eee active */
+	al_iofic_unmask(adapter->mac_ints_base, AL_INT_GROUP_B, AL_BIT(14));
+
+	al_iofic_unmask(adapter->unit_regs, AL_INT_GROUP_D, AL_BIT(11));
+	return 0;
+}
+
+/**
+ * ec and mac interrupt service routine
+ * read and print asserted interrupts
+ *
+ * @param adapter pointer to the private structure
+ *
+ * @return 0 on success. otherwise on failure.
+ */
+int al_eth_ec_mac_isr(struct al_hal_eth_adapter *adapter)
+{
+	uint32_t cause;
+	al_dbg("[%s]: ethernet interrupts handler\n", adapter->name);
+
+	// only udma 0 allowed to init ec
+	if (adapter->udma_id != 0)
+		return -EPERM;
+
+	/* read ec cause */
+	cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_A);
+	al_dbg("[%s]: ethernet group A cause 0x%08x\n", adapter->name, cause);
+	if (cause & 1)
+	{
+		cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_A);
+		al_dbg("[%s]: mac group A cause 0x%08x\n", adapter->name, cause);
+
+		cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_B);
+		al_dbg("[%s]: mac group B cause 0x%08x\n", adapter->name, cause);
+
+		cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_C);
+		al_dbg("[%s]: mac group C cause 0x%08x\n", adapter->name, cause);
+
+		cause = al_iofic_read_cause(adapter->mac_ints_base, AL_INT_GROUP_D);
+		al_dbg("[%s]: mac group D cause 0x%08x\n", adapter->name, cause);
+	}
+	cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_B);
+	al_dbg("[%s]: ethernet group B cause 0x%08x\n", adapter->name, cause);
+	cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_C);
+	al_dbg("[%s]: ethernet group C cause 0x%08x\n", adapter->name, cause);
+	cause = al_iofic_read_cause(adapter->ec_ints_base, AL_INT_GROUP_D);
+	al_dbg("[%s]: ethernet group D cause 0x%08x\n", adapter->name, cause);
+
+	return 0;
+}
+
+/**
+ * stop the DMA of the ethernet adapter
+ */
+int al_eth_adapter_stop(struct al_hal_eth_adapter *adapter)
+{
+	int rc;
+
+	al_dbg("eth [%s]: stop controller's UDMA\n", adapter->name);
+
+	/* disable Tx dma*/
+	rc = al_udma_state_set_wait(&adapter->tx_udma, UDMA_DISABLE);
+	if (rc != 0) {
+		al_warn("[%s] warn: failed to change state, error %d\n",
+			 adapter->tx_udma.name, rc);
+		return rc;
+	}
+
+	al_dbg("eth [%s]: controller's TX UDMA stopped\n",
+		 adapter->name);
+	/* disable Rx dma*/
+	rc = al_udma_state_set_wait(&adapter->rx_udma, UDMA_DISABLE);
+	if (rc != 0) {
+		al_warn("[%s] warn: failed to change state, error %d\n",
+			 adapter->rx_udma.name, rc);
+		return rc;
+	}
+
+	al_dbg("eth [%s]: controller's RX UDMA stopped\n",
+		 adapter->name);
+	return 0;
+}
+
+int al_eth_adapter_reset(struct al_hal_eth_adapter *adapter)
+{
+	al_dbg("eth [%s]: reset controller's UDMA\n", adapter->name);
+
+	return -EPERM;
+}
+
+/* Q management */
+/**
+ * Configure and enable a queue ring
+ */
+int al_eth_queue_config(struct al_hal_eth_adapter *adapter, enum al_udma_type type, uint32_t qid,
+			     struct al_udma_q_params *q_params)
+{
+	struct al_udma *udma;
+	int rc;
+
+	al_dbg("eth [%s]: config UDMA %s queue %d\n", adapter->name,
+		 type == UDMA_TX ? "Tx" : "Rx", qid);
+
+	if (type == UDMA_TX) {
+		udma = &adapter->tx_udma;
+	} else {
+		udma = &adapter->rx_udma;
+	}
+
+	q_params->adapter_rev_id = adapter->rev_id;
+
+	rc = al_udma_q_init(udma, qid, q_params);
+
+	if (rc)
+		return rc;
+
+	if (type == UDMA_RX) {
+		rc = al_udma_s2m_q_compl_coal_config(&udma->udma_q[qid],
+				AL_TRUE, AL_ETH_S2M_UDMA_COMP_COAL_TIMEOUT);
+
+		al_assert(q_params->cdesc_size <= 32);
+
+		if (q_params->cdesc_size > 16)
+			al_reg_write32_masked(&adapter->ec_regs_base->rfw.out_cfg,
+					EC_RFW_OUT_CFG_META_CNT_MASK, 2);
+	}
+	return rc;
+}
+
+int al_eth_queue_enable(struct al_hal_eth_adapter *adapter __attribute__((__unused__)),
+			enum al_udma_type type __attribute__((__unused__)),
+			uint32_t qid __attribute__((__unused__)))
+{
+	return -EPERM;
+}
+int al_eth_queue_disable(struct al_hal_eth_adapter *adapter __attribute__((__unused__)),
+			 enum al_udma_type type __attribute__((__unused__)),
+			 uint32_t qid __attribute__((__unused__)))
+{
+	return -EPERM;
+}
+
+/* MAC layer */
+int al_eth_rx_pkt_limit_config(struct al_hal_eth_adapter *adapter, uint32_t min_rx_len, uint32_t max_rx_len)
+{
+	al_assert(max_rx_len <= AL_ETH_MAX_FRAME_LEN);
+
+	/* EC minimum packet length [bytes] in RX */
+	al_reg_write32(&adapter->ec_regs_base->mac.min_pkt, min_rx_len);
+	/* EC maximum packet length [bytes] in RX */
+	al_reg_write32(&adapter->ec_regs_base->mac.max_pkt, max_rx_len);
+
+	if (adapter->rev_id > AL_ETH_REV_ID_2) {
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, min_rx_len);
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, max_rx_len);
+	}
+
+	/* configure the MAC's max rx length, add 16 bytes so the packet get
+	 * trimmed by the EC/Async_fifo rather by the MAC
+	*/
+	if (AL_ETH_IS_1G_MAC(adapter->mac_mode))
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.frm_len, max_rx_len + 16);
+	else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode))
+		/* 10G MAC control register  */
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.frm_len, (max_rx_len + 16));
+	else
+		al_eth_40g_mac_reg_write(adapter, ETH_MAC_GEN_V3_MAC_40G_FRM_LENGTH_ADDR, (max_rx_len + 16));
+
+	return 0;
+}
+
+/* configure the mac media type. */
+int al_eth_mac_config(struct al_hal_eth_adapter *adapter, enum al_eth_mac_mode mode)
+{
+	switch(mode) {
+	case AL_ETH_MAC_MODE_RGMII:
+		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210);
+
+		/* 1G MAC control register */
+		/* bit[0]  - TX_ENA - zeroed by default. Should be asserted by al_eth_mac_start
+		 * bit[1]  - RX_ENA - zeroed by default. Should be asserted by al_eth_mac_start
+		 * bit[3]  - ETH_SPEED - zeroed to enable 10/100 Mbps Ethernet
+		 * bit[4]  - PROMIS_EN - asserted to enable MAC promiscuous mode
+		 * bit[23] - CNTL_FRM-ENA - asserted to enable control frames
+		 * bit[24] - NO_LGTH_CHECK - asserted to disable length checks, which is done in the controller
+		 */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, 0x01800010);
+
+		/* RX_SECTION_EMPTY,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_empty, 0x00000000);
+		/* RX_SECTION_FULL,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_full, 0x0000000c); /* must be larger than almost empty */
+		/* RX_ALMOST_EMPTY,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_empty, 0x00000008);
+		/* RX_ALMOST_FULL,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_full, 0x00000008);
+
+
+		/* TX_SECTION_EMPTY,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_empty, 0x00000008); /* 8 ? */
+		/* TX_SECTION_FULL, 0 - store and forward, */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_full, 0x0000000c);
+		/* TX_ALMOST_EMPTY,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_empty, 0x00000008);
+		/* TX_ALMOST_FULL,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_full, 0x00000008);
+
+		/* XAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000000);
+
+		/* 1G MACSET 1G */
+		/* taking sel_1000/sel_10 inputs from rgmii PHY, and not from register.
+		 * disabling magic_packets detection in mac */
+		al_reg_write32(&adapter->mac_regs_base->gen.mac_1g_cfg, 0x00000002);
+		/* RGMII set 1G */
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00063910);
+		al_reg_write32(&adapter->mac_regs_base->gen.rgmii_sel, 0xF);
+		break;
+	case AL_ETH_MAC_MODE_SGMII:
+		if (adapter->rev_id > AL_ETH_REV_ID_2) {
+			/* configure and enable the ASYNC FIFO between the MACs and the EC */
+			/* TX min packet size */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000037);
+			/* TX max packet size */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
+			/* TX input bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
+			/* TX output bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020);
+			/* TX Valid/ready configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000121);
+			/* RX min packet size */
+			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */
+			/* RX max packet size */
+			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */
+			/* RX input bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020);
+			/* RX output bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
+			/* RX Valid/ready configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000212);
+			/* V3 additional MAC selection */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000001);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000);
+			/* ASYNC FIFO ENABLE */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
+			/* Timestamp_configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.spare,
+					ETH_MAC_GEN_V3_SPARE_CHICKEN_DISABLE_TIMESTAMP_STRETCH);
+		}
+
+		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40053210);
+
+		/* 1G MAC control register */
+		/* bit[0]  - TX_ENA - zeroed by default. Should be asserted by al_eth_mac_start
+		 * bit[1]  - RX_ENA - zeroed by default. Should be asserted by al_eth_mac_start
+		 * bit[3]  - ETH_SPEED - zeroed to enable 10/100 Mbps Ethernet
+		 * bit[4]  - PROMIS_EN - asserted to enable MAC promiscuous mode
+		 * bit[23] - CNTL_FRM-ENA - asserted to enable control frames
+		 * bit[24] - NO_LGTH_CHECK - asserted to disable length checks, which is done in the controller
+		 */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, 0x01800010);
+
+		/* RX_SECTION_EMPTY,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_empty, 0x00000000);
+		/* RX_SECTION_FULL,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_section_full, 0x0000000c); /* must be larger than almost empty */
+		/* RX_ALMOST_EMPTY,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_empty, 0x00000008);
+		/* RX_ALMOST_FULL,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.rx_almost_full, 0x00000008);
+
+
+		/* TX_SECTION_EMPTY,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_empty, 0x00000008); /* 8 ? */
+		/* TX_SECTION_FULL, 0 - store and forward, */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_section_full, 0x0000000c);
+		/* TX_ALMOST_EMPTY,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_empty, 0x00000008);
+		/* TX_ALMOST_FULL,  */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.tx_almost_full, 0x00000008);
+
+		/* XAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x000000c0);
+
+		/* 1G MACSET 1G */
+		/* taking sel_1000/sel_10 inputs from rgmii_converter, and not from register.
+		 * disabling magic_packets detection in mac */
+		al_reg_write32(&adapter->mac_regs_base->gen.mac_1g_cfg, 0x00000002);
+		/* SerDes configuration */
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00063910);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401);
+
+		// FAST AN -- Testing only
+#ifdef AL_HAL_ETH_FAST_AN
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000012);
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x00000040);
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000013);
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x00000000);
+#endif
+
+		/* Setting PCS i/f mode to SGMII (instead of default 1000Base-X) */
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000014);
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x0000000b);
+		/* setting dev_ability to have speed of 1000Mb, [11:10] = 2'b10 */
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 0x00000004);
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data, 0x000009A0);
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
+				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
+				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
+		break;
+
+	case AL_ETH_MAC_MODE_SGMII_2_5G:
+		if (adapter->rev_id > AL_ETH_REV_ID_2) {
+			/* configure and enable the ASYNC FIFO between the MACs and the EC */
+			/* TX min packet size */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000037);
+			/* TX max packet size */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
+			/* TX input bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
+			/* TX output bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020);
+			/* TX Valid/ready configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023);
+			/* RX input bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020);
+			/* RX output bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
+			/* RX Valid/ready configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012);
+			/* V3 additional MAC selection */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000050);
+			/* ASYNC FIFO ENABLE */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
+		}
+
+		/* MAC register file */
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022830);
+		/* XAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000001);
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.if_mode, 0x00000028);
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.control, 0x00001140);
+		/* RXAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel,
+				      ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00063910);
+		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401);
+
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
+				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
+				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
+		break;
+
+	case AL_ETH_MAC_MODE_10GbE_Serial:
+		if (adapter->rev_id > AL_ETH_REV_ID_2) {
+			/* configure and enable the ASYNC FIFO between the MACs and the EC */
+			/* TX min packet size */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000037);
+			/* TX max packet size */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
+			/* TX input bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
+			/* TX output bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020);
+			/* TX Valid/ready configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023);
+			/* RX min packet size */
+			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */
+			/* RX max packet size */
+			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */
+			/* RX input bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020);
+			/* RX output bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
+			/* RX Valid/ready configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012);
+			/* V3 additional MAC selection */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000050);
+			/* ASYNC FIFO ENABLE */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
+		}
+
+		/* MAC register file */
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810);
+		/* XAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005);
+		/* RXAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1);
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel,
+					~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00073910);
+		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401);
+
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
+				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
+				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
+		break;
+
+	case AL_ETH_MAC_MODE_KR_LL_25G:
+			/* select 25G SERDES lane 0 and lane 1 */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, 0x03821101);
+		if (adapter->rev_id > AL_ETH_REV_ID_2) {
+			/* configure and enable the ASYNC FIFO between the MACs and the EC */
+			/* TX min packet size */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000037);
+			/* TX max packet size */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
+			/* TX input bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
+			/* TX output bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00030020);
+			/* TX Valid/ready configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023);
+			/* RX min packet size */
+			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */
+			/* RX max packet size */
+			/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */
+			/* RX input bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00030020);
+			/* RX output bus configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
+			/* RX Valid/ready configuration */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000012);
+			/* V3 additional MAC selection */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000000);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x000000a0);
+			/* ASYNC FIFO ENABLE */
+			al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
+		}
+
+		/* MAC register file */
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810);
+		/* XAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005);
+		/* RXAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1);
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel,
+					~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00073910);
+		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401);
+
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
+				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
+				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
+		break;
+
+	case AL_ETH_MAC_MODE_10G_SGMII:
+		/* MAC register file */
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810);
+
+		/* XAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000001);
+
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.if_mode, 0x0000002b);
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.control, 0x00009140);
+		// FAST AN -- Testing only
+#ifdef AL_HAL_ETH_FAST_AN
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.link_timer_lo, 0x00000040);
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.link_timer_hi, 0x00000000);
+#endif
+
+		/* RXAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007);
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel,
+					~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00063910);
+		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x40003210);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401);
+
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
+				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
+				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
+		break;
+
+	case AL_ETH_MAC_MODE_XLG_LL_40G:
+		/* configure and enable the ASYNC FIFO between the MACs and the EC */
+		/* TX min packet size */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000037);
+		/* TX max packet size */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
+		/* TX input bus configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
+		/* TX output bus configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00010040);
+		/* TX Valid/ready configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023);
+		/* RX min packet size */
+		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */
+		/* RX max packet size */
+		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */
+		/* RX input bus configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00010040);
+		/* RX output bus configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
+		/* RX Valid/ready configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000112);
+		/* V3 additional MAC selection */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000010);
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000);
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000);
+		/* ASYNC FIFO ENABLE */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
+
+		/* cmd_cfg */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x00000008);
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x01022810);
+		/* speed_ability //Read-Only */
+		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0x00000008); */
+		/* 40G capable */
+		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0x00000002); */
+
+#ifdef AL_HAL_ETH_FAST_AN
+		al_eth_40g_pcs_reg_write(adapter, 0x00010004, 1023);
+		al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0xA04c);
+		al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0x204c);
+
+#endif
+
+		/* XAUI MAC control register */
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel,
+					~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x06883910);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x0000040f);
+
+		/* MAC register file */
+/*		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); */
+		/* XAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005);
+		/* RXAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1);
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
+/*		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00073910); *//* XLG_LL_40G change */
+		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); *//* XLG_LL_40G change */
+/*		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); *//* XLG_LL_40G change */
+
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
+				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
+				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
+		break;
+
+	case AL_ETH_MAC_MODE_XLG_LL_50G:
+
+		/* configure and enable the ASYNC FIFO between the MACs and the EC */
+		/* TX min packet size */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_1, 0x00000037);
+		/* TX max packet size */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_2, 0x00002800);
+		/* TX input bus configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_3, 0x00000080);
+		/* TX output bus configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_4, 0x00010040);
+		/* TX Valid/ready configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.tx_afifo_cfg_5, 0x00000023);
+		/* RX min packet size */
+		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_1, 0x00000040); */
+		/* RX max packet size */
+		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_2, 0x00002800); */
+		/* RX input bus configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_3, 0x00010040);
+		/* RX output bus configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_4, 0x00000080);
+		/* RX Valid/ready configuration */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.rx_afifo_cfg_5, 0x00000112);
+		/* V3 additional MAC selection */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_sel, 0x00000010);
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_cfg, 0x00000000);
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_10g_ll_ctrl, 0x00000000);
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_10g_ll_cfg, 0x00000000);
+		/* ASYNC FIFO ENABLE */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.afifo_ctrl, 0x00003333);
+
+		/* cmd_cfg */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_addr, 0x00000008);
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_data, 0x01022810);
+		/* speed_ability //Read-Only */
+		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_addr, 0x00000008); */
+		/* 40G capable */
+		/* al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_data, 0x00000002); */
+
+		/* select the 25G serdes for lanes 0/1 */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.ext_serdes_ctrl, 0x0382110F);
+		/* configure the PCS to work with 2 lanes */
+		/* configure which two of the 4 PCS Lanes (VL) are combined to one RXLAUI lane */
+		/* use VL 0-2 for RXLAUI lane 0, use VL 1-3 for RXLAUI lane 1 */
+		al_eth_40g_pcs_reg_write(adapter, 0x00010008, 0x0d81);
+		/* configure the PCS to work 32 bit interface */
+		al_reg_write32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_cfg, 0x00440000);
+
+
+#ifdef AL_HAL_ETH_FAST_AN
+		al_eth_40g_pcs_reg_write(adapter, 0x00010004, 1023);
+		al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0xA04c);
+		al_eth_40g_pcs_reg_write(adapter, 0x00000000, 0x204c);
+#endif
+
+		/* XAUI MAC control register */
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x06883910);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x0000040f);
+
+		/* MAC register file */
+/*		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x01022810); */
+		/* XAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.cfg, 0x00000005);
+		/* RXAUI MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->gen.rxaui_cfg, 0x00000007);
+		al_reg_write32(&adapter->mac_regs_base->gen.sd_cfg, 0x000001F1);
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_32_64, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_out, 0x00000401); */
+		al_reg_write32(&adapter->mac_regs_base->gen.xgmii_dfifo_64_32, 0x00000401);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.mac_res_1_in, 0x00000401); */
+/*		al_reg_write32_masked(&adapter->mac_regs_base->gen.mux_sel, ~ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, 0x00073910); *//* XLG_LL_40G change */
+		al_reg_write32(&adapter->mac_regs_base->gen.clk_cfg, 0x10003210);
+/*		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x000004f0); *//* XLG_LL_40G change */
+/*		al_reg_write32(&adapter->mac_regs_base->gen.sd_fifo_ctrl, 0x00000401); *//* XLG_LL_40G change */
+
+		al_reg_write32_masked(&adapter->mac_regs_base->gen.led_cfg,
+				      ETH_MAC_GEN_LED_CFG_SEL_MASK,
+				      ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG);
+		break;
+
+
+	default:
+		al_err("Eth: unsupported MAC mode %d", mode);
+		return -EPERM;
+	}
+	adapter->mac_mode = mode;
+	al_info("configured MAC to %s mode:\n", al_eth_mac_mode_str(mode));
+
+	return 0;
+}
+
+/* start the mac */
+int al_eth_mac_start(struct al_hal_eth_adapter *adapter)
+{
+	if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) {
+		/* 1G MAC control register */
+		al_reg_write32_masked(&adapter->mac_regs_base->mac_1g.cmd_cfg, 0x3, 0x3);
+	} else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
+		/* 10G MAC control register  */
+		al_reg_write32_masked(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x3, 0x3);
+	} else {
+		uint32_t cmd_cfg;
+
+		cmd_cfg = al_eth_40g_mac_reg_read(adapter, ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR);
+
+		cmd_cfg |= (ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_TX_ENA |
+			    ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_RX_ENA);
+
+		al_eth_40g_mac_reg_write(adapter, ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR, cmd_cfg);
+	}
+
+	return 0;
+}
+
+/* stop the mac */
+int al_eth_mac_stop(struct al_hal_eth_adapter *adapter)
+{
+	if (AL_ETH_IS_1G_MAC(adapter->mac_mode))
+		/* 1G MAC control register */
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, 0x0);
+	else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode))
+		/* 10G MAC control register  */
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, 0x0);
+	else
+		al_eth_40g_mac_reg_write(adapter, ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR, 0);
+
+	return 0;
+}
+
+int al_eth_capabilities_get(struct al_hal_eth_adapter *adapter, struct al_eth_capabilities *caps)
+{
+	al_assert(caps);
+
+	caps->speed_10_HD = AL_FALSE;
+	caps->speed_10_FD = AL_FALSE;
+	caps->speed_100_HD = AL_FALSE;
+	caps->speed_100_FD = AL_FALSE;
+	caps->speed_1000_HD = AL_FALSE;
+	caps->speed_1000_FD = AL_FALSE;
+	caps->speed_10000_HD = AL_FALSE;
+	caps->speed_10000_FD = AL_FALSE;
+	caps->pfc = AL_FALSE;
+	caps->eee = AL_FALSE;
+
+	switch (adapter->mac_mode) {
+		case AL_ETH_MAC_MODE_RGMII:
+		case AL_ETH_MAC_MODE_SGMII:
+			caps->speed_10_HD = AL_TRUE;
+			caps->speed_10_FD = AL_TRUE;
+			caps->speed_100_HD = AL_TRUE;
+			caps->speed_100_FD = AL_TRUE;
+			caps->speed_1000_FD = AL_TRUE;
+			caps->eee = AL_TRUE;
+			break;
+		case AL_ETH_MAC_MODE_10GbE_Serial:
+			caps->speed_10000_FD = AL_TRUE;
+			caps->pfc = AL_TRUE;
+			break;
+		default:
+		al_err("Eth: unsupported MAC mode %d", adapter->mac_mode);
+		return -EPERM;
+	}
+	return 0;
+}
+
+/* update link speed and duplex mode */
+int al_eth_mac_link_config(struct al_hal_eth_adapter *adapter,
+			   al_bool force_1000_base_x,
+			   al_bool an_enable,
+			   uint32_t speed,
+			   al_bool full_duplex)
+{
+	uint32_t mac_ctrl;
+	uint32_t sgmii_ctrl = 0;
+	uint32_t sgmii_if_mode = 0;
+	uint32_t rgmii_ctrl = 0;
+
+	if (!AL_ETH_IS_1G_MAC(adapter->mac_mode)) {
+		al_err("eth [%s]: this function not supported in this mac mode.\n",
+			       adapter->name);
+		return -EINVAL;
+	}
+
+	if ((adapter->mac_mode != AL_ETH_MAC_MODE_RGMII) && (an_enable)) {
+		/*
+		 * an_enable is not relevant to RGMII mode.
+		 * in AN mode speed and duplex aren't relevant.
+		 */
+		al_info("eth [%s]: set auto negotiation to enable\n", adapter->name);
+	} else {
+		al_info("eth [%s]: set link speed to %dMbps. %s duplex.\n", adapter->name,
+			speed, full_duplex == AL_TRUE ? "full" : "half");
+
+		if ((speed != 10) && (speed != 100) && (speed != 1000)) {
+			al_err("eth [%s]: bad speed parameter (%d).\n",
+				       adapter->name, speed);
+			return -EINVAL;
+		}
+		if ((speed == 1000) && (full_duplex == AL_FALSE)) {
+			al_err("eth [%s]: half duplex in 1Gbps is not supported.\n",
+				       adapter->name);
+			return -EINVAL;
+		}
+	}
+
+	mac_ctrl = al_reg_read32(&adapter->mac_regs_base->mac_1g.cmd_cfg);
+
+	if (adapter->mac_mode == AL_ETH_MAC_MODE_SGMII) {
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr,
+			       ETH_MAC_SGMII_REG_ADDR_CTRL_REG);
+		sgmii_ctrl = al_reg_read32(&adapter->mac_regs_base->sgmii.reg_data);
+		/*
+		 * in case bit 0 is off in sgmii_if_mode register all the other
+		 * bits are ignored.
+		 */
+		if (force_1000_base_x == AL_FALSE)
+			sgmii_if_mode = ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_EN;
+
+		if (an_enable == AL_TRUE) {
+			sgmii_if_mode |= ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_AN;
+			sgmii_ctrl |= ETH_MAC_SGMII_REG_DATA_CTRL_AN_ENABLE;
+		} else {
+			sgmii_ctrl &= ~(ETH_MAC_SGMII_REG_DATA_CTRL_AN_ENABLE);
+		}
+	}
+
+	if (adapter->mac_mode == AL_ETH_MAC_MODE_RGMII) {
+		/*
+		 * Use the speed provided by the MAC instead of the PHY
+		 */
+		rgmii_ctrl = al_reg_read32(&adapter->mac_regs_base->gen.rgmii_cfg);
+
+		AL_REG_MASK_CLEAR(rgmii_ctrl, ETH_MAC_GEN_RGMII_CFG_ENA_AUTO);
+		AL_REG_MASK_CLEAR(rgmii_ctrl, ETH_MAC_GEN_RGMII_CFG_SET_1000_SEL);
+		AL_REG_MASK_CLEAR(rgmii_ctrl, ETH_MAC_GEN_RGMII_CFG_SET_10_SEL);
+
+		al_reg_write32(&adapter->mac_regs_base->gen.rgmii_cfg, rgmii_ctrl);
+	}
+
+	if (full_duplex == AL_TRUE) {
+		AL_REG_MASK_CLEAR(mac_ctrl, AL_ETH_1G_MAC_CTRL_HD_EN);
+	} else {
+		AL_REG_MASK_SET(mac_ctrl, AL_ETH_1G_MAC_CTRL_HD_EN);
+		sgmii_if_mode |= ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_DUPLEX;
+	}
+
+	if (speed == 1000) {
+		AL_REG_MASK_SET(mac_ctrl, AL_ETH_1G_MAC_CTRL_1G_SPD);
+		sgmii_if_mode |= ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_1000;
+	} else {
+		AL_REG_MASK_CLEAR(mac_ctrl, AL_ETH_1G_MAC_CTRL_1G_SPD);
+		if (speed == 10) {
+			AL_REG_MASK_SET(mac_ctrl, AL_ETH_1G_MAC_CTRL_10M_SPD);
+		} else {
+			sgmii_if_mode |= ETH_MAC_SGMII_REG_DATA_IF_MODE_SGMII_SPEED_100;
+			AL_REG_MASK_CLEAR(mac_ctrl, AL_ETH_1G_MAC_CTRL_10M_SPD);
+		}
+	}
+
+	if (adapter->mac_mode == AL_ETH_MAC_MODE_SGMII) {
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr,
+			       ETH_MAC_SGMII_REG_ADDR_IF_MODE_REG);
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data,
+			       sgmii_if_mode);
+
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr,
+			       ETH_MAC_SGMII_REG_ADDR_CTRL_REG);
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_data,
+			       sgmii_ctrl);
+	}
+
+	al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, mac_ctrl);
+
+	return 0;
+}
+
+int al_eth_mac_loopback_config(struct al_hal_eth_adapter *adapter, int enable)
+{
+	const char *state = (enable) ? "enable" : "disable";
+
+	al_dbg("eth [%s]: loopback %s\n", adapter->name, state);
+	if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) {
+		uint32_t reg;
+		reg = al_reg_read32(&adapter->mac_regs_base->mac_1g.cmd_cfg);
+		if (enable)
+			reg |= AL_BIT(15);
+		else
+			reg &= ~AL_BIT(15);
+		al_reg_write32(&adapter->mac_regs_base->mac_1g.cmd_cfg, reg);
+	} else if ((AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode))
+			&& (adapter->rev_id == AL_ETH_REV_ID_3)) {
+		uint32_t reg;
+		al_reg_write16(
+			(uint16_t *)&adapter->mac_regs_base->kr.pcs_addr, ETH_MAC_KR_PCS_CONTROL_1_ADDR);
+		reg = al_reg_read16(
+			(uint16_t *)&adapter->mac_regs_base->kr.pcs_data);
+		if (enable)
+			reg |= AL_BIT(14);
+		else
+			reg &= ~AL_BIT(14);
+		al_reg_write16(
+			(uint16_t *)&adapter->mac_regs_base->kr.pcs_addr, ETH_MAC_KR_PCS_CONTROL_1_ADDR);
+		al_reg_write16(
+			(uint16_t *)&adapter->mac_regs_base->kr.pcs_data, reg);
+	} else if (adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_40G ||
+			(adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_50G)) {
+		uint32_t reg;
+		reg = al_eth_40g_pcs_reg_read(adapter, ETH_MAC_GEN_V3_PCS_40G_CONTROL_STATUS_ADDR);
+		if (enable)
+			reg |= AL_BIT(14);
+		else
+			reg &= ~AL_BIT(14);
+		al_eth_40g_pcs_reg_write(adapter, ETH_MAC_GEN_V3_PCS_40G_CONTROL_STATUS_ADDR, reg);
+	} else {
+		al_err("Eth: mac loopback not supported in this mode %d", adapter->mac_mode);
+		return -EPERM;
+	}
+	return 0;
+}
+
+/* MDIO */
+int al_eth_mdio_config(
+	struct al_hal_eth_adapter	*adapter,
+	enum al_eth_mdio_type		mdio_type,
+	al_bool				shared_mdio_if,
+	enum al_eth_ref_clk_freq	ref_clk_freq,
+	unsigned int			mdio_clk_freq_khz)
+{
+	enum al_eth_mdio_if mdio_if = AL_ETH_MDIO_IF_10G_MAC;
+	const char *if_name = (mdio_if == AL_ETH_MDIO_IF_1G_MAC) ? "10/100/1G MAC" : "10G MAC";
+	const char *type_name = (mdio_type == AL_ETH_MDIO_TYPE_CLAUSE_22) ? "Clause 22" : "Clause 45";
+	const char *shared_name = (shared_mdio_if == AL_TRUE) ? "Yes" : "No";
+
+	unsigned int ref_clk_freq_khz;
+	uint32_t val;
+
+	al_dbg("eth [%s]: mdio config: interface %s. type %s. shared: %s\n", adapter->name, if_name, type_name, shared_name);
+	adapter->shared_mdio_if = shared_mdio_if;
+
+	val = al_reg_read32(&adapter->mac_regs_base->gen.cfg);
+	al_dbg("eth [%s]: mdio config: 10G mac \n", adapter->name);
+
+	switch(mdio_if)
+	{
+		case AL_ETH_MDIO_IF_1G_MAC:
+			val &= ~AL_BIT(10);
+			break;
+		case AL_ETH_MDIO_IF_10G_MAC:
+			val |= AL_BIT(10);
+			break;
+	}
+	al_reg_write32(&adapter->mac_regs_base->gen.cfg, val);
+	adapter->mdio_if = mdio_if;
+
+
+	if (mdio_if == AL_ETH_MDIO_IF_10G_MAC)
+	{
+		val = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status);
+		switch(mdio_type)
+		{
+			case AL_ETH_MDIO_TYPE_CLAUSE_22:
+				val &= ~AL_BIT(6);
+				break;
+			case AL_ETH_MDIO_TYPE_CLAUSE_45:
+				val |= AL_BIT(6);
+				break;
+		}
+
+		/* set clock div to get 'mdio_clk_freq_khz' */
+		switch (ref_clk_freq) {
+		default:
+			al_err("eth [%s]: %s: invalid reference clock frequency"
+				" (%d)\n",
+				adapter->name, __func__, ref_clk_freq);
+		case AL_ETH_REF_FREQ_375_MHZ:
+			ref_clk_freq_khz = 375000;
+			break;
+		case AL_ETH_REF_FREQ_187_5_MHZ:
+			ref_clk_freq_khz = 187500;
+			break;
+		case AL_ETH_REF_FREQ_250_MHZ:
+			ref_clk_freq_khz = 250000;
+			break;
+		case AL_ETH_REF_FREQ_500_MHZ:
+			ref_clk_freq_khz = 500000;
+			break;
+                case AL_ETH_REF_FREQ_428_MHZ:
+                        ref_clk_freq_khz = 428000;
+                        break;
+		};
+
+		val &= ~(0x1FF << 7);
+		val |= (ref_clk_freq_khz / (2 * mdio_clk_freq_khz)) << 7;
+		AL_REG_FIELD_SET(val, ETH_10G_MAC_MDIO_CFG_HOLD_TIME_MASK,
+				 ETH_10G_MAC_MDIO_CFG_HOLD_TIME_SHIFT,
+				 ETH_10G_MAC_MDIO_CFG_HOLD_TIME_7_CLK);
+		al_reg_write32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status, val);
+	}else{
+		if(mdio_type != AL_ETH_MDIO_TYPE_CLAUSE_22) {
+			al_err("eth [%s] mdio type not supported for this interface\n",
+				 adapter->name);
+			return -EINVAL;
+		}
+	}
+	adapter->mdio_type = mdio_type;
+
+	return 0;
+}
+
+static int al_eth_mdio_1g_mac_read(struct al_hal_eth_adapter *adapter,
+			    uint32_t phy_addr __attribute__((__unused__)),
+			    uint32_t reg, uint16_t *val)
+{
+	*val = al_reg_read32(
+		&adapter->mac_regs_base->mac_1g.phy_regs_base + reg);
+	return 0;
+}
+
+static int al_eth_mdio_1g_mac_write(struct al_hal_eth_adapter *adapter,
+			     uint32_t phy_addr __attribute__((__unused__)),
+			     uint32_t reg, uint16_t val)
+{
+	al_reg_write32(
+		&adapter->mac_regs_base->mac_1g.phy_regs_base + reg, val);
+	return 0;
+}
+
+static int al_eth_mdio_10g_mac_wait_busy(struct al_hal_eth_adapter *adapter)
+{
+	int	count = 0;
+	uint32_t mdio_cfg_status;
+
+	do {
+		mdio_cfg_status = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status);
+/*
+		if (mdio_cfg_status & AL_BIT(1)){ //error
+			al_err(" %s mdio read failed on error. phy_addr 0x%x reg 0x%x\n",
+				udma_params.name, phy_addr, reg);
+			return -EIO;
+		}*/
+		if (mdio_cfg_status & AL_BIT(0)){
+			if (count > 0)
+				al_dbg("eth [%s] mdio: still busy!\n", adapter->name);
+		}else{
+			return 0;
+		}
+		al_udelay(AL_ETH_MDIO_DELAY_PERIOD);
+	}while(count++ < AL_ETH_MDIO_DELAY_COUNT);
+
+	return -ETIMEDOUT;
+}
+
+static int al_eth_mdio_10g_mac_type22(
+	struct al_hal_eth_adapter *adapter,
+	int read, uint32_t phy_addr, uint32_t reg, uint16_t *val)
+{
+	int rc;
+	const char *op = (read == 1) ? "read":"write";
+	uint32_t mdio_cfg_status;
+	uint16_t mdio_cmd;
+
+	//wait if the HW is busy
+	rc = al_eth_mdio_10g_mac_wait_busy(adapter);
+	if (rc) {
+		al_err(" eth [%s] mdio %s failed. HW is busy\n", adapter->name, op);
+		return rc;
+	}
+
+	mdio_cmd = (uint16_t)(0x1F & reg);
+	mdio_cmd |= (0x1F & phy_addr) << 5;
+
+	if (read)
+		mdio_cmd |= AL_BIT(15); //READ command
+
+	al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_cmd,
+			mdio_cmd);
+	if (!read)
+		al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_data,
+				*val);
+
+	//wait for the busy to clear
+	rc = al_eth_mdio_10g_mac_wait_busy(adapter);
+	if (rc != 0) {
+		al_err(" %s mdio %s failed on timeout\n", adapter->name, op);
+		return -ETIMEDOUT;
+	}
+
+	mdio_cfg_status = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status);
+
+	if (mdio_cfg_status & AL_BIT(1)){ //error
+		al_err(" %s mdio %s failed on error. phy_addr 0x%x reg 0x%x\n",
+			adapter->name, op, phy_addr, reg);
+			return -EIO;
+	}
+	if (read)
+		*val = al_reg_read16(
+			(uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_data);
+	return 0;
+}
+
+static int al_eth_mdio_10g_mac_type45(
+	struct al_hal_eth_adapter *adapter,
+	int read, uint32_t port_addr, uint32_t device, uint32_t reg, uint16_t *val)
+{
+	int rc;
+	const char *op = (read == 1) ? "read":"write";
+	uint32_t mdio_cfg_status;
+	uint16_t mdio_cmd;
+
+	//wait if the HW is busy
+	rc = al_eth_mdio_10g_mac_wait_busy(adapter);
+	if (rc) {
+		al_err(" %s mdio %s failed. HW is busy\n", adapter->name, op);
+		return rc;
+	}
+	// set command register
+	mdio_cmd = (uint16_t)(0x1F & device);
+	mdio_cmd |= (0x1F & port_addr) << 5;
+	al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_cmd,
+			mdio_cmd);
+
+	// send address frame
+	al_reg_write16(&adapter->mac_regs_base->mac_10g.mdio_regaddr, reg);
+	//wait for the busy to clear
+	rc = al_eth_mdio_10g_mac_wait_busy(adapter);
+	if (rc) {
+		al_err(" %s mdio %s (address frame) failed on timeout\n", adapter->name, op);
+		return rc;
+	}
+
+	// if read, write again to the command register with READ bit set
+	if (read) {
+		mdio_cmd |= AL_BIT(15); //READ command
+		al_reg_write16(
+			(uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_cmd,
+			mdio_cmd);
+	} else {
+		al_reg_write16(
+			(uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_data,
+			*val);
+	}
+	//wait for the busy to clear
+	rc = al_eth_mdio_10g_mac_wait_busy(adapter);
+	if (rc) {
+		al_err(" %s mdio %s failed on timeout\n", adapter->name, op);
+		return rc;
+	}
+
+	mdio_cfg_status = al_reg_read32(&adapter->mac_regs_base->mac_10g.mdio_cfg_status);
+
+	if (mdio_cfg_status & AL_BIT(1)){ //error
+		al_err(" %s mdio %s failed on error. port 0x%x, device 0x%x reg 0x%x\n",
+			adapter->name, op, port_addr, device, reg);
+			return -EIO;
+	}
+	if (read)
+		*val = al_reg_read16(
+			(uint16_t *)&adapter->mac_regs_base->mac_10g.mdio_data);
+	return 0;
+}
+
+/**
+ * acquire mdio interface ownership
+ * when mdio interface shared between multiple eth controllers, this function waits until the ownership granted for this controller.
+ * this function does nothing when the mdio interface is used only by this controller.
+ *
+ * @param adapter
+ * @return 0 on success, -ETIMEDOUT  on timeout.
+ */
+static int al_eth_mdio_lock(struct al_hal_eth_adapter *adapter)
+{
+	int	count = 0;
+	uint32_t mdio_ctrl_1;
+
+	if (adapter->shared_mdio_if == AL_FALSE)
+		return 0; /* nothing to do when interface is not shared */
+
+	do {
+		mdio_ctrl_1 = al_reg_read32(&adapter->mac_regs_base->gen.mdio_ctrl_1);
+/*
+		if (mdio_cfg_status & AL_BIT(1)){ //error
+			al_err(" %s mdio read failed on error. phy_addr 0x%x reg 0x%x\n",
+				udma_params.name, phy_addr, reg);
+			return -EIO;
+		}*/
+		if (mdio_ctrl_1 & AL_BIT(0)){
+			if (count > 0)
+				al_dbg("eth %s mdio interface still busy!\n", adapter->name);
+		}else{
+			return 0;
+		}
+		al_udelay(AL_ETH_MDIO_DELAY_PERIOD);
+	}while(count++ < (AL_ETH_MDIO_DELAY_COUNT * 4));
+	al_err(" %s mdio failed to take ownership. MDIO info reg: 0x%08x\n",
+		adapter->name, al_reg_read32(&adapter->mac_regs_base->gen.mdio_1));
+
+	return -ETIMEDOUT;
+}
+
+/**
+ * free mdio interface ownership
+ * when mdio interface shared between multiple eth controllers, this function releases the ownership granted for this controller.
+ * this function does nothing when the mdio interface is used only by this controller.
+ *
+ * @param adapter
+ * @return 0.
+ */
+static int al_eth_mdio_free(struct al_hal_eth_adapter *adapter)
+{
+	if (adapter->shared_mdio_if == AL_FALSE)
+		return 0; /* nothing to do when interface is not shared */
+
+	al_reg_write32(&adapter->mac_regs_base->gen.mdio_ctrl_1, 0);
+
+	/*
+	 * Addressing RMN: 2917
+	 *
+	 * RMN description:
+	 * The HW spin-lock is stateless and doesn't maintain any scheduling
+	 * policy.
+	 *
+	 * Software flow:
+	 * After getting the lock wait 2 times the delay period in order to give
+	 * the other port chance to take the lock and prevent starvation.
+	 * This is not scalable to more than two ports.
+	 */
+	al_udelay(2 * AL_ETH_MDIO_DELAY_PERIOD);
+
+	return 0;
+}
+
+int al_eth_mdio_read(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, uint32_t device, uint32_t reg, uint16_t *val)
+{
+	int rc;
+	rc = al_eth_mdio_lock(adapter);
+
+	/*"interface ownership taken"*/
+	if (rc)
+		return rc;
+
+	if (adapter->mdio_if == AL_ETH_MDIO_IF_1G_MAC)
+		rc = al_eth_mdio_1g_mac_read(adapter, phy_addr, reg, val);
+	else
+		if (adapter->mdio_type == AL_ETH_MDIO_TYPE_CLAUSE_22)
+			rc = al_eth_mdio_10g_mac_type22(adapter, 1, phy_addr, reg, val);
+		else
+			rc = al_eth_mdio_10g_mac_type45(adapter, 1, phy_addr, device, reg, val);
+
+	al_eth_mdio_free(adapter);
+	al_dbg("eth mdio read: phy_addr %x, device %x, reg %x val %x\n", phy_addr, device, reg, *val);
+	return rc;
+}
+
+int al_eth_mdio_write(struct al_hal_eth_adapter *adapter, uint32_t phy_addr, uint32_t device, uint32_t reg, uint16_t val)
+{
+	int rc;
+	al_dbg("eth mdio write: phy_addr %x, device %x, reg %x, val %x\n", phy_addr, device, reg, val);
+	rc = al_eth_mdio_lock(adapter);
+	/* interface ownership taken */
+	if (rc)
+		return rc;
+
+	if (adapter->mdio_if == AL_ETH_MDIO_IF_1G_MAC)
+		rc = al_eth_mdio_1g_mac_write(adapter, phy_addr, reg, val);
+	else
+		if (adapter->mdio_type == AL_ETH_MDIO_TYPE_CLAUSE_22)
+			rc = al_eth_mdio_10g_mac_type22(adapter, 0, phy_addr, reg, &val);
+		else
+			rc = al_eth_mdio_10g_mac_type45(adapter, 0, phy_addr, device, reg, &val);
+
+	al_eth_mdio_free(adapter);
+	return rc;
+}
+
+static void al_dump_tx_desc(union al_udma_desc *tx_desc)
+{
+	uint32_t *ptr = (uint32_t *)tx_desc;
+	al_dbg("eth tx desc:\n");
+	al_dbg("0x%08x\n", *(ptr++));
+	al_dbg("0x%08x\n", *(ptr++));
+	al_dbg("0x%08x\n", *(ptr++));
+	al_dbg("0x%08x\n", *(ptr++));
+}
+
+static void
+al_dump_tx_pkt(struct al_udma_q *tx_dma_q, struct al_eth_pkt *pkt)
+{
+	const char *tso = (pkt->flags & AL_ETH_TX_FLAGS_TSO) ? "TSO" : "";
+	const char *l3_csum = (pkt->flags & AL_ETH_TX_FLAGS_IPV4_L3_CSUM) ? "L3 CSUM" : "";
+	const char *l4_csum = (pkt->flags & AL_ETH_TX_FLAGS_L4_CSUM) ?
+	  ((pkt->flags & AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM) ? "L4 PARTIAL CSUM" : "L4 FULL CSUM") : "";
+	const char *fcs = (pkt->flags & AL_ETH_TX_FLAGS_L2_DIS_FCS) ? "Disable FCS" : "";
+	const char *ptp = (pkt->flags & AL_ETH_TX_FLAGS_TS) ? "TX_PTP" : "";
+	const char *l3_proto_name = "unknown";
+	const char *l4_proto_name = "unknown";
+	const char *outer_l3_proto_name = "N/A";
+	const char *tunnel_mode = ((pkt->tunnel_mode & AL_ETH_TUNNEL_WITH_UDP) ==
+				  AL_ETH_TUNNEL_WITH_UDP) ?
+				  "TUNNEL_WITH_UDP" :
+				  ((pkt->tunnel_mode & AL_ETH_TUNNEL_NO_UDP) ==
+				  AL_ETH_TUNNEL_NO_UDP) ?
+				  "TUNNEL_NO_UDP" : "";
+	uint32_t total_len = 0;
+	int i;
+
+	al_dbg("[%s %d]: flags: %s %s %s %s %s %s\n", tx_dma_q->udma->name, tx_dma_q->qid,
+		 tso, l3_csum, l4_csum, fcs, ptp, tunnel_mode);
+
+	switch (pkt->l3_proto_idx) {
+	case AL_ETH_PROTO_ID_IPv4:
+		l3_proto_name = "IPv4";
+		break;
+	case AL_ETH_PROTO_ID_IPv6:
+		l3_proto_name = "IPv6";
+		break;
+	default:
+		l3_proto_name = "unknown";
+		break;
+	}
+
+	switch (pkt->l4_proto_idx) {
+	case AL_ETH_PROTO_ID_TCP:
+		l4_proto_name = "TCP";
+		break;
+	case AL_ETH_PROTO_ID_UDP:
+		l4_proto_name = "UDP";
+		break;
+	default:
+		l4_proto_name = "unknown";
+		break;
+	}
+
+	switch (pkt->outer_l3_proto_idx) {
+	case AL_ETH_PROTO_ID_IPv4:
+		outer_l3_proto_name = "IPv4";
+		break;
+	case AL_ETH_PROTO_ID_IPv6:
+		outer_l3_proto_name = "IPv6";
+		break;
+	default:
+		outer_l3_proto_name = "N/A";
+		break;
+	}
+
+	al_dbg("[%s %d]: L3 proto: %d (%s). L4 proto: %d (%s). Outer_L3 proto: %d (%s). vlan source count %d. mod add %d. mod del %d\n",
+			tx_dma_q->udma->name, tx_dma_q->qid, pkt->l3_proto_idx,
+			l3_proto_name, pkt->l4_proto_idx, l4_proto_name,
+			pkt->outer_l3_proto_idx, outer_l3_proto_name,
+			pkt->source_vlan_count, pkt->vlan_mod_add_count,
+			pkt->vlan_mod_del_count);
+
+	if (pkt->meta) {
+		const char * store = pkt->meta->store ? "Yes" : "No";
+
+		al_dbg("[%s %d]: tx pkt with meta data. words valid %x\n",
+			tx_dma_q->udma->name, tx_dma_q->qid,
+			pkt->meta->words_valid);
+		if (tx_dma_q->adapter_rev_id == AL_ETH_REV_ID_0)
+			al_dbg("[%s %d]: meta: store to cache %s. l3 hdr len %d. l3 hdr offset %d. l4 hdr len %d. mss sel %d\n"
+				, tx_dma_q->udma->name, tx_dma_q->qid, store,
+				pkt->meta->l3_header_len, pkt->meta->l3_header_offset,
+				pkt->meta->l4_header_len,
+				pkt->meta->mss_idx_sel);
+		else {
+			const char *ptp_val = (pkt->flags & AL_ETH_TX_FLAGS_TS) ? "Yes" : "No";
+			al_dbg("[%s %d]: meta: store to cache %s. l3 hdr len %d. l3 hdr offset %d. l4 hdr len %d. mss val %d ts_index %d ts_val:%s\n"
+				, tx_dma_q->udma->name, tx_dma_q->qid, store,
+				pkt->meta->l3_header_len, pkt->meta->l3_header_offset,
+				pkt->meta->l4_header_len, pkt->meta->mss_val,
+				pkt->meta->ts_index, ptp_val);
+			al_dbg("outer_l3_hdr_offset %d. outer_l3_len %d.\n",
+				pkt->meta->outer_l3_offset, pkt->meta->outer_l3_len);
+		}
+	}
+
+	al_dbg("[%s %d]: num of bufs: %d\n", tx_dma_q->udma->name, tx_dma_q->qid,
+		pkt->num_of_bufs);
+	for (i = 0; i < pkt->num_of_bufs; i++) {
+		al_dbg("eth [%s %d]: buf[%d]: len 0x%08x. address 0x%016llx\n", tx_dma_q->udma->name, tx_dma_q->qid,
+			i, pkt->bufs[i].len, (unsigned long long)pkt->bufs[i].addr);
+		total_len += pkt->bufs[i].len;
+	}
+	al_dbg("[%s %d]: total len: 0x%08x\n", tx_dma_q->udma->name, tx_dma_q->qid, total_len);
+
+}
+
+/* TX */
+/**
+ * add packet to transmission queue
+ */
+int al_eth_tx_pkt_prepare(struct al_udma_q *tx_dma_q, struct al_eth_pkt *pkt)
+{
+	union al_udma_desc *tx_desc;
+	uint32_t tx_descs;
+	uint32_t flags = AL_M2S_DESC_FIRST |
+			AL_M2S_DESC_CONCAT |
+			(pkt->flags & AL_ETH_TX_FLAGS_INT);
+	uint64_t vmid = ((uint64_t)pkt->vmid) << AL_UDMA_DESC_VMID_SHIFT;
+	uint32_t meta_ctrl;
+	uint32_t ring_id;
+	int buf_idx;
+
+	al_dbg("[%s %d]: new tx pkt\n", tx_dma_q->udma->name, tx_dma_q->qid);
+
+	al_dump_tx_pkt(tx_dma_q, pkt);
+
+	tx_descs = pkt->num_of_bufs;
+	if (pkt->meta) {
+		tx_descs += 1;
+	}
+#ifdef AL_ETH_EX
+	al_assert((pkt->ext_meta_data == NULL) || (tx_dma_q->adapter_rev_id > AL_ETH_REV_ID_2));
+
+	tx_descs += al_eth_ext_metadata_needed_descs(pkt->ext_meta_data);
+	al_dbg("[%s %d]: %d Descriptors: ext_meta (%d). meta (%d). buffer (%d) ",
+			tx_dma_q->udma->name, tx_dma_q->qid, tx_descs,
+			al_eth_ext_metadata_needed_descs(pkt->ext_meta_data),
+			(pkt->meta != NULL), pkt->num_of_bufs);
+#endif
+
+	if (unlikely(al_udma_available_get(tx_dma_q) < tx_descs)) {
+		al_dbg("[%s %d]: failed to allocate (%d) descriptors",
+			 tx_dma_q->udma->name, tx_dma_q->qid, tx_descs);
+		return 0;
+	}
+
+#ifdef AL_ETH_EX
+	if (pkt->ext_meta_data != NULL) {
+		al_eth_ext_metadata_create(tx_dma_q, &flags, pkt->ext_meta_data);
+		flags &= ~(AL_M2S_DESC_FIRST | AL_ETH_TX_FLAGS_INT);
+	}
+#endif
+
+	if (pkt->meta) {
+		uint32_t meta_word_0 = 0;
+		uint32_t meta_word_1 = 0;
+		uint32_t meta_word_2 = 0;
+		uint32_t meta_word_3 = 0;
+
+		meta_word_0 |= flags | AL_M2S_DESC_META_DATA;
+		meta_word_0 &=  ~AL_M2S_DESC_CONCAT;
+		flags &= ~(AL_M2S_DESC_FIRST | AL_ETH_TX_FLAGS_INT);
+
+		tx_desc = al_udma_desc_get(tx_dma_q);
+		/* get ring id, and clear FIRST and Int flags */
+		ring_id = al_udma_ring_id_get(tx_dma_q) <<
+			AL_M2S_DESC_RING_ID_SHIFT;
+
+		meta_word_0 |= ring_id;
+		meta_word_0 |= pkt->meta->words_valid << 12;
+
+		if (pkt->meta->store)
+			meta_word_0 |= AL_ETH_TX_META_STORE;
+
+		if (pkt->meta->words_valid & 1) {
+			meta_word_0 |= pkt->meta->vlan1_cfi_sel;
+			meta_word_0 |= pkt->meta->vlan2_vid_sel << 2;
+			meta_word_0 |= pkt->meta->vlan2_cfi_sel << 4;
+			meta_word_0 |= pkt->meta->vlan2_pbits_sel << 6;
+			meta_word_0 |= pkt->meta->vlan2_ether_sel << 8;
+		}
+
+		if (pkt->meta->words_valid & 2) {
+			meta_word_1 = pkt->meta->vlan1_new_vid;
+			meta_word_1 |= pkt->meta->vlan1_new_cfi << 12;
+			meta_word_1 |= pkt->meta->vlan1_new_pbits << 13;
+			meta_word_1 |= pkt->meta->vlan2_new_vid << 16;
+			meta_word_1 |= pkt->meta->vlan2_new_cfi << 28;
+			meta_word_1 |= pkt->meta->vlan2_new_pbits << 29;
+		}
+
+		if (pkt->meta->words_valid & 4) {
+			meta_word_2 = pkt->meta->l3_header_len & AL_ETH_TX_META_L3_LEN_MASK;
+			meta_word_2 |= (pkt->meta->l3_header_offset & AL_ETH_TX_META_L3_OFF_MASK) <<
+				AL_ETH_TX_META_L3_OFF_SHIFT;
+			meta_word_2 |= (pkt->meta->l4_header_len & 0x3f) << 16;
+
+			if (tx_dma_q->adapter_rev_id == AL_ETH_REV_ID_0) {
+				meta_word_2 |= (pkt->meta->mss_idx_sel & 7) << 24;
+			} else {
+				uint32_t l3_offset;
+
+				if (unlikely(pkt->flags & AL_ETH_TX_FLAGS_TS))
+					meta_word_0 |= pkt->meta->ts_index << AL_ETH_TX_META_MSS_MSB_TS_VAL_SHIFT;
+				else
+					meta_word_0 |= (((pkt->meta->mss_val & 0x3c00) >> 10)
+							<< AL_ETH_TX_META_MSS_MSB_TS_VAL_SHIFT);
+				meta_word_2 |= ((pkt->meta->mss_val & 0x03ff)
+						<< AL_ETH_TX_META_MSS_LSB_VAL_SHIFT);
+
+				/*
+				 * move from bytes to multiplication of 2 as the HW
+				 * expect to get it
+				 */
+				l3_offset = (pkt->meta->outer_l3_offset >> 1);
+
+				meta_word_0 |=
+					(((l3_offset &
+					   AL_ETH_TX_META_OUTER_L3_OFF_HIGH_MASK) >> 3)
+					   << AL_ETH_TX_META_OUTER_L3_OFF_HIGH_SHIFT);
+
+				meta_word_3 |=
+					((l3_offset &
+					   AL_ETH_TX_META_OUTER_L3_OFF_LOW_MASK)
+					   << AL_ETH_TX_META_OUTER_L3_OFF_LOW_SHIFT);
+
+				/*
+				 * shift right 2 bits to work in multiplication of 4
+				 * as the HW expect to get it
+				 */
+				meta_word_3 |=
+					(((pkt->meta->outer_l3_len >> 2) &
+					   AL_ETH_TX_META_OUTER_L3_LEN_MASK)
+					   << AL_ETH_TX_META_OUTER_L3_LEN_SHIFT);
+			}
+		}
+
+		tx_desc->tx_meta.len_ctrl = swap32_to_le(meta_word_0);
+		tx_desc->tx_meta.meta_ctrl = swap32_to_le(meta_word_1);
+		tx_desc->tx_meta.meta1 = swap32_to_le(meta_word_2);
+		tx_desc->tx_meta.meta2 = swap32_to_le(meta_word_3);
+		al_dump_tx_desc(tx_desc);
+	}
+
+	meta_ctrl = pkt->flags & AL_ETH_TX_PKT_META_FLAGS;
+
+	/* L4_PARTIAL_CSUM without L4_CSUM is invalid option  */
+	al_assert((pkt->flags & (AL_ETH_TX_FLAGS_L4_CSUM|AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM)) !=
+		  AL_ETH_TX_FLAGS_L4_PARTIAL_CSUM);
+
+	/* TSO packets can't have Timestamp enabled */
+	al_assert((pkt->flags & (AL_ETH_TX_FLAGS_TSO|AL_ETH_TX_FLAGS_TS)) !=
+		  (AL_ETH_TX_FLAGS_TSO|AL_ETH_TX_FLAGS_TS));
+
+	meta_ctrl |= pkt->l3_proto_idx;
+	meta_ctrl |= pkt->l4_proto_idx << AL_ETH_TX_L4_PROTO_IDX_SHIFT;
+	meta_ctrl |= pkt->source_vlan_count << AL_ETH_TX_SRC_VLAN_CNT_SHIFT;
+	meta_ctrl |= pkt->vlan_mod_add_count << AL_ETH_TX_VLAN_MOD_ADD_SHIFT;
+	meta_ctrl |= pkt->vlan_mod_del_count << AL_ETH_TX_VLAN_MOD_DEL_SHIFT;
+	meta_ctrl |= pkt->vlan_mod_v1_ether_sel << AL_ETH_TX_VLAN_MOD_E_SEL_SHIFT;
+	meta_ctrl |= pkt->vlan_mod_v1_vid_sel << AL_ETH_TX_VLAN_MOD_VID_SEL_SHIFT;
+	meta_ctrl |= pkt->vlan_mod_v1_pbits_sel << AL_ETH_TX_VLAN_MOD_PBIT_SEL_SHIFT;
+
+#ifdef AL_ETH_EX
+	if ((pkt->ext_meta_data != NULL) && (pkt->ext_meta_data->tx_crypto_data != NULL))
+		meta_ctrl |= AL_ETH_TX_FLAGS_ENCRYPT;
+#endif
+
+	if (tx_dma_q->adapter_rev_id > AL_ETH_REV_ID_0) {
+		meta_ctrl |= pkt->tunnel_mode << AL_ETH_TX_TUNNEL_MODE_SHIFT;
+		if (pkt->outer_l3_proto_idx == AL_ETH_PROTO_ID_IPv4)
+			meta_ctrl |= 1 << AL_ETH_TX_OUTER_L3_PROTO_SHIFT;
+	}
+
+	flags |= pkt->flags & AL_ETH_TX_PKT_UDMA_FLAGS;
+	for(buf_idx = 0; buf_idx < pkt->num_of_bufs; buf_idx++ ) {
+		uint32_t flags_len = flags;
+
+		tx_desc = al_udma_desc_get(tx_dma_q);
+		/* get ring id, and clear FIRST and Int flags */
+		ring_id = al_udma_ring_id_get(tx_dma_q) <<
+			AL_M2S_DESC_RING_ID_SHIFT;
+
+		flags_len |= ring_id;
+
+		if (buf_idx == (pkt->num_of_bufs - 1))
+			flags_len |= AL_M2S_DESC_LAST;
+
+		/* clear First and Int flags */
+		flags &= AL_ETH_TX_FLAGS_NO_SNOOP;
+		flags |= AL_M2S_DESC_CONCAT;
+
+		flags_len |= pkt->bufs[buf_idx].len & AL_M2S_DESC_LEN_MASK;
+		tx_desc->tx.len_ctrl = swap32_to_le(flags_len);
+		if (buf_idx == 0)
+			tx_desc->tx.meta_ctrl = swap32_to_le(meta_ctrl);
+		tx_desc->tx.buf_ptr = swap64_to_le(
+			pkt->bufs[buf_idx].addr | vmid);
+		al_dump_tx_desc(tx_desc);
+	}
+
+	al_dbg("[%s %d]: pkt descriptors written into the tx queue. descs num (%d)\n",
+		tx_dma_q->udma->name, tx_dma_q->qid, tx_descs);
+
+	return tx_descs;
+}
+
+
+void al_eth_tx_dma_action(struct al_udma_q *tx_dma_q, uint32_t tx_descs)
+{
+	/* add tx descriptors */
+	al_udma_desc_action_add(tx_dma_q, tx_descs);
+}
+
+/**
+ * get number of completed tx descriptors, upper layer should derive from
+ */
+int al_eth_comp_tx_get(struct al_udma_q *tx_dma_q)
+{
+	int rc;
+
+	rc = al_udma_cdesc_get_all(tx_dma_q, NULL);
+	if (rc != 0) {
+		al_udma_cdesc_ack(tx_dma_q, rc);
+		al_dbg("[%s %d]: tx completion: descs (%d)\n",
+			 tx_dma_q->udma->name, tx_dma_q->qid, rc);
+	}
+
+	return rc;
+}
+
+/**
+ * configure the TSO MSS val
+ */
+int al_eth_tso_mss_config(struct al_hal_eth_adapter *adapter, uint8_t idx, uint32_t mss_val)
+{
+
+	al_assert(idx <= 8); /*valid MSS index*/
+	al_assert(mss_val <= AL_ETH_TSO_MSS_MAX_VAL); /*valid MSS val*/
+	al_assert(mss_val >= AL_ETH_TSO_MSS_MIN_VAL); /*valid MSS val*/
+
+	al_reg_write32(&adapter->ec_regs_base->tso_sel[idx].mss, mss_val);
+	return 0;
+}
+
+
+/* RX */
+/**
+ * config the rx descriptor fields
+ */
+void al_eth_rx_desc_config(
+			struct al_hal_eth_adapter *adapter,
+			enum al_eth_rx_desc_lro_context_val_res lro_sel,
+			enum al_eth_rx_desc_l4_offset_sel l4_offset_sel,
+			enum al_eth_rx_desc_l3_offset_sel l3_offset_sel,
+			enum al_eth_rx_desc_l4_chk_res_sel l4_sel,
+			enum al_eth_rx_desc_l3_chk_res_sel l3_sel,
+			enum al_eth_rx_desc_l3_proto_idx_sel l3_proto_sel,
+			enum al_eth_rx_desc_l4_proto_idx_sel l4_proto_sel,
+			enum al_eth_rx_desc_frag_sel frag_sel)
+{
+	uint32_t reg_val = 0;
+
+	reg_val |= (lro_sel == AL_ETH_L4_OFFSET) ?
+			EC_RFW_CFG_A_0_LRO_CONTEXT_SEL : 0;
+
+	reg_val |= (l4_sel == AL_ETH_L4_INNER_OUTER_CHK) ?
+			EC_RFW_CFG_A_0_META_L4_CHK_RES_SEL : 0;
+
+	reg_val |= l3_sel << EC_RFW_CFG_A_0_META_L3_CHK_RES_SEL_SHIFT;
+
+	al_reg_write32(&adapter->ec_regs_base->rfw.cfg_a_0, reg_val);
+
+	reg_val = al_reg_read32(&adapter->ec_regs_base->rfw.meta);
+	if (l3_proto_sel == AL_ETH_L3_PROTO_IDX_INNER)
+		reg_val |= EC_RFW_META_L3_PROT_SEL;
+	else
+		reg_val &= ~EC_RFW_META_L3_PROT_SEL;
+
+	if (l4_proto_sel == AL_ETH_L4_PROTO_IDX_INNER)
+		reg_val |= EC_RFW_META_L4_PROT_SEL;
+	else
+		reg_val &= ~EC_RFW_META_L4_PROT_SEL;
+
+	if (l4_offset_sel == AL_ETH_L4_OFFSET_INNER)
+		reg_val |= EC_RFW_META_L4_OFFSET_SEL;
+	else
+		reg_val &= ~EC_RFW_META_L4_OFFSET_SEL;
+
+	if (l3_offset_sel == AL_ETH_L3_OFFSET_INNER)
+		reg_val |= EC_RFW_META_L3_OFFSET_SEL;
+	else
+		reg_val &= ~EC_RFW_META_L3_OFFSET_SEL;
+
+	if (frag_sel == AL_ETH_FRAG_INNER)
+		reg_val |= EC_RFW_META_FRAG_SEL;
+	else
+		reg_val &= ~EC_RFW_META_FRAG_SEL;
+
+
+	al_reg_write32(&adapter->ec_regs_base->rfw.meta, reg_val);
+}
+
+/**
+ * Configure RX header split
+ */
+int al_eth_rx_header_split_config(struct al_hal_eth_adapter *adapter, al_bool enable, uint32_t header_len)
+{
+	uint32_t	reg;
+
+	if (adapter->rev_id < AL_ETH_REV_ID_1) {
+		al_err("[%s]: header split feature not supported by this revision\n", adapter->name);
+		return -EINVAL;
+	}
+	reg = al_reg_read32(&adapter->ec_regs_base->rfw.hdr_split);
+	if (enable == AL_TRUE)
+		reg |= EC_RFW_HDR_SPLIT_EN;
+	else
+		reg &= ~EC_RFW_HDR_SPLIT_EN;
+
+	AL_REG_FIELD_SET(reg, EC_RFW_HDR_SPLIT_DEF_LEN_MASK, EC_RFW_HDR_SPLIT_DEF_LEN_SHIFT, header_len);
+	al_reg_write32(&adapter->ec_regs_base->rfw.hdr_split, reg);
+	return 0;
+}
+
+
+/**
+ * enable / disable header split in the udma queue.
+ * length will be taken from the udma configuration to enable different length per queue.
+ */
+int al_eth_rx_header_split_force_len_config(struct al_hal_eth_adapter *adapter,
+					al_bool enable,
+					uint32_t qid,
+					uint32_t header_len)
+{
+	al_udma_s2m_q_compl_hdr_split_config(&(adapter->rx_udma.udma_q[qid]), enable,
+					     AL_TRUE, header_len);
+
+	return 0;
+}
+
+
+/**
+ * add buffer to receive queue
+ */
+int al_eth_rx_buffer_add(struct al_udma_q *rx_dma_q,
+			      struct al_buf *buf, uint32_t flags,
+			      struct al_buf *header_buf)
+{
+	uint64_t vmid = ((uint64_t)flags & AL_ETH_RX_FLAGS_VMID_MASK) <<
+		AL_UDMA_DESC_VMID_SHIFT;
+	uint32_t flags_len = flags & ~AL_ETH_RX_FLAGS_VMID_MASK;
+	union al_udma_desc *rx_desc;
+
+	al_dbg("[%s %d]: add rx buffer.\n", rx_dma_q->udma->name, rx_dma_q->qid);
+
+#if 1
+	if (unlikely(al_udma_available_get(rx_dma_q) < 1)) {
+		al_dbg("[%s]: rx q (%d) has no enough free descriptor",
+			 rx_dma_q->udma->name, rx_dma_q->qid);
+		return -ENOSPC;
+	}
+#endif
+	rx_desc = al_udma_desc_get(rx_dma_q);
+
+	flags_len |= al_udma_ring_id_get(rx_dma_q) << AL_S2M_DESC_RING_ID_SHIFT;
+	flags_len |= buf->len & AL_S2M_DESC_LEN_MASK;
+
+	if (flags & AL_S2M_DESC_DUAL_BUF) {
+		al_assert(header_buf != NULL); /*header valid in dual buf */
+		al_assert((rx_dma_q->udma->rev_id >= AL_UDMA_REV_ID_2) ||
+			(AL_ADDR_HIGH(buf->addr) == AL_ADDR_HIGH(header_buf->addr)));
+
+		flags_len |= ((header_buf->len >> AL_S2M_DESC_LEN2_GRANULARITY_SHIFT)
+			<< AL_S2M_DESC_LEN2_SHIFT) & AL_S2M_DESC_LEN2_MASK;
+		rx_desc->rx.buf2_ptr_lo = swap32_to_le(AL_ADDR_LOW(header_buf->addr));
+	}
+	rx_desc->rx.len_ctrl = swap32_to_le(flags_len);
+	rx_desc->rx.buf1_ptr = swap64_to_le(buf->addr | vmid);
+
+	return 0;
+}
+
+/**
+ * notify the hw engine about rx descriptors that were added to the receive queue
+ */
+void al_eth_rx_buffer_action(struct al_udma_q *rx_dma_q, uint32_t descs_num)
+{
+	al_dbg("[%s]: update the rx engine tail pointer: queue %d. descs %d\n",
+		 rx_dma_q->udma->name, rx_dma_q->qid, descs_num);
+
+	/* add rx descriptor */
+	al_udma_desc_action_add(rx_dma_q, descs_num);
+}
+
+/**
+ * get packet from RX completion ring
+ */
+uint32_t al_eth_pkt_rx(struct al_udma_q *rx_dma_q,
+			      struct al_eth_pkt *pkt)
+{
+	volatile union al_udma_cdesc *cdesc;
+	volatile al_eth_rx_cdesc *rx_desc;
+	uint32_t i;
+	uint32_t rc;
+
+	rc = al_udma_cdesc_packet_get(rx_dma_q, &cdesc);
+	if (rc == 0)
+		return 0;
+
+	al_assert(rc <= AL_ETH_PKT_MAX_BUFS);
+
+	al_dbg("[%s]: fetch rx packet: queue %d.\n",
+		 rx_dma_q->udma->name, rx_dma_q->qid);
+
+	pkt->rx_header_len = 0;
+	for (i = 0; i < rc; i++) {
+		uint32_t buf1_len, buf2_len;
+
+		/* get next descriptor */
+		rx_desc = (volatile al_eth_rx_cdesc *)al_cdesc_next(rx_dma_q, cdesc, i);
+
+		buf1_len = swap32_from_le(rx_desc->len);
+
+		if ((i == 0) && (swap32_from_le(rx_desc->word2) &
+			AL_UDMA_CDESC_BUF2_USED)) {
+			buf2_len = swap32_from_le(rx_desc->word2);
+			pkt->rx_header_len = (buf2_len & AL_S2M_DESC_LEN2_MASK) >>
+			AL_S2M_DESC_LEN2_SHIFT;
+			}
+		if ((swap32_from_le(rx_desc->ctrl_meta) & AL_UDMA_CDESC_BUF1_USED) &&
+			((swap32_from_le(rx_desc->ctrl_meta) & AL_UDMA_CDESC_DDP) == 0))
+			pkt->bufs[i].len = buf1_len & AL_S2M_DESC_LEN_MASK;
+		else
+			pkt->bufs[i].len = 0;
+	}
+	/* get flags from last desc */
+	pkt->flags = swap32_from_le(rx_desc->ctrl_meta);
+#ifdef AL_ETH_RX_DESC_RAW_GET
+	pkt->rx_desc_raw[0] = pkt->flags;
+	pkt->rx_desc_raw[1] = swap32_from_le(rx_desc->len);
+	pkt->rx_desc_raw[2] = swap32_from_le(rx_desc->word2);
+	pkt->rx_desc_raw[3] = swap32_from_le(rx_desc->word3);
+#endif
+	/* update L3/L4 proto index */
+	pkt->l3_proto_idx = pkt->flags & AL_ETH_RX_L3_PROTO_IDX_MASK;
+	pkt->l4_proto_idx = (pkt->flags >> AL_ETH_RX_L4_PROTO_IDX_SHIFT) &
+				AL_ETH_RX_L4_PROTO_IDX_MASK;
+	pkt->rxhash = (swap32_from_le(rx_desc->len) & AL_ETH_RX_HASH_MASK) >>
+			AL_ETH_RX_HASH_SHIFT;
+	pkt->l3_offset = (swap32_from_le(rx_desc->word2) & AL_ETH_RX_L3_OFFSET_MASK) >> AL_ETH_RX_L3_OFFSET_SHIFT;
+
+	al_udma_cdesc_ack(rx_dma_q, rc);
+	return rc;
+}
+
+
+int al_eth_rx_parser_entry_update(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_epe_p_reg_entry *reg_entry,
+		struct al_eth_epe_control_entry *control_entry)
+{
+	al_eth_epe_entry_set(adapter, idx, reg_entry, control_entry);
+	return 0;
+}
+
+#define AL_ETH_THASH_UDMA_SHIFT		0
+#define AL_ETH_THASH_UDMA_MASK		(0xF << AL_ETH_THASH_UDMA_SHIFT)
+
+#define AL_ETH_THASH_Q_SHIFT		4
+#define AL_ETH_THASH_Q_MASK		(0x3 << AL_ETH_THASH_Q_SHIFT)
+
+int al_eth_thash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma, uint32_t queue)
+{
+	uint32_t entry;
+	al_assert(idx < AL_ETH_RX_THASH_TABLE_SIZE); /*valid THASH index*/
+
+	entry = (udma << AL_ETH_THASH_UDMA_SHIFT) & AL_ETH_THASH_UDMA_MASK;
+	entry |= (queue << AL_ETH_THASH_Q_SHIFT) & AL_ETH_THASH_Q_MASK;
+
+	al_reg_write32(&adapter->ec_regs_base->rfw.thash_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->rfw.thash_table_data, entry);
+	return 0;
+}
+
+int al_eth_fsm_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry)
+{
+
+	al_assert(idx < AL_ETH_RX_FSM_TABLE_SIZE); /*valid FSM index*/
+
+
+	al_reg_write32(&adapter->ec_regs_base->rfw.fsm_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->rfw.fsm_table_data, entry);
+	return 0;
+}
+
+static uint32_t	al_eth_fwd_ctrl_entry_to_val(struct al_eth_fwd_ctrl_table_entry *entry)
+{
+	uint32_t val = 0;
+	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(3,0), 0, entry->prio_sel);
+	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(7,4), 4, entry->queue_sel_1);
+	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(9,8), 8, entry->queue_sel_2);
+	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(13,10), 10, entry->udma_sel);
+	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(17,15), 15, entry->hdr_split_len_sel);
+	if (entry->hdr_split_len_sel != AL_ETH_CTRL_TABLE_HDR_SPLIT_LEN_SEL_0)
+		val |= AL_BIT(18);
+	AL_REG_BIT_VAL_SET(val, 19, !!(entry->filter == AL_TRUE));
+
+	return val;
+}
+
+static int al_eth_ctrl_index_match(struct al_eth_fwd_ctrl_table_index *index, uint32_t i) {
+	if ((index->vlan_table_out != AL_ETH_FWD_CTRL_IDX_VLAN_TABLE_OUT_ANY)
+		&& (index->vlan_table_out != AL_REG_BIT_GET(i, 0)))
+		return 0;
+	if ((index->tunnel_exist != AL_ETH_FWD_CTRL_IDX_TUNNEL_ANY)
+		&& (index->tunnel_exist != AL_REG_BIT_GET(i, 1)))
+		return 0;
+	if ((index->vlan_exist != AL_ETH_FWD_CTRL_IDX_VLAN_ANY)
+		&& (index->vlan_exist != AL_REG_BIT_GET(i, 2)))
+		return 0;
+	if ((index->mac_table_match != AL_ETH_FWD_CTRL_IDX_MAC_TABLE_ANY)
+		&& (index->mac_table_match != AL_REG_BIT_GET(i, 3)))
+		return 0;
+	if ((index->protocol_id != AL_ETH_PROTO_ID_ANY)
+		&& (index->protocol_id != AL_REG_FIELD_GET(i, AL_FIELD_MASK(8,4),4)))
+		return 0;
+	if ((index->mac_type != AL_ETH_FWD_CTRL_IDX_MAC_DA_TYPE_ANY)
+		&& (index->mac_type != AL_REG_FIELD_GET(i, AL_FIELD_MASK(10,9),9)))
+		return 0;
+	return 1;
+}
+
+int al_eth_ctrl_table_set(struct al_hal_eth_adapter *adapter,
+			  struct al_eth_fwd_ctrl_table_index *index,
+			  struct al_eth_fwd_ctrl_table_entry *entry)
+{
+	uint32_t val = al_eth_fwd_ctrl_entry_to_val(entry);
+	uint32_t i;
+
+	for (i = 0; i < AL_ETH_RX_CTRL_TABLE_SIZE; i++) {
+		if (al_eth_ctrl_index_match(index, i)) {
+			al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_addr, i);
+			al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_data, val);
+		}
+	}
+	return 0;
+}
+
+int al_eth_ctrl_table_def_set(struct al_hal_eth_adapter *adapter,
+			      al_bool use_table,
+			      struct al_eth_fwd_ctrl_table_entry *entry)
+{
+	uint32_t val = al_eth_fwd_ctrl_entry_to_val(entry);
+
+	if (use_table)
+		val |= EC_RFW_CTRL_TABLE_DEF_SEL;
+
+	al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_def, val);
+
+	return 0;
+}
+
+int al_eth_ctrl_table_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t entry)
+{
+
+	al_assert(idx < AL_ETH_RX_CTRL_TABLE_SIZE); /* valid CTRL index */
+
+
+	al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_data, entry);
+	return 0;
+}
+
+int al_eth_ctrl_table_def_raw_set(struct al_hal_eth_adapter *adapter, uint32_t val)
+{
+	al_reg_write32(&adapter->ec_regs_base->rfw.ctrl_table_def, val);
+
+	return 0;
+}
+
+int al_eth_hash_key_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t val)
+{
+
+	al_assert(idx < AL_ETH_RX_HASH_KEY_NUM); /*valid CTRL index*/
+
+	al_reg_write32(&adapter->ec_regs_base->rfw_hash[idx].key, val);
+
+	return 0;
+}
+
+static uint32_t	al_eth_fwd_mac_table_entry_to_val(struct al_eth_fwd_mac_table_entry *entry)
+{
+	uint32_t val = 0;
+
+	val |= (entry->filter == AL_TRUE) ? EC_FWD_MAC_CTRL_RX_VAL_DROP : 0;
+	val |= ((entry->udma_mask << EC_FWD_MAC_CTRL_RX_VAL_UDMA_SHIFT) &
+					EC_FWD_MAC_CTRL_RX_VAL_UDMA_MASK);
+
+	val |= ((entry->qid << EC_FWD_MAC_CTRL_RX_VAL_QID_SHIFT) &
+					EC_FWD_MAC_CTRL_RX_VAL_QID_MASK);
+
+	val |= (entry->rx_valid == AL_TRUE) ? EC_FWD_MAC_CTRL_RX_VALID : 0;
+
+	val |= ((entry->tx_target << EC_FWD_MAC_CTRL_TX_VAL_SHIFT) &
+					EC_FWD_MAC_CTRL_TX_VAL_MASK);
+
+	val |= (entry->tx_valid == AL_TRUE) ? EC_FWD_MAC_CTRL_TX_VALID : 0;
+
+	return val;
+}
+
+int al_eth_fwd_mac_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+			     struct al_eth_fwd_mac_table_entry *entry)
+{
+	uint32_t val;
+
+	al_assert(idx < AL_ETH_FWD_MAC_NUM); /*valid FWD MAC index */
+
+	val = (entry->addr[2] << 24) | (entry->addr[3] << 16) |
+	      (entry->addr[4] << 8) | entry->addr[5];
+	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_l, val);
+	val = (entry->addr[0] << 8) | entry->addr[1];
+	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_h, val);
+	val = (entry->mask[2] << 24) | (entry->mask[3] << 16) |
+	      (entry->mask[4] << 8) | entry->mask[5];
+	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_l, val);
+	val = (entry->mask[0] << 8) | entry->mask[1];
+	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_h, val);
+
+	val = al_eth_fwd_mac_table_entry_to_val(entry);
+	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].ctrl, val);
+	return 0;
+}
+
+
+
+int al_eth_fwd_mac_addr_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t addr_lo, uint32_t addr_hi, uint32_t mask_lo, uint32_t mask_hi)
+{
+	al_assert(idx < AL_ETH_FWD_MAC_NUM); /*valid FWD MAC index */
+
+	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_l, addr_lo);
+	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].data_h, addr_hi);
+	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_l, mask_lo);
+	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].mask_h, mask_hi);
+
+	return 0;
+}
+
+int al_eth_fwd_mac_ctrl_raw_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint32_t ctrl)
+{
+	al_assert(idx < AL_ETH_FWD_MAC_NUM); /*valid FWD MAC index */
+
+	al_reg_write32(&adapter->ec_regs_base->fwd_mac[idx].ctrl, ctrl);
+
+	return 0;
+}
+
+int al_eth_mac_addr_store(void * __iomem ec_base, uint32_t idx, uint8_t *addr)
+{
+	struct al_ec_regs __iomem *ec_regs_base = (struct al_ec_regs __iomem*)ec_base;
+	uint32_t val;
+
+	al_assert(idx < AL_ETH_FWD_MAC_NUM); /*valid FWD MAC index */
+
+	val = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
+	al_reg_write32(&ec_regs_base->fwd_mac[idx].data_l, val);
+	val = (addr[0] << 8) | addr[1];
+	al_reg_write32(&ec_regs_base->fwd_mac[idx].data_h, val);
+	return 0;
+}
+
+int al_eth_mac_addr_read(void * __iomem ec_base, uint32_t idx, uint8_t *addr)
+{
+	struct al_ec_regs __iomem *ec_regs_base = (struct al_ec_regs __iomem*)ec_base;
+	uint32_t addr_lo = al_reg_read32(&ec_regs_base->fwd_mac[idx].data_l);
+	uint16_t addr_hi = al_reg_read32(&ec_regs_base->fwd_mac[idx].data_h);
+
+	addr[5] = addr_lo & 0xff;
+	addr[4] = (addr_lo >> 8) & 0xff;
+	addr[3] = (addr_lo >> 16) & 0xff;
+	addr[2] = (addr_lo >> 24) & 0xff;
+	addr[1] = addr_hi & 0xff;
+	addr[0] = (addr_hi >> 8) & 0xff;
+	return 0;
+}
+
+int al_eth_fwd_mhash_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t udma_mask, uint8_t qid)
+{
+	uint32_t val = 0;
+	al_assert(idx < AL_ETH_FWD_MAC_HASH_NUM); /* valid MHASH index */
+
+	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(3,0), 0, udma_mask);
+	AL_REG_FIELD_SET(val,  AL_FIELD_MASK(5,4), 4, qid);
+
+	al_reg_write32(&adapter->ec_regs_base->rfw.mhash_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->rfw.mhash_table_data, val);
+	return 0;
+}
+static uint32_t	al_eth_fwd_vid_entry_to_val(struct al_eth_fwd_vid_table_entry *entry)
+{
+	uint32_t val = 0;
+	AL_REG_BIT_VAL_SET(val, 0, entry->control);
+	AL_REG_BIT_VAL_SET(val, 1, entry->filter);
+	AL_REG_FIELD_SET(val, AL_FIELD_MASK(5,2), 2, entry->udma_mask);
+
+	return val;
+}
+
+int al_eth_fwd_vid_config_set(struct al_hal_eth_adapter *adapter, al_bool use_table,
+			      struct al_eth_fwd_vid_table_entry *default_entry,
+			      uint32_t default_vlan)
+{
+	uint32_t reg;
+
+	reg = al_eth_fwd_vid_entry_to_val(default_entry);
+	if (use_table)
+		reg |= EC_RFW_VID_TABLE_DEF_SEL;
+	else
+		reg &= ~EC_RFW_VID_TABLE_DEF_SEL;
+	al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_def, reg);
+	al_reg_write32(&adapter->ec_regs_base->rfw.default_vlan, default_vlan);
+
+	return 0;
+}
+
+int al_eth_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+			     struct al_eth_fwd_vid_table_entry *entry)
+{
+	uint32_t val;
+	al_assert(idx < AL_ETH_FWD_VID_TABLE_NUM); /* valid VID index */
+
+	val = al_eth_fwd_vid_entry_to_val(entry);
+	al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->rfw.vid_table_data, val);
+	return 0;
+}
+
+int al_eth_fwd_pbits_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio)
+{
+
+	al_assert(idx < AL_ETH_FWD_PBITS_TABLE_NUM); /* valid PBIT index */
+	al_assert(prio < AL_ETH_FWD_PRIO_TABLE_NUM); /* valid PRIO index */
+	al_reg_write32(&adapter->ec_regs_base->rfw.pbits_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->rfw.pbits_table_data, prio);
+	return 0;
+}
+
+int al_eth_fwd_priority_table_set(struct al_hal_eth_adapter *adapter, uint8_t prio, uint8_t qid)
+{
+	al_assert(prio < AL_ETH_FWD_PRIO_TABLE_NUM); /* valid PRIO index */
+
+	al_reg_write32(&adapter->ec_regs_base->rfw_priority[prio].queue, qid);
+	return 0;
+}
+
+
+int al_eth_fwd_dscp_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio)
+{
+
+	al_assert(idx < AL_ETH_FWD_DSCP_TABLE_NUM); /* valid DSCP index */
+
+
+	al_reg_write32(&adapter->ec_regs_base->rfw.dscp_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->rfw.dscp_table_data, prio);
+	return 0;
+}
+
+int al_eth_fwd_tc_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx, uint8_t prio)
+{
+
+	al_assert(idx < AL_ETH_FWD_TC_TABLE_NUM); /* valid TC index */
+
+
+	al_reg_write32(&adapter->ec_regs_base->rfw.tc_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->rfw.tc_table_data, prio);
+	return 0;
+}
+
+/** Configure default UDMA register */
+int al_eth_fwd_default_udma_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
+				   uint8_t udma_mask)
+{
+	al_reg_write32_masked(&adapter->ec_regs_base->rfw_default[idx].opt_1,
+			       EC_RFW_DEFAULT_OPT_1_UDMA_MASK,
+			       udma_mask << EC_RFW_DEFAULT_OPT_1_UDMA_SHIFT);
+	return 0;
+}
+
+/** Configure default queue register */
+int al_eth_fwd_default_queue_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
+				   uint8_t qid)
+{
+	al_reg_write32_masked(&adapter->ec_regs_base->rfw_default[idx].opt_1,
+			       EC_RFW_DEFAULT_OPT_1_QUEUE_MASK,
+			       qid << EC_RFW_DEFAULT_OPT_1_QUEUE_SHIFT);
+	return 0;
+}
+
+/** Configure default priority register */
+int al_eth_fwd_default_priority_config(struct al_hal_eth_adapter *adapter, uint32_t idx,
+				   uint8_t prio)
+{
+	al_reg_write32_masked(&adapter->ec_regs_base->rfw_default[idx].opt_1,
+			       EC_RFW_DEFAULT_OPT_1_PRIORITY_MASK,
+			       prio << EC_RFW_DEFAULT_OPT_1_PRIORITY_SHIFT);
+	return 0;
+}
+
+int al_eth_switching_config_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t forward_all_to_mac, uint8_t enable_int_switching,
+					enum al_eth_tx_switch_vid_sel_type vid_sel_type,
+					enum al_eth_tx_switch_dec_type uc_dec,
+					enum al_eth_tx_switch_dec_type mc_dec,
+					enum al_eth_tx_switch_dec_type bc_dec)
+{
+	uint32_t reg;
+
+	if (udma_id == 0) {
+		reg = al_reg_read32(&adapter->ec_regs_base->tfw.tx_gen);
+		if (forward_all_to_mac)
+			reg |= EC_TFW_TX_GEN_FWD_ALL_TO_MAC;
+		else
+			reg &= ~EC_TFW_TX_GEN_FWD_ALL_TO_MAC;
+		al_reg_write32(&adapter->ec_regs_base->tfw.tx_gen, reg);
+	}
+
+	reg = enable_int_switching;
+	reg |= (vid_sel_type & 7) << 1;
+	reg |= (bc_dec & 3) << 4;
+	reg |= (mc_dec & 3) << 6;
+	reg |= (uc_dec & 3) << 8;
+	al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].fwd_dec, reg);
+
+	return 0;
+}
+
+#define AL_ETH_RFW_FILTER_SUPPORTED(rev_id)	\
+	(AL_ETH_RFW_FILTER_UNDET_MAC | \
+	AL_ETH_RFW_FILTER_DET_MAC | \
+	AL_ETH_RFW_FILTER_TAGGED | \
+	AL_ETH_RFW_FILTER_UNTAGGED | \
+	AL_ETH_RFW_FILTER_BC | \
+	AL_ETH_RFW_FILTER_MC | \
+	AL_ETH_RFW_FILTER_VLAN_VID | \
+	AL_ETH_RFW_FILTER_CTRL_TABLE | \
+	AL_ETH_RFW_FILTER_PROT_INDEX | \
+	((rev_id > AL_ETH_REV_ID_0) ? ((AL_ETH_RFW_FILTER_WOL) | (AL_ETH_RFW_FILTER_PARSE)) : 0))
+
+/* Configure the receive filters */
+int al_eth_filter_config(struct al_hal_eth_adapter *adapter, struct al_eth_filter_params *params)
+{
+	uint32_t reg;
+
+	al_assert(params); /* valid params pointer */
+
+	if (params->filters & ~(AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id))) {
+		al_err("[%s]: unsupported filter options (0x%08x)\n", adapter->name, params->filters);
+		return -EINVAL;
+	}
+
+	reg = al_reg_read32(&adapter->ec_regs_base->rfw.out_cfg);
+	if (params->enable == AL_TRUE)
+		AL_REG_MASK_SET(reg, EC_RFW_OUT_CFG_DROP_EN);
+	else
+		AL_REG_MASK_CLEAR(reg, EC_RFW_OUT_CFG_DROP_EN);
+	al_reg_write32(&adapter->ec_regs_base->rfw.out_cfg, reg);
+
+	al_reg_write32_masked(
+		&adapter->ec_regs_base->rfw.filter,
+		AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id),
+		params->filters);
+	if (params->filters & AL_ETH_RFW_FILTER_PROT_INDEX) {
+		int i;
+		for (i = 0; i < AL_ETH_PROTOCOLS_NUM; i++) {
+			reg = al_reg_read32(&adapter->ec_regs_base->epe_a[i].prot_act);
+			if (params->filter_proto[i] == AL_TRUE)
+				AL_REG_MASK_SET(reg, EC_EPE_A_PROT_ACT_DROP);
+			else
+				AL_REG_MASK_CLEAR(reg, EC_EPE_A_PROT_ACT_DROP);
+			al_reg_write32(&adapter->ec_regs_base->epe_a[i].prot_act, reg);
+		}
+	}
+	return 0;
+}
+
+/* Configure the receive override filters */
+int al_eth_filter_override_config(struct al_hal_eth_adapter *adapter,
+				  struct al_eth_filter_override_params *params)
+{
+	uint32_t reg;
+
+	al_assert(params); /* valid params pointer */
+
+	if (params->filters & ~(AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id))) {
+		al_err("[%s]: unsupported override filter options (0x%08x)\n", adapter->name, params->filters);
+		return -EINVAL;
+	}
+
+	al_reg_write32_masked(
+		&adapter->ec_regs_base->rfw.filter,
+		AL_ETH_RFW_FILTER_SUPPORTED(adapter->rev_id) << 16,
+		params->filters << 16);
+
+	reg = al_reg_read32(&adapter->ec_regs_base->rfw.default_or);
+	AL_REG_FIELD_SET(reg, EC_RFW_DEFAULT_OR_UDMA_MASK, EC_RFW_DEFAULT_OR_UDMA_SHIFT, params->udma);
+	AL_REG_FIELD_SET(reg, EC_RFW_DEFAULT_OR_QUEUE_MASK, EC_RFW_DEFAULT_OR_QUEUE_SHIFT, params->qid);
+	al_reg_write32(&adapter->ec_regs_base->rfw.default_or, reg);
+	return 0;
+}
+
+
+
+int al_eth_switching_default_bitmap_set(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint8_t udma_uc_bitmask,
+						uint8_t udma_mc_bitmask,uint8_t udma_bc_bitmask)
+{
+	al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].uc_udma, udma_uc_bitmask);
+	al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].mc_udma, udma_mc_bitmask);
+	al_reg_write32(&adapter->ec_regs_base->tfw_udma[udma_id].bc_udma, udma_bc_bitmask);
+
+	return 0;
+}
+
+int al_eth_flow_control_config(struct al_hal_eth_adapter *adapter, struct al_eth_flow_control_params *params)
+{
+	uint32_t reg;
+	int i;
+	al_assert(params); /* valid params pointer */
+
+	switch(params->type){
+	case AL_ETH_FLOW_CONTROL_TYPE_LINK_PAUSE:
+		al_dbg("[%s]: config flow control to link pause mode.\n", adapter->name);
+
+		/* config the mac */
+		if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) {
+			/* set quanta value */
+			al_reg_write32(
+				&adapter->mac_regs_base->mac_1g.pause_quant,
+				params->quanta);
+			al_reg_write32(
+				&adapter->ec_regs_base->efc.xoff_timer_1g,
+				params->quanta_th);
+
+		} else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
+			/* set quanta value */
+			al_reg_write32(
+				&adapter->mac_regs_base->mac_10g.cl01_pause_quanta,
+				params->quanta);
+			/* set quanta threshold value */
+			al_reg_write32(
+				&adapter->mac_regs_base->mac_10g.cl01_quanta_thresh,
+				params->quanta_th);
+		} else {
+			/* set quanta value */
+			al_eth_40g_mac_reg_write(adapter,
+				ETH_MAC_GEN_V3_MAC_40G_CL01_PAUSE_QUANTA_ADDR,
+				params->quanta);
+			/* set quanta threshold value */
+			al_eth_40g_mac_reg_write(adapter,
+				ETH_MAC_GEN_V3_MAC_40G_CL01_QUANTA_THRESH_ADDR,
+				params->quanta_th);
+		}
+
+		if (params->obay_enable == AL_TRUE)
+			/* Tx path FIFO, unmask pause_on from MAC when PAUSE packet received */
+			al_reg_write32(&adapter->ec_regs_base->efc.ec_pause, 1);
+		else
+			al_reg_write32(&adapter->ec_regs_base->efc.ec_pause, 0);
+
+
+		/* Rx path */
+		if (params->gen_enable == AL_TRUE)
+			/* enable generating xoff from ec fifo almost full indication in hysteresis mode */
+			al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 1 << EC_EFC_EC_XOFF_MASK_2_SHIFT);
+		else
+			al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0);
+
+		if (AL_ETH_IS_1G_MAC(adapter->mac_mode))
+			/* in 1G mode, enable generating xon from ec fifo in hysteresis mode*/
+			al_reg_write32(&adapter->ec_regs_base->efc.xon, EC_EFC_XON_MASK_2 | EC_EFC_XON_MASK_1);
+
+		/* set hysteresis mode thresholds */
+		al_reg_write32(&adapter->ec_regs_base->efc.rx_fifo_hyst, params->rx_fifo_th_low | (params->rx_fifo_th_high << EC_EFC_RX_FIFO_HYST_TH_HIGH_SHIFT));
+
+		for (i = 0; i < 4; i++) {
+			if (params->obay_enable == AL_TRUE)
+				/* Tx path UDMA, unmask pause_on for all queues */
+				al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0,
+						params->prio_q_map[i][0]);
+			else
+				al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0, 0);
+
+			if (params->gen_enable == AL_TRUE)
+				/* Rx path UDMA, enable generating xoff from UDMA queue almost full indication */
+				al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0, params->prio_q_map[i][0]);
+			else
+				al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0, 0);
+		}
+	break;
+	case AL_ETH_FLOW_CONTROL_TYPE_PFC:
+		al_dbg("[%s]: config flow control to PFC mode.\n", adapter->name);
+		al_assert(!AL_ETH_IS_1G_MAC(adapter->mac_mode)); /* pfc not available for RGMII mode */;
+
+		for (i = 0; i < 4; i++) {
+			int prio;
+			for (prio = 0; prio < 8; prio++) {
+				if (params->obay_enable == AL_TRUE)
+					/* Tx path UDMA, unmask pause_on for all queues */
+					al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0 + prio,
+							params->prio_q_map[i][prio]);
+				else
+					al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_pause_0 + prio,
+							0);
+
+				if (params->gen_enable == AL_TRUE)
+					al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0 + prio,
+							params->prio_q_map[i][prio]);
+				else
+					al_reg_write32(&adapter->ec_regs_base->fc_udma[i].q_xoff_0 + prio,
+							0);
+			}
+		}
+
+		/* Rx path */
+		/* enable generating xoff from ec fifo almost full indication in hysteresis mode */
+		if (params->gen_enable == AL_TRUE)
+			al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0xFF << EC_EFC_EC_XOFF_MASK_2_SHIFT);
+		else
+			al_reg_write32(&adapter->ec_regs_base->efc.ec_xoff, 0);
+
+		/* set hysteresis mode thresholds */
+		al_reg_write32(&adapter->ec_regs_base->efc.rx_fifo_hyst, params->rx_fifo_th_low | (params->rx_fifo_th_high << EC_EFC_RX_FIFO_HYST_TH_HIGH_SHIFT));
+
+		if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
+			/* config the 10g_mac */
+			/* set quanta value (same value for all prios) */
+			reg = params->quanta | (params->quanta << 16);
+			al_reg_write32(
+				&adapter->mac_regs_base->mac_10g.cl01_pause_quanta, reg);
+			al_reg_write32(
+				&adapter->mac_regs_base->mac_10g.cl23_pause_quanta, reg);
+			al_reg_write32(
+				&adapter->mac_regs_base->mac_10g.cl45_pause_quanta, reg);
+			al_reg_write32(
+				&adapter->mac_regs_base->mac_10g.cl67_pause_quanta, reg);
+			/* set quanta threshold value (same value for all prios) */
+			reg = params->quanta_th | (params->quanta_th << 16);
+			al_reg_write32(
+				&adapter->mac_regs_base->mac_10g.cl01_quanta_thresh, reg);
+			al_reg_write32(
+				&adapter->mac_regs_base->mac_10g.cl23_quanta_thresh, reg);
+			al_reg_write32(
+				&adapter->mac_regs_base->mac_10g.cl45_quanta_thresh, reg);
+			al_reg_write32(
+				&adapter->mac_regs_base->mac_10g.cl67_quanta_thresh, reg);
+
+			/* enable PFC in the 10g_MAC */
+			reg = al_reg_read32(&adapter->mac_regs_base->mac_10g.cmd_cfg);
+			reg |= 1 << 19;
+			al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, reg);
+		} else {
+			/* config the 40g_mac */
+			/* set quanta value (same value for all prios) */
+			reg = params->quanta | (params->quanta << 16);
+			al_eth_40g_mac_reg_write(adapter,
+				ETH_MAC_GEN_V3_MAC_40G_CL01_PAUSE_QUANTA_ADDR, reg);
+			al_eth_40g_mac_reg_write(adapter,
+				ETH_MAC_GEN_V3_MAC_40G_CL23_PAUSE_QUANTA_ADDR, reg);
+			al_eth_40g_mac_reg_write(adapter,
+				ETH_MAC_GEN_V3_MAC_40G_CL45_PAUSE_QUANTA_ADDR, reg);
+			al_eth_40g_mac_reg_write(adapter,
+				ETH_MAC_GEN_V3_MAC_40G_CL67_PAUSE_QUANTA_ADDR, reg);
+			/* set quanta threshold value (same value for all prios) */
+			reg = params->quanta_th | (params->quanta_th << 16);
+			al_eth_40g_mac_reg_write(adapter,
+				ETH_MAC_GEN_V3_MAC_40G_CL01_QUANTA_THRESH_ADDR, reg);
+			al_eth_40g_mac_reg_write(adapter,
+				ETH_MAC_GEN_V3_MAC_40G_CL23_QUANTA_THRESH_ADDR, reg);
+			al_eth_40g_mac_reg_write(adapter,
+				ETH_MAC_GEN_V3_MAC_40G_CL45_QUANTA_THRESH_ADDR, reg);
+			al_eth_40g_mac_reg_write(adapter,
+				ETH_MAC_GEN_V3_MAC_40G_CL67_QUANTA_THRESH_ADDR, reg);
+
+			/* enable PFC in the 40g_MAC */
+			reg = al_reg_read32(&adapter->mac_regs_base->mac_10g.cmd_cfg);
+			reg |= 1 << 19;
+			al_reg_write32(&adapter->mac_regs_base->mac_10g.cmd_cfg, reg);
+			reg = al_eth_40g_mac_reg_read(adapter, ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR);
+
+			reg |= ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_PFC_MODE;
+
+			al_eth_40g_mac_reg_write(adapter, ETH_MAC_GEN_V3_MAC_40G_COMMAND_CONFIG_ADDR, reg);
+		}
+
+	break;
+	default:
+		al_err("[%s]: unsupported flow control type %d\n", adapter->name, params->type);
+		return -EINVAL;
+
+	}
+	return 0;
+}
+
+int al_eth_vlan_mod_config(struct al_hal_eth_adapter *adapter, uint8_t udma_id, uint16_t udma_etype, uint16_t vlan1_data, uint16_t vlan2_data)
+{
+	al_dbg("[%s]: config vlan modification registers. udma id %d.\n", adapter->name, udma_id);
+
+	al_reg_write32(&adapter->ec_regs_base->tpm_sel[udma_id].etype, udma_etype);
+	al_reg_write32(&adapter->ec_regs_base->tpm_udma[udma_id].vlan_data, vlan1_data | (vlan2_data << 16));
+
+	return 0;
+}
+
+int al_eth_eee_get(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params)
+{
+	uint32_t reg;
+
+	al_dbg("[%s]: getting eee.\n", adapter->name);
+
+	reg = al_reg_read32(&adapter->ec_regs_base->eee.cfg_e);
+	params->enable = (reg & EC_EEE_CFG_E_ENABLE) ? AL_TRUE : AL_FALSE;
+
+	params->tx_eee_timer = al_reg_read32(&adapter->ec_regs_base->eee.pre_cnt);
+	params->min_interval = al_reg_read32(&adapter->ec_regs_base->eee.post_cnt);
+	params->stop_cnt = al_reg_read32(&adapter->ec_regs_base->eee.stop_cnt);
+
+	return 0;
+}
+
+
+int al_eth_eee_config(struct al_hal_eth_adapter *adapter, struct al_eth_eee_params *params)
+{
+	uint32_t reg;
+	al_dbg("[%s]: config eee.\n", adapter->name);
+
+	if (params->enable == 0) {
+		al_dbg("[%s]: disable eee.\n", adapter->name);
+		al_reg_write32(&adapter->ec_regs_base->eee.cfg_e, 0);
+		return 0;
+	}
+	if (AL_ETH_IS_10G_MAC(adapter->mac_mode)) {
+		reg = ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL << ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_SHIFT;
+		al_reg_write32_masked(
+			&adapter->mac_regs_base->kr.pcs_cfg,
+			ETH_MAC_KR_PCS_CFG_EEE_TIMER_VAL_MASK, reg);
+	}
+
+	al_reg_write32(&adapter->ec_regs_base->eee.pre_cnt, params->tx_eee_timer);
+	al_reg_write32(&adapter->ec_regs_base->eee.post_cnt, params->min_interval);
+	al_reg_write32(&adapter->ec_regs_base->eee.stop_cnt, params->stop_cnt);
+
+	reg = EC_EEE_CFG_E_MASK_EC_TMI_STOP | EC_EEE_CFG_E_MASK_MAC_EEE |
+	       EC_EEE_CFG_E_ENABLE |
+	       EC_EEE_CFG_E_USE_EC_TX_FIFO | EC_EEE_CFG_E_USE_EC_RX_FIFO;
+
+	/*
+	 * Addressing RMN: 3732
+	 *
+	 * RMN description:
+	 * When the HW get into eee mode, it can't transmit any pause packet
+	 * (when flow control policy is enabled).
+	 * In such case, the HW has no way to handle extreme pushback from
+	 * the Rx_path fifos.
+	 *
+	 * Software flow:
+	 * Configure RX_FIFO empty as eee mode term.
+	 * That way, nothing will prevent pause packet transmittion in
+	 * case of extreme pushback from the Rx_path fifos.
+	 *
+	 */
+
+	al_reg_write32(&adapter->ec_regs_base->eee.cfg_e, reg);
+
+	return 0;
+}
+
+/* Timestamp */
+/* prepare the adapter for doing Timestamps for Rx packets. */
+int al_eth_ts_init(struct al_hal_eth_adapter *adapter)
+{
+	uint32_t reg;
+
+	/*TODO:
+	 * return error when:
+	 * - working in 1G mode and MACSEC enabled
+	 * - RX completion descriptor is not 8 words
+	 */
+	reg = al_reg_read32(&adapter->ec_regs_base->gen.en_ext);
+	if (AL_ETH_IS_1G_MAC(adapter->mac_mode))
+		reg &= ~EC_GEN_EN_EXT_PTH_1_10_SEL;
+	else
+		reg |= EC_GEN_EN_EXT_PTH_1_10_SEL;
+	/*
+	 * set completion bypass so tx timestamps won't be inserted to tx cmpl
+	 * (in order to disable unverified flow)
+	 */
+	reg |= EC_GEN_EN_EXT_PTH_COMPLETION_BYPASS;
+	al_reg_write32(&adapter->ec_regs_base->gen.en_ext, reg);
+
+	/*TODO: add the following when we have updated regs file:
+	 * reg_rfw_out_cfg_timestamp_sample_out
+		0 (default) – use the timestamp from the SOP info (10G MAC)
+		1 – use the timestamp from the EOP (1G MAC) (noly when MACSEC is disabled)
+	 */
+	return 0;
+}
+
+/* read Timestamp sample value of previously transmitted packet. */
+int al_eth_tx_ts_val_get(struct al_hal_eth_adapter *adapter, uint8_t ts_index,
+			 uint32_t *timestamp)
+{
+	al_assert(ts_index < AL_ETH_PTH_TX_SAMPLES_NUM);
+
+	/* in 1G mode, only indexes 1-7 are allowed*/
+	if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) {
+		al_assert(ts_index <= 7);
+		al_assert(ts_index >= 1);
+	}
+
+	/*TODO: check if sample is valid */
+	*timestamp = al_reg_read32(&adapter->ec_regs_base->pth_db[ts_index].ts);
+	return 0;
+}
+
+/* Read the systime value */
+int al_eth_pth_systime_read(struct al_hal_eth_adapter *adapter,
+			    struct al_eth_pth_time *systime)
+{
+	uint32_t reg;
+
+	/* first we must read the subseconds MSB so the seconds register will be
+	 * shadowed
+	 */
+	reg = al_reg_read32(&adapter->ec_regs_base->pth.system_time_subseconds_msb);
+	systime->femto = (uint64_t)reg << 18;
+	reg = al_reg_read32(&adapter->ec_regs_base->pth.system_time_seconds);
+	systime->seconds = reg;
+
+	return 0;
+}
+
+/* Set the clock period to a given value. */
+int al_eth_pth_clk_period_write(struct al_hal_eth_adapter *adapter,
+				uint64_t clk_period)
+{
+	uint32_t reg;
+	/* first write the LSB so it will be shadowed */
+	/* bits 31:14 of the clock period lsb register contains bits 17:0 of the
+	 * period.
+	 */
+	reg = (clk_period & AL_BIT_MASK(18)) << EC_PTH_CLOCK_PERIOD_LSB_VAL_SHIFT;
+	al_reg_write32(&adapter->ec_regs_base->pth.clock_period_lsb, reg);
+	reg = clk_period >> 18;
+	al_reg_write32(&adapter->ec_regs_base->pth.clock_period_msb, reg);
+
+	return 0;
+}
+
+/* Configure the systime internal update */
+int al_eth_pth_int_update_config(struct al_hal_eth_adapter *adapter,
+				 struct al_eth_pth_int_update_params *params)
+{
+	uint32_t reg;
+
+	reg = al_reg_read32(&adapter->ec_regs_base->pth.int_update_ctrl);
+	if (params->enable == AL_FALSE) {
+		reg &= ~EC_PTH_INT_UPDATE_CTRL_INT_TRIG_EN;
+	} else {
+		reg |= EC_PTH_INT_UPDATE_CTRL_INT_TRIG_EN;
+		AL_REG_FIELD_SET(reg, EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_MASK,
+				 EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_SHIFT,
+				 params->method);
+		if (params->trigger == AL_ETH_PTH_INT_TRIG_REG_WRITE)
+			reg |= EC_PTH_INT_UPDATE_CTRL_UPDATE_TRIG;
+		else
+			reg &= ~EC_PTH_INT_UPDATE_CTRL_UPDATE_TRIG;
+	}
+	al_reg_write32(&adapter->ec_regs_base->pth.int_update_ctrl, reg);
+	return 0;
+}
+/* set internal update time */
+int al_eth_pth_int_update_time_set(struct al_hal_eth_adapter *adapter,
+				   struct al_eth_pth_time *time)
+{
+	uint32_t reg;
+
+	al_reg_write32(&adapter->ec_regs_base->pth.int_update_seconds,
+		       time->seconds);
+	reg = time->femto & AL_BIT_MASK(18);
+	reg = reg << EC_PTH_INT_UPDATE_SUBSECONDS_LSB_VAL_SHIFT;
+	al_reg_write32(&adapter->ec_regs_base->pth.int_update_subseconds_lsb,
+		       reg);
+	reg = time->femto >> 18;
+	al_reg_write32(&adapter->ec_regs_base->pth.int_update_subseconds_msb,
+		       reg);
+
+	return 0;
+}
+
+/* Configure the systime external update */
+int al_eth_pth_ext_update_config(struct al_hal_eth_adapter *adapter,
+				 struct al_eth_pth_ext_update_params * params)
+{
+	uint32_t reg;
+
+	reg = al_reg_read32(&adapter->ec_regs_base->pth.int_update_ctrl);
+	AL_REG_FIELD_SET(reg, EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_MASK,
+			 EC_PTH_INT_UPDATE_CTRL_UPDATE_METHOD_SHIFT,
+			 params->method);
+
+	AL_REG_FIELD_SET(reg, EC_PTH_EXT_UPDATE_CTRL_EXT_TRIG_EN_MASK,
+			 EC_PTH_EXT_UPDATE_CTRL_EXT_TRIG_EN_SHIFT,
+			 params->triggers);
+	al_reg_write32(&adapter->ec_regs_base->pth.int_update_ctrl, reg);
+	return 0;
+}
+
+/* set external update time */
+int al_eth_pth_ext_update_time_set(struct al_hal_eth_adapter *adapter,
+				   struct al_eth_pth_time *time)
+{
+	uint32_t reg;
+
+	al_reg_write32(&adapter->ec_regs_base->pth.ext_update_seconds,
+		       time->seconds);
+	reg = time->femto & AL_BIT_MASK(18);
+	reg = reg << EC_PTH_EXT_UPDATE_SUBSECONDS_LSB_VAL_SHIFT;
+	al_reg_write32(&adapter->ec_regs_base->pth.ext_update_subseconds_lsb,
+		       reg);
+	reg = time->femto >> 18;
+	al_reg_write32(&adapter->ec_regs_base->pth.ext_update_subseconds_msb,
+		       reg);
+
+	return 0;
+};
+
+/* set the read compensation delay */
+int al_eth_pth_read_compensation_set(struct al_hal_eth_adapter *adapter,
+				     uint64_t subseconds)
+{
+	uint32_t reg;
+
+	/* first write to lsb to ensure atomicity */
+	reg = (subseconds & AL_BIT_MASK(18)) << EC_PTH_READ_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT;
+	al_reg_write32(&adapter->ec_regs_base->pth.read_compensation_subseconds_lsb, reg);
+
+	reg = subseconds >> 18;
+	al_reg_write32(&adapter->ec_regs_base->pth.read_compensation_subseconds_msb, reg);
+	return 0;
+}
+
+/* set the internal write compensation delay */
+int al_eth_pth_int_write_compensation_set(struct al_hal_eth_adapter *adapter,
+					  uint64_t subseconds)
+{
+	uint32_t reg;
+
+	/* first write to lsb to ensure atomicity */
+	reg = (subseconds & AL_BIT_MASK(18)) << EC_PTH_INT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT;
+	al_reg_write32(&adapter->ec_regs_base->pth.int_write_compensation_subseconds_lsb, reg);
+
+	reg = subseconds >> 18;
+	al_reg_write32(&adapter->ec_regs_base->pth.int_write_compensation_subseconds_msb, reg);
+	return 0;
+}
+
+/* set the external write compensation delay */
+int al_eth_pth_ext_write_compensation_set(struct al_hal_eth_adapter *adapter,
+					  uint64_t subseconds)
+{
+	uint32_t reg;
+
+	/* first write to lsb to ensure atomicity */
+	reg = (subseconds & AL_BIT_MASK(18)) << EC_PTH_EXT_WRITE_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT;
+	al_reg_write32(&adapter->ec_regs_base->pth.ext_write_compensation_subseconds_lsb, reg);
+
+	reg = subseconds >> 18;
+	al_reg_write32(&adapter->ec_regs_base->pth.ext_write_compensation_subseconds_msb, reg);
+	return 0;
+}
+
+/* set the sync compensation delay */
+int al_eth_pth_sync_compensation_set(struct al_hal_eth_adapter *adapter,
+				     uint64_t subseconds)
+{
+	uint32_t reg;
+
+	/* first write to lsb to ensure atomicity */
+	reg = (subseconds & AL_BIT_MASK(18)) << EC_PTH_SYNC_COMPENSATION_SUBSECONDS_LSB_VAL_SHIFT;
+	al_reg_write32(&adapter->ec_regs_base->pth.sync_compensation_subseconds_lsb, reg);
+
+	reg = subseconds >> 18;
+	al_reg_write32(&adapter->ec_regs_base->pth.sync_compensation_subseconds_msb, reg);
+	return 0;
+}
+
+/* Configure an output pulse */
+int al_eth_pth_pulse_out_config(struct al_hal_eth_adapter *adapter,
+				struct al_eth_pth_pulse_out_params *params)
+{
+	uint32_t reg;
+
+	if (params->index >= AL_ETH_PTH_PULSE_OUT_NUM) {
+		al_err("eth [%s] PTH out pulse index out of range\n",
+				 adapter->name);
+		return -EINVAL;
+	}
+	reg = al_reg_read32(&adapter->ec_regs_base->pth_egress[params->index].trigger_ctrl);
+	if (params->enable == AL_FALSE) {
+		reg &= ~EC_PTH_EGRESS_TRIGGER_CTRL_EN;
+	} else {
+		reg |= EC_PTH_EGRESS_TRIGGER_CTRL_EN;
+		if (params->periodic == AL_FALSE)
+			reg &= ~EC_PTH_EGRESS_TRIGGER_CTRL_PERIODIC;
+		else
+			reg |= EC_PTH_EGRESS_TRIGGER_CTRL_PERIODIC;
+
+		AL_REG_FIELD_SET(reg, EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SUBSEC_MASK,
+				 EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SUBSEC_SHIFT,
+				 params->period_us);
+		AL_REG_FIELD_SET(reg, EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SEC_MASK,
+				 EC_PTH_EGRESS_TRIGGER_CTRL_PERIOD_SEC_SHIFT,
+				 params->period_sec);
+	}
+	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_ctrl, reg);
+
+	/* set trigger time */
+	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_seconds,
+		       params->start_time.seconds);
+	reg = params->start_time.femto & AL_BIT_MASK(18);
+	reg = reg << EC_PTH_EGRESS_TRIGGER_SUBSECONDS_LSB_VAL_SHIFT;
+	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_subseconds_lsb,
+		       reg);
+	reg = params->start_time.femto >> 18;
+	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].trigger_subseconds_msb,
+		       reg);
+
+	/* set pulse width */
+	reg = params->pulse_width & AL_BIT_MASK(18);
+	reg = reg << EC_PTH_EGRESS_PULSE_WIDTH_SUBSECONDS_LSB_VAL_SHIFT;
+	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].pulse_width_subseconds_lsb, reg);
+
+	reg = params->pulse_width  >> 18;
+	al_reg_write32(&adapter->ec_regs_base->pth_egress[params->index].pulse_width_subseconds_msb, reg);
+
+	return 0;
+}
+
+/** get link status */
+int al_eth_link_status_get(struct al_hal_eth_adapter *adapter,
+			   struct al_eth_link_status *status)
+{
+	uint32_t reg;
+
+	if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
+		reg = al_reg_read32(&adapter->mac_regs_base->gen.mac_10g_stat);
+
+		status->link_up = AL_TRUE;
+
+		if (reg & (ETH_MAC_GEN_MAC_10G_STAT_LOC_FAULT |
+					ETH_MAC_GEN_MAC_10G_STAT_REM_FAULT))
+			status->link_up = AL_FALSE;
+
+	} else if (adapter->mac_mode == AL_ETH_MAC_MODE_SGMII) {
+		al_reg_write32(&adapter->mac_regs_base->sgmii.reg_addr, 1);
+		/*
+		 * This register is latched low so need to read twice to get
+		 * the current link status
+		 */
+		reg = al_reg_read32(&adapter->mac_regs_base->sgmii.reg_data);
+		reg = al_reg_read32(&adapter->mac_regs_base->sgmii.reg_data);
+
+		status->link_up = AL_FALSE;
+
+		if (reg & AL_BIT(2))
+			status->link_up = AL_TRUE;
+
+		reg = al_reg_read32(&adapter->mac_regs_base->sgmii.link_stat);
+
+		if ((reg & AL_BIT(3)) == 0)
+			status->link_up = AL_FALSE;
+
+	} else if (adapter->mac_mode == AL_ETH_MAC_MODE_RGMII) {
+		reg = al_reg_read32(&adapter->mac_regs_base->gen.rgmii_stat);
+
+		status->link_up = AL_FALSE;
+
+		if (reg & AL_BIT(4))
+			status->link_up = AL_TRUE;
+
+	} else if ((adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_40G) ||
+			(adapter->mac_mode == AL_ETH_MAC_MODE_XLG_LL_50G)) {
+		reg = al_reg_read32(&adapter->mac_regs_base->gen_v3.pcs_40g_ll_status);
+
+		status->link_up = AL_FALSE;
+
+		if ((reg & 0x1F) == 0x1F) {
+			reg = al_reg_read32(&adapter->mac_regs_base->gen_v3.mac_40g_ll_status);
+			if ((reg & (ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_REM_FAULT |
+ETH_MAC_GEN_V3_MAC_40G_LL_STATUS_LOC_FAULT)) == 0)
+				status->link_up = AL_TRUE;
+		}
+
+	} else {
+		/* not implemented yet */
+		return -EPERM;
+	}
+
+	al_dbg("[%s]: mac %s port. link_status: %s.\n", adapter->name,
+		al_eth_mac_mode_str(adapter->mac_mode),
+		(status->link_up == AL_TRUE) ? "LINK_UP" : "LINK_DOWN");
+
+	return 0;
+}
+
+/** set LED mode and value */
+int al_eth_led_set(struct al_hal_eth_adapter *adapter, al_bool link_is_up)
+{
+	uint32_t reg = 0;
+	uint32_t mode  = ETH_MAC_GEN_LED_CFG_SEL_DEFAULT_REG;
+
+	if (link_is_up)
+		mode = ETH_MAC_GEN_LED_CFG_SEL_LINK_ACTIVITY;
+
+	AL_REG_FIELD_SET(reg,  ETH_MAC_GEN_LED_CFG_SEL_MASK,
+			 ETH_MAC_GEN_LED_CFG_SEL_SHIFT, mode);
+
+	AL_REG_FIELD_SET(reg, ETH_MAC_GEN_LED_CFG_BLINK_TIMER_MASK,
+			 ETH_MAC_GEN_LED_CFG_BLINK_TIMER_SHIFT,
+			 ETH_MAC_GEN_LED_CFG_BLINK_TIMER_VAL);
+
+	AL_REG_FIELD_SET(reg, ETH_MAC_GEN_LED_CFG_ACT_TIMER_MASK,
+			 ETH_MAC_GEN_LED_CFG_ACT_TIMER_SHIFT,
+			 ETH_MAC_GEN_LED_CFG_ACT_TIMER_VAL);
+
+	al_reg_write32(&adapter->mac_regs_base->gen.led_cfg, reg);
+
+	return 0;
+}
+
+/* get statistics */
+int al_eth_mac_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_mac_stats *stats)
+{
+	al_assert(stats);
+
+	if (AL_ETH_IS_1G_MAC(adapter->mac_mode)) {
+		void __iomem *mac_1g_regs_base = &adapter->mac_regs_base->mac_1g;
+
+		stats->ifInUcastPkts = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x90));
+		stats->ifInMulticastPkts = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x94));
+		stats->ifInBroadcastPkts = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x98));
+		stats->etherStatsPkts = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xb4));
+		stats->ifOutUcastPkts = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xa0));
+		stats->ifOutMulticastPkts = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xa4));
+		stats->ifOutBroadcastPkts = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xa8));
+		stats->ifInErrors = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x88));
+		stats->ifOutErrors = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x8c));
+
+		stats->aFramesReceivedOK = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x6c));
+		stats->aFramesTransmittedOK = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x68));
+
+		stats->aOctetsReceivedOK = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x7c));
+		stats->aOctetsTransmittedOK = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x78));
+
+		stats->etherStatsUndersizePkts = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xB8));
+		stats->etherStatsFragments = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xE0));
+		stats->etherStatsJabbers = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xDC));
+		stats->etherStatsOversizePkts = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xBC));
+
+		stats->aFrameCheckSequenceErrors = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x70));
+		stats->aAlignmentErrors = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x74));
+		stats->etherStatsDropEvents = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xAC));
+
+		stats->aPAUSEMACCtrlFramesTransmitted = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x80));
+		stats->aPAUSEMACCtrlFramesReceived = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0x84));
+		stats->aFrameTooLongErrors = 0; /* N/A */
+		stats->aInRangeLengthErrors = 0; /* N/A */
+		stats->VLANTransmittedOK = 0; /* N/A */
+		stats->VLANReceivedOK = 0; /* N/A */
+		stats->etherStatsOctets = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xB0));
+
+		stats->etherStatsPkts64Octets = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xC0));
+		stats->etherStatsPkts65to127Octets = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xC4));
+		stats->etherStatsPkts128to255Octets = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xC8));
+		stats->etherStatsPkts256to511Octets = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xCC));
+		stats->etherStatsPkts512to1023Octets = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xD0));
+		stats->etherStatsPkts1024to1518Octets = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xD4));
+		stats->etherStatsPkts1519toX = al_reg_read32((void *)((uint32_t)mac_1g_regs_base + 0xD8));
+	} else if (AL_ETH_IS_10G_MAC(adapter->mac_mode) || AL_ETH_IS_25G_MAC(adapter->mac_mode)) {
+		if (adapter->rev_id < AL_ETH_REV_ID_3) {
+			void __iomem *mac_10g_regs_base = &adapter->mac_regs_base->mac_10g;
+			uint64_t octets;
+
+			stats->ifInUcastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xE0));
+			stats->ifInMulticastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xE8));
+			stats->ifInBroadcastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xF0));
+			stats->etherStatsPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x130));
+			stats->ifOutUcastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x108));
+			stats->ifOutMulticastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x110));
+			stats->ifOutBroadcastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x118));
+			stats->ifInErrors = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x190));
+			stats->ifOutErrors = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xf8));
+
+			stats->aFramesReceivedOK = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x88));
+			stats->aFramesTransmittedOK = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x80));
+			/* aOctetsReceivedOK = ifInOctets - 18 * aFramesReceivedOK - 4 * VLANReceivedOK */
+			octets = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xD8));
+			octets |= (uint64_t)(al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xDC))) << 32;
+			octets -= 18 * stats->aFramesReceivedOK;
+			octets -= 4 * al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xC8));
+			stats->aOctetsReceivedOK = octets;
+
+			/* aOctetsTransmittedOK = ifOutOctets - 18 * aFramesTransmittedOK - 4 * VLANTransmittedOK */
+			octets = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xD0));
+			octets |= (uint64_t)(al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xD4))) << 32;
+			octets -= 18 * stats->aFramesTransmittedOK;
+			octets -= 4 * al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xC0));
+			stats->aOctetsTransmittedOK = octets;
+
+			stats->etherStatsUndersizePkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x138));
+			stats->etherStatsFragments = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x188));
+			stats->etherStatsJabbers = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x180));
+			stats->etherStatsOversizePkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base  + 0x178));
+
+			stats->aFrameCheckSequenceErrors = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x90));
+			stats->aAlignmentErrors = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x98));
+			stats->etherStatsDropEvents = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x120));
+
+			stats->aPAUSEMACCtrlFramesTransmitted = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xA0));
+			stats->aPAUSEMACCtrlFramesReceived = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xA8));
+			stats->aFrameTooLongErrors = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xB0));
+			stats->aInRangeLengthErrors = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xB8));
+			stats->VLANTransmittedOK = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xC0));
+			stats->VLANReceivedOK = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0xC8));
+			stats->etherStatsOctets = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x128));
+
+			stats->etherStatsPkts64Octets = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x140));
+			stats->etherStatsPkts65to127Octets = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x148));
+			stats->etherStatsPkts128to255Octets = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x150));
+			stats->etherStatsPkts256to511Octets = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x158));
+			stats->etherStatsPkts512to1023Octets = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x160));
+			stats->etherStatsPkts1024to1518Octets = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x168));
+			stats->etherStatsPkts1519toX = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x170));
+		} else {
+			void __iomem *mac_10g_regs_base = &adapter->mac_regs_base->mac_10g;
+			uint64_t octets;
+			/* TODO - change to 64 bit */
+			stats->ifInUcastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x140));
+			stats->ifInMulticastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x148));
+			stats->ifInBroadcastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x150));
+			stats->etherStatsPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x160));
+			stats->ifOutUcastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x240));
+			stats->ifOutMulticastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x248));
+			stats->ifOutBroadcastPkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x250));
+			stats->ifInErrors = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x138));
+			stats->ifOutErrors = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x238));
+
+			stats->aFramesReceivedOK = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x120)); /*frames_ok*/
+			stats->aFramesTransmittedOK = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x220)); /*frames_ok*/
+			/* aOctetsReceivedOK = ifInOctets - 18 * aFramesReceivedOK - 4 * VLANReceivedOK */
+			octets = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x108)); /*OctetsOK*/
+			octets |= (uint64_t)(al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x10C))) << 32;
+			octets -= 18 * stats->aFramesReceivedOK;
+			octets -= 4 * al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x130)); /*VLANOK*/
+			stats->aOctetsReceivedOK = octets;
+
+			/* aOctetsTransmittedOK = ifOutOctets - 18 * aFramesTransmittedOK - 4 * VLANTransmittedOK */
+			octets = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x208)); /*OctetsOK*/
+			octets |= (uint64_t)(al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x20c))) << 32;
+			octets -= 18 * stats->aFramesTransmittedOK;
+			octets -= 4 * al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x230)); /*VLANOK*/
+			stats->aOctetsTransmittedOK = octets;
+
+			stats->etherStatsUndersizePkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x168));
+			stats->etherStatsFragments = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x1b8));
+			stats->etherStatsJabbers = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x1b0));
+			stats->etherStatsOversizePkts = al_reg_read32((void *)((uint32_t)mac_10g_regs_base  + 0x1a8));
+
+			stats->aFrameCheckSequenceErrors = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x128)); /* CRCErrors */
+			/* stats->aAlignmentErrors = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x98)); */ /* not implemented */
+			stats->etherStatsDropEvents = al_reg_read32((void *)((uint32_t)mac_10g_regs_base + 0x158));
+		}
+	} else {
+		uint64_t octets;
+		/* TODO - change to 64 bit */
+		stats->ifInUcastPkts = al_eth_40g_mac_reg_read(adapter, 0x140);
+		stats->ifInMulticastPkts = al_eth_40g_mac_reg_read(adapter, 0x148);
+		stats->ifInBroadcastPkts = al_eth_40g_mac_reg_read(adapter, 0x150);
+		stats->etherStatsPkts = al_eth_40g_mac_reg_read(adapter, 0x160);
+		stats->ifOutUcastPkts = al_eth_40g_mac_reg_read(adapter, 0x240);
+		stats->ifOutMulticastPkts = al_eth_40g_mac_reg_read(adapter, 0x248);
+		stats->ifOutBroadcastPkts = al_eth_40g_mac_reg_read(adapter, 0x250);
+		stats->ifInErrors = al_eth_40g_mac_reg_read(adapter, 0x138);
+		stats->ifOutErrors = al_eth_40g_mac_reg_read(adapter, 0x238);
+		stats->aFramesReceivedOK = al_eth_40g_mac_reg_read(adapter, 0x120);
+		stats->aFramesTransmittedOK = al_eth_40g_mac_reg_read(adapter, 0x220);
+
+		/* aOctetsReceivedOK = ifInOctets - 18 * aFramesReceivedOK - 4 * VLANReceivedOK */
+		octets = al_eth_40g_mac_reg_read(adapter, 0x100);
+		octets |= (uint64_t)(al_eth_40g_mac_reg_read(adapter, 0x104)) << 32;
+		octets -= 18 * stats->aFramesReceivedOK;
+		octets -= 4 * al_eth_40g_mac_reg_read(adapter, 0x130); /*VLANOK*/
+		stats->aOctetsTransmittedOK = octets;
+
+		/* aOctetsTransmittedOK = ifOutOctets - 18 * aFramesTransmittedOK - 4 * VLANTransmittedOK */
+		octets = al_eth_40g_mac_reg_read(adapter, 0x200);
+		octets |= (uint64_t)(al_eth_40g_mac_reg_read(adapter, 0x204)) << 32;
+		octets -= 18 * stats->aFramesReceivedOK;
+		octets -= 4 * al_eth_40g_mac_reg_read(adapter, 0x230); /*VLANOK*/
+		stats->aOctetsReceivedOK = octets;
+
+		stats->etherStatsUndersizePkts = al_eth_40g_mac_reg_read(adapter, 0x168);
+		stats->etherStatsFragments = al_eth_40g_mac_reg_read(adapter, 0x1b8);
+		stats->etherStatsJabbers = al_eth_40g_mac_reg_read(adapter, 0x1b0);
+		stats->etherStatsOversizePkts = al_eth_40g_mac_reg_read(adapter, 0x1a8);
+		stats->aFrameCheckSequenceErrors = al_eth_40g_mac_reg_read(adapter, 0x128);
+		stats->aAlignmentErrors = al_eth_40g_mac_reg_read(adapter, 0x110);
+		stats->etherStatsDropEvents = al_eth_40g_mac_reg_read(adapter, 0x158);
+	}
+
+	stats->eee_in = al_reg_read32(&adapter->mac_regs_base->stat.eee_in);
+	stats->eee_out = al_reg_read32(&adapter->mac_regs_base->stat.eee_out);
+
+/*	stats->etherStatsPkts = 1; */
+	return 0;
+}
+
+/**
+* read ec_stat_counters
+*/
+int al_eth_ec_stats_get(struct al_hal_eth_adapter *adapter, struct al_eth_ec_stats *stats)
+{
+	al_assert(stats);
+	stats->faf_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.faf_in_rx_pkt);
+	stats->faf_in_rx_short = al_reg_read32(&adapter->ec_regs_base->stat.faf_in_rx_short);
+	stats->faf_in_rx_long = al_reg_read32(&adapter->ec_regs_base->stat.faf_in_rx_long);
+	stats->faf_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_rx_pkt);
+	stats->faf_out_rx_short = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_rx_short);
+	stats->faf_out_rx_long = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_rx_long);
+	stats->faf_out_drop = al_reg_read32(&adapter->ec_regs_base->stat.faf_out_drop);
+	stats->rxf_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_in_rx_pkt);
+	stats->rxf_in_fifo_err = al_reg_read32(&adapter->ec_regs_base->stat.rxf_in_fifo_err);
+	stats->lbf_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.lbf_in_rx_pkt);
+	stats->lbf_in_fifo_err = al_reg_read32(&adapter->ec_regs_base->stat.lbf_in_fifo_err);
+	stats->rxf_out_rx_1_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_rx_1_pkt);
+	stats->rxf_out_rx_2_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_rx_2_pkt);
+	stats->rxf_out_drop_1_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_drop_1_pkt);
+	stats->rxf_out_drop_2_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rxf_out_drop_2_pkt);
+	stats->rpe_1_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_1_in_rx_pkt);
+	stats->rpe_1_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_1_out_rx_pkt);
+	stats->rpe_2_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_2_in_rx_pkt);
+	stats->rpe_2_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_2_out_rx_pkt);
+	stats->rpe_3_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_3_in_rx_pkt);
+	stats->rpe_3_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rpe_3_out_rx_pkt);
+	stats->tpe_in_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tpe_in_tx_pkt);
+	stats->tpe_out_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tpe_out_tx_pkt);
+	stats->tpm_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tpm_tx_pkt);
+	stats->tfw_in_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tfw_in_tx_pkt);
+	stats->tfw_out_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.tfw_out_tx_pkt);
+	stats->rfw_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_rx_pkt);
+	stats->rfw_in_vlan_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_vlan_drop);
+	stats->rfw_in_parse_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_parse_drop);
+	stats->rfw_in_mc = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_mc);
+	stats->rfw_in_bc = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_bc);
+	stats->rfw_in_vlan_exist = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_vlan_exist);
+	stats->rfw_in_vlan_nexist = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_vlan_nexist);
+	stats->rfw_in_mac_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_mac_drop);
+	stats->rfw_in_mac_ndet_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_mac_ndet_drop);
+	stats->rfw_in_ctrl_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_ctrl_drop);
+	stats->rfw_in_prot_i_drop = al_reg_read32(&adapter->ec_regs_base->stat.rfw_in_prot_i_drop);
+	stats->eee_in = al_reg_read32(&adapter->ec_regs_base->stat.eee_in);
+	return 0;
+}
+
+/**
+ * read per_udma_counters
+ */
+int al_eth_ec_stat_udma_get(struct al_hal_eth_adapter *adapter, uint8_t idx, struct al_eth_ec_stat_udma *stats)
+{
+
+	al_assert(idx <= 3); /*valid udma_id*/
+	al_assert(stats);
+	stats->rfw_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].rfw_out_rx_pkt);
+	stats->rfw_out_drop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].rfw_out_drop);
+	stats->msw_in_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_in_rx_pkt);
+	stats->msw_drop_q_full = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_drop_q_full);
+	stats->msw_drop_sop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_drop_sop);
+	stats->msw_drop_eop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_drop_eop);
+	stats->msw_wr_eop = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_wr_eop);
+	stats->msw_out_rx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].msw_out_rx_pkt);
+	stats->tso_no_tso_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_no_tso_pkt);
+	stats->tso_tso_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_tso_pkt);
+	stats->tso_seg_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_seg_pkt);
+	stats->tso_pad_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tso_pad_pkt);
+	stats->tpm_tx_spoof = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tpm_tx_spoof);
+	stats->tmi_in_tx_pkt = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tmi_in_tx_pkt);
+	stats->tmi_out_to_mac = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tmi_out_to_mac);
+	stats->tmi_out_to_rx = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tmi_out_to_rx);
+	stats->tx_q0_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q0_bytes);
+	stats->tx_q1_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q1_bytes);
+	stats->tx_q2_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q2_bytes);
+	stats->tx_q3_bytes = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q3_bytes);
+	stats->tx_q0_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q0_pkts);
+	stats->tx_q1_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q1_pkts);
+	stats->tx_q2_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q2_pkts);
+	stats->tx_q3_pkts = al_reg_read32(&adapter->ec_regs_base->stat_udma[idx].tx_q3_pkts);
+	return 0;
+}
+
+/* Traffic control */
+
+
+int al_eth_flr_rmn(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val),
+		   int (* pci_write_config_u32)(void *handle, int where, uint32_t val),
+		   void *handle,
+		   void __iomem	*mac_base)
+{
+	struct al_eth_mac_regs __iomem *mac_regs_base =
+		(struct	al_eth_mac_regs __iomem *)mac_base;
+	uint32_t cfg_reg_store[6];
+	uint32_t reg;
+	uint32_t mux_sel;
+	int i = 0;
+
+	(*pci_read_config_u32)(handle, AL_ADAPTER_GENERIC_CONTROL_0, &reg);
+
+	/* reset 1G mac */
+	AL_REG_MASK_SET(reg, AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC);
+	(*pci_write_config_u32)(handle, AL_ADAPTER_GENERIC_CONTROL_0, reg);
+	al_udelay(1000);
+	/* don't reset 1G mac */
+	AL_REG_MASK_CLEAR(reg, AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC);
+	/* prevent 1G mac reset on FLR */
+	AL_REG_MASK_CLEAR(reg, AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC_ON_FLR);
+	/* prevent adapter reset */
+	(*pci_write_config_u32)(handle, AL_ADAPTER_GENERIC_CONTROL_0, reg);
+
+	mux_sel = al_reg_read32(&mac_regs_base->gen.mux_sel);
+
+	/* save pci register that get reset due to flr*/
+	(*pci_read_config_u32)(handle, AL_PCI_COMMAND, &cfg_reg_store[i++]);
+	(*pci_read_config_u32)(handle, 0xC, &cfg_reg_store[i++]);
+	(*pci_read_config_u32)(handle, 0x10, &cfg_reg_store[i++]);
+	(*pci_read_config_u32)(handle, 0x18, &cfg_reg_store[i++]);
+	(*pci_read_config_u32)(handle, 0x20, &cfg_reg_store[i++]);
+	(*pci_read_config_u32)(handle, 0x110, &cfg_reg_store[i++]);
+
+	/* do flr */
+	(*pci_write_config_u32)(handle, AL_PCI_EXP_CAP_BASE + AL_PCI_EXP_DEVCTL, AL_PCI_EXP_DEVCTL_BCR_FLR);
+	al_udelay(1000);
+	/* restore command */
+	i = 0;
+	(*pci_write_config_u32)(handle, AL_PCI_COMMAND, cfg_reg_store[i++]);
+	(*pci_write_config_u32)(handle, 0xC, cfg_reg_store[i++]);
+	(*pci_write_config_u32)(handle, 0x10, cfg_reg_store[i++]);
+	(*pci_write_config_u32)(handle, 0x18, cfg_reg_store[i++]);
+	(*pci_write_config_u32)(handle, 0x20, cfg_reg_store[i++]);
+	(*pci_write_config_u32)(handle, 0x110, cfg_reg_store[i++]);
+
+	al_reg_write32_masked(&mac_regs_base->gen.mux_sel, ETH_MAC_GEN_MUX_SEL_KR_IN_MASK, mux_sel);
+
+	/* set SGMII clock to 125MHz */
+	al_reg_write32(mac_base + 0xB08, 0x03320501);
+
+	/* reset 1G mac */
+	AL_REG_MASK_SET(reg, AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC);
+	(*pci_write_config_u32)(handle, AL_ADAPTER_GENERIC_CONTROL_0, reg);
+
+	al_udelay(1000);
+
+	/* clear 1G mac reset */
+	AL_REG_MASK_CLEAR(reg, AL_ADAPTER_GENERIC_CONTROL_0_ETH_RESET_1GMAC);
+	(*pci_write_config_u32)(handle, AL_ADAPTER_GENERIC_CONTROL_0, reg);
+
+	/* reset SGMII mac clock to default */
+	al_reg_write32(mac_base + 0xB08, 0x00320501);
+	al_udelay(1000);
+	/* reset async fifo */
+	reg = al_reg_read32((void*)((uint32_t)mac_base + 0x95c));
+	AL_REG_MASK_SET(reg, 0xF0);
+	al_reg_write32((void*)((uint32_t)mac_base + 0x95c), reg);
+	reg = al_reg_read32((void*)((uint32_t)mac_base + 0x95c));
+	AL_REG_MASK_CLEAR(reg, 0xF0);
+	al_reg_write32((void*)((uint32_t)mac_base + 0x95c), reg);
+
+	return 0;
+}
+
+int al_eth_flr_rmn_restore_params(int (* pci_read_config_u32)(void *handle, int where, uint32_t *val),
+		int (* pci_write_config_u32)(void *handle, int where, uint32_t val),
+		void *handle,
+		void __iomem    *mac_base,
+		void __iomem    *ec_base,
+		int     mac_addresses_num
+		)
+{
+	struct al_eth_board_params params = { .media_type = 0 };
+	uint8_t mac_addr[6];
+	int rc;
+
+	/* not implemented yet */
+	if (mac_addresses_num > 1)
+		return -EPERM;
+
+	/* save board params so we restore it after reset */
+	al_eth_board_params_get(mac_base, &params);
+	al_eth_mac_addr_read(ec_base, 0, mac_addr);
+
+	rc = al_eth_flr_rmn(pci_read_config_u32, pci_write_config_u32, handle, mac_base);
+	al_eth_board_params_set(mac_base, &params);
+	al_eth_mac_addr_store(ec_base, 0, mac_addr);
+
+	return rc;
+}
+
+/* board params register 1 */
+#define AL_HAL_ETH_MEDIA_TYPE_MASK	(AL_FIELD_MASK(3, 0))
+#define AL_HAL_ETH_MEDIA_TYPE_SHIFT	0
+#define AL_HAL_ETH_EXT_PHY_SHIFT	4
+#define AL_HAL_ETH_PHY_ADDR_MASK	(AL_FIELD_MASK(9, 5))
+#define AL_HAL_ETH_PHY_ADDR_SHIFT	5
+#define AL_HAL_ETH_SFP_EXIST_SHIFT	10
+#define AL_HAL_ETH_AN_ENABLE_SHIFT	11
+#define AL_HAL_ETH_KR_LT_ENABLE_SHIFT	12
+#define AL_HAL_ETH_KR_FEC_ENABLE_SHIFT	13
+#define AL_HAL_ETH_MDIO_FREQ_MASK	(AL_FIELD_MASK(15, 14))
+#define AL_HAL_ETH_MDIO_FREQ_SHIFT	14
+#define AL_HAL_ETH_I2C_ADAPTER_ID_MASK	(AL_FIELD_MASK(19, 16))
+#define AL_HAL_ETH_I2C_ADAPTER_ID_SHIFT	16
+#define AL_HAL_ETH_EXT_PHY_IF_MASK	(AL_FIELD_MASK(21, 20))
+#define AL_HAL_ETH_EXT_PHY_IF_SHIFT	20
+#define AL_HAL_ETH_AUTO_NEG_MODE_SHIFT	22
+#define AL_HAL_ETH_SERDES_GRP_MASK	(AL_FIELD_MASK(26, 25))
+#define AL_HAL_ETH_SERDES_GRP_SHIFT	25
+#define AL_HAL_ETH_SERDES_LANE_MASK	(AL_FIELD_MASK(28, 27))
+#define AL_HAL_ETH_SERDES_LANE_SHIFT	27
+#define AL_HAL_ETH_REF_CLK_FREQ_MASK	(AL_FIELD_MASK(31, 29))
+#define AL_HAL_ETH_REF_CLK_FREQ_SHIFT	29
+
+/* board params register 2 */
+#define AL_HAL_ETH_DONT_OVERRIDE_SERDES_SHIFT	0
+#define AL_HAL_ETH_1000_BASE_X_SHIFT		1
+#define AL_HAL_ETH_1G_AN_DISABLE_SHIFT		2
+#define AL_HAL_ETH_1G_SPEED_MASK		(AL_FIELD_MASK(4, 3))
+#define AL_HAL_ETH_1G_SPEED_SHIFT		3
+#define AL_HAL_ETH_1G_HALF_DUPLEX_SHIFT		5
+#define AL_HAL_ETH_1G_FC_DISABLE_SHIFT		6
+#define AL_HAL_ETH_RETIMER_EXIST_SHIFT		7
+#define AL_HAL_ETH_RETIMER_BUS_ID_MASK		(AL_FIELD_MASK(11, 8))
+#define AL_HAL_ETH_RETIMER_BUS_ID_SHIFT		8
+#define AL_HAL_ETH_RETIMER_I2C_ADDR_MASK	(AL_FIELD_MASK(18, 12))
+#define AL_HAL_ETH_RETIMER_I2C_ADDR_SHIFT	12
+#define AL_HAL_ETH_RETIMER_CHANNEL_SHIFT	19
+#define AL_HAL_ETH_DAC_LENGTH_MASK		(AL_FIELD_MASK(23, 20))
+#define AL_HAL_ETH_DAC_LENGTH_SHIFT		20
+#define AL_HAL_ETH_DAC_SHIFT			24
+#define AL_HAL_ETH_RETIMER_TYPE_MASK		(AL_FIELD_MASK(26, 25))
+#define AL_HAL_ETH_RETIMER_TYPE_SHIFT		25
+#define AL_HAL_ETH_RETIMER_CHANNEL_2_SHIFT	27
+
+int al_eth_board_params_set(void * __iomem mac_base, struct al_eth_board_params *params){
+	uint32_t	reg = 0;
+
+	/* ************* Setting Board params register 1 **************** */
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_MEDIA_TYPE_MASK,
+			 AL_HAL_ETH_MEDIA_TYPE_SHIFT, params->media_type);
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_EXT_PHY_SHIFT, params->phy_exist == AL_TRUE);
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_PHY_ADDR_MASK,
+			 AL_HAL_ETH_PHY_ADDR_SHIFT, params->phy_mdio_addr);
+
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_SFP_EXIST_SHIFT, params->sfp_plus_module_exist == AL_TRUE);
+
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_AN_ENABLE_SHIFT, params->autoneg_enable == AL_TRUE);
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_KR_LT_ENABLE_SHIFT, params->kr_lt_enable == AL_TRUE);
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_KR_FEC_ENABLE_SHIFT, params->kr_fec_enable == AL_TRUE);
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_MDIO_FREQ_MASK,
+			 AL_HAL_ETH_MDIO_FREQ_SHIFT, params->mdio_freq);
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_I2C_ADAPTER_ID_MASK,
+			 AL_HAL_ETH_I2C_ADAPTER_ID_SHIFT, params->i2c_adapter_id);
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_EXT_PHY_IF_MASK,
+			 AL_HAL_ETH_EXT_PHY_IF_SHIFT, params->phy_if);
+
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_AUTO_NEG_MODE_SHIFT,
+			   params->an_mode == AL_ETH_BOARD_AUTONEG_IN_BAND);
+
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_SERDES_GRP_MASK,
+			 AL_HAL_ETH_SERDES_GRP_SHIFT, params->serdes_grp);
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_SERDES_LANE_MASK,
+			 AL_HAL_ETH_SERDES_LANE_SHIFT, params->serdes_lane);
+
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_REF_CLK_FREQ_MASK,
+			 AL_HAL_ETH_REF_CLK_FREQ_SHIFT, params->ref_clk_freq);
+
+	al_assert(reg != 0);
+
+	al_reg_write32(mac_base + 0x4, reg);
+
+	/* ************* Setting Board params register 2 **************** */
+	reg = 0;
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_DONT_OVERRIDE_SERDES_SHIFT,
+			   params->dont_override_serdes == AL_TRUE);
+
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_1000_BASE_X_SHIFT,
+			   params->force_1000_base_x == AL_TRUE);
+
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_1G_AN_DISABLE_SHIFT,
+			   params->an_disable == AL_TRUE);
+
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_1G_SPEED_MASK,
+			 AL_HAL_ETH_1G_SPEED_SHIFT, params->speed);
+
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_1G_HALF_DUPLEX_SHIFT,
+			   params->half_duplex == AL_TRUE);
+
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_1G_FC_DISABLE_SHIFT,
+			   params->fc_disable == AL_TRUE);
+
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_RETIMER_EXIST_SHIFT, params->retimer_exist == AL_TRUE);
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_BUS_ID_MASK,
+			 AL_HAL_ETH_RETIMER_BUS_ID_SHIFT, params->retimer_bus_id);
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_I2C_ADDR_MASK,
+			 AL_HAL_ETH_RETIMER_I2C_ADDR_SHIFT, params->retimer_i2c_addr);
+
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_RETIMER_CHANNEL_SHIFT,
+				((params->retimer_channel == AL_ETH_RETIMER_CHANNEL_B) ||
+				 (params->retimer_channel == AL_ETH_RETIMER_CHANNEL_D)));
+
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_RETIMER_CHANNEL_2_SHIFT,
+				((params->retimer_channel == AL_ETH_RETIMER_CHANNEL_C) ||
+				 (params->retimer_channel == AL_ETH_RETIMER_CHANNEL_D)));
+
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_DAC_LENGTH_MASK,
+			 AL_HAL_ETH_DAC_LENGTH_SHIFT, params->dac_len);
+	AL_REG_BIT_VAL_SET(reg, AL_HAL_ETH_DAC_SHIFT, params->dac);
+
+	AL_REG_FIELD_SET(reg, AL_HAL_ETH_RETIMER_TYPE_MASK,
+			 AL_HAL_ETH_RETIMER_TYPE_SHIFT, params->retimer_type);
+
+	al_reg_write32(mac_base + 0x404, reg);
+	return 0;
+}
+
+int al_eth_board_params_get(void * __iomem mac_base, struct al_eth_board_params *params){
+	uint32_t	reg = al_reg_read32((void*)((uint32_t)mac_base + 0x4));
+
+	/* check if the register was initialized, 0 is not a valid value */
+	if (reg == 0)
+		return -ENOENT;
+
+	/* ************* Getting Board params register 1 **************** */
+	params->media_type = AL_REG_FIELD_GET(reg, AL_HAL_ETH_MEDIA_TYPE_MASK,
+					      AL_HAL_ETH_MEDIA_TYPE_SHIFT);
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_EXT_PHY_SHIFT))
+		params->phy_exist = AL_TRUE;
+	else
+		params->phy_exist = AL_FALSE;
+
+	params->phy_mdio_addr = AL_REG_FIELD_GET(reg, AL_HAL_ETH_PHY_ADDR_MASK,
+						 AL_HAL_ETH_PHY_ADDR_SHIFT);
+
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_SFP_EXIST_SHIFT))
+		params->sfp_plus_module_exist = AL_TRUE;
+	else
+		params->sfp_plus_module_exist = AL_FALSE;
+
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_AN_ENABLE_SHIFT))
+		params->autoneg_enable = AL_TRUE;
+	else
+		params->autoneg_enable = AL_FALSE;
+
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_KR_LT_ENABLE_SHIFT))
+		params->kr_lt_enable = AL_TRUE;
+	else
+		params->kr_lt_enable = AL_FALSE;
+
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_KR_FEC_ENABLE_SHIFT))
+		params->kr_fec_enable = AL_TRUE;
+	else
+		params->kr_fec_enable = AL_FALSE;
+
+	params->mdio_freq = AL_REG_FIELD_GET(reg,
+					     AL_HAL_ETH_MDIO_FREQ_MASK,
+					     AL_HAL_ETH_MDIO_FREQ_SHIFT);
+
+	params->i2c_adapter_id = AL_REG_FIELD_GET(reg,
+						  AL_HAL_ETH_I2C_ADAPTER_ID_MASK,
+						  AL_HAL_ETH_I2C_ADAPTER_ID_SHIFT);
+
+	params->phy_if = AL_REG_FIELD_GET(reg,
+					  AL_HAL_ETH_EXT_PHY_IF_MASK,
+					  AL_HAL_ETH_EXT_PHY_IF_SHIFT);
+
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_AUTO_NEG_MODE_SHIFT))
+		params->an_mode = AL_TRUE;
+	else
+		params->an_mode = AL_FALSE;
+
+	params->serdes_grp = AL_REG_FIELD_GET(reg,
+					      AL_HAL_ETH_SERDES_GRP_MASK,
+					      AL_HAL_ETH_SERDES_GRP_SHIFT);
+
+	params->serdes_lane = AL_REG_FIELD_GET(reg,
+					       AL_HAL_ETH_SERDES_LANE_MASK,
+					       AL_HAL_ETH_SERDES_LANE_SHIFT);
+
+	params->ref_clk_freq = AL_REG_FIELD_GET(reg,
+						AL_HAL_ETH_REF_CLK_FREQ_MASK,
+						AL_HAL_ETH_REF_CLK_FREQ_SHIFT);
+
+	/* ************* Getting Board params register 2 **************** */
+	reg = al_reg_read32((void*)((uint32_t)mac_base + 0x404));
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_DONT_OVERRIDE_SERDES_SHIFT))
+		params->dont_override_serdes = AL_TRUE;
+	else
+		params->dont_override_serdes = AL_FALSE;
+
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_1000_BASE_X_SHIFT))
+		params->force_1000_base_x = AL_TRUE;
+	else
+		params->force_1000_base_x = AL_FALSE;
+
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_1G_AN_DISABLE_SHIFT))
+		params->an_disable = AL_TRUE;
+	else
+		params->an_disable = AL_FALSE;
+
+	params->speed = AL_REG_FIELD_GET(reg,
+					 AL_HAL_ETH_1G_SPEED_MASK,
+					 AL_HAL_ETH_1G_SPEED_SHIFT);
+
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_1G_HALF_DUPLEX_SHIFT))
+		params->half_duplex = AL_TRUE;
+	else
+		params->half_duplex = AL_FALSE;
+
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_1G_FC_DISABLE_SHIFT))
+		params->fc_disable = AL_TRUE;
+	else
+		params->fc_disable = AL_FALSE;
+
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_RETIMER_EXIST_SHIFT))
+		params->retimer_exist = AL_TRUE;
+	else
+		params->retimer_exist = AL_FALSE;
+
+	params->retimer_bus_id = AL_REG_FIELD_GET(reg,
+					       AL_HAL_ETH_RETIMER_BUS_ID_MASK,
+					       AL_HAL_ETH_RETIMER_BUS_ID_SHIFT);
+	params->retimer_i2c_addr = AL_REG_FIELD_GET(reg,
+					       AL_HAL_ETH_RETIMER_I2C_ADDR_MASK,
+					       AL_HAL_ETH_RETIMER_I2C_ADDR_SHIFT);
+
+	params->retimer_channel =
+		((AL_REG_BIT_GET(reg, AL_HAL_ETH_RETIMER_CHANNEL_SHIFT)) |
+		 (AL_REG_BIT_GET(reg, AL_HAL_ETH_RETIMER_CHANNEL_2_SHIFT) << 1));
+
+	params->dac_len = AL_REG_FIELD_GET(reg,
+					   AL_HAL_ETH_DAC_LENGTH_MASK,
+					   AL_HAL_ETH_DAC_LENGTH_SHIFT);
+
+	if (AL_REG_BIT_GET(reg, AL_HAL_ETH_DAC_SHIFT))
+		params->dac = AL_TRUE;
+	else
+		params->dac = AL_FALSE;
+
+	params->retimer_type = AL_REG_FIELD_GET(reg,
+					   AL_HAL_ETH_RETIMER_TYPE_MASK,
+					   AL_HAL_ETH_RETIMER_TYPE_SHIFT);
+
+	return 0;
+}
+
+/* Wake-On-Lan (WoL) */
+static inline void al_eth_byte_arr_to_reg(
+		uint32_t *reg, uint8_t *arr, unsigned int num_bytes)
+{
+	uint32_t mask = 0xff;
+	unsigned int i;
+
+	al_assert(num_bytes <= 4);
+
+	*reg = 0;
+
+	for (i = 0 ; i < num_bytes ; i++) {
+		AL_REG_FIELD_SET(*reg, mask, (sizeof(uint8_t) * i), arr[i]);
+		mask = mask << sizeof(uint8_t);
+	}
+}
+
+int al_eth_wol_enable(
+		struct al_hal_eth_adapter *adapter,
+		struct al_eth_wol_params *wol)
+{
+	uint32_t reg = 0;
+
+	if (wol->int_mask & AL_ETH_WOL_INT_MAGIC_PSWD) {
+		al_assert(wol->pswd != NULL);
+
+		al_eth_byte_arr_to_reg(&reg, &wol->pswd[0], 4);
+		al_reg_write32(&adapter->ec_regs_base->wol.magic_pswd_l, reg);
+
+		al_eth_byte_arr_to_reg(&reg, &wol->pswd[4], 2);
+		al_reg_write32(&adapter->ec_regs_base->wol.magic_pswd_h, reg);
+	}
+
+	if (wol->int_mask & AL_ETH_WOL_INT_IPV4) {
+		al_assert(wol->ipv4 != NULL);
+
+		al_eth_byte_arr_to_reg(&reg, &wol->ipv4[0], 4);
+		al_reg_write32(&adapter->ec_regs_base->wol.ipv4_dip, reg);
+	}
+
+	if (wol->int_mask & AL_ETH_WOL_INT_IPV6) {
+		al_assert(wol->ipv6 != NULL);
+
+		al_eth_byte_arr_to_reg(&reg, &wol->ipv6[0], 4);
+		al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word0, reg);
+
+		al_eth_byte_arr_to_reg(&reg, &wol->ipv6[4], 4);
+		al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word1, reg);
+
+		al_eth_byte_arr_to_reg(&reg, &wol->ipv6[8], 4);
+		al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word2, reg);
+
+		al_eth_byte_arr_to_reg(&reg, &wol->ipv6[12], 4);
+		al_reg_write32(&adapter->ec_regs_base->wol.ipv6_dip_word3, reg);
+	}
+
+	if (wol->int_mask &
+		(AL_ETH_WOL_INT_ETHERTYPE_BC | AL_ETH_WOL_INT_ETHERTYPE_DA)) {
+
+		reg = ((uint32_t)wol->ethr_type2 << 16);
+		reg |= wol->ethr_type1;
+
+		al_reg_write32(&adapter->ec_regs_base->wol.ethertype, reg);
+	}
+
+	/* make sure we dont forwarding packets without interrupt */
+	al_assert((wol->forward_mask | wol->int_mask) == wol->int_mask);
+
+	reg = ((uint32_t)wol->forward_mask << 16);
+	reg |= wol->int_mask;
+	al_reg_write32(&adapter->ec_regs_base->wol.wol_en, reg);
+
+	return 0;
+}
+
+int al_eth_wol_disable(
+		struct al_hal_eth_adapter *adapter)
+{
+	al_reg_write32(&adapter->ec_regs_base->wol.wol_en, 0);
+
+	return 0;
+}
+
+int al_eth_tx_fwd_vid_table_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+				uint8_t udma_mask, al_bool fwd_to_mac)
+{
+	uint32_t	val = 0;
+	al_assert(idx < AL_ETH_FWD_VID_TABLE_NUM); /* valid VID index */
+	AL_REG_FIELD_SET(val,  AL_ETH_TX_VLAN_TABLE_UDMA_MASK, 0, udma_mask);
+	AL_REG_FIELD_SET(val,  AL_ETH_TX_VLAN_TABLE_FWD_TO_MAC, 4, fwd_to_mac);
+
+	al_reg_write32(&adapter->ec_regs_base->tfw.tx_vid_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->tfw.tx_vid_table_data, val);
+	return 0;
+}
+
+int al_eth_tx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_tx_gpd_cam_entry *tx_gpd_entry)
+{
+	uint64_t gpd_data;
+	uint64_t gpd_mask;
+
+	gpd_data = ((uint64_t)tx_gpd_entry->l3_proto_idx & AL_ETH_TX_GPD_L3_PROTO_MASK) <<
+		AL_ETH_TX_GPD_L3_PROTO_SHIFT;
+	gpd_data |= ((uint64_t)tx_gpd_entry->l4_proto_idx & AL_ETH_TX_GPD_L4_PROTO_MASK) <<
+		AL_ETH_TX_GPD_L4_PROTO_SHIFT;
+	gpd_data |= ((uint64_t)tx_gpd_entry->tunnel_control & AL_ETH_TX_GPD_TUNNEL_CTRL_MASK) <<
+		AL_ETH_TX_GPD_TUNNEL_CTRL_SHIFT;
+	gpd_data |= ((uint64_t)tx_gpd_entry->source_vlan_count & AL_ETH_TX_GPD_SRC_VLAN_CNT_MASK) <<
+		AL_ETH_TX_GPD_SRC_VLAN_CNT_SHIFT;
+	gpd_mask  = ((uint64_t)tx_gpd_entry->l3_proto_idx_mask & AL_ETH_TX_GPD_L3_PROTO_MASK) <<
+		AL_ETH_TX_GPD_L3_PROTO_SHIFT;
+	gpd_mask |= ((uint64_t)tx_gpd_entry->l4_proto_idx_mask & AL_ETH_TX_GPD_L4_PROTO_MASK) <<
+		AL_ETH_TX_GPD_L4_PROTO_SHIFT;
+	gpd_mask |= ((uint64_t)tx_gpd_entry->tunnel_control_mask & AL_ETH_TX_GPD_TUNNEL_CTRL_MASK) <<
+		AL_ETH_TX_GPD_TUNNEL_CTRL_SHIFT;
+	gpd_mask |= ((uint64_t)tx_gpd_entry->source_vlan_count_mask & AL_ETH_TX_GPD_SRC_VLAN_CNT_MASK) <<
+		AL_ETH_TX_GPD_SRC_VLAN_CNT_SHIFT;
+
+	/* Tx Generic protocol detect Cam compare table */
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_ctrl,
+			(uint32_t)((tx_gpd_entry->tx_gpd_cam_ctrl) << AL_ETH_TX_GPD_CAM_CTRL_VALID_SHIFT));
+	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], tx_gpd_cam_ctrl: %#x", idx, tx_gpd_entry->tx_gpd_cam_ctrl);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_mask_2,
+			(uint32_t)(gpd_mask >> AL_ETH_TX_GPD_CAM_MASK_2_SHIFT));
+	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], tx_gpd_cam_mask_2: %#x", idx, (uint32_t)(gpd_mask >> AL_ETH_TX_GPD_CAM_MASK_2_SHIFT));
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_mask_1,
+			(uint32_t)(gpd_mask));
+	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], tx_gpd_cam_mask_1: %#x", idx, (uint32_t)(gpd_mask));
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_data_2,
+			(uint32_t)(gpd_data >> AL_ETH_TX_GPD_CAM_DATA_2_SHIFT));
+	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], tx_gpd_cam_data_2: %#x", idx, (uint32_t)(gpd_data >> AL_ETH_TX_GPD_CAM_DATA_2_SHIFT));
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gpd_cam_data_1,
+			(uint32_t)(gpd_data));
+	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], tx_gpd_cam_data_1: %#x", idx, (uint32_t)(gpd_data));
+	return 0;
+}
+
+int al_eth_tx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_tx_gcp_table_entry *tx_gcp_entry)
+{
+	uint32_t gcp_table_gen;
+	uint32_t tx_alu_opcode;
+	uint32_t tx_alu_opsel;
+
+	gcp_table_gen  = (tx_gcp_entry->poly_sel & AL_ETH_TX_GCP_POLY_SEL_MASK) <<
+		AL_ETH_TX_GCP_POLY_SEL_SHIFT;
+	gcp_table_gen |= (tx_gcp_entry->crc32_bit_comp & AL_ETH_TX_GCP_CRC32_BIT_COMP_MASK) <<
+		AL_ETH_TX_GCP_CRC32_BIT_COMP_SHIFT;
+	gcp_table_gen |= (tx_gcp_entry->crc32_bit_swap & AL_ETH_TX_GCP_CRC32_BIT_SWAP_MASK) <<
+		AL_ETH_TX_GCP_CRC32_BIT_SWAP_SHIFT;
+	gcp_table_gen |= (tx_gcp_entry->crc32_byte_swap & AL_ETH_TX_GCP_CRC32_BYTE_SWAP_MASK) <<
+		AL_ETH_TX_GCP_CRC32_BYTE_SWAP_SHIFT;
+	gcp_table_gen |= (tx_gcp_entry->data_bit_swap & AL_ETH_TX_GCP_DATA_BIT_SWAP_MASK) <<
+		AL_ETH_TX_GCP_DATA_BIT_SWAP_SHIFT;
+	gcp_table_gen |= (tx_gcp_entry->data_byte_swap & AL_ETH_TX_GCP_DATA_BYTE_SWAP_MASK) <<
+		AL_ETH_TX_GCP_DATA_BYTE_SWAP_SHIFT;
+	gcp_table_gen |= (tx_gcp_entry->trail_size & AL_ETH_TX_GCP_TRAIL_SIZE_MASK) <<
+		AL_ETH_TX_GCP_TRAIL_SIZE_SHIFT;
+	gcp_table_gen |= (tx_gcp_entry->head_size & AL_ETH_TX_GCP_HEAD_SIZE_MASK) <<
+		AL_ETH_TX_GCP_HEAD_SIZE_SHIFT;
+	gcp_table_gen |= (tx_gcp_entry->head_calc & AL_ETH_TX_GCP_HEAD_CALC_MASK) <<
+		AL_ETH_TX_GCP_HEAD_CALC_SHIFT;
+	gcp_table_gen |= (tx_gcp_entry->mask_polarity & AL_ETH_TX_GCP_MASK_POLARITY_MASK) <<
+		AL_ETH_TX_GCP_MASK_POLARITY_SHIFT;
+	al_dbg("al_eth_tx_generic_crc_entry_set, line [%d], gcp_table_gen: %#x", idx, gcp_table_gen);
+
+	tx_alu_opcode  = (tx_gcp_entry->tx_alu_opcode_1 & AL_ETH_TX_GCP_OPCODE_1_MASK) <<
+		AL_ETH_TX_GCP_OPCODE_1_SHIFT;
+	tx_alu_opcode |= (tx_gcp_entry->tx_alu_opcode_2 & AL_ETH_TX_GCP_OPCODE_2_MASK) <<
+		AL_ETH_TX_GCP_OPCODE_2_SHIFT;
+	tx_alu_opcode |= (tx_gcp_entry->tx_alu_opcode_3 & AL_ETH_TX_GCP_OPCODE_3_MASK) <<
+		AL_ETH_TX_GCP_OPCODE_3_SHIFT;
+	tx_alu_opsel  = (tx_gcp_entry->tx_alu_opsel_1 & AL_ETH_TX_GCP_OPSEL_1_MASK) <<
+		AL_ETH_TX_GCP_OPSEL_1_SHIFT;
+	tx_alu_opsel |= (tx_gcp_entry->tx_alu_opsel_2 & AL_ETH_TX_GCP_OPSEL_2_MASK) <<
+		AL_ETH_TX_GCP_OPSEL_2_SHIFT;
+	tx_alu_opsel |= (tx_gcp_entry->tx_alu_opsel_3 & AL_ETH_TX_GCP_OPSEL_3_MASK) <<
+		AL_ETH_TX_GCP_OPSEL_3_SHIFT;
+	tx_alu_opsel |= (tx_gcp_entry->tx_alu_opsel_4 & AL_ETH_TX_GCP_OPSEL_4_MASK) <<
+		AL_ETH_TX_GCP_OPSEL_4_SHIFT;
+
+	/*  Tx Generic crc prameters table general */
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_gen,
+			gcp_table_gen);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_1,
+			tx_gcp_entry->gcp_mask[0]);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_2,
+			tx_gcp_entry->gcp_mask[1]);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_3,
+			tx_gcp_entry->gcp_mask[2]);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_4,
+			tx_gcp_entry->gcp_mask[3]);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_5,
+			tx_gcp_entry->gcp_mask[4]);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_mask_6,
+			tx_gcp_entry->gcp_mask[5]);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_crc_init,
+			tx_gcp_entry->crc_init);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_res,
+			tx_gcp_entry->gcp_table_res);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_alu_opcode,
+			tx_alu_opcode);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_alu_opsel,
+			tx_alu_opsel);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_table_alu_val,
+			tx_gcp_entry->alu_val);
+	return 0;
+}
+
+int al_eth_tx_crc_chksum_replace_cmd_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry *tx_replace_entry)
+{
+	uint32_t replace_table_address;
+	uint32_t tx_replace_cmd;
+
+	/*  Tx crc_chksum_replace_cmd */
+	replace_table_address = L4_CHECKSUM_DIS_AND_L3_CHECKSUM_DIS | idx;
+	tx_replace_cmd  = (uint32_t)(tx_replace_entry->l3_csum_en_00) << 0;
+	tx_replace_cmd |= (uint32_t)(tx_replace_entry->l4_csum_en_00) << 1;
+	tx_replace_cmd |= (uint32_t)(tx_replace_entry->crc_en_00)     << 2;
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table,
+			tx_replace_cmd);
+	replace_table_address = L4_CHECKSUM_DIS_AND_L3_CHECKSUM_EN | idx;
+	tx_replace_cmd  = (uint32_t)(tx_replace_entry->l3_csum_en_01) << 0;
+	tx_replace_cmd |= (uint32_t)(tx_replace_entry->l4_csum_en_01) << 1;
+	tx_replace_cmd |= (uint32_t)(tx_replace_entry->crc_en_01)     << 2;
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table,
+			tx_replace_cmd);
+	replace_table_address = L4_CHECKSUM_EN_AND_L3_CHECKSUM_DIS | idx;
+	tx_replace_cmd  = (uint32_t)(tx_replace_entry->l3_csum_en_10) << 0;
+	tx_replace_cmd |= (uint32_t)(tx_replace_entry->l4_csum_en_10) << 1;
+	tx_replace_cmd |= (uint32_t)(tx_replace_entry->crc_en_10)     << 2;
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table,
+			tx_replace_cmd);
+	replace_table_address = L4_CHECKSUM_EN_AND_L3_CHECKSUM_EN | idx;
+	tx_replace_cmd  = (uint32_t)(tx_replace_entry->l3_csum_en_11) << 0;
+	tx_replace_cmd |= (uint32_t)(tx_replace_entry->l4_csum_en_11) << 1;
+	tx_replace_cmd |= (uint32_t)(tx_replace_entry->crc_en_11)     << 2;
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table_addr, replace_table_address);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace_table,
+			tx_replace_cmd);
+
+	return 0;
+}
+
+int al_eth_rx_protocol_detect_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_rx_gpd_cam_entry *rx_gpd_entry)
+{
+	uint64_t gpd_data;
+	uint64_t gpd_mask;
+
+	gpd_data  = ((uint64_t)rx_gpd_entry->outer_l3_proto_idx & AL_ETH_RX_GPD_OUTER_L3_PROTO_MASK) <<
+		AL_ETH_RX_GPD_OUTER_L3_PROTO_SHIFT;
+	gpd_data |= ((uint64_t)rx_gpd_entry->outer_l4_proto_idx & AL_ETH_RX_GPD_OUTER_L4_PROTO_MASK) <<
+		AL_ETH_RX_GPD_OUTER_L4_PROTO_SHIFT;
+	gpd_data |= ((uint64_t)rx_gpd_entry->inner_l3_proto_idx & AL_ETH_RX_GPD_INNER_L3_PROTO_MASK) <<
+		AL_ETH_RX_GPD_INNER_L3_PROTO_SHIFT;
+	gpd_data |= ((uint64_t)rx_gpd_entry->inner_l4_proto_idx & AL_ETH_RX_GPD_INNER_L4_PROTO_MASK) <<
+		AL_ETH_RX_GPD_INNER_L4_PROTO_SHIFT;
+	gpd_data |= ((uint64_t)rx_gpd_entry->parse_ctrl & AL_ETH_RX_GPD_OUTER_PARSE_CTRL_MASK) <<
+		AL_ETH_RX_GPD_OUTER_PARSE_CTRL_SHIFT;
+	gpd_data |= ((uint64_t)rx_gpd_entry->outer_l3_len & AL_ETH_RX_GPD_INNER_PARSE_CTRL_MASK) <<
+		AL_ETH_RX_GPD_INNER_PARSE_CTRL_SHIFT;
+	gpd_data |= ((uint64_t)rx_gpd_entry->l3_priority & AL_ETH_RX_GPD_L3_PRIORITY_MASK) <<
+		AL_ETH_RX_GPD_L3_PRIORITY_SHIFT;
+	gpd_data |= ((uint64_t)rx_gpd_entry->l4_dst_port_lsb & AL_ETH_RX_GPD_L4_DST_PORT_LSB_MASK) <<
+		AL_ETH_RX_GPD_L4_DST_PORT_LSB_SHIFT;
+
+	gpd_mask  = ((uint64_t)rx_gpd_entry->outer_l3_proto_idx_mask & AL_ETH_RX_GPD_OUTER_L3_PROTO_MASK) <<
+		AL_ETH_RX_GPD_OUTER_L3_PROTO_SHIFT;
+	gpd_mask |= ((uint64_t)rx_gpd_entry->outer_l4_proto_idx_mask & AL_ETH_RX_GPD_OUTER_L4_PROTO_MASK) <<
+		AL_ETH_RX_GPD_OUTER_L4_PROTO_SHIFT;
+	gpd_mask |= ((uint64_t)rx_gpd_entry->inner_l3_proto_idx_mask & AL_ETH_RX_GPD_INNER_L3_PROTO_MASK) <<
+		AL_ETH_RX_GPD_INNER_L3_PROTO_SHIFT;
+	gpd_mask |= ((uint64_t)rx_gpd_entry->inner_l4_proto_idx_mask & AL_ETH_RX_GPD_INNER_L4_PROTO_MASK) <<
+		AL_ETH_RX_GPD_INNER_L4_PROTO_SHIFT;
+	gpd_mask |= ((uint64_t)rx_gpd_entry->parse_ctrl_mask & AL_ETH_RX_GPD_OUTER_PARSE_CTRL_MASK) <<
+		AL_ETH_RX_GPD_OUTER_PARSE_CTRL_SHIFT;
+	gpd_mask |= ((uint64_t)rx_gpd_entry->outer_l3_len_mask & AL_ETH_RX_GPD_INNER_PARSE_CTRL_MASK) <<
+		AL_ETH_RX_GPD_INNER_PARSE_CTRL_SHIFT;
+	gpd_mask |= ((uint64_t)rx_gpd_entry->l3_priority_mask & AL_ETH_RX_GPD_L3_PRIORITY_MASK) <<
+		AL_ETH_RX_GPD_L3_PRIORITY_SHIFT;
+	gpd_mask |= ((uint64_t)rx_gpd_entry->l4_dst_port_lsb_mask & AL_ETH_RX_GPD_L4_DST_PORT_LSB_MASK) <<
+		AL_ETH_RX_GPD_L4_DST_PORT_LSB_SHIFT;
+
+	/* Rx Generic protocol detect Cam compare table */
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_ctrl,
+			(uint32_t)((rx_gpd_entry->rx_gpd_cam_ctrl) << AL_ETH_RX_GPD_CAM_CTRL_VALID_SHIFT));
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_mask_2,
+			(uint32_t)(gpd_mask >> AL_ETH_RX_GPD_CAM_MASK_2_SHIFT));
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_mask_1,
+			(uint32_t)(gpd_mask));
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_data_2,
+			(uint32_t)(gpd_data >> AL_ETH_RX_GPD_CAM_DATA_2_SHIFT));
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gpd_cam_data_1,
+			(uint32_t)(gpd_data));
+	return 0;
+}
+
+int al_eth_rx_generic_crc_table_entry_set(struct al_hal_eth_adapter *adapter, uint32_t idx,
+		struct al_eth_rx_gcp_table_entry *rx_gcp_entry)
+{
+	uint32_t gcp_table_gen;
+	uint32_t rx_alu_opcode;
+	uint32_t rx_alu_opsel;
+
+	gcp_table_gen  = (rx_gcp_entry->poly_sel & AL_ETH_RX_GCP_POLY_SEL_MASK) <<
+		AL_ETH_RX_GCP_POLY_SEL_SHIFT;
+	gcp_table_gen |= (rx_gcp_entry->crc32_bit_comp & AL_ETH_RX_GCP_CRC32_BIT_COMP_MASK) <<
+		AL_ETH_RX_GCP_CRC32_BIT_COMP_SHIFT;
+	gcp_table_gen |= (rx_gcp_entry->crc32_bit_swap & AL_ETH_RX_GCP_CRC32_BIT_SWAP_MASK) <<
+		AL_ETH_RX_GCP_CRC32_BIT_SWAP_SHIFT;
+	gcp_table_gen |= (rx_gcp_entry->crc32_byte_swap & AL_ETH_RX_GCP_CRC32_BYTE_SWAP_MASK) <<
+		AL_ETH_RX_GCP_CRC32_BYTE_SWAP_SHIFT;
+	gcp_table_gen |= (rx_gcp_entry->data_bit_swap & AL_ETH_RX_GCP_DATA_BIT_SWAP_MASK) <<
+		AL_ETH_RX_GCP_DATA_BIT_SWAP_SHIFT;
+	gcp_table_gen |= (rx_gcp_entry->data_byte_swap & AL_ETH_RX_GCP_DATA_BYTE_SWAP_MASK) <<
+		AL_ETH_RX_GCP_DATA_BYTE_SWAP_SHIFT;
+	gcp_table_gen |= (rx_gcp_entry->trail_size & AL_ETH_RX_GCP_TRAIL_SIZE_MASK) <<
+		AL_ETH_RX_GCP_TRAIL_SIZE_SHIFT;
+	gcp_table_gen |= (rx_gcp_entry->head_size & AL_ETH_RX_GCP_HEAD_SIZE_MASK) <<
+		AL_ETH_RX_GCP_HEAD_SIZE_SHIFT;
+	gcp_table_gen |= (rx_gcp_entry->head_calc & AL_ETH_RX_GCP_HEAD_CALC_MASK) <<
+		AL_ETH_RX_GCP_HEAD_CALC_SHIFT;
+	gcp_table_gen |= (rx_gcp_entry->mask_polarity & AL_ETH_RX_GCP_MASK_POLARITY_MASK) <<
+		AL_ETH_RX_GCP_MASK_POLARITY_SHIFT;
+
+	rx_alu_opcode  = (rx_gcp_entry->rx_alu_opcode_1 & AL_ETH_RX_GCP_OPCODE_1_MASK) <<
+		AL_ETH_RX_GCP_OPCODE_1_SHIFT;
+	rx_alu_opcode |= (rx_gcp_entry->rx_alu_opcode_2 & AL_ETH_RX_GCP_OPCODE_2_MASK) <<
+		AL_ETH_RX_GCP_OPCODE_2_SHIFT;
+	rx_alu_opcode |= (rx_gcp_entry->rx_alu_opcode_3 & AL_ETH_RX_GCP_OPCODE_3_MASK) <<
+		AL_ETH_RX_GCP_OPCODE_3_SHIFT;
+	rx_alu_opsel  = (rx_gcp_entry->rx_alu_opsel_1 & AL_ETH_RX_GCP_OPSEL_1_MASK) <<
+		AL_ETH_RX_GCP_OPSEL_1_SHIFT;
+	rx_alu_opsel |= (rx_gcp_entry->rx_alu_opsel_2 & AL_ETH_RX_GCP_OPSEL_2_MASK) <<
+		AL_ETH_RX_GCP_OPSEL_2_SHIFT;
+	rx_alu_opsel |= (rx_gcp_entry->rx_alu_opsel_3 & AL_ETH_RX_GCP_OPSEL_3_MASK) <<
+		AL_ETH_RX_GCP_OPSEL_3_SHIFT;
+	rx_alu_opsel |= (rx_gcp_entry->rx_alu_opsel_4 & AL_ETH_RX_GCP_OPSEL_4_MASK) <<
+		AL_ETH_RX_GCP_OPSEL_4_SHIFT;
+
+	/*  Rx Generic crc prameters table general */
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_addr, idx);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_gen,
+			gcp_table_gen);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_1,
+			rx_gcp_entry->gcp_mask[0]);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_2,
+			rx_gcp_entry->gcp_mask[1]);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_3,
+			rx_gcp_entry->gcp_mask[2]);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_4,
+			rx_gcp_entry->gcp_mask[3]);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_5,
+			rx_gcp_entry->gcp_mask[4]);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_mask_6,
+			rx_gcp_entry->gcp_mask[5]);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_crc_init,
+			rx_gcp_entry->crc_init);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_res,
+			rx_gcp_entry->gcp_table_res);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_alu_opcode,
+			rx_alu_opcode);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_alu_opsel,
+			rx_alu_opsel);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_table_alu_val,
+			rx_gcp_entry->alu_val);
+	return 0;
+}
+
+
+#define AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM 9
+#define AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM 32
+
+static struct al_eth_tx_gpd_cam_entry
+al_eth_generic_tx_crc_gpd[AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM] = {
+
+	/* [0] roce (with grh, bth) */
+	{22,		0,		0,		0,		1,
+	 0x1f,		0x0,		0x0,		0x0,		},
+	/* [1] fcoe */
+	{21,		0,		0,		0,		1,
+	 0x1f,		0x0,		0x0,		0x0,		},
+	/* [2] routable_roce that is refered as l4_protocol, over IPV4 (and udp) */
+	{8,		23,		0,		0,		1,
+	 0x1f,		0x1f,		0x0,		0x0,		},
+	/* [3] routable_roce that is refered as l4_protocol, over IPV6 (and udp) */
+	{11,		23,		0,		0,		1,
+	 0x1f,		0x1f,		0x0,		0x0,		},
+	/* [4] routable_roce that is refered as tunneled_packet, over outer IPV4 and udp */
+	{23,		0,		5,		0,		1,
+	 0x1f,		0x0,		0x5,		0x0,		},
+	/* [5] routable_roce that is refered as tunneled_packet, over outer IPV6 and udp */
+	{23,		0,		3,		0,		1,
+	 0x1f,		0x0,		0x5,		0x0		},
+	/* [6] GENERIC_STORAGE_READ over IPV4 (and udp) */
+	{8,		2,		0,		0,		1,
+	 0x1f,		0x1f,		0x0,		0x0,		},
+	/* [7] GENERIC_STORAGE_READ over IPV6 (and udp) */
+	{11,		2,		0,		0,		1,
+	 0x1f,		0x1f,		0x0,		0x0,		},
+	/* [8] default match */
+	{0,		0,		0,		0,		1,
+	 0x0,		0x0,		0x0,		0x0		}
+};
+
+static struct al_eth_tx_gcp_table_entry
+al_eth_generic_tx_crc_gcp[AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM] = {
+
+	/* [0] roce (with grh, bth) */
+	{0,		1,		1,		0,		1,
+	 0,		4,		8,		0,		1,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0xffff7f03,	0x00000000,	0x00000000,
+	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
+	 0},
+	/* [1] fcoe */
+	{0,		1,		0,		0,		1,
+	 0,		8,		14,		1,		1,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
+	 0},
+	/* [2] routable_roce that is refered as l4_protocol, over IPV4 (and udp) */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
+	 0},
+	/* [3] routable_roce that is refered as l4_protocol, over IPV6 (and udp) */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
+	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
+	 0},
+	/* [4] routable_roce that is refered as tunneled_packet, over outer IPV4 and udp */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 2,		0,		0,		0,		10,
+	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
+	 28},
+	/* [5] routable_roce that is refered as tunneled_packet, over outer IPV6 and udp */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 2,		0,		0,		0,		10,
+	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
+	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
+	 48},
+	/* [6] GENERIC_STORAGE_READ over IPV4 (and udp) */
+	{1,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 1,		0,		1,		0,		2,
+	 10,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
+	 8},
+	/* [7] GENERIC_STORAGE_READ over IPV6 (and udp) */
+	{1,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 1,		0,		1,		0,		2,
+	 10,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0,
+	 8},
+	/* [8] default match */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	  0x00000000},	0x00000000,	0x0,
+	 0}
+};
+
+static struct al_eth_tx_crc_chksum_replace_cmd_for_protocol_num_entry
+al_eth_tx_crc_chksum_replace_cmd[AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM] = {
+
+	/* [0] roce (with grh, bth) */
+	{0,1,0,1,		0,0,0,0,		0,0,0,0},
+	/* [1] fcoe */
+	{0,1,0,1,		0,0,0,0,		0,0,0,0},
+	/* [2] routable_roce that is refered as l4_protocol, over IPV4 (and udp) */
+	{0,0,1,1,		0,0,0,0,		0,1,0,1},
+	/* [3] routable_roce that is refered as l4_protocol, over IPV6 (and udp) */
+	{0,0,1,1,		0,0,0,0,		0,0,0,0},
+	/* [4] routable_roce that is refered as tunneled_packet, over outer IPV4 and udp */
+	{0,1,0,1,		0,0,0,0,		0,0,0,0},
+	/* [5] routable_roce that is refered as tunneled_packet, over outer IPV6 and udp */
+	{0,1,0,1,		0,0,0,0,		0,0,0,0},
+	/* [6] GENERIC_STORAGE_READ over IPV4 (and udp) */
+	{0,0,1,1,		0,0,0,0,		0,1,0,1},
+	/* [7] GENERIC_STORAGE_READ over IPV6 (and udp) */
+	{0,0,1,1,		0,0,0,0,		0,0,0,0},
+	/* [8] default match */
+	{0,0,0,0,		0,0,1,1,		0,1,0,1}
+};
+
+static struct al_eth_rx_gpd_cam_entry
+al_eth_generic_rx_crc_gpd[AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM] = {
+
+	/* [0] roce (with grh, bth) */
+	{22,		0,		0,		0,
+	 0,		0,		0,		0,		1,
+	 0x1f,		0x0,		0x0,		0x0,
+	 0x4,		0x0,		0x0,		0x0},
+	/* [1] fcoe */
+	{21,		0,		0,		0,
+	 0,		0,		0,		0,		1,
+	 0x1f,		0x0,		0x0,		0x0,
+	 0x4,		0x0,		0x0,		0x0},
+	/* [2] routable_roce that is refered as l4_protocol, over IPV4 (and udp) */
+	{8,		23,		0,		0,
+	 0,		0,		0,		0,		1,
+	 0x1f,		0x1f,		0x0,		0x0,
+	 0x4,		0x0,		0x0,		0x0},
+	/* [3] routable_roce that is refered as l4_protocol, over IPV6 (and udp) */
+	{11,		23,		0,		0,
+	 0,		0,		0,		0,		1,
+	 0x1f,		0x1f,		0x0,		0x0,
+	 0x4,		0x0,		0x0,		0x0},
+	/* [4] routable_roce that is refered as tunneled_packet, over outer IPV4 and udp */
+	{8,		13,		23,		0,
+	 0,		0,		0,		0,		1,
+	 0x1f,		0x1f,		0x1f,		0x0,
+	 0x4,		0x0,		0x0,		0x0},
+	/* [5] routable_roce that is refered as tunneled_packet, over outer IPV6 and udp */
+	{11,		13,		23,		0,
+	 0,		0,		0,		0,		1,
+	 0x1f,		0x1f,		0x1f,		0x0,
+	 0x4,		0x0,		0x0,		0x0},
+	/* [6] tunneled roce (with grh, bth) over GRE over IPV4 */
+	{8,		0,		22,		0,
+	 4,		0,		0,		0,		1,
+	 0x1f,		0x0,		0x1f,		0x0,
+	 0x4,		0x0,		0x0,		0x0},
+	/* [7] tunneled roce (with grh, bth) over GRE over IPV6 */
+	{11,		0,		22,		0,
+	 4,		0,		0,		0,		1,
+	 0x1f,		0x0,		0x1f,		0x0,
+	 0x4,		0x0,		0x0,		0x0},
+	/* [8] tunneled fcoe over IPV4 */
+	{8,		0,		21,		0,
+	 4,		0,		0,		0,		1,
+	 0x1f,		0x0,		0x1f,		0x0,
+	 0x4,		0x0,		0x0,		0x0},
+        /* [9] tunneled fcoe over IPV6 */
+        {11,		0,		21,		0,
+	 4,		0,		0,		0,		1,
+         0x1f,		0x0,		0x1f,		0x0,
+	 0x4,		0x0,		0x0,		0x0},
+	/* [10] tunneled routable_roce that is refered as l4_protocol, over IPV4 (and udp) over IPV4 */
+	{8,             0,              8,              23,
+	 4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1f,
+	 0x4,		0x0,		0x0,		0x0},
+	/* [11] tunneled routable_roce that is refered as l4_protocol, over IPV4 (and udp) over IPV6 */
+	{11,		0,		8,		23,
+	4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1f,
+	0x4,		0x0,		0x0,		0x0},
+	/* [12] tunneled routable_roce that is refered as l4_protocol, over IPV6 (and udp) over IPV4 */
+	{8,		0,		11,		23,
+	4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1f,
+	0x4,		0x0,		0x0,		0x0},
+	/* [13] tunneled routable_roce that is refered as l4_protocol, over IPV6 (and udp) over IPV6 */
+	{11,		0,		11,		23,
+	4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1f,
+	0x4,		0x0,		0x0,		0x0},
+	/* [14] l3_pkt - IPV4 */
+	{8,		0,		0,		0,
+	0,		0,		0,		0,		1,
+	0x1f,		0x1f,		0x0,		0x0,
+	0x4,		0x0,		0x0,		0x0},
+	/* [15] l4_hdr over IPV4 */
+	{8,		12,		0,		0,
+	0,		0,		0,		0,		1,
+	0x1f,		0x1e,		0x0,		0x0,
+	0x4,		0x0,		0x0,		0x0},
+	/* [16] l3_pkt - IPV6 */
+	{11,		0,		0,		0,
+	0,		0,		0,		0,		1,
+	0x1f,		0x1f,		0x0,		0x0,
+	0x4,		0x0,		0x0,		0x0},
+	/* [17] l4_hdr over IPV6 */
+	{11,		12,		0,		0,
+	0,		0,		0,		0,		1,
+	0x1f,		0x1e,		0x0,		0x0,
+	0x4,		0x0,		0x0,		0x0},
+	/* [18] IPV4 over IPV4 */
+	{8,		0,		8,		0,
+	4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1f,
+	0x4,		0x0,		0x0,		0x0},
+	/* [19] l4_hdr over IPV4 over IPV4 */
+	{8,		0,		8,		12,
+	4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1e,
+	0x4,		0x0,		0x0,		0x0},
+	/* [20] IPV4 over IPV6 */
+	{11,		0,		8,		0,
+	4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1f,
+	0x4,		0x0,		0x0,		0x0},
+	/* [21] l4_hdr over IPV4 over IPV6 */
+	{11,		0,		8,		12,
+	4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1e,
+	0x4,		0x0,		0x0,		0x0},
+	/* [22] IPV6 over IPV4 */
+	{8,		0,		11,		0,
+	4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1f,
+	0x4,		0x0,		0x0,		0x0},
+	/* [23] l4_hdr over IPV6 over IPV4 */
+	{8,		0,		11,		12,
+	4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1e,
+	0x4,		0x0,		0x0,		0x0},
+	/* [24] IPV6 over IPV6 */
+	{11,		0,		11,		0,
+	4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1f,
+	0x4,		0x0,		0x0,		0x0},
+	/* [25] l4_hdr over IPV6 over IPV6 */
+	{11,		0,		11,		12,
+	4,		0,		0,		0,		1,
+	0x1f,		0x0,		0x1f,		0x1e,
+	0x4,		0x0,		0x0,		0x0},
+	/* [26] GENERIC_STORAGE_READ, over IPV4 (and udp) */
+	{8,		2,		0,		0,
+	0,		0,		0,		0,		1,
+	0x1f,		0x1f,		0x0,		0x0,
+	0x4,		0x0,		0x0,		0x0},
+	/* [27] GENERIC_STORAGE_READ, over IPV6 (and udp) */
+	{11,		2,		0,		0,
+	0,		0,		0,		0,		1,
+	0x1f,		0x1f,		0x0,		0x0,
+	0x4,		0x0,		0x0,		0x0},
+	/* [28] tunneled GENERIC_STORAGE_READ over IPV4 (and udp) over IPV4/IPV6 */
+	{8,		0,		8,		2,
+	4,		0,		0,		0,		1,
+	0x18,		0x0,		0x1f,		0x1f,
+	0x4,		0x0,		0x0,		0x0},
+	/* [29] tunneled GENERIC_STORAGE_READ over IPV6 (and udp)  over IPV4/IPV6 */
+	{8,		0,		11,		2,
+	4,		0,		0,		0,		1,
+	0x18,		0x0,		0x1f,		0x1f,
+	0x4,		0x0,		0x0,		0x0},
+	/* [30] tunneled L2 over GRE over IPV4 */
+	{8,		0,		0,		0,
+	 4,		0,		0,		0,		1,
+	 0x1f,		0x0,		0x1f,		0x0,
+	 0x4,		0x0,		0x0,		0x0},
+	/* [31] default match */
+	{0,		0,		0,		0,
+	 0,		0,		0,		0,		1,
+	 0x0,		0x0,		0x0,		0x0,
+	 0x0,		0x0,		0x0,		0x0}
+};
+
+static struct al_eth_rx_gcp_table_entry
+al_eth_generic_rx_crc_gcp[AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM] = {
+
+	/* [0] roce (with grh, bth) */
+	{0,		 1,		1,		0,		1,
+	 0,		4,		8,		0,		1,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0xffff7f03,	0x00000000,	0x00000000,
+	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
+	 0},
+	/* [1] fcoe */
+	{0,		1,		0,		0,		1,
+	 0,		8,		14,		1,		1,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
+	 0},
+	/* [2] routable_roce that is refered as l4_protocol, over IPV4 (and udp) */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000011,
+	 0},
+	/* [3] routable_roce that is refered as l4_protocol, over IPV6 (and udp) */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
+	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
+	 0},
+	/* [4] routable_roce that is refered as tunneled_packet, over outer IPV4 and udp */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 2,		0,		0,		0,		10,
+	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x0302201c,
+	 28},
+	/* [5] routable_roce that is refered as tunneled_packet, over outer IPV6 and udp */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 2,		0,		0,		0,		10,
+	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
+	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03002018,
+	 48},
+	/* [6] tunneled roce (with grh, bth) over IPV4 */
+	{0,		1,		1,		0,		1,
+	 0,		4,		8,		0,		1,
+	 0,		0,		0,		1,		0,
+	 0,		0,		{0xffff7f03,	0x00000000,	0x00000000,
+	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03020014,
+	 0},
+	/* [7] tunneled roce (with grh, bth) over IPV6 */
+	{0,		1,		1,		0,		1,
+	 0,		4,		8,		0,		1,
+	 0,		0,		0,		1,		0,
+	 0,		0,		{0xffff7f03,	0x00000000,	0x00000000,
+	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
+	 0},
+	/* [8] tunneled fcoe over IPV4 */
+	{0,		1,		0,		0,		1,
+	 0,		8,		14,		1,		1,
+	 0,		0,		0,		1,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03020014,
+	 0},
+	/* [9] tunneled fcoe over IPV6 */
+	{0,		1,		0,		0,		1,
+	 0,		8,		14,		1,		1,
+	 0,		0,		0,		1,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
+	 0},
+	/* [10] tunneled routable_roce that is refered as l4_protocol, over IPV4 (and udp) over IPV4 */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		1,		0,
+	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03020015,
+	 0},
+	/* [11] tunneled routable_roce that is refered as l4_protocol, over IPV4 (and udp) over IPV6 */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		1,		0,
+	 0,		0,		{0x3000cf00,	0x00000f00,	0xc0000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000011,
+	 0},
+	/* [12] tunneled routable_roce that is refered as l4_protocol, over IPV6 (and udp) over IPV4 */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		1,		0,
+	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
+	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03020014,
+	 0},
+	/* [13] tunneled routable_roce that is refered as l4_protocol, over IPV6 (and udp) over IPV6 */
+	{0,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		1,		0,
+	 0,		0,		{0x7f030000,	0x00000000,	0x00000003,
+	 0x00c00000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
+	 0},
+	/* [14] l3_pkt - IPV4 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000001,
+	 0},
+	/* [15] l4_hdr over IPV4 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000003,
+	 0},
+	/* [16] l3_pkt - IPV6 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000000,
+	 0},
+	/* [17] l4_hdr over IPV6 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000002,
+	 0},
+	/* [18] IPV4 over IPV4 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00020005,
+	 0},
+	/* [19] l4_hdr over IPV4 over IPV4 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00020007,
+	 0},
+	/* [20] IPV4 over IPV6 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000001,
+	 0},
+	/* [21] l4_hdr over IPV4 over IPV6 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000003,
+	 0},
+	/* [22] IPV6 over IPV4 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00020004,
+	 0},
+	/* [23] l4_hdr over IPV6 over IPV4 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00020006,
+	 0},
+	/* [24] IPV6 over IPV6 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000000,
+	 0},
+	/* [25] l4_hdr over IPV6 over IPV6 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00000002,
+	 0},
+	/* [26] GENERIC_STORAGE_READ, over IPV4 (and udp) */
+	{1,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		2,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000011,
+	 0},
+	/* [27] GENERIC_STORAGE_READ, over IPV6 (and udp) */
+	{1,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		2,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
+	 0},
+	/* [28] tunneled GENERIC_STORAGE_READ over IPV4 (and udp) over IPV4/IPV6 */
+	{1,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		3,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000011,
+	 0},
+	/* [29] tunneled GENERIC_STORAGE_READ over IPV6 (and udp)  over IPV4/IPV6 */
+	{1,		1,		1,		0,		1,
+	 0,		4,		0,		0,		1,
+	 0,		0,		0,		3,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0xffffffff,	0x03000010,
+	 0},
+	/* [30] tunneled L2 over GRE over IPV4 */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x00020004,
+	 0},
+	/* [31] default match */
+	{0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		0,		0,		0,
+	 0,		0,		{0x00000000,	0x00000000,	0x00000000,
+	 0x00000000,	0x00000000,	0x00000000},	0x00000000,	0x0,
+	 0}
+};
+
+int al_eth_tx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter)
+{
+	int idx;
+	al_assert((adapter->rev_id > AL_ETH_REV_ID_2));
+
+	for (idx = 0; idx < AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM; idx++)
+		al_eth_tx_protocol_detect_table_entry_set(adapter, idx,
+				&al_eth_generic_tx_crc_gpd[idx]);
+
+	return 0;
+}
+
+int al_eth_tx_generic_crc_table_init(struct al_hal_eth_adapter *adapter)
+{
+	int idx;
+	al_assert((adapter->rev_id > AL_ETH_REV_ID_2));
+
+	al_dbg("eth [%s]: enable tx_generic_crc\n", adapter->name);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.tx_gcp_legacy, 0x0);
+	al_reg_write32(&adapter->ec_regs_base->tfw_v3.crc_csum_replace, 0x0);
+	for (idx = 0; idx < AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM; idx++)
+		al_eth_tx_generic_crc_table_entry_set(adapter, idx,
+				&al_eth_generic_tx_crc_gcp[idx]);
+
+	return 0;
+}
+
+int al_eth_tx_crc_chksum_replace_cmd_init(struct al_hal_eth_adapter *adapter)
+{
+	int idx;
+	al_assert((adapter->rev_id > AL_ETH_REV_ID_2));
+
+	for (idx = 0; idx < AL_ETH_TX_GENERIC_CRC_ENTRIES_NUM; idx++)
+		al_eth_tx_crc_chksum_replace_cmd_entry_set(adapter, idx,
+				&al_eth_tx_crc_chksum_replace_cmd[idx]);
+
+	return 0;
+}
+
+int al_eth_rx_protocol_detect_table_init(struct al_hal_eth_adapter *adapter)
+{
+	int idx;
+	al_assert((adapter->rev_id > AL_ETH_REV_ID_2));
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p1,
+			AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L3_PROTO_IDX_OFFSET);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p2,
+			AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L4_PROTO_IDX_OFFSET);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p3,
+			AL_ETH_RX_GPD_PARSE_RESULT_INNER_L3_PROTO_IDX_OFFSET);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p4,
+			AL_ETH_RX_GPD_PARSE_RESULT_INNER_L4_PROTO_IDX_OFFSET);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p5,
+			AL_ETH_RX_GPD_PARSE_RESULT_OUTER_PARSE_CTRL);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p6,
+			AL_ETH_RX_GPD_PARSE_RESULT_INNER_PARSE_CTRL);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p7,
+			AL_ETH_RX_GPD_PARSE_RESULT_L3_PRIORITY);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.gpd_p8,
+			AL_ETH_RX_GPD_PARSE_RESULT_OUTER_L4_DST_PORT_LSB);
+
+	for (idx = 0; idx < AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM; idx++)
+		al_eth_rx_protocol_detect_table_entry_set(adapter, idx,
+				&al_eth_generic_rx_crc_gpd[idx]);
+	return 0;
+}
+
+int al_eth_rx_generic_crc_table_init(struct al_hal_eth_adapter *adapter)
+	{
+	int idx;
+	uint32_t val;
+
+	al_assert((adapter->rev_id > AL_ETH_REV_ID_2));
+
+	al_dbg("eth [%s]: enable rx_generic_crc\n", adapter->name);
+	al_reg_write32(&adapter->ec_regs_base->rfw_v3.rx_gcp_legacy, 0x0);
+
+	for (idx = 0; idx < AL_ETH_RX_PROTOCOL_DETECT_ENTRIES_NUM; idx++)
+		al_eth_rx_generic_crc_table_entry_set(adapter, idx,
+				&al_eth_generic_rx_crc_gcp[idx]);
+
+	val = EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_15_CRC_RES_SEL |
+			EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_14_L3_CKS_RES_SEL |
+			EC_GEN_V3_RX_COMP_DESC_W3_DEC_STAT_13_L4_CKS_RES_SEL |
+			EC_GEN_V3_RX_COMP_DESC_W0_L3_CKS_RES_SEL;
+	al_reg_write32_masked(&adapter->ec_regs_base->gen_v3.rx_comp_desc,
+			val, val);
+	return 0;
+}
+
+/** @} end of Ethernet group */
+

From 6c822626b7cb0e8fa301dbcad29f08d6dfd4bf32 Mon Sep 17 00:00:00 2001
From: hselasky <hselasky@FreeBSD.org>
Date: Tue, 26 Jan 2016 15:26:35 +0000
Subject: [PATCH 035/113] Update and add various macros to the LinuxKPI and
 resolve a macro redefinition issue in the cxgb driver.

MFC after:	1 week
Sponsored by:	Mellanox Technologies
Reviewed by:	np @
---
 sys/compat/linuxkpi/common/include/asm/atomic.h        |  2 ++
 sys/compat/linuxkpi/common/include/linux/clocksource.h |  9 +++++----
 sys/compat/linuxkpi/common/include/linux/completion.h  |  4 +++-
 sys/compat/linuxkpi/common/include/linux/gfp.h         |  1 +
 sys/compat/linuxkpi/common/include/linux/kernel.h      | 10 ++++++----
 sys/dev/cxgb/cxgb_osdep.h                              |  4 +++-
 6 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/sys/compat/linuxkpi/common/include/asm/atomic.h b/sys/compat/linuxkpi/common/include/asm/atomic.h
index ee85624fd927..70560f1f08f7 100644
--- a/sys/compat/linuxkpi/common/include/asm/atomic.h
+++ b/sys/compat/linuxkpi/common/include/asm/atomic.h
@@ -35,6 +35,8 @@
 #include <sys/types.h>
 #include <machine/atomic.h>
 
+#define	ATOMIC_INIT(x)	{ .counter = (x) }
+
 typedef struct {
 	volatile int counter;
 } atomic_t;
diff --git a/sys/compat/linuxkpi/common/include/linux/clocksource.h b/sys/compat/linuxkpi/common/include/linux/clocksource.h
index f4d17f188796..5e2cd5ee95e9 100644
--- a/sys/compat/linuxkpi/common/include/linux/clocksource.h
+++ b/sys/compat/linuxkpi/common/include/linux/clocksource.h
@@ -2,7 +2,7 @@
  * Copyright (c) 2010 Isilon Systems, Inc.
  * Copyright (c) 2010 iX Systems, Inc.
  * Copyright (c) 2010 Panasas, Inc.
- * Copyright (c) 2013, 2014 Mellanox Technologies, Ltd.
+ * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -29,12 +29,13 @@
  * $FreeBSD$
  */
 #ifndef _LINUX_CLOCKSOURCE_H
-#define _LINUX_CLOCKSOURCE_H
+#define	_LINUX_CLOCKSOURCE_H
 
 #include <asm/types.h>
 
+#define	CLOCKSOURCE_MASK(x) ((cycle_t)(-1ULL >> ((-(x)) & 63)))
+
 /* clocksource cycle base type */
 typedef u64 cycle_t;
 
-
-#endif /* _LINUX_CLOCKSOURCE_H */
+#endif					/* _LINUX_CLOCKSOURCE_H */
diff --git a/sys/compat/linuxkpi/common/include/linux/completion.h b/sys/compat/linuxkpi/common/include/linux/completion.h
index 7cfb10db86be..92ccc61f38da 100644
--- a/sys/compat/linuxkpi/common/include/linux/completion.h
+++ b/sys/compat/linuxkpi/common/include/linux/completion.h
@@ -40,7 +40,9 @@ struct completion {
 #define	INIT_COMPLETION(c) \
 	((c).done = 0)
 #define	init_completion(c) \
-	((c)->done = 0)
+	do { (c)->done = 0; } while (0)
+#define	reinit_completion(c) \
+	do { (c)->done = 0; } while (0)
 #define	complete(c)				\
 	linux_complete_common((c), 0)
 #define	complete_all(c)				\
diff --git a/sys/compat/linuxkpi/common/include/linux/gfp.h b/sys/compat/linuxkpi/common/include/linux/gfp.h
index 38a0222a8e8d..d0fb0ac0d00d 100644
--- a/sys/compat/linuxkpi/common/include/linux/gfp.h
+++ b/sys/compat/linuxkpi/common/include/linux/gfp.h
@@ -54,6 +54,7 @@
 #define	GFP_HIGHUSER	M_WAITOK
 #define	GFP_HIGHUSER_MOVABLE	M_WAITOK
 #define	GFP_IOFS	M_NOWAIT
+#define	GFP_NOIO	M_NOWAIT
 
 static inline void *
 page_address(struct page *page)
diff --git a/sys/compat/linuxkpi/common/include/linux/kernel.h b/sys/compat/linuxkpi/common/include/linux/kernel.h
index bfc3b7d7b6b0..6b6c0afa918c 100644
--- a/sys/compat/linuxkpi/common/include/linux/kernel.h
+++ b/sys/compat/linuxkpi/common/include/linux/kernel.h
@@ -2,7 +2,7 @@
  * Copyright (c) 2010 Isilon Systems, Inc.
  * Copyright (c) 2010 iX Systems, Inc.
  * Copyright (c) 2010 Panasas, Inc.
- * Copyright (c) 2013-2015 Mellanox Technologies, Ltd.
+ * Copyright (c) 2013-2016 Mellanox Technologies, Ltd.
  * Copyright (c) 2014-2015 François Tigeot
  * All rights reserved.
  *
@@ -159,9 +159,10 @@
   
 #define	ARRAY_SIZE(x)	(sizeof(x) / sizeof((x)[0]))
 
-#define	simple_strtoul	strtoul
-#define	simple_strtol	strtol
-#define kstrtol(a,b,c) ({*(c) = strtol(a,0,b);})
+#define	simple_strtoul(...) strtoul(__VA_ARGS__)
+#define	simple_strtol(...) strtol(__VA_ARGS__)
+#define	kstrtol(a,b,c) ({*(c) = strtol(a,0,b); 0;})
+#define	kstrtoint(a,b,c) ({*(c) = strtol(a,0,b); 0;})
 
 #define min(x, y)	((x) < (y) ? (x) : (y))
 #define max(x, y)	((x) > (y) ? (x) : (y))
@@ -185,6 +186,7 @@
 #define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1)
 #define round_down(x, y) ((x) & ~__round_mask(x, y))
 
+#define	smp_processor_id()	PCPU_GET(cpuid)
 #define	num_possible_cpus()	mp_ncpus
 #define	num_online_cpus()	mp_ncpus
 
diff --git a/sys/dev/cxgb/cxgb_osdep.h b/sys/dev/cxgb/cxgb_osdep.h
index ddef730426aa..b9ca32fe5ced 100644
--- a/sys/dev/cxgb/cxgb_osdep.h
+++ b/sys/dev/cxgb/cxgb_osdep.h
@@ -231,7 +231,9 @@ static const int debug_flags = DBG_RX;
 #define le16_to_cpu(x) le16toh(x)
 #define cpu_to_le32(x) htole32(x)
 #define swab32(x) bswap32(x)
-#define simple_strtoul strtoul
+#ifndef simple_strtoul
+#define simple_strtoul(...) strtoul(__VA_ARGS__)
+#endif
 
 
 #ifndef LINUX_TYPES_DEFINED

From c782b7ca11b520419203458b8b74985cb9738f38 Mon Sep 17 00:00:00 2001
From: hiren <hiren@FreeBSD.org>
Date: Tue, 26 Jan 2016 16:33:38 +0000
Subject: [PATCH 036/113] Persist timers TCPTV_PERSMIN and TCPTV_PERSMAX are
 hardcoded with 5 seconds and 60 seconds, respectively. Turn them into sysctls
 that can be tuned live. The default values of 5 seconds and 60 seconds have
 been retained.

Submitted by:		Jason Wolfe (j at nitrology dot com)
Reviewed by:		gnn, rrs, hiren, bz
MFC after:		1 week
Sponsored by:		Limelight Networks
Differential Revision:	https://reviews.freebsd.org/D5024
---
 sys/netinet/tcp_output.c | 2 +-
 sys/netinet/tcp_subr.c   | 2 ++
 sys/netinet/tcp_timer.c  | 8 ++++++++
 sys/netinet/tcp_timer.h  | 4 +++-
 4 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/sys/netinet/tcp_output.c b/sys/netinet/tcp_output.c
index 55cf209cba44..cdfed3663bff 100644
--- a/sys/netinet/tcp_output.c
+++ b/sys/netinet/tcp_output.c
@@ -1626,7 +1626,7 @@ tcp_setpersist(struct tcpcb *tp)
 	 * Start/restart persistance timer.
 	 */
 	TCPT_RANGESET(tt, t * tcp_backoff[tp->t_rxtshift],
-		      TCPTV_PERSMIN, TCPTV_PERSMAX);
+		      tcp_persmin, tcp_persmax);
 	tcp_timer_activate(tp, TT_PERSIST, tt);
 	if (tp->t_rxtshift < TCP_MAXRXTSHIFT)
 		tp->t_rxtshift++;
diff --git a/sys/netinet/tcp_subr.c b/sys/netinet/tcp_subr.c
index 0ef86935d200..6358e8173283 100644
--- a/sys/netinet/tcp_subr.c
+++ b/sys/netinet/tcp_subr.c
@@ -675,6 +675,8 @@ tcp_init(void)
 	tcp_rexmit_min = TCPTV_MIN;
 	if (tcp_rexmit_min < 1)
 		tcp_rexmit_min = 1;
+	tcp_persmin = TCPTV_PERSMIN;
+	tcp_persmax = TCPTV_PERSMAX;
 	tcp_rexmit_slop = TCPTV_CPU_VAR;
 	tcp_finwait2_timeout = TCPTV_FINWAIT2_TIMEOUT;
 	tcp_tcbhashsize = hashsize;
diff --git a/sys/netinet/tcp_timer.c b/sys/netinet/tcp_timer.c
index 0dfeb13564f3..303f9a20270e 100644
--- a/sys/netinet/tcp_timer.c
+++ b/sys/netinet/tcp_timer.c
@@ -77,6 +77,14 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp_debug.h>
 #endif
 
+int    tcp_persmin;
+SYSCTL_PROC(_net_inet_tcp, OID_AUTO, persmin, CTLTYPE_INT|CTLFLAG_RW,
+    &tcp_persmin, 0, sysctl_msec_to_ticks, "I", "minimum persistence interval");
+
+int    tcp_persmax;
+SYSCTL_PROC(_net_inet_tcp, OID_AUTO, persmax, CTLTYPE_INT|CTLFLAG_RW,
+    &tcp_persmax, 0, sysctl_msec_to_ticks, "I", "maximum persistence interval");
+
 int	tcp_keepinit;
 SYSCTL_PROC(_net_inet_tcp, TCPCTL_KEEPINIT, keepinit, CTLTYPE_INT|CTLFLAG_RW,
     &tcp_keepinit, 0, sysctl_msec_to_ticks, "I", "time to establish connection");
diff --git a/sys/netinet/tcp_timer.h b/sys/netinet/tcp_timer.h
index 2758069097ef..252560a4c099 100644
--- a/sys/netinet/tcp_timer.h
+++ b/sys/netinet/tcp_timer.h
@@ -77,7 +77,7 @@
 						   if 0, no idea yet */
 #define	TCPTV_RTOBASE	(  3*hz)		/* assumed RTO if no info */
 
-#define	TCPTV_PERSMIN	(  5*hz)		/* retransmit persistence */
+#define	TCPTV_PERSMIN	(  5*hz)		/* minimum persist interval */
 #define	TCPTV_PERSMAX	( 60*hz)		/* maximum persist interval */
 
 #define	TCPTV_KEEP_INIT	( 75*hz)		/* initial connect keepalive */
@@ -173,6 +173,8 @@ struct tcp_timer {
 #define	TP_KEEPCNT(tp)	((tp)->t_keepcnt ? (tp)->t_keepcnt : tcp_keepcnt)
 #define	TP_MAXIDLE(tp)	(TP_KEEPCNT(tp) * TP_KEEPINTVL(tp))
 
+extern int tcp_persmin;			/* minimum persist interval */
+extern int tcp_persmax;			/* maximum persist interval */
 extern int tcp_keepinit;		/* time to establish connection */
 extern int tcp_keepidle;		/* time before keepalive probes begin */
 extern int tcp_keepintvl;		/* time between keepalive probes */

From be53d5f660ed4d28616fc734e38ec55324ebc93e Mon Sep 17 00:00:00 2001
From: avos <avos@FreeBSD.org>
Date: Tue, 26 Jan 2016 16:34:27 +0000
Subject: [PATCH 037/113] rtwn: use ieee80211_restart_all() for device reset

Tested by:	kevlo
Reviewed by:	kevlo
Approved by:	adrian (mentor)
Differential Revision:	https://reviews.freebsd.org/D5057
---
 sys/dev/rtwn/if_rtwn.c    | 29 +----------------------------
 sys/dev/rtwn/if_rtwnreg.h |  1 -
 2 files changed, 1 insertion(+), 29 deletions(-)

diff --git a/sys/dev/rtwn/if_rtwn.c b/sys/dev/rtwn/if_rtwn.c
index 886b281a9108..f6a5949bc398 100644
--- a/sys/dev/rtwn/if_rtwn.c
+++ b/sys/dev/rtwn/if_rtwn.c
@@ -186,11 +186,9 @@ static void	rtwn_iq_calib(struct rtwn_softc *);
 static void	rtwn_lc_calib(struct rtwn_softc *);
 static void	rtwn_temp_calib(struct rtwn_softc *);
 static void	rtwn_init_locked(struct rtwn_softc *);
-static void	rtwn_init(struct rtwn_softc *);
 static void	rtwn_stop_locked(struct rtwn_softc *);
 static void	rtwn_stop(struct rtwn_softc *);
 static void	rtwn_intr(void *);
-static void	rtwn_hw_reset(void *, int);
 
 /* Aliases. */
 #define	rtwn_bb_write	rtwn_write_4
@@ -295,7 +293,6 @@ rtwn_attach(device_t dev)
 	RTWN_LOCK_INIT(sc);
 	callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0);
 	callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0);
-	TASK_INIT(&sc->sc_reinit_task, 0, rtwn_hw_reset, sc);
 	mbufq_init(&sc->sc_snd, ifqmaxlen);
 
 	error = rtwn_read_chipid(sc);
@@ -406,7 +403,6 @@ rtwn_detach(device_t dev)
 	int i;
 
 	if (sc->sc_ic.ic_softc != NULL) {
-		ieee80211_draintask(&sc->sc_ic, &sc->sc_reinit_task);
 		rtwn_stop(sc);
 
 		callout_drain(&sc->calib_to);
@@ -1899,7 +1895,7 @@ rtwn_watchdog(void *arg)
 
 	if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) {
 		ic_printf(ic, "device timeout\n");
-		ieee80211_runtask(ic, &sc->sc_reinit_task);
+		ieee80211_restart_all(ic);
 		return;
 	}
 	callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc);
@@ -3360,18 +3356,6 @@ rtwn_init_locked(struct rtwn_softc *sc)
 	rtwn_stop_locked(sc);
 }
 
-static void
-rtwn_init(struct rtwn_softc *sc)
-{
-
-	RTWN_LOCK(sc);
-	rtwn_init_locked(sc);
-	RTWN_UNLOCK(sc);
-
-	if (sc->sc_flags & RTWN_RUNNING)
-		ieee80211_start_all(&sc->sc_ic);
-}
-
 static void
 rtwn_stop_locked(struct rtwn_softc *sc)
 {
@@ -3481,14 +3465,3 @@ rtwn_intr(void *arg)
 
 	RTWN_UNLOCK(sc);
 }
-
-static void
-rtwn_hw_reset(void *arg0, int pending)
-{
-	struct rtwn_softc *sc = arg0;
-	struct ieee80211com *ic = &sc->sc_ic;
-
-	rtwn_stop(sc);
-	rtwn_init(sc);
-	ieee80211_notify_radio(ic, 1);
-}
diff --git a/sys/dev/rtwn/if_rtwnreg.h b/sys/dev/rtwn/if_rtwnreg.h
index a5f1cc282b31..09a31fad84b0 100644
--- a/sys/dev/rtwn/if_rtwnreg.h
+++ b/sys/dev/rtwn/if_rtwnreg.h
@@ -1295,7 +1295,6 @@ struct rtwn_softc {
 	bus_size_t			sc_mapsize;
 	int				sc_cap_off;
 
-	struct task			sc_reinit_task;
 	struct callout			calib_to;
 	struct callout			watchdog_to;
 

From 7068dcff871523b9644b64bb3e56eabd80acedf5 Mon Sep 17 00:00:00 2001
From: avos <avos@FreeBSD.org>
Date: Tue, 26 Jan 2016 16:50:59 +0000
Subject: [PATCH 038/113] rtwn: do not start vap when initialization fails

- Start vap(s) (via ieee80211_start_all()) only when initialization
succeeds; stop the first vap otherwise (via ieee80211_stop());
- Do not try to stop a device multiple times
(move (sc->sc_flags & RTWN_RUNNING) check to urtwn_stop_locked()).

Tested by:	kevlo
Reviewed by:	kevlo
Approved by:	adrian (mentor)
Differential Revision:	https://reviews.freebsd.org/D5058
---
 sys/dev/rtwn/if_rtwn.c | 47 ++++++++++++++++++++++++------------------
 1 file changed, 27 insertions(+), 20 deletions(-)

diff --git a/sys/dev/rtwn/if_rtwn.c b/sys/dev/rtwn/if_rtwn.c
index f6a5949bc398..0d817fbc8c0c 100644
--- a/sys/dev/rtwn/if_rtwn.c
+++ b/sys/dev/rtwn/if_rtwn.c
@@ -185,7 +185,7 @@ static void	rtwn_iq_calib_write_results(struct rtwn_softc *, uint16_t[2],
 static void	rtwn_iq_calib(struct rtwn_softc *);
 static void	rtwn_lc_calib(struct rtwn_softc *);
 static void	rtwn_temp_calib(struct rtwn_softc *);
-static void	rtwn_init_locked(struct rtwn_softc *);
+static int	rtwn_init(struct rtwn_softc *);
 static void	rtwn_stop_locked(struct rtwn_softc *);
 static void	rtwn_stop(struct rtwn_softc *);
 static void	rtwn_intr(void *);
@@ -1845,19 +1845,15 @@ static void
 rtwn_parent(struct ieee80211com *ic)
 {
 	struct rtwn_softc *sc = ic->ic_softc;
-	int startall = 0;
+	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
 
-	RTWN_LOCK(sc);
-	if (ic->ic_nrunning> 0) {
-		if (!(sc->sc_flags & RTWN_RUNNING)) {
-			rtwn_init_locked(sc);
-			startall = 1;
-		}
-	} else if (sc->sc_flags & RTWN_RUNNING)
-		 rtwn_stop_locked(sc);
-	RTWN_UNLOCK(sc);
-	if (startall)
-		ieee80211_start_all(ic);
+	if (ic->ic_nrunning > 0) {
+		if (rtwn_init(sc) == 0)
+			ieee80211_start_all(ic);
+		else
+			ieee80211_stop(vap);
+	} else
+		rtwn_stop(sc);
 }
 
 static void
@@ -3218,8 +3214,8 @@ rtwn_temp_calib(struct rtwn_softc *sc)
 	}
 }
 
-static void
-rtwn_init_locked(struct rtwn_softc *sc)
+static int
+rtwn_init(struct rtwn_softc *sc)
 {
 	struct ieee80211com *ic = &sc->sc_ic;
 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
@@ -3227,7 +3223,13 @@ rtwn_init_locked(struct rtwn_softc *sc)
 	uint8_t macaddr[IEEE80211_ADDR_LEN];
 	int i, error;
 
-	RTWN_LOCK_ASSERT(sc);
+	RTWN_LOCK(sc);
+
+	if (sc->sc_flags & RTWN_RUNNING) {
+		RTWN_UNLOCK(sc);
+		return 0;
+	}
+	sc->sc_flags |= RTWN_RUNNING;
 
 	/* Init firmware commands ring. */
 	sc->fwcur = 0;
@@ -3347,13 +3349,15 @@ rtwn_init_locked(struct rtwn_softc *sc)
 	/* Enable interrupts. */
 	rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE);
 
-	sc->sc_flags |= RTWN_RUNNING;
-
 	callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc);
-	return;
 
 fail:
-	rtwn_stop_locked(sc);
+	if (error != 0)
+		rtwn_stop_locked(sc);
+
+	RTWN_UNLOCK(sc);
+
+	return error;
 }
 
 static void
@@ -3364,6 +3368,9 @@ rtwn_stop_locked(struct rtwn_softc *sc)
 
 	RTWN_LOCK_ASSERT(sc);
 
+	if (!(sc->sc_flags & RTWN_RUNNING))
+		return;
+
 	sc->sc_tx_timer = 0;
 	callout_stop(&sc->watchdog_to);
 	callout_stop(&sc->calib_to);

From 6b1bfc333f0dfda88eea4b8a365522145c396084 Mon Sep 17 00:00:00 2001
From: emaste <emaste@FreeBSD.org>
Date: Tue, 26 Jan 2016 18:20:25 +0000
Subject: [PATCH 039/113] Add STT_SPARC_REGISTER ELF definition

MFC after:	1 week
---
 sys/sys/elf_common.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/sys/sys/elf_common.h b/sys/sys/elf_common.h
index 99f05496fa0a..b4574f3a9747 100644
--- a/sys/sys/elf_common.h
+++ b/sys/sys/elf_common.h
@@ -771,8 +771,9 @@ typedef struct {
 #define	STT_LOOS	10	/* Reserved range for operating system */
 #define	STT_GNU_IFUNC	10
 #define	STT_HIOS	12	/*   specific semantics. */
-#define	STT_LOPROC	13	/* reserved range for processor */
-#define	STT_HIPROC	15	/*   specific semantics. */
+#define	STT_LOPROC	13	/* Start of processor reserved range. */
+#define	STT_SPARC_REGISTER 13	/* SPARC register information. */
+#define	STT_HIPROC	15	/* End of processor reserved range. */
 
 /* Symbol visibility - ELFNN_ST_VISIBILITY - st_other */
 #define	STV_DEFAULT	0x0	/* Default visibility (see binding). */

From e006e85d52442ba276643b5d2f11da59797c7de1 Mon Sep 17 00:00:00 2001
From: imp <imp@FreeBSD.org>
Date: Tue, 26 Jan 2016 18:39:23 +0000
Subject: [PATCH 040/113] Add a comment about why at is turned off in the
 exception handler. Only k0 and k1 may be touched until we save registers
 somewhere.

MFC After: 2 days
---
 sys/mips/mips/exception.S | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/sys/mips/mips/exception.S b/sys/mips/mips/exception.S
index 6eddd19af882..01fd2106e53a 100644
--- a/sys/mips/mips/exception.S
+++ b/sys/mips/mips/exception.S
@@ -177,6 +177,12 @@ MipsDoTLBMiss:
 VECTOR(MipsException, unknown)
 /*
  * Find out what mode we came from and jump to the proper handler.
+ *
+ * Note: at turned off here because we cannot trash the at register
+ * in this exception code. Only k0 and k1 may be modified before
+ * we save registers. This is true of all functions called through
+ * the pointer magic: Mips{User,Kern}Intr, Mips{User,Kern}GenException
+ * and MipsTLBInvalidException
  */
 	.set	noat
 	mfc0	k0, MIPS_COP_0_STATUS		# Get the status register

From 19f104028738505031cf8b086c2c28575105709f Mon Sep 17 00:00:00 2001
From: imp <imp@FreeBSD.org>
Date: Tue, 26 Jan 2016 18:39:30 +0000
Subject: [PATCH 041/113] Remove static from these two. They slipped through
 the cracks.

MFC After: 1 week
---
 sys/boot/mips/beri/boot2/boot2.c | 2 +-
 sys/boot/pc98/boot2/boot2.c      | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/sys/boot/mips/beri/boot2/boot2.c b/sys/boot/mips/beri/boot2/boot2.c
index 9728a20b9bcf..2a0fd816a625 100644
--- a/sys/boot/mips/beri/boot2/boot2.c
+++ b/sys/boot/mips/beri/boot2/boot2.c
@@ -132,7 +132,7 @@ static struct dsk {
 } dsk;
 static char cmd[512], cmddup[512], knamebuf[1024];
 static const char *kname;
-static uint32_t opts;
+uint32_t opts;
 #if 0
 static int comspeed = SIOSPD;
 #endif
diff --git a/sys/boot/pc98/boot2/boot2.c b/sys/boot/pc98/boot2/boot2.c
index aed07262f4a2..a9bf47594664 100644
--- a/sys/boot/pc98/boot2/boot2.c
+++ b/sys/boot/pc98/boot2/boot2.c
@@ -104,7 +104,7 @@ static struct dsk {
 } dsk;
 static char cmd[512], cmddup[512], knamebuf[1024];
 static const char *kname;
-static uint32_t opts;
+uint32_t opts;
 static struct bootinfo bootinfo;
 #if SERIAL
 static int comspeed = SIOSPD;

From 1def741dc225d64b4a5b9f6ef7a3fb0b865294f5 Mon Sep 17 00:00:00 2001
From: imp <imp@FreeBSD.org>
Date: Tue, 26 Jan 2016 18:39:31 +0000
Subject: [PATCH 042/113] Default NANO_DRIVE to ada0 not ad0. This shouldn't
 affect working configs (since they'd have to change NANO_DRIVE to be ada0 to
 work), but will fix old ones that used to work.

MFC After: 1 week
---
 tools/tools/nanobsd/defaults.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/tools/nanobsd/defaults.sh b/tools/tools/nanobsd/defaults.sh
index 3534ba248244..8084bfaf0fcb 100755
--- a/tools/tools/nanobsd/defaults.sh
+++ b/tools/tools/nanobsd/defaults.sh
@@ -93,7 +93,7 @@ NANO_LATE_CUSTOMIZE=""
 NANO_NEWFS="-b 4096 -f 512 -i 8192 -U"
 
 # The drive name of the media at runtime
-NANO_DRIVE=ad0
+NANO_DRIVE=ada0
 
 # Target media size in 512 bytes sectors
 NANO_MEDIASIZE=2000000

From cd4a0ee266068abaf08833b8d76b0ad8b0cea721 Mon Sep 17 00:00:00 2001
From: jhb <jhb@FreeBSD.org>
Date: Tue, 26 Jan 2016 19:07:09 +0000
Subject: [PATCH 043/113] Add support to libsysdecode for decoding system call
 names.

A new sysdecode_syscallname() function accepts a system call code and
returns a string of the corresponding name (or NULL if the code is
unknown).  To support different process ABIs, the new function accepts a
value from a new sysdecode_abi enum as its first argument to select the
ABI in use.  Current ABIs supported include FREEBSD (native binaries),
FREEBSD32, LINUX, LINUX32, and CLOUDABI64.  Note that not all ABIs are
supported by all platforms.  In general, a given ABI is only supported
if a platform can execute binaries for that ABI.

To simplify the implementation, libsysdecode's build reuses the
existing pre-generated files from the kernel source tree rather than
duplicating new copies of said files during the build.

kdump(1) and truss(1) now use these functions to map system call
identifiers to names.  For kdump(1), a new 'syscallname()' function
consolidates duplicated code from ktrsyscall() and ktrsyscallret().
The Linux ABI no longer requires custom handling for ktrsyscall() and
linux_ktrsyscall() has been removed as a result.

Reviewed by:	bdrewery
Differential Revision:	https://reviews.freebsd.org/D4823
---
 lib/libsysdecode/Makefile                 |   9 +-
 lib/libsysdecode/syscallnames.c           | 105 +++++++++++++++++
 lib/libsysdecode/sysdecode.3              |  28 ++++-
 lib/libsysdecode/sysdecode.h              |  10 ++
 lib/libsysdecode/sysdecode_syscallnames.3 |  67 +++++++++++
 usr.bin/kdump/Makefile                    |  19 ---
 usr.bin/kdump/kdump.c                     | 136 ++++++++--------------
 usr.bin/truss/Makefile                    |  23 +---
 usr.bin/truss/aarch64-cloudabi64.c        |   5 +-
 usr.bin/truss/aarch64-freebsd.c           |   6 +-
 usr.bin/truss/amd64-cloudabi64.c          |   5 +-
 usr.bin/truss/amd64-freebsd.c             |   6 +-
 usr.bin/truss/amd64-freebsd32.c           |   9 +-
 usr.bin/truss/amd64-linux32.c             |   6 +-
 usr.bin/truss/arm-freebsd.c               |   6 +-
 usr.bin/truss/i386-freebsd.c              |   9 +-
 usr.bin/truss/i386-linux.c                |   6 +-
 usr.bin/truss/main.c                      |   1 +
 usr.bin/truss/mips-freebsd.c              |   6 +-
 usr.bin/truss/powerpc-freebsd.c           |   6 +-
 usr.bin/truss/powerpc64-freebsd.c         |   6 +-
 usr.bin/truss/powerpc64-freebsd32.c       |   6 +-
 usr.bin/truss/setup.c                     |   4 +-
 usr.bin/truss/sparc64-freebsd.c           |   6 +-
 usr.bin/truss/truss.h                     |   3 +-
 25 files changed, 300 insertions(+), 193 deletions(-)
 create mode 100644 lib/libsysdecode/syscallnames.c
 create mode 100644 lib/libsysdecode/sysdecode_syscallnames.3

diff --git a/lib/libsysdecode/Makefile b/lib/libsysdecode/Makefile
index a6d3ba13961c..e1e69fef64e8 100644
--- a/lib/libsysdecode/Makefile
+++ b/lib/libsysdecode/Makefile
@@ -4,11 +4,14 @@
 
 LIB=	sysdecode
 
-SRCS=	ioctl.c utrace.c
+SRCS=	ioctl.c syscallnames.c utrace.c
 INCS=	sysdecode.h
 
+CFLAGS+= -I${.CURDIR}/../../sys
+
 MAN+=	sysdecode.3 \
 	sysdecode_ioctlname.3 \
+	sysdecode_syscallnames.3 \
 	sysdecode_utrace.3
 
 CLEANFILES= ioctl.c
@@ -23,6 +26,10 @@ CFLAGS+=-DPF
 
 # Workaround duplicate declarations in <netinet/ip_compat.h>
 CFLAGS.gcc.ioctl.c+= -Wno-redundant-decls
+
+# Workaround warning for unused ssi_cables[] in <dev/lmc/if_lmc.h>
+CFLAGS.gcc.ioctl.c+= -Wno-unused
+
 CFLAGS.gcc+=	${CFLAGS.gcc.${.IMPSRC}}
 
 ioctl.c: mkioctls
diff --git a/lib/libsysdecode/syscallnames.c b/lib/libsysdecode/syscallnames.c
new file mode 100644
index 000000000000..cfe50a6a6ea9
--- /dev/null
+++ b/lib/libsysdecode/syscallnames.c
@@ -0,0 +1,105 @@
+/*-
+ * Copyright (c) 2015 John H. Baldwin <jhb@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * Map system call codes to names for the supported ABIs on each
+ * platform.  Rather than regnerating system call name tables locally
+ * during the build, use the generated tables in the kernel source
+ * tree.
+ */
+
+#include <sys/param.h>
+#include <stdio.h>
+#include <sysdecode.h>
+
+static
+#include <kern/syscalls.c>
+
+#if defined(__amd64__) || defined(__powerpc64__)
+static
+#include <compat/freebsd32/freebsd32_syscalls.c>
+#endif
+
+#if defined(__amd64__) || defined(__i386__)
+static
+#ifdef __amd64__
+#include <amd64/linux/linux_syscalls.c>
+#else
+#include <i386/linux/linux_syscalls.c>
+#endif
+#endif
+
+#ifdef __amd64__
+static
+#include <amd64/linux32/linux32_syscalls.c>
+#endif
+
+#if defined(__amd64__) || defined(__aarch64__)
+static
+#include <compat/cloudabi64/cloudabi64_syscalls.c>
+#endif
+
+const char *
+sysdecode_syscallname(enum sysdecode_abi abi, unsigned int code)
+{
+
+	switch (abi) {
+	case FREEBSD:
+		if (code < nitems(syscallnames))
+			return (syscallnames[code]);
+		break;
+#if defined(__amd64__) || defined(__powerpc64__)
+	case FREEBSD32:
+		if (code < nitems(freebsd32_syscallnames))
+			return (freebsd32_syscallnames[code]);
+		break;
+#endif
+#if defined(__amd64__) || defined(__i386__)
+	case LINUX:
+		if (code < nitems(linux_syscallnames))
+			return (linux_syscallnames[code]);
+		break;
+#endif
+#ifdef __amd64__
+	case LINUX32:
+		if (code < nitems(linux32_syscallnames))
+			return (linux32_syscallnames[code]);
+		break;
+#endif
+#if defined(__amd64__) || defined(__aarch64__)
+	case CLOUDABI64:
+		if (code < nitems(cloudabi64_syscallnames))
+			return (cloudabi64_syscallnames[code]);
+		break;
+#endif
+	default:
+		break;
+	}
+	return (NULL);
+}
diff --git a/lib/libsysdecode/sysdecode.3 b/lib/libsysdecode/sysdecode.3
index 52faf5373dc9..994d278fe001 100644
--- a/lib/libsysdecode/sysdecode.3
+++ b/lib/libsysdecode/sysdecode.3
@@ -25,7 +25,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd December 10, 2015
+.Dd January 24, 2016
 .Dt SYSDECODE 3
 .Os
 .Sh NAME
@@ -38,8 +38,34 @@ The
 .Nm
 library includes several functions that provide descriptive names of
 values associated with system calls.
+.Ss Supported ABIs
+Some functions in this library provide ABI-specific descriptions.
+The supported ABIs are named by the
+.Vt enum sysdecode_abi
+enumeration.
+.Pp
+.Bl -tag -width "Li UNKNOWN_ABI" -compact
+.It Li FREEBSD
+Native FreeBSD binaries.
+Supported on all platforms.
+.It Li FREEBSD32
+32-bit FreeBSD binaries.
+Supported on amd64 and powerpc64.
+.It Li LINUX
+Linux binaries of the same platform.
+Supported on amd64 and i386.
+.It Li LINUX32
+32-bit Linux binaries.
+Supported on amd64.
+.It Li CLOUDABI64
+64-bit CloudABI binaries.
+Supported on aarch64 and amd64.
+.It Li UNKNOWN_ABI
+A placeholder for use when the ABI is not known.
+.El
 .Sh SEE ALSO
 .Xr sysdecode_ioctlname 3 ,
+.Xr sysdecode_syscallnames 3 ,
 .Xr sysdecode_utrace 3
 .Sh HISTORY
 The
diff --git a/lib/libsysdecode/sysdecode.h b/lib/libsysdecode/sysdecode.h
index aa95838e78d7..c2c3a9e801e5 100644
--- a/lib/libsysdecode/sysdecode.h
+++ b/lib/libsysdecode/sysdecode.h
@@ -29,7 +29,17 @@
 #ifndef __SYSDECODE_H__
 #define	__SYSDECODE_H__
 
+enum sysdecode_abi {
+	UNKNOWN_ABI = 0,
+	FREEBSD,
+	FREEBSD32,
+	LINUX,
+	LINUX32,
+	CLOUDABI64
+};
+
 const char *sysdecode_ioctlname(unsigned long _val);
+const char *sysdecode_syscallname(enum sysdecode_abi _abi, unsigned int _code);
 int	sysdecode_utrace(FILE *_fp, void *_buf, size_t _len);
 
 #endif /* !__SYSDECODE_H__ */
diff --git a/lib/libsysdecode/sysdecode_syscallnames.3 b/lib/libsysdecode/sysdecode_syscallnames.3
new file mode 100644
index 000000000000..1c75ab6e9d17
--- /dev/null
+++ b/lib/libsysdecode/sysdecode_syscallnames.3
@@ -0,0 +1,67 @@
+.\"
+.\" Copyright (c) 2016 John Baldwin <jhb@FreeBSD.org>
+.\" All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that the following conditions
+.\" are met:
+.\" 1. Redistributions of source code must retain the above copyright
+.\"    notice, this list of conditions and the following disclaimer.
+.\" 2. Redistributions in binary form must reproduce the above copyright
+.\"    notice, this list of conditions and the following disclaimer in the
+.\"    documentation and/or other materials provided with the distribution.
+.\"
+.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+.\" ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+.\" SUCH DAMAGE.
+.\"
+.\" $FreeBSD$
+.\"
+.Dd January 24, 2016
+.Dt sysdecode_syscallnames 3
+.Os
+.Sh NAME
+.Nm sysdecode_syscallnames
+.Nd lookup name of system calls
+.Sh LIBRARY
+.Lb libsysdecode
+.Sh SYNOPSIS
+.Ft const char *
+.Fn sysdecode_syscallnames "enum sysdecode_abi abi" "unsigned int code"
+.Sh DESCRIPTION
+This function returns a pointer to the name of a system call identified by
+.Fa code
+for the process ABI
+.Fa abi .
+If
+.Fa code
+specifies an unknown system call or
+.Fa abi
+is an unsupported ABI,
+.Nm
+returns
+.Dv NULL .
+.Pp
+For the list of supported ABIs,
+see
+.Xr sysdecode 3 .
+.Sh RETURN VALUES
+The
+.Nm
+function returns a pointer to a string on success or
+.Dv NULL
+if either
+.Fa code
+or
+.Fa ABI
+is invalid .
+.Sh SEE ALSO
+.Xr sysdecode 3
diff --git a/usr.bin/kdump/Makefile b/usr.bin/kdump/Makefile
index f149e80fa109..40109f0ca3ab 100644
--- a/usr.bin/kdump/Makefile
+++ b/usr.bin/kdump/Makefile
@@ -19,25 +19,6 @@ NO_WERROR?=	YES
 
 CLEANFILES=	kdump_subr.c kdump_subr.h
 
-.if (${MACHINE_ARCH} == "amd64" || ${MACHINE_ARCH} == "i386")
-beforedepend: linux_syscalls.c
-
-CLEANFILES+=	linux_syscalls.c
-kdump.o: linux_syscalls.c
-linux_syscalls.c:	linux_syscalls.conf
-	sh ${.CURDIR}/../../sys/kern/makesyscalls.sh \
-	    ${.CURDIR}/../../sys/${MACHINE_ARCH}/linux/syscalls.master ${.CURDIR}/linux_syscalls.conf
-.endif
-.if (${MACHINE_ARCH} == "amd64")
-beforedepend: linux32_syscalls.c
-
-CLEANFILES+=	linux32_syscalls.c
-kdump.o: linux32_syscalls.c
-linux32_syscalls.c: linux32_syscalls.conf
-	sh ${.CURDIR}/../../sys/kern/makesyscalls.sh \
-	    ${.CURDIR}/../../sys/${MACHINE_ARCH}/linux32/syscalls.master ${.CURDIR}/linux32_syscalls.conf
-.endif
-
 kdump_subr.h: mksubr
 	sh ${.CURDIR}/mksubr ${DESTDIR}${INCLUDEDIR} | \
 	    sed -n 's/^\([a-z].*)\)$$/void \1;/p' >${.TARGET}
diff --git a/usr.bin/kdump/kdump.c b/usr.bin/kdump/kdump.c
index 7af99fb58659..d4406545fc4d 100644
--- a/usr.bin/kdump/kdump.c
+++ b/usr.bin/kdump/kdump.c
@@ -122,8 +122,7 @@ void usage(void);
 #define	TIMESTAMP_ELAPSED	0x2
 #define	TIMESTAMP_RELATIVE	0x4
 
-extern const char *signames[], *syscallnames[];
-extern int nsyscalls;
+extern const char *signames[];
 
 static int timestamp, decimal, fancy = 1, suppressdata, tail, threads, maxdata,
     resolv = 0, abiflag = 0, syscallno = 0;
@@ -145,11 +144,7 @@ static struct ktr_header ktr_header;
 
 #if defined(__amd64__) || defined(__i386__)
 
-void linux_ktrsyscall(struct ktr_syscall *, u_int);
 void linux_ktrsysret(struct ktr_sysret *, u_int);
-extern const char *linux_syscallnames[];
-
-#include <linux_syscalls.c>
 
 /*
  * from linux.h
@@ -169,12 +164,6 @@ static int bsd_to_linux_errno[ELAST + 1] = {
 };
 #endif
 
-#if defined(__amd64__)
-extern const char *linux32_syscallnames[];
-
-#include <linux32_syscalls.c>
-#endif
-
 struct proc_info
 {
 	TAILQ_ENTRY(proc_info)	info;
@@ -401,13 +390,7 @@ main(int argc, char *argv[])
 		drop_logged = 0;
 		switch (ktr_header.ktr_type) {
 		case KTR_SYSCALL:
-#if defined(__amd64__) || defined(__i386__)
-			if ((sv_flags & SV_ABI_MASK) == SV_ABI_LINUX)
-				linux_ktrsyscall((struct ktr_syscall *)m,
-				    sv_flags);
-			else
-#endif
-				ktrsyscall((struct ktr_syscall *)m, sv_flags);
+			ktrsyscall((struct ktr_syscall *)m, sv_flags);
 			break;
 		case KTR_SYSRET:
 #if defined(__amd64__) || defined(__i386__)
@@ -687,10 +670,6 @@ dumpheader(struct ktr_header *kth)
 }
 
 #include <sys/syscall.h>
-#define KTRACE
-#include <sys/kern/syscalls.c>
-#undef KTRACE
-int nsyscalls = sizeof (syscallnames) / sizeof (syscallnames[0]);
 
 static void
 ioctlname(unsigned long val)
@@ -706,26 +685,57 @@ ioctlname(unsigned long val)
 		printf("%#lx", val);
 }
 
+static enum sysdecode_abi
+syscallabi(u_int sv_flags)
+{
+
+	if (sv_flags == 0)
+		return (FREEBSD);
+	switch (sv_flags & SV_ABI_MASK) {
+	case SV_ABI_FREEBSD:
+		return (FREEBSD);
+#if defined(__amd64__) || defined(__i386__)
+	case SV_ABI_LINUX:
+#ifdef __amd64__
+		if (sv_flags & SV_ILP32)
+			return (LINUX32);
+#endif
+		return (LINUX);
+#endif
+	default:
+		return (UNKNOWN_ABI);
+	}
+}
+
+static void
+syscallname(u_int code, u_int sv_flags)
+{
+	const char *name;
+
+	name = sysdecode_syscallname(syscallabi(sv_flags), code);
+	if (name == NULL)
+		printf("[%d]", code);
+	else {
+		printf("%s", name);
+		if (syscallno)
+			printf("[%d]", code);
+	}
+}
+
 void
-ktrsyscall(struct ktr_syscall *ktr, u_int flags)
+ktrsyscall(struct ktr_syscall *ktr, u_int sv_flags)
 {
 	int narg = ktr->ktr_narg;
 	register_t *ip;
 	intmax_t arg;
 
-	if ((flags != 0 && ((flags & SV_ABI_MASK) != SV_ABI_FREEBSD)) ||
-	    (ktr->ktr_code >= nsyscalls || ktr->ktr_code < 0))
-		printf("[%d]", ktr->ktr_code);
-	else {
-		printf("%s", syscallnames[ktr->ktr_code]);
-		if (syscallno)
-			printf("[%d]", ktr->ktr_code);
-	}
+	syscallname(ktr->ktr_code, sv_flags);
 	ip = &ktr->ktr_args[0];
 	if (narg) {
 		char c = '(';
 		if (fancy &&
-		    (flags == 0 || (flags & SV_ABI_MASK) == SV_ABI_FREEBSD)) {
+		    (sv_flags == 0 ||
+		    (sv_flags & SV_ABI_MASK) == SV_ABI_FREEBSD)) {
 			switch (ktr->ktr_code) {
 			case SYS_bindat:
 			case SYS_connectat:
@@ -1332,21 +1342,13 @@ ktrsyscall(struct ktr_syscall *ktr, u_int flags)
 }
 
 void
-ktrsysret(struct ktr_sysret *ktr, u_int flags)
+ktrsysret(struct ktr_sysret *ktr, u_int sv_flags)
 {
 	register_t ret = ktr->ktr_retval;
 	int error = ktr->ktr_error;
-	int code = ktr->ktr_code;
 
-	if ((flags != 0 && ((flags & SV_ABI_MASK) != SV_ABI_FREEBSD)) ||
-	    (code >= nsyscalls || code < 0))
-		printf("[%d] ", code);
-	else {
-		printf("%s", syscallnames[code]);
-		if (syscallno)
-			printf("[%d]", code);
-		printf(" ");
-	}
+	syscallname(ktr->ktr_code, sv_flags);
+	printf(" ");
 
 	if (error == 0) {
 		if (fancy) {
@@ -1851,56 +1853,14 @@ ktrfaultend(struct ktr_faultend *ktr)
 }
 
 #if defined(__amd64__) || defined(__i386__)
-
-#if defined(__amd64__)
-#define	NLINUX_SYSCALLS(v)		((v) & SV_ILP32 ?		\
-	    nitems(linux32_syscallnames) : nitems(linux_syscallnames))
-#define	LINUX_SYSCALLNAMES(v, i)	((v) & SV_ILP32 ?		\
-	    linux32_syscallnames[i] : linux_syscallnames[i])
-#else
-#define	NLINUX_SYSCALLS(v)		(nitems(linux_syscallnames))
-#define	LINUX_SYSCALLNAMES(v, i)	(linux_syscallnames[i])
-#endif
-
-void
-linux_ktrsyscall(struct ktr_syscall *ktr, u_int sv_flags)
-{
-	int narg = ktr->ktr_narg;
-	unsigned code = ktr->ktr_code;
-	register_t *ip;
-
-	if (ktr->ktr_code < 0 || code >= NLINUX_SYSCALLS(sv_flags))
-		printf("[%d]", ktr->ktr_code);
-	else {
-		printf("%s", LINUX_SYSCALLNAMES(sv_flags, ktr->ktr_code));
-		if (syscallno)
-			printf("[%d]", ktr->ktr_code);
-	}
-	ip = &ktr->ktr_args[0];
-	if (narg) {
-		char c = '(';
-		while (narg > 0)
-			print_number(ip, narg, c);
-		putchar(')');
-	}
-	putchar('\n');
-}
-
 void
 linux_ktrsysret(struct ktr_sysret *ktr, u_int sv_flags)
 {
 	register_t ret = ktr->ktr_retval;
-	unsigned code = ktr->ktr_code;
 	int error = ktr->ktr_error;
 
-	if (ktr->ktr_code < 0 || code >= NLINUX_SYSCALLS(sv_flags))
-		printf("[%d] ", ktr->ktr_code);
-	else {
-		printf("%s ", LINUX_SYSCALLNAMES(sv_flags, code));
-		if (syscallno)
-			printf("[%d]", code);
-		printf(" ");
-	}
+	syscallname(ktr->ktr_code, sv_flags);
+	printf(" ");
 
 	if (error == 0) {
 		if (fancy) {
diff --git a/usr.bin/truss/Makefile b/usr.bin/truss/Makefile
index a6e45243e180..b28098c802a8 100644
--- a/usr.bin/truss/Makefile
+++ b/usr.bin/truss/Makefile
@@ -8,13 +8,6 @@ LIBADD=	sysdecode
 
 CFLAGS+= -I${.CURDIR} -I. -I${.CURDIR}/../../sys
 
-# Define where to generate syscalls for each ABI.
-ABI_SYSPATH.freebsd=		sys/kern
-ABI_SYSPATH.freebsd32=		sys/compat/freebsd32
-ABI_SYSPATH.cloudabi64=		sys/compat/cloudabi64
-ABI_SYSPATH.i386-linux=		sys/i386/linux
-ABI_SYSPATH.amd64-linux32=	sys/amd64/linux32
-
 ABIS+=		freebsd
 # Each ABI is expected to have an ABI.c, MACHINE_ARCH-ABI.c or
 # MACHINE_CPUARCH-ABI.c file that will be used to map the syscall arguments.
@@ -42,21 +35,7 @@ ABI_SRCS=	${abi}.c ${MACHINE_ARCH}-${abi}.c ${MACHINE_CPUARCH}-${abi}.c
 abi_src=	${f}
 .endif
 .endfor
-SRCS:=		${SRCS} ${abi_src} ${abi}_syscalls.h
-CLEANFILES+=	${abi}_syscalls.conf ${abi}_syscalls.master ${abi}_syscalls.h
-${abi}_syscalls.conf: ${.CURDIR}/makesyscallsconf.sh
-	/bin/sh ${.CURDIR}/makesyscallsconf.sh ${abi} ${.TARGET}
-
-${abi}_syscalls.master:	${.CURDIR:H:H}/${ABI_SYSPATH.${abi}}/syscalls.master
-	cp -f ${.ALLSRC} ${.TARGET}
-
-${abi}_syscalls.h:	${abi}_syscalls.master ${abi}_syscalls.conf \
-			${.CURDIR:H:H}/sys/kern/makesyscalls.sh
-	/bin/sh ${.CURDIR:H:H}/sys/kern/makesyscalls.sh \
-	    ${abi}_syscalls.master ${abi}_syscalls.conf
-# Eliminate compiler warning about non-static global.
-	sed -i '' '/^const char \*/s/^/static /' ${.TARGET}.tmp
-	mv ${.TARGET}.tmp ${.TARGET}
+SRCS:=		${SRCS} ${abi_src}
 .endfor
 
 .include <bsd.prog.mk>
diff --git a/usr.bin/truss/aarch64-cloudabi64.c b/usr.bin/truss/aarch64-cloudabi64.c
index ad6afc260b5e..099cb1e7d746 100644
--- a/usr.bin/truss/aarch64-cloudabi64.c
+++ b/usr.bin/truss/aarch64-cloudabi64.c
@@ -33,9 +33,9 @@ __FBSDID("$FreeBSD$");
 
 #include <errno.h>
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "cloudabi.h"
-#include "cloudabi64_syscalls.h"
 #include "truss.h"
 
 static int
@@ -81,8 +81,7 @@ aarch64_cloudabi64_fetch_retval(struct trussinfo *trussinfo, long *retval,
 
 static struct procabi aarch64_cloudabi64 = {
 	"CloudABI ELF64",
-	syscallnames,
-	nitems(syscallnames),
+	CLOUDABI64,
 	aarch64_cloudabi64_fetch_args,
 	aarch64_cloudabi64_fetch_retval
 };
diff --git a/usr.bin/truss/aarch64-freebsd.c b/usr.bin/truss/aarch64-freebsd.c
index 1ec2b66c9f60..454bba7d77ca 100644
--- a/usr.bin/truss/aarch64-freebsd.c
+++ b/usr.bin/truss/aarch64-freebsd.c
@@ -39,11 +39,10 @@ __FBSDID("$FreeBSD$");
 #include <machine/ucontext.h>
 
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "freebsd_syscalls.h"
-
 static int
 aarch64_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -100,8 +99,7 @@ aarch64_fetch_retval(struct trussinfo *trussinfo, long *retval, int *errorp)
 
 static struct procabi aarch64_freebsd = {
 	"FreeBSD ELF64",
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD,
 	aarch64_fetch_args,
 	aarch64_fetch_retval
 };
diff --git a/usr.bin/truss/amd64-cloudabi64.c b/usr.bin/truss/amd64-cloudabi64.c
index 5982b66b4aeb..38768ff0074d 100644
--- a/usr.bin/truss/amd64-cloudabi64.c
+++ b/usr.bin/truss/amd64-cloudabi64.c
@@ -33,9 +33,9 @@ __FBSDID("$FreeBSD$");
 
 #include <errno.h>
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "cloudabi.h"
-#include "cloudabi64_syscalls.h"
 #include "truss.h"
 
 static int
@@ -90,8 +90,7 @@ amd64_cloudabi64_fetch_retval(struct trussinfo *trussinfo, long *retval,
 
 static struct procabi amd64_cloudabi64 = {
 	"CloudABI ELF64",
-	syscallnames,
-	nitems(syscallnames),
+	CLOUDABI64,
 	amd64_cloudabi64_fetch_args,
 	amd64_cloudabi64_fetch_retval
 };
diff --git a/usr.bin/truss/amd64-freebsd.c b/usr.bin/truss/amd64-freebsd.c
index 0461616100f4..8a211a0ce474 100644
--- a/usr.bin/truss/amd64-freebsd.c
+++ b/usr.bin/truss/amd64-freebsd.c
@@ -41,11 +41,10 @@ __FBSDID("$FreeBSD$");
 #include <machine/psl.h>
 
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "freebsd_syscalls.h"
-
 static int
 amd64_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -122,8 +121,7 @@ amd64_fetch_retval(struct trussinfo *trussinfo, long *retval, int *errorp)
 
 static struct procabi amd64_freebsd = {
 	"FreeBSD ELF64",
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD,
 	amd64_fetch_args,
 	amd64_fetch_retval
 };
diff --git a/usr.bin/truss/amd64-freebsd32.c b/usr.bin/truss/amd64-freebsd32.c
index 82eb6cd59c45..adce798b7c5c 100644
--- a/usr.bin/truss/amd64-freebsd32.c
+++ b/usr.bin/truss/amd64-freebsd32.c
@@ -42,11 +42,10 @@ __FBSDID("$FreeBSD$");
 
 #include <stdio.h>
 #include <stdlib.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "freebsd32_syscalls.h"
-
 static int
 amd64_freebsd32_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -118,8 +117,7 @@ amd64_freebsd32_fetch_retval(struct trussinfo *trussinfo, long *retval,
 
 static struct procabi amd64_freebsd32 = {
 	"FreeBSD ELF32",
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD32,
 	amd64_freebsd32_fetch_args,
 	amd64_freebsd32_fetch_retval
 };
@@ -128,8 +126,7 @@ PROCABI(amd64_freebsd32);
 
 static struct procabi amd64_freebsd32_aout = {
 	"FreeBSD a.out",
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD32,
 	amd64_freebsd32_fetch_args,
 	amd64_freebsd32_fetch_retval
 };
diff --git a/usr.bin/truss/amd64-linux32.c b/usr.bin/truss/amd64-linux32.c
index 17e5fdc2b29a..dd1d83361095 100644
--- a/usr.bin/truss/amd64-linux32.c
+++ b/usr.bin/truss/amd64-linux32.c
@@ -40,11 +40,10 @@ __FBSDID("$FreeBSD$");
 #include <machine/psl.h>
 
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "amd64-linux32_syscalls.h"
-
 static int
 amd64_linux32_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -132,8 +131,7 @@ amd64_linux32_fetch_retval(struct trussinfo *trussinfo, long *retval,
 
 static struct procabi amd64_linux32 = {
 	"Linux ELF32",
-	syscallnames,
-	nitems(syscallnames),
+	LINUX32,
 	amd64_linux32_fetch_args,
 	amd64_linux32_fetch_retval
 };
diff --git a/usr.bin/truss/arm-freebsd.c b/usr.bin/truss/arm-freebsd.c
index aa7bcccd5c3f..5722c91442fb 100644
--- a/usr.bin/truss/arm-freebsd.c
+++ b/usr.bin/truss/arm-freebsd.c
@@ -42,11 +42,10 @@ __FBSDID("$FreeBSD$");
 #include <machine/ucontext.h>
 
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "freebsd_syscalls.h"
-
 static int
 arm_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -129,8 +128,7 @@ arm_fetch_retval(struct trussinfo *trussinfo, long *retval, int *errorp)
 
 static struct procabi arm_freebsd = {
 	"FreeBSD ELF32",
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD,
 	arm_fetch_args,
 	arm_fetch_retval
 };
diff --git a/usr.bin/truss/i386-freebsd.c b/usr.bin/truss/i386-freebsd.c
index d9d72aa28589..c166596dcb11 100644
--- a/usr.bin/truss/i386-freebsd.c
+++ b/usr.bin/truss/i386-freebsd.c
@@ -41,11 +41,10 @@ __FBSDID("$FreeBSD$");
 #include <machine/psl.h>
 
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "freebsd_syscalls.h"
-
 static int
 i386_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -111,8 +110,7 @@ i386_fetch_retval(struct trussinfo *trussinfo, long *retval, int *errorp)
 
 static struct procabi i386_freebsd = {
 	"FreeBSD ELF32",
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD,
 	i386_fetch_args,
 	i386_fetch_retval
 };
@@ -121,8 +119,7 @@ PROCABI(i386_freebsd);
 
 static struct procabi i386_freebsd_aout = {
 	"FreeBSD a.out",
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD,
 	i386_fetch_args,
 	i386_fetch_retval
 };
diff --git a/usr.bin/truss/i386-linux.c b/usr.bin/truss/i386-linux.c
index 91662711676b..5fdae8ee958c 100644
--- a/usr.bin/truss/i386-linux.c
+++ b/usr.bin/truss/i386-linux.c
@@ -40,11 +40,10 @@ __FBSDID("$FreeBSD$");
 #include <machine/psl.h>
 
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "i386-linux_syscalls.h"
-
 static int
 i386_linux_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -131,8 +130,7 @@ i386_linux_fetch_retval(struct trussinfo *trussinfo, long *retval, int *errorp)
 
 static struct procabi i386_linux = {
 	"Linux ELF32",
-	syscallnames,
-	nitems(syscallnames),
+	LINUX,
 	i386_linux_fetch_args,
 	i386_linux_fetch_retval
 };
diff --git a/usr.bin/truss/main.c b/usr.bin/truss/main.c
index 5eec9538f50c..531d7dbb4c12 100644
--- a/usr.bin/truss/main.c
+++ b/usr.bin/truss/main.c
@@ -44,6 +44,7 @@ __FBSDID("$FreeBSD$");
 #include <signal.h>
 #include <stdio.h>
 #include <stdlib.h>
+#include <sysdecode.h>
 #include <time.h>
 #include <unistd.h>
 
diff --git a/usr.bin/truss/mips-freebsd.c b/usr.bin/truss/mips-freebsd.c
index 0c504b88fd63..f4b5a7eb2aa0 100644
--- a/usr.bin/truss/mips-freebsd.c
+++ b/usr.bin/truss/mips-freebsd.c
@@ -41,11 +41,10 @@ __FBSDID("$FreeBSD$");
 #include <machine/reg.h>
 
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "freebsd_syscalls.h"
-
 static int
 mips_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -132,8 +131,7 @@ static struct procabi mips_freebsd = {
 #else
 	"FreeBSD ELF32",
 #endif
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD,
 	mips_fetch_args,
 	mips_fetch_retval
 };
diff --git a/usr.bin/truss/powerpc-freebsd.c b/usr.bin/truss/powerpc-freebsd.c
index 90c3663d3c9c..6a245df76c6a 100644
--- a/usr.bin/truss/powerpc-freebsd.c
+++ b/usr.bin/truss/powerpc-freebsd.c
@@ -37,11 +37,10 @@ __FBSDID("$FreeBSD$");
 #include <machine/frame.h>
 
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "freebsd_syscalls.h"
-
 static int
 powerpc_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -113,8 +112,7 @@ powerpc_fetch_retval(struct trussinfo *trussinfo, long *retval, int *errorp)
 
 static struct procabi powerpc_freebsd = {
 	"FreeBSD ELF32",
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD,
 	powerpc_fetch_args,
 	powerpc_fetch_retval
 };
diff --git a/usr.bin/truss/powerpc64-freebsd.c b/usr.bin/truss/powerpc64-freebsd.c
index fafaa1bde5bf..68a0b5d36abe 100644
--- a/usr.bin/truss/powerpc64-freebsd.c
+++ b/usr.bin/truss/powerpc64-freebsd.c
@@ -37,11 +37,10 @@ __FBSDID("$FreeBSD$");
 #include <machine/frame.h>
 
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "freebsd_syscalls.h"
-
 static int
 powerpc64_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -109,8 +108,7 @@ powerpc64_fetch_retval(struct trussinfo *trussinfo, long *retval, int *errorp)
 
 static struct procabi powerpc64_freebsd = {
 	"FreeBSD ELF64",
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD,
 	powerpc64_fetch_args,
 	powerpc64_fetch_retval
 };
diff --git a/usr.bin/truss/powerpc64-freebsd32.c b/usr.bin/truss/powerpc64-freebsd32.c
index fc0ffb8dbddb..ee37ead3cc11 100644
--- a/usr.bin/truss/powerpc64-freebsd32.c
+++ b/usr.bin/truss/powerpc64-freebsd32.c
@@ -37,11 +37,10 @@ __FBSDID("$FreeBSD$");
 #include <machine/frame.h>
 
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "freebsd32_syscalls.h"
-
 static int
 powerpc64_freebsd32_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -118,8 +117,7 @@ powerpc64_freebsd32_fetch_retval(struct trussinfo *trussinfo, long *retval, int
 
 static struct procabi powerpc64_freebsd32 = {
 	"FreeBSD ELF32",
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD32,
 	powerpc64_freebsd32_fetch_args,
 	powerpc64_freebsd32_fetch_retval
 };
diff --git a/usr.bin/truss/setup.c b/usr.bin/truss/setup.c
index 74678e6ac2df..c0c15f0c7458 100644
--- a/usr.bin/truss/setup.c
+++ b/usr.bin/truss/setup.c
@@ -49,6 +49,7 @@ __FBSDID("$FreeBSD$");
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <sysdecode.h>
 #include <time.h>
 #include <unistd.h>
 
@@ -335,8 +336,7 @@ enter_syscall(struct trussinfo *info, struct ptrace_lwpinfo *pl)
 		return;
 	}
 
-	if (t->cs.number >= 0 && t->cs.number < t->proc->abi->nsyscalls)
-		t->cs.name = t->proc->abi->syscallnames[t->cs.number];
+	t->cs.name = sysdecode_syscallname(t->proc->abi->abi, t->cs.number);
 	if (t->cs.name == NULL)
 		fprintf(info->outfile, "-- UNKNOWN %s SYSCALL %d --\n",
 		    t->proc->abi->type, t->cs.number);
diff --git a/usr.bin/truss/sparc64-freebsd.c b/usr.bin/truss/sparc64-freebsd.c
index a4dba92e63e7..23486d76baa4 100644
--- a/usr.bin/truss/sparc64-freebsd.c
+++ b/usr.bin/truss/sparc64-freebsd.c
@@ -43,11 +43,10 @@ __FBSDID("$FreeBSD$");
 
 #include <stddef.h>
 #include <stdio.h>
+#include <sysdecode.h>
 
 #include "truss.h"
 
-#include "freebsd_syscalls.h"
-
 static int
 sparc64_fetch_args(struct trussinfo *trussinfo, u_int narg)
 {
@@ -116,8 +115,7 @@ sparc64_fetch_retval(struct trussinfo *trussinfo, long *retval, int *errorp)
 
 static struct procabi sparc64_freebsd = {
 	"FreeBSD ELF64",
-	syscallnames,
-	nitems(syscallnames),
+	FREEBSD,
 	sparc64_fetch_args,
 	sparc64_fetch_retval
 };
diff --git a/usr.bin/truss/truss.h b/usr.bin/truss/truss.h
index 5a57de7003c1..5ef24447c25a 100644
--- a/usr.bin/truss/truss.h
+++ b/usr.bin/truss/truss.h
@@ -41,8 +41,7 @@ struct trussinfo;
 
 struct procabi {
 	const char *type;
-	const char **syscallnames;
-	int nsyscalls;
+	enum sysdecode_abi abi;
 	int (*fetch_args)(struct trussinfo *, u_int);
 	int (*fetch_retval)(struct trussinfo *, long *, int *);
 };

From fe646209558875d3dc38bed64fe8e78e8b146203 Mon Sep 17 00:00:00 2001
From: jhb <jhb@FreeBSD.org>
Date: Tue, 26 Jan 2016 21:24:49 +0000
Subject: [PATCH 044/113] Various style fixes.

- Wrap long lines.
- Fix indentation.
- Remove excessive parens.
- Whitespace fixes in struct definitions.

Reviewed by:	kib
Differential Revision:	https://reviews.freebsd.org/D5025
---
 sys/kern/vfs_aio.c | 75 ++++++++++++++++++++++++----------------------
 1 file changed, 40 insertions(+), 35 deletions(-)

diff --git a/sys/kern/vfs_aio.c b/sys/kern/vfs_aio.c
index 1d99a566abb1..14a66c3bb7d7 100644
--- a/sys/kern/vfs_aio.c
+++ b/sys/kern/vfs_aio.c
@@ -125,17 +125,16 @@ FEATURE(aio, "Asynchronous I/O");
 
 static MALLOC_DEFINE(M_LIO, "lio", "listio aio control block list");
 
-static SYSCTL_NODE(_vfs, OID_AUTO, aio, CTLFLAG_RW, 0, "Async IO management");
+static SYSCTL_NODE(_vfs, OID_AUTO, aio, CTLFLAG_RW, 0,
+    "Async IO management");
 
 static int max_aio_procs = MAX_AIO_PROCS;
-SYSCTL_INT(_vfs_aio, OID_AUTO, max_aio_procs,
-	CTLFLAG_RW, &max_aio_procs, 0,
-	"Maximum number of kernel processes to use for handling async IO ");
+SYSCTL_INT(_vfs_aio, OID_AUTO, max_aio_procs, CTLFLAG_RW, &max_aio_procs, 0,
+    "Maximum number of kernel processes to use for handling async IO ");
 
 static int num_aio_procs = 0;
-SYSCTL_INT(_vfs_aio, OID_AUTO, num_aio_procs,
-	CTLFLAG_RD, &num_aio_procs, 0,
-	"Number of presently active kernel processes for async IO");
+SYSCTL_INT(_vfs_aio, OID_AUTO, num_aio_procs, CTLFLAG_RD, &num_aio_procs, 0,
+    "Number of presently active kernel processes for async IO");
 
 /*
  * The code will adjust the actual number of AIO processes towards this
@@ -143,7 +142,8 @@ SYSCTL_INT(_vfs_aio, OID_AUTO, num_aio_procs,
  */
 static int target_aio_procs = TARGET_AIO_PROCS;
 SYSCTL_INT(_vfs_aio, OID_AUTO, target_aio_procs, CTLFLAG_RW, &target_aio_procs,
-	0, "Preferred number of ready kernel processes for async IO");
+    0,
+    "Preferred number of ready kernel processes for async IO");
 
 static int max_queue_count = MAX_AIO_QUEUE;
 SYSCTL_INT(_vfs_aio, OID_AUTO, max_aio_queue, CTLFLAG_RW, &max_queue_count, 0,
@@ -172,7 +172,8 @@ SYSCTL_INT(_vfs_aio, OID_AUTO, unloadable, CTLFLAG_RW, &unloadable, 0,
 
 static int max_aio_per_proc = MAX_AIO_PER_PROC;
 SYSCTL_INT(_vfs_aio, OID_AUTO, max_aio_per_proc, CTLFLAG_RW, &max_aio_per_proc,
-    0, "Maximum active aio requests per process (stored in the process)");
+    0,
+    "Maximum active aio requests per process (stored in the process)");
 
 static int max_aio_queue_per_proc = MAX_AIO_QUEUE_PER_PROC;
 SYSCTL_INT(_vfs_aio, OID_AUTO, max_aio_queue_per_proc, CTLFLAG_RW,
@@ -231,7 +232,7 @@ struct aiocblist {
 	struct	vm_page *pages[btoc(MAXPHYS)+1]; /* BIO backend pages */
 	int	npages;			/* BIO backend number of pages */
 	struct	proc *userproc;		/* (*) user process */
-	struct  ucred *cred;		/* (*) active credential when created */
+	struct	ucred *cred;		/* (*) active credential when created */
 	struct	file *fd_file;		/* (*) pointer to file structure */
 	struct	aioliojob *lio;		/* (*) optional lio job */
 	struct	aiocb *uuaiocb;		/* (*) pointer in userspace of aiocb */
@@ -254,9 +255,9 @@ struct aiocblist {
 #define AIOP_FREE	0x1			/* proc on free queue */
 
 struct aioproc {
-	int aioprocflags;			/* (c) AIO proc flags */
+	int	aioprocflags;			/* (c) AIO proc flags */
 	TAILQ_ENTRY(aioproc) list;		/* (c) list of processes */
-	struct proc *aioproc;			/* (*) the AIO proc */
+	struct	proc *aioproc;			/* (*) the AIO proc */
 };
 
 /*
@@ -268,7 +269,7 @@ struct aioliojob {
 	int	lioj_finished_count;		/* (a) listio flags */
 	struct	sigevent lioj_signal;		/* (a) signal on all I/O done */
 	TAILQ_ENTRY(aioliojob) lioj_list;	/* (a) lio list */
-	struct  knlist klist;			/* (a) list of knotes */
+	struct	knlist klist;			/* (a) list of knotes */
 	ksiginfo_t lioj_ksi;			/* (a) Realtime signal info */
 };
 
@@ -280,7 +281,7 @@ struct aioliojob {
  * per process aio data structure
  */
 struct kaioinfo {
-	struct mtx	kaio_mtx;	/* the lock to protect this struct */
+	struct	mtx kaio_mtx;		/* the lock to protect this struct */
 	int	kaio_flags;		/* (a) per process kaio flags */
 	int	kaio_maxactive_count;	/* (*) maximum number of AIOs */
 	int	kaio_active_count;	/* (c) number of currently used AIOs */
@@ -288,13 +289,13 @@ struct kaioinfo {
 	int	kaio_count;		/* (a) size of AIO queue */
 	int	kaio_ballowed_count;	/* (*) maximum number of buffers */
 	int	kaio_buffer_count;	/* (a) number of physio buffers */
-	TAILQ_HEAD(,aiocblist) kaio_all;	/* (a) all AIOs in the process */
+	TAILQ_HEAD(,aiocblist) kaio_all;	/* (a) all AIOs in a process */
 	TAILQ_HEAD(,aiocblist) kaio_done;	/* (a) done queue for process */
 	TAILQ_HEAD(,aioliojob) kaio_liojoblist; /* (a) list of lio jobs */
 	TAILQ_HEAD(,aiocblist) kaio_jobqueue;	/* (a) job queue for process */
-	TAILQ_HEAD(,aiocblist) kaio_bufqueue;	/* (a) buffer job queue for process */
+	TAILQ_HEAD(,aiocblist) kaio_bufqueue;	/* (a) buffer job queue */
 	TAILQ_HEAD(,aiocblist) kaio_syncqueue;	/* (a) queue for aio_fsync */
-	struct	task	kaio_task;	/* (*) task to kick aio processes */
+	struct	task kaio_task;		/* (*) task to kick aio processes */
 };
 
 #define AIO_LOCK(ki)		mtx_lock(&(ki)->kaio_mtx)
@@ -303,7 +304,7 @@ struct kaioinfo {
 #define AIO_MTX(ki)		(&(ki)->kaio_mtx)
 
 #define KAIO_RUNDOWN	0x1	/* process is being run down */
-#define KAIO_WAKEUP	0x2	/* wakeup process when there is a significant event */
+#define KAIO_WAKEUP	0x2	/* wakeup process when AIO completes */
 
 /*
  * Operations used to interact with userland aio control blocks.
@@ -333,15 +334,17 @@ static void	aio_process_sync(struct aiocblist *aiocbe);
 static void	aio_process_mlock(struct aiocblist *aiocbe);
 static int	aio_newproc(int *);
 int		aio_aqueue(struct thread *td, struct aiocb *job,
-			struct aioliojob *lio, int type, struct aiocb_ops *ops);
+		    struct aioliojob *lio, int type, struct aiocb_ops *ops);
 static void	aio_physwakeup(struct bio *bp);
 static void	aio_proc_rundown(void *arg, struct proc *p);
-static void	aio_proc_rundown_exec(void *arg, struct proc *p, struct image_params *imgp);
+static void	aio_proc_rundown_exec(void *arg, struct proc *p,
+		    struct image_params *imgp);
 static int	aio_qphysio(struct proc *p, struct aiocblist *iocb);
 static void	aio_daemon(void *param);
 static void	aio_swake_cb(struct socket *, struct sockbuf *);
 static int	aio_unload(void);
-static void	aio_bio_done_notify(struct proc *userp, struct aiocblist *aiocbe, int type);
+static void	aio_bio_done_notify(struct proc *userp,
+		    struct aiocblist *aiocbe, int type);
 #define DONE_BUF	1
 #define DONE_QUEUE	2
 static int	aio_kick(struct proc *userp);
@@ -472,8 +475,8 @@ aio_onceonly(void)
 	aio_swake = &aio_swake_cb;
 	exit_tag = EVENTHANDLER_REGISTER(process_exit, aio_proc_rundown, NULL,
 	    EVENTHANDLER_PRI_ANY);
-	exec_tag = EVENTHANDLER_REGISTER(process_exec, aio_proc_rundown_exec, NULL,
-	    EVENTHANDLER_PRI_ANY);
+	exec_tag = EVENTHANDLER_REGISTER(process_exec, aio_proc_rundown_exec,
+	    NULL, EVENTHANDLER_PRI_ANY);
 	kqueue_add_filteropts(EVFILT_AIO, &aio_filtops);
 	kqueue_add_filteropts(EVFILT_LIO, &lio_filtops);
 	TAILQ_INIT(&aio_freeproc);
@@ -700,7 +703,8 @@ aio_free_entry(struct aiocblist *aiocbe)
 }
 
 static void
-aio_proc_rundown_exec(void *arg, struct proc *p, struct image_params *imgp __unused)
+aio_proc_rundown_exec(void *arg, struct proc *p,
+    struct image_params *imgp __unused)
 {
    	aio_proc_rundown(arg, p);
 }
@@ -819,8 +823,8 @@ aio_selectjob(struct aioproc *aiop)
 }
 
 /*
- *  Move all data to a permanent storage device, this code
- *  simulates fsync syscall.
+ * Move all data to a permanent storage device.  This code
+ * simulates the fsync syscall.
  */
 static int
 aio_fsync_vnode(struct thread *td, struct vnode *vp)
@@ -1027,7 +1031,8 @@ aio_bio_done_notify(struct proc *userp, struct aiocblist *aiocbe, int type)
 				if (--scb->pending == 0) {
 					mtx_lock(&aio_job_mtx);
 					scb->jobstate = JOBST_JOBQGLOBAL;
-					TAILQ_REMOVE(&ki->kaio_syncqueue, scb, list);
+					TAILQ_REMOVE(&ki->kaio_syncqueue, scb,
+					    list);
 					TAILQ_INSERT_TAIL(&aio_jobs, scb, list);
 					aio_kick_nowait(userp);
 					mtx_unlock(&aio_job_mtx);
@@ -1788,9 +1793,9 @@ aio_kick_nowait(struct proc *userp)
 		TAILQ_REMOVE(&aio_freeproc, aiop, list);
 		aiop->aioprocflags &= ~AIOP_FREE;
 		wakeup(aiop->aioproc);
-	} else if (((num_aio_resv_start + num_aio_procs) < max_aio_procs) &&
-	    ((ki->kaio_active_count + num_aio_resv_start) <
-	    ki->kaio_maxactive_count)) {
+	} else if (num_aio_resv_start + num_aio_procs < max_aio_procs &&
+	    ki->kaio_active_count + num_aio_resv_start <
+	    ki->kaio_maxactive_count) {
 		taskqueue_enqueue(taskqueue_aiod_kick, &ki->kaio_task);
 	}
 }
@@ -1808,9 +1813,9 @@ aio_kick(struct proc *userp)
 		TAILQ_REMOVE(&aio_freeproc, aiop, list);
 		aiop->aioprocflags &= ~AIOP_FREE;
 		wakeup(aiop->aioproc);
-	} else if (((num_aio_resv_start + num_aio_procs) < max_aio_procs) &&
-	    ((ki->kaio_active_count + num_aio_resv_start) <
-	    ki->kaio_maxactive_count)) {
+	} else if (num_aio_resv_start + num_aio_procs < max_aio_procs &&
+	    ki->kaio_active_count + num_aio_resv_start <
+	    ki->kaio_maxactive_count) {
 		num_aio_resv_start++;
 		mtx_unlock(&aio_job_mtx);
 		error = aio_newproc(&num_aio_resv_start);
@@ -2643,8 +2648,8 @@ typedef struct aiocb32 {
 	uint32_t __spare2__;
 	int	aio_lio_opcode;		/* LIO opcode */
 	int	aio_reqprio;		/* Request priority -- ignored */
-	struct __aiocb_private32 _aiocb_private;
-	struct sigevent32 aio_sigevent;	/* Signal to deliver */
+	struct	__aiocb_private32 _aiocb_private;
+	struct	sigevent32 aio_sigevent;	/* Signal to deliver */
 } aiocb32_t;
 
 static int

From 9d75f130a36668f0047128ee0c2f2d7bde39f09c Mon Sep 17 00:00:00 2001
From: davidcs <davidcs@FreeBSD.org>
Date: Tue, 26 Jan 2016 22:32:58 +0000
Subject: [PATCH 045/113] Upgrade FW to 5.4.56 Update driver version to 3.10.26

---
 sys/dev/qlxgbe/ql_fw.c  | 295670 ++++++++++++++++++-------------------
 sys/dev/qlxgbe/ql_ver.h |      2 +-
 2 files changed, 147833 insertions(+), 147839 deletions(-)

diff --git a/sys/dev/qlxgbe/ql_fw.c b/sys/dev/qlxgbe/ql_fw.c
index c5e4848f8a9e..0160c422ff78 100644
--- a/sys/dev/qlxgbe/ql_fw.c
+++ b/sys/dev/qlxgbe/ql_fw.c
@@ -35,31 +35,31 @@ __FBSDID("$FreeBSD$");
 
 unsigned int ql83xx_firmware_version_major = 5;
 unsigned int ql83xx_firmware_version_minor = 4;
-unsigned int ql83xx_firmware_version_sub = 55;
+unsigned int ql83xx_firmware_version_sub = 56;
 
 unsigned char ql83xx_firmware[] = {
-  0x03, 0x00, 0x40, 0x40, 0x05, 0x04, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0xa4, 0x44, 0x1b, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0xdf, 0xab, 0xb2, 0x6d, 0x14, 0xbc, 0xac, 0x79,
+  0x03, 0x00, 0x40, 0x40, 0x05, 0x04, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x60, 0x44, 0x1b, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x65, 0x29, 0xa5, 0xc3, 0x36, 0x3d, 0x7d, 0x98,
   0x00, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0xe0, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0xea, 0x03, 0x00,
+  0xe0, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0xea, 0x03, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x20, 0x2c, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xef, 0xf3, 0x03, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x45, 0x8f, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xf3, 0x03, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0xf7, 0x8e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x2e, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0x9b, 0x4e, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x34, 0x83, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0xe7, 0x82, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x77, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x65, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x90, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -69,117 +69,117 @@ unsigned char ql83xx_firmware[] = {
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0xab, 0x8d, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x5e, 0x8d, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x7e, 0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0x65, 0x00,
   0x00, 0x00, 0x00, 0x00, 0xd0, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x29, 0xa3, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0x04, 0x00, 0x00,
+  0xdc, 0xa2, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0x04, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0xe4, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x40, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf9, 0xa7, 0x17, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0xa7, 0x17, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x92, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0xf8, 0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x38, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x8b, 0xba, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x3e, 0xba, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x36, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x30, 0x66, 0x00,
   0x00, 0x00, 0x00, 0x00, 0xd0, 0x5d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0xc1, 0xd8, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe6, 0x0b, 0x00, 0x00,
+  0x74, 0xd8, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe6, 0x0b, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x80, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7, 0xe4, 0x17, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5a, 0xe4, 0x17, 0x00,
   0x00, 0x00, 0x00, 0x00, 0xb7, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0xb4, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x17, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x5e, 0xeb, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x11, 0xeb, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x77, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcc, 0x66, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x90, 0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0xd5, 0x0e, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0b, 0x00, 0x00,
+  0x88, 0x0e, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0b, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe1, 0x19, 0x18, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x19, 0x18, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x89, 0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x54, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x55, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x6a, 0x36, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x1d, 0x36, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x2a, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xac, 0x67, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x20, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x94, 0x3f, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x08, 0x00, 0x00,
+  0x47, 0x3f, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x08, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00,
   0xa0, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x47, 0x18, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5b, 0x47, 0x18, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x52, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0xe0, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0xfa, 0x4a, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0xad, 0x4a, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x28, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0x67, 0x00,
   0x00, 0x00, 0x00, 0x00, 0xf0, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x22, 0x4d, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0xca, 0x0a, 0x00, 0x00,
+  0xd5, 0x4c, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0xca, 0x0a, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x30, 0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0x57, 0x18, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9f, 0x57, 0x18, 0x00,
   0x00, 0x00, 0x00, 0x00, 0xb6, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x1c, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x6d, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0xa2, 0x78, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x7b, 0x9e, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xca, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x55, 0x78, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x81, 0x9e, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xca, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x1d, 0x17, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00, 0xba, 0x00, 0x00, 0x00,
+  0xd6, 0x16, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00, 0xba, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0xa6, 0xd0, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x44, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0xd7, 0x17, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x90, 0x17, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x45, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xea, 0xd1, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0xc1, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -189,7 +189,7 @@ unsigned char ql83xx_firmware[] = {
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x0c, 0x8c, 0x02,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd8, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x04, 0x0c, 0x8c, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x1c, 0x3d, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0xd5, 0x3c, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x6d, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
   0x00, 0x00, 0x00, 0x00, 0x58, 0xe0, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -232,8 +232,8 @@ unsigned char ql83xx_firmware[] = {
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x46, 0x1a, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x21, 0xfd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x46, 0x1a, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x25, 0xfd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0xcc, 0x5f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xae, 0x05, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -250,664 +250,664 @@ unsigned char ql83xx_firmware[] = {
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 0xda, 0xec, 0x3d,
   0x6d, 0x70, 0x5c, 0xd5, 0x75, 0xf7, 0x7d, 0xec, 0xee, 0xd3, 0x6a, 0x57,
-  0x5a, 0x1b, 0xd9, 0x11, 0x46, 0xae, 0x9f, 0x8d, 0xb1, 0xc5, 0x47, 0x98,
-  0x67, 0x63, 0x1c, 0x63, 0xdc, 0xf0, 0x24, 0xcb, 0x8e, 0x6d, 0x24, 0x50,
-  0x43, 0x03, 0xe6, 0x23, 0x20, 0xd2, 0x06, 0x04, 0x21, 0x58, 0x74, 0xa0,
-  0x23, 0x83, 0x07, 0x3f, 0xd9, 0x92, 0x6c, 0x40, 0x4e, 0x64, 0xec, 0x38,
-  0x0e, 0xa1, 0xb0, 0x92, 0x6d, 0x4a, 0x52, 0xda, 0x2e, 0x93, 0x8f, 0x32,
-  0x6d, 0x67, 0x58, 0xdb, 0x99, 0xd8, 0x10, 0x3c, 0x71, 0x7e, 0xd0, 0x86,
-  0x74, 0x68, 0xb6, 0x93, 0xa6, 0xa3, 0x12, 0xa0, 0x9b, 0x76, 0x4a, 0x64,
-  0x52, 0x43, 0xef, 0xf7, 0x7b, 0xf7, 0xee, 0x7b, 0x6f, 0xf7, 0xca, 0xb2,
-  0x33, 0xed, 0x58, 0x99, 0x09, 0x3a, 0xbe, 0xf7, 0x9c, 0x77, 0xee, 0xb9,
-  0xe7, 0x9e, 0x73, 0xee, 0x39, 0xe7, 0x3d, 0x01, 0x0d, 0x90, 0x1f, 0x13,
-  0x18, 0x40, 0x07, 0x77, 0x83, 0xf3, 0xf0, 0xff, 0x4d, 0x98, 0xfc, 0xf4,
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-  0xdf, 0x9d, 0x69, 0xe2, 0xff, 0x41, 0x26, 0x63, 0xc4, 0xcf, 0xf0, 0x55,
-  0xc6, 0x7e, 0x36, 0xd5, 0x27, 0x88, 0xf5, 0x08, 0xe3, 0xed, 0x3e, 0xc3,
-  0xd3, 0x4a, 0xca, 0xff, 0xbe, 0x4a, 0xe5, 0x27, 0x5f, 0xde, 0xfa, 0xf9,
-  0x66, 0x7c, 0xc6, 0x4e, 0x9d, 0x1f, 0xd9, 0x8f, 0xa3, 0xc8, 0x35, 0x4f,
-  0xe5, 0x29, 0x80, 0x65, 0x9b, 0xaf, 0x9a, 0xa2, 0x6b, 0x80, 0xf3, 0xd5,
-  0x57, 0x8e, 0xd1, 0xfa, 0xf9, 0x67, 0xc8, 0x93, 0x4e, 0x59, 0xb0, 0x82,
-  0x61, 0x27, 0xb2, 0x17, 0xfa, 0x19, 0x30, 0xcc, 0xf3, 0xeb, 0x16, 0x4f,
-  0xf6, 0x64, 0xb1, 0xd5, 0x8f, 0x57, 0xbc, 0x10, 0xea, 0x5b, 0x64, 0x93,
-  0x13, 0xfb, 0xbd, 0x80, 0xa1, 0x69, 0xcb, 0x5e, 0xe4, 0x14, 0x40, 0xe9,
-  0x1c, 0x68, 0x4c, 0xc2, 0x83, 0x4b, 0xdf, 0x55, 0x3b, 0x4f, 0x1e, 0x84,
-  0xbf, 0x54, 0x17, 0xf7, 0x43, 0x8a, 0x97, 0x32, 0x49, 0xf3, 0xb1, 0xdd,
-  0x32, 0xe5, 0x4f, 0xb9, 0x17, 0x8f, 0x70, 0xbc, 0x97, 0x20, 0xe3, 0x57,
-  0xe8, 0xfc, 0x77, 0x6a, 0xf3, 0x25, 0xec, 0xd5, 0xba, 0x99, 0xe6, 0x3b,
+  0xcb, 0x11, 0xf9, 0x47, 0xaf, 0xd8, 0x1f, 0x9f, 0x35, 0xe7, 0xf6, 0x1d,
+  0x49, 0x1f, 0x34, 0x57, 0x30, 0xf0, 0x7c, 0xa7, 0xe8, 0xf0, 0xf5, 0x8f,
+  0xd2, 0x4b, 0x83, 0xd0, 0xcb, 0x10, 0xb5, 0x37, 0xfd, 0x5b, 0xd7, 0x43,
+  0x91, 0x8f, 0x28, 0xe5, 0x1b, 0x12, 0xf5, 0x8a, 0x54, 0x76, 0x7b, 0x1b,
+  0xdf, 0xed, 0x4a, 0x7c, 0x23, 0x93, 0x5e, 0xec, 0x2e, 0x80, 0xa7, 0xec,
+  0xc9, 0xfc, 0x4c, 0x9e, 0x5c, 0xe7, 0xa9, 0x7f, 0x73, 0x8b, 0xb1, 0xde,
+  0xca, 0x7f, 0xcc, 0xea, 0x09, 0x99, 0x38, 0xc4, 0x9b, 0xa5, 0x44, 0xaf,
+  0x31, 0x54, 0x55, 0xb0, 0xe8, 0xe6, 0x9e, 0x36, 0xe9, 0x27, 0x52, 0x0f,
+  0x24, 0xf0, 0x55, 0x58, 0xff, 0xd7, 0x62, 0xf8, 0x3c, 0xa6, 0x72, 0xf9,
+  0x91, 0x78, 0x47, 0x90, 0x96, 0xcf, 0xe8, 0x23, 0x46, 0x4f, 0xd9, 0x70,
+  0xfc, 0xf4, 0xf9, 0x5f, 0x62, 0xfd, 0xe3, 0x22, 0xce, 0x7f, 0xff, 0x2f,
+  0xf4, 0xfc, 0xff, 0xf6, 0x25, 0x3a, 0xff, 0xcd, 0xfb, 0x95, 0xbe, 0x5e,
+  0xff, 0xd7, 0xf6, 0xe7, 0xff, 0x2b, 0xff, 0xdf, 0xe5, 0x45, 0xec, 0xe1,
+  0xc8, 0xf9, 0x95, 0xfb, 0xdf, 0x33, 0x4f, 0xfe, 0x2f, 0xf9, 0x7b, 0x93,
+  0x3e, 0x29, 0xf1, 0xaf, 0x95, 0xbd, 0xf4, 0xab, 0xbd, 0xdf, 0xcd, 0x9f,
+  0x97, 0x8c, 0xfa, 0xbc, 0xbc, 0x66, 0x2f, 0x9b, 0xf6, 0x5c, 0x0e, 0xbf,
+  0x9d, 0xfd, 0x77, 0xa9, 0xa8, 0x2f, 0x96, 0xf5, 0xc8, 0x63, 0x81, 0x2e,
+  0x6f, 0x8f, 0xe8, 0xd7, 0x92, 0x7f, 0xe2, 0x55, 0xdc, 0xff, 0xe7, 0x27,
+  0xe9, 0xff, 0x61, 0xbc, 0x4d, 0xd6, 0xd7, 0xc7, 0xc9, 0x63, 0x4b, 0x7d,
+  0x9f, 0xc3, 0x7d, 0x71, 0xe3, 0xe1, 0xf7, 0x9e, 0x0a, 0xf7, 0x7f, 0xaf,
+  0xb6, 0xff, 0xca, 0x5f, 0xfa, 0xe6, 0xaf, 0xe6, 0x7e, 0xeb, 0x9f, 0x66,
+  0x7b, 0xfd, 0x3d, 0x31, 0xeb, 0x8d, 0xcc, 0xf3, 0x76, 0xc9, 0xf6, 0xb3,
+  0xe5, 0xfa, 0x27, 0xef, 0xdf, 0xcf, 0x7f, 0xbd, 0x7f, 0xbf, 0x90, 0xf3,
+  0x2f, 0xbc, 0x97, 0x72, 0xff, 0xf9, 0xf9, 0x3f, 0x32, 0xd4, 0xa7, 0x9d,
+  0xff, 0x2e, 0xc5, 0x0f, 0x32, 0x06, 0x7f, 0x98, 0x37, 0xbd, 0x18, 0xf4,
+  0xd8, 0x74, 0xfe, 0xeb, 0x3a, 0x3f, 0xfa, 0xf5, 0xf9, 0xbf, 0xc8, 0xf3,
+  0xaf, 0xed, 0x6f, 0xcc, 0xf9, 0x37, 0xf8, 0xff, 0xfc, 0xf6, 0xf3, 0x97,
+  0xef, 0xbc, 0x1b, 0x78, 0x2f, 0x2a, 0x5e, 0xf7, 0x7d, 0xb3, 0xbf, 0x89,
+  0x2d, 0xe2, 0x95, 0x88, 0xe3, 0x7b, 0x8f, 0xda, 0x3c, 0x5f, 0x29, 0x6b,
+  0xc4, 0x37, 0xa6, 0x35, 0xfc, 0x76, 0xf5, 0xae, 0x02, 0x1f, 0x28, 0x5c,
+  0x10, 0x3d, 0x7e, 0xf0, 0xb6, 0x03, 0x7c, 0x7e, 0x02, 0x7f, 0xef, 0x81,
+  0x8e, 0xb7, 0x4a, 0xfc, 0xa0, 0x69, 0xc0, 0xeb, 0x9f, 0x77, 0x59, 0xb4,
+  0xfe, 0x19, 0xc0, 0x4e, 0x2b, 0x88, 0xf4, 0x3f, 0x93, 0xf9, 0x6f, 0x96,
+  0xcc, 0xb7, 0xa2, 0x0f, 0xa4, 0x90, 0xdb, 0xbe, 0xca, 0x5f, 0xad, 0xe7,
+  0xbd, 0xd6, 0xfe, 0x7b, 0x59, 0x9f, 0xcb, 0x81, 0x8a, 0x0e, 0x8d, 0xbd,
+  0x0c, 0xd7, 0x80, 0x46, 0x5e, 0xe1, 0x61, 0x07, 0x72, 0x7c, 0x5f, 0xc6,
+  0x0f, 0xa7, 0x5e, 0x84, 0xb5, 0x48, 0xfc, 0x50, 0xaf, 0xef, 0x7d, 0x56,
+  0xe1, 0xe7, 0x6e, 0xa6, 0xfd, 0xab, 0x90, 0xef, 0x02, 0x6f, 0xd4, 0xa2,
+  0xf5, 0x6b, 0xbc, 0x9e, 0xe6, 0x33, 0x91, 0x7a, 0xc8, 0x9d, 0x32, 0x5f,
+  0xe6, 0xa7, 0x1c, 0xbf, 0x96, 0xcf, 0x6b, 0xdc, 0x6a, 0xf2, 0xe7, 0xb7,
+  0xe8, 0x07, 0xa5, 0xea, 0xff, 0x45, 0x3f, 0x28, 0x3f, 0xbd, 0xbe, 0xb1,
+  0xbe, 0x2a, 0x21, 0x9f, 0xc3, 0x88, 0x4f, 0x83, 0x8c, 0x91, 0xdf, 0x56,
+  0xc7, 0xd8, 0x81, 0xcb, 0x68, 0x72, 0xcf, 0x3f, 0x01, 0xb0, 0x3b, 0xf7,
+  0xe9, 0x1e, 0xf6, 0xeb, 0x9b, 0x46, 0x98, 0xaa, 0x89, 0x87, 0xd8, 0xfe,
+  0x4f, 0x7c, 0xc1, 0x82, 0x8f, 0x40, 0x1c, 0xa9, 0xa7, 0x97, 0xf5, 0xee,
+  0x20, 0x60, 0xf1, 0xdf, 0xc0, 0xca, 0x44, 0xf1, 0x67, 0x41, 0x5d, 0xed,
+  0x1f, 0x7b, 0x9b, 0x8c, 0xf7, 0x4d, 0x9b, 0xac, 0x8f, 0x17, 0x57, 0x2f,
+  0xbf, 0x05, 0xf1, 0xfa, 0x3c, 0x81, 0xa7, 0x6b, 0xe2, 0x47, 0xdb, 0xfa,
+  0x7e, 0x35, 0xff, 0xfe, 0xeb, 0x08, 0x04, 0x19, 0x14, 0xd6, 0xd7, 0xf3,
+  0x73, 0xa9, 0x9e, 0xef, 0x9f, 0x10, 0xf1, 0x97, 0x5d, 0x80, 0xd1, 0x5b,
+  0xd8, 0xbf, 0x45, 0xc3, 0xd3, 0x0f, 0xe9, 0xe5, 0xeb, 0x34, 0x35, 0x6f,
+  0xec, 0x9b, 0xf0, 0x0c, 0x6c, 0x4c, 0xf1, 0xfc, 0xf7, 0x7e, 0x3b, 0x99,
+  0xbe, 0x24, 0xfe, 0xeb, 0x97, 0x7e, 0xf0, 0x95, 0x3c, 0xd0, 0xf1, 0x1b,
+  0x50, 0x8b, 0xfa, 0x55, 0x21, 0x8f, 0x30, 0xe4, 0xfb, 0x8b, 0xd3, 0xf3,
+  0x27, 0x55, 0xfe, 0x5b, 0xc2, 0xf9, 0x16, 0x78, 0x36, 0xea, 0x7c, 0xde,
+  0xce, 0xeb, 0x85, 0x0a, 0xfb, 0x46, 0x9e, 0x79, 0xb5, 0x90, 0xa9, 0x1e,
+  0x19, 0x61, 0x79, 0x87, 0xf8, 0xdb, 0x0e, 0xa2, 0xf8, 0x35, 0x36, 0x9d,
+  0x6a, 0x99, 0x3d, 0x4f, 0xe5, 0xfb, 0x20, 0xbd, 0x5f, 0xe6, 0xa8, 0x8a,
+  0xbf, 0x05, 0x5e, 0x95, 0xdd, 0x5f, 0x24, 0xf7, 0xcb, 0xf7, 0x0f, 0x84,
+  0x7d, 0xe3, 0xc1, 0x4e, 0x1c, 0x14, 0x7d, 0x0b, 0x0c, 0x9c, 0x63, 0x78,
+  0x0b, 0x49, 0xe7, 0xf1, 0xda, 0xa8, 0x3d, 0x14, 0xf1, 0x97, 0x00, 0x70,
+  0x02, 0x44, 0xf7, 0x23, 0xac, 0x77, 0x16, 0xf4, 0x64, 0x4f, 0x81, 0x80,
+  0xf6, 0x1b, 0x98, 0x7b, 0x98, 0xf5, 0xa3, 0x58, 0xba, 0x97, 0xa5, 0x18,
+  0xe1, 0x9b, 0x79, 0x5d, 0x3a, 0x46, 0x45, 0x80, 0xd7, 0xbc, 0x70, 0x1b,
+  0x0c, 0xd7, 0x77, 0x99, 0xc4, 0xdb, 0x17, 0xf1, 0xf7, 0xaf, 0x6b, 0xe3,
+  0x49, 0x78, 0xaf, 0xf0, 0xfc, 0xeb, 0xf1, 0x68, 0xbe, 0x7e, 0x13, 0xae,
+  0xe8, 0x87, 0x57, 0xc3, 0xe8, 0x31, 0x72, 0xbd, 0xfb, 0xdf, 0x67, 0xed,
+  0x39, 0x18, 0x54, 0xe3, 0xe8, 0x65, 0x0b, 0xda, 0x9c, 0x21, 0xf4, 0x0e,
+  0xcf, 0x80, 0xc6, 0x58, 0x32, 0xde, 0xc1, 0x6d, 0x09, 0xf8, 0x72, 0x9c,
+  0x3f, 0x70, 0xfc, 0x05, 0xde, 0x0f, 0x46, 0xae, 0x07, 0xe1, 0x23, 0x0d,
+  0x15, 0x8f, 0xc7, 0x56, 0x02, 0xbe, 0x01, 0x5b, 0xcf, 0x7a, 0x06, 0x85,
+  0xcf, 0xbb, 0x30, 0xfc, 0x10, 0xe8, 0x5e, 0x2a, 0xfc, 0x90, 0x69, 0xad,
+  0x3e, 0x3b, 0xac, 0xef, 0x9d, 0xb3, 0xd8, 0xf7, 0x83, 0x14, 0x3f, 0xad,
+  0x4a, 0xeb, 0x77, 0x6d, 0x7f, 0x42, 0xe2, 0xad, 0xd3, 0x8f, 0xc0, 0xef,
+  0x91, 0xf4, 0x57, 0x9e, 0x33, 0xf1, 0x79, 0xf8, 0x7c, 0x7d, 0xca, 0xcf,
+  0x32, 0x9d, 0x92, 0x5e, 0x73, 0x20, 0xc8, 0xd2, 0x7e, 0x05, 0x34, 0x60,
+  0x7f, 0x05, 0x64, 0x85, 0x8c, 0xec, 0xb3, 0x46, 0xf5, 0xdf, 0x93, 0xf8,
+  0xe5, 0xa3, 0x82, 0xbe, 0x40, 0x3d, 0x1d, 0x9f, 0x7d, 0x9b, 0x9e, 0xaf,
+  0xa4, 0xec, 0x6b, 0x9f, 0xc6, 0x6d, 0xd9, 0x7e, 0xe4, 0xa3, 0xf5, 0x8f,
+  0xe4, 0x81, 0x68, 0x11, 0x91, 0x07, 0xc3, 0xfd, 0x54, 0xce, 0x91, 0xf1,
+  0x77, 0x65, 0x9a, 0xf8, 0x7f, 0x90, 0xc9, 0x18, 0xf1, 0x33, 0x7c, 0x95,
+  0xb1, 0x9f, 0x4d, 0xf5, 0x09, 0x62, 0x3d, 0xc2, 0x78, 0xbb, 0xcf, 0xf0,
+  0xb4, 0x92, 0xf2, 0xbf, 0xaf, 0x52, 0xf9, 0xc9, 0x97, 0xb7, 0x7e, 0xbe,
+  0x19, 0x9f, 0xb1, 0x53, 0xe7, 0x47, 0xf6, 0x13, 0x28, 0x72, 0xcd, 0x53,
+  0x79, 0x0a, 0x60, 0xd9, 0xe6, 0xab, 0xa6, 0xe8, 0x1a, 0xe0, 0x7c, 0xf5,
+  0xd5, 0x63, 0xb4, 0x7e, 0xfe, 0x59, 0xf2, 0xa4, 0x53, 0x16, 0xac, 0x60,
+  0xd8, 0x89, 0xec, 0x85, 0x7e, 0x06, 0x0c, 0xf3, 0xfc, 0xba, 0xc5, 0xbb,
+  0x7b, 0xb2, 0xd8, 0xea, 0xc7, 0x2b, 0x5e, 0x0c, 0xf5, 0x2d, 0xb2, 0xc9,
+  0x89, 0xfd, 0x5e, 0xc0, 0xd0, 0xb4, 0x65, 0x2f, 0x72, 0x0a, 0xa0, 0x74,
+  0x0e, 0x34, 0x76, 0xc3, 0x83, 0x4b, 0xdf, 0x5d, 0x3b, 0x4f, 0x1e, 0x84,
+  0xbf, 0x54, 0x17, 0xf7, 0x43, 0x8a, 0x97, 0xb2, 0x9b, 0xe6, 0x63, 0xbb,
+  0x65, 0xca, 0x9f, 0x72, 0x2f, 0x1d, 0xe1, 0x78, 0x2f, 0x41, 0xc6, 0xaf,
+  0xd0, 0xf9, 0x8f, 0x68, 0xf3, 0x25, 0xec, 0xd5, 0xba, 0x85, 0xe6, 0x3b,
   0x83, 0x75, 0xa8, 0x7c, 0x80, 0xe1, 0xad, 0x48, 0xfb, 0x21, 0xc3, 0xfb,
-  0x25, 0xd1, 0x7c, 0xa9, 0x03, 0x64, 0xcc, 0xdd, 0x2e, 0xaf, 0x3f, 0xdf,
+  0x25, 0xd1, 0x7c, 0xa9, 0x03, 0x64, 0xcc, 0x5d, 0x2e, 0xaf, 0x3f, 0xdf,
   0x24, 0xfd, 0x2b, 0xcb, 0x78, 0xfd, 0x52, 0x1e, 0x6d, 0x66, 0x58, 0xad,
   0x67, 0x1c, 0x9f, 0xad, 0x4f, 0x55, 0xac, 0x77, 0x1f, 0x68, 0x07, 0x0f,
-  0x85, 0xf6, 0xe7, 0xd8, 0x7a, 0x3b, 0xf5, 0xe2, 0xad, 0xe5, 0xf4, 0x06,
+  0x85, 0xf6, 0xe7, 0xd8, 0x7a, 0x07, 0xf5, 0xe2, 0xad, 0xe5, 0xf4, 0x06,
   0xae, 0x96, 0xe3, 0x2f, 0x89, 0xc5, 0xc7, 0xa6, 0xf7, 0x6f, 0x24, 0xf7,
   0xab, 0xf8, 0xbb, 0xbc, 0x9f, 0x02, 0x6b, 0xc4, 0xf6, 0x87, 0x90, 0xfc,
   0x45, 0xd0, 0x87, 0x2d, 0xe6, 0x77, 0x18, 0xb4, 0x87, 0xd7, 0xa2, 0xc6,
@@ -918,609 +918,609 @@ unsigned char ql83xx_firmware[] = {
   0x69, 0x7e, 0xd7, 0xc7, 0xcf, 0x2f, 0xd3, 0x62, 0x7e, 0x89, 0xe3, 0x5d,
   0x17, 0x3b, 0x5e, 0x02, 0x5e, 0x8f, 0xa2, 0xf7, 0xc3, 0xb4, 0xa1, 0x52,
   0xec, 0x78, 0x2c, 0xff, 0x69, 0x4e, 0xd2, 0xeb, 0x3a, 0x79, 0xb4, 0x63,
-  0xf1, 0x53, 0x58, 0xbd, 0x5a, 0xb4, 0x9e, 0x50, 0x7c, 0x5e, 0x56, 0xf2,
-  0xd4, 0x81, 0xd1, 0xe7, 0x85, 0xe3, 0xbf, 0x4d, 0xeb, 0xaf, 0x54, 0x5e,
-  0xbf, 0x50, 0xc8, 0x03, 0xca, 0xff, 0x97, 0x29, 0xfe, 0x5f, 0x1a, 0x65,
-  0x68, 0x78, 0xb8, 0x7c, 0x1b, 0xd9, 0xd7, 0xa5, 0x1e, 0x66, 0x5c, 0xb5,
+  0xf1, 0x53, 0x58, 0xbd, 0x5a, 0xb4, 0x9e, 0x50, 0x7c, 0x5e, 0x51, 0xf2,
+  0xd4, 0x81, 0xd1, 0xe7, 0x85, 0xe3, 0xbf, 0x43, 0xeb, 0xaf, 0x54, 0x5e,
+  0xbf, 0x50, 0xc8, 0x03, 0xca, 0xff, 0x97, 0x29, 0xfe, 0x5f, 0x1a, 0x63,
+  0x68, 0x78, 0xb8, 0x7c, 0x3b, 0xd9, 0xd7, 0xa5, 0x1e, 0x66, 0x5c, 0xb5,
   0x3e, 0x58, 0x41, 0xd9, 0x7e, 0x5a, 0x72, 0x27, 0xe5, 0xef, 0xd9, 0xf3,
-  0xe7, 0xcf, 0x2f, 0x20, 0xff, 0xdc, 0xf7, 0xad, 0x2d, 0xb0, 0x58, 0xbf,
-  0xa6, 0x6f, 0xb4, 0xb2, 0x73, 0x17, 0xf0, 0xaf, 0xe8, 0xc4, 0x21, 0x5e,
-  0x1b, 0xe7, 0xd7, 0x65, 0x56, 0x7f, 0x38, 0xf1, 0x72, 0x25, 0xb7, 0x81,
-  0x76, 0x1c, 0xaa, 0xbd, 0xe8, 0x42, 0xab, 0xbc, 0xbd, 0x0f, 0xb9, 0x3d,
-  0xc3, 0xa8, 0xb4, 0xc0, 0xc6, 0x36, 0xd1, 0x65, 0xf6, 0xed, 0x73, 0xf3,
-  0x57, 0xbd, 0xbe, 0x16, 0x34, 0x3a, 0xa8, 0x7e, 0xf4, 0x8a, 0xac, 0xbf,
-  0x38, 0xbf, 0x92, 0x88, 0x13, 0x44, 0x59, 0x30, 0x78, 0x1c, 0x52, 0x79,
-  0x85, 0x89, 0x7c, 0xec, 0x07, 0xc7, 0x91, 0xdd, 0x01, 0x8a, 0x6b, 0x46,
-  0xff, 0x9a, 0xc9, 0xcf, 0xf7, 0x80, 0x9b, 0x2c, 0xd4, 0xe9, 0xdf, 0xb6,
-  0xea, 0xd5, 0xdf, 0xb2, 0x28, 0xbf, 0xec, 0x02, 0xc7, 0xc9, 0xbd, 0xa3,
-  0x3b, 0x57, 0xa1, 0xe7, 0x11, 0xd1, 0xcf, 0x67, 0xd7, 0x0c, 0x11, 0xcd,
-  0xca, 0xe2, 0x3a, 0xfe, 0x7e, 0xc0, 0xf0, 0x49, 0x9c, 0x5a, 0xc1, 0x8a,
-  0xe1, 0x9f, 0x65, 0x70, 0xb8, 0x4e, 0xbf, 0xc7, 0x76, 0x79, 0x41, 0xdc,
-  0xf7, 0x01, 0xf8, 0x16, 0xfb, 0x1e, 0xd8, 0x38, 0xf6, 0x7b, 0x1f, 0x34,
-  0xd8, 0xf7, 0xca, 0x9e, 0x41, 0x46, 0x3f, 0x0c, 0x60, 0xe0, 0x01, 0x87,
-  0xfa, 0xe4, 0x02, 0x50, 0xfd, 0x7b, 0x58, 0xba, 0x36, 0x56, 0xde, 0x50,
-  0x11, 0x17, 0x9d, 0x44, 0xcb, 0xf3, 0x62, 0x5c, 0x37, 0xed, 0x77, 0x53,
-  0xfe, 0x70, 0x9d, 0xd5, 0x52, 0x16, 0x79, 0xe1, 0xa6, 0xd2, 0xff, 0x0e,
-  0xf7, 0x50, 0x49, 0xa8, 0xc6, 0x3b, 0x2d, 0xe8, 0xcb, 0xeb, 0xa2, 0x42,
-  0x6c, 0x7c, 0xeb, 0x27, 0xe0, 0x06, 0x86, 0x5f, 0xd2, 0xf4, 0x3c, 0x2a,
-  0xff, 0xbb, 0x23, 0xf4, 0x49, 0x66, 0x3f, 0xc4, 0xf8, 0xbf, 0xc8, 0x07,
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+  0xbb, 0x67, 0xf3, 0xd1, 0x7c, 0x34, 0xfc, 0xf1, 0xd9, 0x48, 0xbf, 0xca,
+  0x4e, 0xc0, 0xf0, 0x44, 0xa2, 0xfd, 0xc6, 0x43, 0x7f, 0x78, 0x67, 0x13,
+  0xbe, 0x52, 0x1c, 0x3d, 0x8d, 0x16, 0xc2, 0xfd, 0x0b, 0x34, 0x3c, 0x2f,
+  0x27, 0x8c, 0xd7, 0xd5, 0xa0, 0xc2, 0x5b, 0x58, 0xc0, 0x79, 0xc0, 0xfd,
+  0xe4, 0x40, 0xf0, 0xfc, 0x31, 0x81, 0xbf, 0x99, 0xfb, 0x74, 0x0f, 0xb3,
+  0xa6, 0xbe, 0x24, 0x70, 0x5f, 0xba, 0x27, 0x7b, 0x6c, 0xff, 0x68, 0xaf,
+  0xc2, 0xa3, 0xb6, 0xc1, 0xcd, 0x74, 0xbf, 0x10, 0xc3, 0xaf, 0xaa, 0x6a,
+  0xfa, 0xc5, 0xbc, 0xf0, 0x28, 0xa9, 0x18, 0xbb, 0x28, 0x3c, 0xca, 0xa0,
+  0x09, 0xef, 0x98, 0x3f, 0x3f, 0xcc, 0xcf, 0x97, 0xf3, 0x39, 0x77, 0x63,
+  0xe7, 0xb8, 0xf2, 0xdf, 0xab, 0xf3, 0xa1, 0xf0, 0xc9, 0x36, 0x6a, 0xfa,
+  0x28, 0xe1, 0xc6, 0x41, 0x50, 0x40, 0x48, 0xf4, 0x97, 0x3c, 0xa8, 0xce,
+  0xdf, 0xdc, 0xc3, 0x9b, 0xf8, 0xfa, 0xf1, 0xfd, 0x79, 0x85, 0xd7, 0x4f,
+  0x90, 0xf3, 0xbf, 0x0d, 0x05, 0x6e, 0xeb, 0xfd, 0x79, 0xa6, 0x90, 0xac,
+  0x5f, 0x14, 0x4a, 0xd1, 0xf7, 0x0d, 0xb4, 0x7c, 0x35, 0xe9, 0xaf, 0xfb,
+  0xc4, 0x6c, 0x92, 0xbf, 0x6e, 0x1b, 0xd4, 0xe2, 0x1d, 0xca, 0xdf, 0xb8,
+  0xcb, 0xec, 0xcf, 0x8a, 0x22, 0xf8, 0xce, 0xf8, 0x71, 0x31, 0xde, 0x62,
+  0xd0, 0xb8, 0x8b, 0xfa, 0x6f, 0x88, 0x41, 0xb8, 0x84, 0xc7, 0x67, 0xa6,
+  0x35, 0x7f, 0x45, 0xf3, 0xf3, 0x4e, 0xf2, 0xf7, 0x1d, 0x3d, 0xc3, 0xf2,
+  0xbd, 0xda, 0xf4, 0x0f, 0x9e, 0xcd, 0xb7, 0xe8, 0x17, 0xf9, 0xd9, 0x84,
+  0xf5, 0x49, 0xa9, 0x97, 0xb0, 0x8c, 0x7a, 0x09, 0x2b, 0xbd, 0x5e, 0xc2,
+  0xc4, 0xb7, 0x14, 0xfe, 0x33, 0xdf, 0xe0, 0x1f, 0x21, 0x3d, 0x49, 0x7d,
+  0xd9, 0x0a, 0x0a, 0x1c, 0xef, 0x47, 0xe6, 0x0f, 0xd5, 0x72, 0xd8, 0xe9,
+  0xf6, 0xea, 0xcc, 0x9f, 0x26, 0x09, 0xeb, 0x29, 0xb1, 0x9e, 0x75, 0x30,
+  0x7d, 0x94, 0x9c, 0xa7, 0x53, 0x83, 0x16, 0xd7, 0xbf, 0xe5, 0x79, 0xff,
+  0x9c, 0x3c, 0xef, 0x0c, 0x8f, 0x9b, 0xf6, 0x8f, 0xde, 0x05, 0xa3, 0xfc,
+  0x2e, 0x52, 0xff, 0x19, 0x17, 0x4f, 0x0b, 0xe7, 0x37, 0x48, 0xd6, 0x7f,
+  0x19, 0x65, 0xf3, 0x8f, 0x08, 0x7d, 0x37, 0xbd, 0x5e, 0x53, 0xd5, 0x87,
+  0x89, 0x7c, 0xf2, 0x01, 0x2b, 0x5c, 0x4c, 0x1f, 0x95, 0x55, 0x7d, 0x35,
+  0x04, 0xa7, 0xd9, 0xfe, 0x3f, 0x25, 0x84, 0xc5, 0xe6, 0xb5, 0x7a, 0xbf,
+  0xd7, 0x24, 0x7a, 0xa3, 0xf9, 0xcb, 0xf9, 0x65, 0x44, 0x52, 0xc8, 0xfc,
+  0x74, 0x72, 0xbd, 0x69, 0x79, 0xc4, 0xfe, 0x07, 0xeb, 0xa4, 0x01, 0x96,
+  0x88, 0x57, 0xa6, 0xaf, 0x3f, 0x08, 0xe3, 0xf7, 0x0d, 0x58, 0x6b, 0xc2,
+  0xd3, 0x90, 0xca, 0x97, 0xc7, 0xf1, 0x81, 0x79, 0x3e, 0x39, 0x68, 0x1c,
+  0x9d, 0xb0, 0xe9, 0x8f, 0xd5, 0x7a, 0x0e, 0x47, 0xf0, 0xc9, 0xaf, 0x73,
+  0x68, 0x3d, 0x83, 0xe0, 0xe7, 0xec, 0xeb, 0xa7, 0x54, 0x7c, 0xc1, 0xf4,
+  0x17, 0xf3, 0x87, 0x8f, 0x33, 0xbc, 0x81, 0xba, 0x86, 0x07, 0x11, 0x6f,
+  0xaf, 0xaa, 0x7a, 0x93, 0xd9, 0xf4, 0xfe, 0xaa, 0x9f, 0x9b, 0xcd, 0xa7,
+  0xd2, 0xff, 0x37, 0x13, 0xe8, 0x5f, 0x9e, 0xff, 0x03, 0xed, 0x8e, 0x1f,
+  0x98, 0xeb, 0xe9, 0x45, 0xd7, 0xef, 0x90, 0x8a, 0xa7, 0xaa, 0xfe, 0xbc,
+  0xfe, 0x3d, 0xd4, 0x9f, 0xbb, 0x4a, 0xb8, 0xd1, 0x3d, 0xb6, 0x00, 0x9f,
+  0x3b, 0x7a, 0xd4, 0x16, 0xf1, 0x97, 0xe2, 0x49, 0xb0, 0x9e, 0x21, 0xe9,
+  0xed, 0x62, 0xf5, 0x86, 0xcd, 0xcf, 0xef, 0x3c, 0x3a, 0xe8, 0x86, 0xfa,
+  0x1f, 0x00, 0x53, 0x50, 0xdf, 0xbf, 0x48, 0xbe, 0x48, 0xa3, 0x99, 0x3e,
+  0x4f, 0x09, 0x7a, 0x83, 0x6b, 0xbc, 0xb9, 0x1d, 0xcb, 0x5d, 0x6c, 0xee,
+  0x9f, 0x0d, 0x41, 0x9d, 0xcd, 0xb7, 0x6e, 0x37, 0x6e, 0x2a, 0xfa, 0x07,
+  0x5b, 0xed, 0x9f, 0xdc, 0x8f, 0xc3, 0x62, 0x3d, 0x8a, 0xac, 0x9e, 0x9a,
+  0xf2, 0xff, 0xd1, 0xd8, 0xf3, 0x46, 0xeb, 0x5d, 0xfa, 0xa3, 0xf3, 0x17,
+  0xf4, 0x78, 0xb7, 0x5a, 0xbf, 0x40, 0xb3, 0x9f, 0x02, 0x70, 0x02, 0xb1,
+  0xf8, 0xf9, 0x4e, 0x96, 0xdf, 0x51, 0x5b, 0x06, 0xf0, 0xfe, 0xcd, 0x64,
+  0xfd, 0x36, 0xef, 0xe4, 0x78, 0xea, 0x45, 0xf6, 0xb6, 0x5b, 0xb2, 0x37,
+  0xfd, 0xc3, 0xb5, 0x1c, 0x8f, 0xde, 0xd9, 0x0a, 0xd1, 0xa2, 0x09, 0x0f,
+  0xec, 0x9f, 0xb3, 0xfc, 0xdd, 0xb0, 0xe6, 0xce, 0xce, 0xae, 0xda, 0xec,
+  0x6f, 0xc0, 0xff, 0x3a, 0x42, 0x86, 0xcb, 0x66, 0xf1, 0xfe, 0x21, 0xd0,
+  0x58, 0x7d, 0x6a, 0xe3, 0xd8, 0xd6, 0x4a, 0x8d, 0x10, 0x31, 0xe1, 0x2f,
+  0x22, 0xaf, 0xf9, 0x23, 0xe2, 0xf9, 0x81, 0xb7, 0x05, 0xa2, 0x7c, 0x89,
+  0xd8, 0x32, 0xf5, 0xf3, 0x2b, 0x29, 0xfe, 0x19, 0x78, 0x58, 0xe8, 0x32,
+  0x02, 0x8f, 0x14, 0x56, 0x24, 0x3e, 0x8b, 0x90, 0x17, 0xd3, 0x16, 0xaf,
+  0x8f, 0x7d, 0x43, 0xe0, 0x19, 0x4c, 0xeb, 0xf1, 0xd4, 0x26, 0x7e, 0xa7,
+  0xfa, 0x65, 0x48, 0xbc, 0x55, 0x9d, 0x5e, 0x9a, 0xe2, 0xcb, 0x91, 0x7c,
+  0x47, 0x4c, 0xfd, 0x1d, 0x9d, 0x00, 0x5a, 0xbe, 0x23, 0xf1, 0xc1, 0xbb,
+  0x3e, 0xc3, 0xf1, 0x98, 0xee, 0x22, 0xeb, 0x3b, 0x53, 0xca, 0xe3, 0xa6,
+  0xf8, 0x33, 0xcb, 0x1f, 0x7f, 0xc6, 0x4a, 0x8a, 0xef, 0xb5, 0x1d, 0x7f,
+  0x0e, 0xcc, 0xfc, 0x12, 0x19, 0x6f, 0x7e, 0x49, 0x7b, 0x5f, 0x39, 0xde,
+  0x3b, 0x76, 0xc8, 0x78, 0xa9, 0x58, 0x9f, 0xe0, 0x21, 0x8e, 0x57, 0xdd,
+  0xb2, 0x1f, 0xf3, 0xa8, 0xcc, 0x08, 0xfa, 0x49, 0x3c, 0x5e, 0x87, 0xe2,
+  0xbf, 0x2d, 0xf2, 0xaf, 0xa5, 0x3f, 0x06, 0x88, 0xfc, 0xeb, 0x46, 0x7a,
+  0xbc, 0x7a, 0xb0, 0x37, 0x56, 0xff, 0xe1, 0x6f, 0x73, 0xab, 0xc3, 0xf4,
+  0x17, 0x5b, 0xe2, 0x99, 0x1f, 0x20, 0x63, 0xaf, 0x61, 0xd7, 0xd2, 0xdd,
+  0x52, 0x7b, 0x8c, 0xdb, 0xf7, 0xdd, 0x13, 0x3c, 0x9f, 0xe1, 0xcf, 0xed,
+  0x32, 0x18, 0x2e, 0x4d, 0xe2, 0x57, 0x16, 0x02, 0x58, 0x0e, 0x06, 0xc6,
+  0xbe, 0x26, 0xf0, 0x26, 0x8f, 0x2d, 0x22, 0xf7, 0x5e, 0xdf, 0x03, 0xc6,
+  0xcb, 0x3b, 0x7a, 0x86, 0xbb, 0x3f, 0xce, 0xeb, 0x65, 0x7c, 0x37, 0x97,
+  0xa4, 0xef, 0xd3, 0xaf, 0x1d, 0x5b, 0xe3, 0xdf, 0x86, 0x7e, 0x0c, 0x34,
+  0xfd, 0x25, 0x81, 0xdf, 0xd1, 0xfa, 0x86, 0x29, 0x46, 0xc4, 0xdb, 0x66,
+  0x1f, 0xa5, 0xff, 0x1d, 0xba, 0x8b, 0x71, 0x1e, 0xdc, 0x5d, 0x29, 0x1f,
+  0xbb, 0x91, 0xd8, 0xfb, 0x7f, 0x49, 0x1e, 0x33, 0xfa, 0xe1, 0x3d, 0xb8,
+  0x4a, 0xe4, 0xf1, 0x75, 0x0e, 0xb5, 0xdf, 0xcf, 0x68, 0xfc, 0xa7, 0xf2,
+  0x36, 0x49, 0x4f, 0x44, 0xdf, 0x7b, 0x9a, 0xc6, 0x98, 0xa5, 0xbe, 0x92,
+  0x5e, 0x5f, 0x69, 0x13, 0x7d, 0x81, 0xd7, 0x63, 0xb6, 0x57, 0x5f, 0x99,
+  0x24, 0xaf, 0x1a, 0xb2, 0xbe, 0xb0, 0xc9, 0x1e, 0x8a, 0xf8, 0x5b, 0x98,
+  0xbd, 0xab, 0xf7, 0x6b, 0x90, 0x4b, 0xb7, 0xbd, 0xf8, 0x07, 0x19, 0x5d,
+  0xdf, 0xe0, 0xf2, 0x3e, 0xc4, 0x53, 0x3f, 0x0d, 0xcb, 0x63, 0x71, 0xf1,
+  0x4d, 0xaa, 0xcf, 0x55, 0x59, 0x3e, 0x08, 0xd3, 0xbf, 0x8d, 0x7e, 0xd7,
+  0xec, 0xee, 0x1c, 0x77, 0xc0, 0xfa, 0x21, 0x3f, 0x0c, 0x72, 0xe2, 0x79,
+  0xf1, 0x78, 0xe4, 0xcf, 0xaa, 0xf3, 0x48, 0xe9, 0x89, 0xe7, 0xaf, 0x69,
+  0xfc, 0x14, 0xa7, 0xff, 0x7e, 0x92, 0xe5, 0x6b, 0x12, 0x2e, 0x90, 0xa8,
+  0x0f, 0x9a, 0x78, 0xe6, 0x72, 0x3c, 0x75, 0x7f, 0x51, 0xaf, 0x3f, 0x31,
+  0xee, 0x07, 0x39, 0xb5, 0x5e, 0xf1, 0xfc, 0xe2, 0xc9, 0xa4, 0xfb, 0x19,
+  0x2d, 0x3c, 0x95, 0x0d, 0xf9, 0x4d, 0x7a, 0x3f, 0x16, 0x6a, 0x89, 0x82,
+  0x6e, 0x1f, 0x46, 0xfb, 0x7f, 0x6f, 0xd0, 0xf8, 0x41, 0x49, 0xea, 0x03,
+  0xaf, 0x27, 0xe9, 0x33, 0xbc, 0xbe, 0x46, 0x5f, 0xbf, 0xed, 0x29, 0xeb,
+  0xe7, 0xd1, 0x6f, 0xf6, 0x87, 0xf1, 0xb7, 0x76, 0xd6, 0x4f, 0xd1, 0x8f,
+  0x8c, 0xdf, 0xe9, 0xcf, 0x03, 0x63, 0x29, 0xcf, 0xcb, 0x45, 0x9e, 0x47,
+  0xc5, 0x2f, 0xb3, 0xff, 0x4a, 0xda, 0xef, 0x83, 0xb1, 0xd4, 0xfd, 0xe6,
+  0xf9, 0xb9, 0x35, 0x87, 0xeb, 0x7b, 0xd1, 0x7a, 0x20, 0x95, 0x8f, 0x2e,
+  0xd6, 0x2b, 0x61, 0xfe, 0x41, 0xd3, 0xfe, 0xa7, 0xbf, 0x2f, 0x9e, 0xe7,
+  0xfd, 0xbf, 0xb4, 0xf4, 0xe5, 0x03, 0x81, 0x47, 0x2c, 0xed, 0xcf, 0xc0,
+  0xc0, 0xab, 0x69, 0xd2, 0x9f, 0xef, 0x94, 0xf5, 0x9d, 0xaf, 0xa7, 0xcb,
+  0x9f, 0xcb, 0xd4, 0x8f, 0xa4, 0x4d, 0x7c, 0x14, 0x73, 0x7d, 0x56, 0x8a,
+  0xf5, 0x51, 0xf2, 0x4a, 0xf8, 0x6b, 0xc2, 0xf8, 0x40, 0xaf, 0x46, 0xaf,
+  0x0d, 0xa1, 0xaf, 0x09, 0x6d, 0x6b, 0xfb, 0x66, 0x2b, 0xdd, 0x9f, 0xaa,
+  0xeb, 0xbf, 0xa1, 0x3e, 0x71, 0xf9, 0xf1, 0x09, 0xda, 0xc5, 0xd7, 0xe3,
+  0xeb, 0x35, 0x25, 0xd6, 0x6b, 0x06, 0xea, 0xeb, 0x65, 0xd2, 0xeb, 0x82,
+  0x2e, 0x83, 0x5e, 0xf1, 0xda, 0x34, 0x7a, 0xad, 0x83, 0x2e, 0x79, 0x3e,
+  0x2f, 0x13, 0xfe, 0x8c, 0x2e, 0xaf, 0x30, 0xfa, 0x3c, 0xaf, 0x9f, 0x8e,
+  0xec, 0x3f, 0x4a, 0xaf, 0xc7, 0x96, 0xf2, 0x55, 0xe5, 0x27, 0x21, 0xae,
+  0xff, 0xe7, 0x61, 0xf4, 0x5a, 0x9d, 0x07, 0x41, 0xff, 0xf9, 0x89, 0x59,
+  0x8a, 0xdc, 0x82, 0x37, 0x7c, 0x32, 0x31, 0xdf, 0x12, 0x86, 0x01, 0xa5,
+  0xd4, 0xfe, 0x01, 0x28, 0x9a, 0xff, 0xfe, 0x50, 0x31, 0xc9, 0xff, 0xbe,
+  0x07, 0x69, 0xf3, 0x33, 0xeb, 0x81, 0xc9, 0xef, 0x5c, 0x6a, 0xff, 0x9c,
+  0x35, 0xf0, 0xbd, 0x8b, 0x32, 0x5e, 0x2d, 0xf5, 0x4f, 0x3c, 0xaf, 0xfa,
+  0x2d, 0xf3, 0xbc, 0xe4, 0x3f, 0x2f, 0xeb, 0xdf, 0xa7, 0xc3, 0xf3, 0xdc,
+  0x30, 0xf2, 0x39, 0x23, 0xef, 0x33, 0xb5, 0x30, 0xe9, 0x7d, 0xda, 0x7a,
+  0x9e, 0xda, 0xcf, 0xe6, 0xfd, 0xd9, 0x0a, 0xda, 0xd9, 0x9f, 0x07, 0xf7,
+  0xca, 0xfd, 0x51, 0xfe, 0xe9, 0x58, 0xbc, 0xb9, 0x64, 0x7d, 0xec, 0xb4,
+  0x99, 0x0f, 0xde, 0x66, 0xbd, 0x52, 0xbb, 0xfc, 0xea, 0xfb, 0x1a, 0xfd,
+  0xba, 0xcd, 0xf8, 0x02, 0x96, 0x81, 0x2f, 0xd0, 0x82, 0x9e, 0xe5, 0xfc,
+  0x22, 0xf9, 0x76, 0x3a, 0x3d, 0x5b, 0x71, 0xf6, 0xad, 0x72, 0x2e, 0xbe,
+  0xe7, 0xf4, 0xa3, 0x82, 0x9e, 0xad, 0x5a, 0xa1, 0xa9, 0xde, 0x09, 0xbc,
+  0x4b, 0xe1, 0x7f, 0xaa, 0x7a, 0xa6, 0x2b, 0xe2, 0xe9, 0x69, 0xda, 0xd0,
+  0x67, 0x85, 0xf5, 0xd3, 0xc2, 0x3f, 0xf0, 0xb3, 0x04, 0xff, 0x43, 0x02,
+  0x7d, 0x04, 0x85, 0x8c, 0xa8, 0x4f, 0x21, 0x56, 0x54, 0x10, 0xc5, 0xeb,
+  0x0e, 0xe3, 0x25, 0x85, 0x8b, 0xa0, 0x77, 0xac, 0xf0, 0x1e, 0xcc, 0x7e,
+  0x60, 0xe4, 0xbc, 0x3d, 0x59, 0x4a, 0xce, 0xdf, 0x8b, 0xf8, 0xdf, 0x51,
+  0x52, 0xfd, 0xd0, 0xa4, 0xe6, 0xcf, 0x89, 0xd7, 0x27, 0x42, 0xbc, 0x89,
+  0xb6, 0xe6, 0x5b, 0x57, 0xeb, 0xc1, 0xbe, 0x8e, 0xe4, 0xa7, 0xa2, 0x30,
+  0x7f, 0x45, 0xc4, 0x07, 0x81, 0x16, 0x1f, 0x88, 0xc9, 0x3f, 0x02, 0xf5,
+  0x1d, 0x05, 0xc3, 0xbf, 0xa3, 0xc6, 0x57, 0xa1, 0x73, 0x32, 0x5e, 0x19,
+  0x34, 0xf7, 0x03, 0xc2, 0x14, 0x3a, 0xb0, 0x10, 0x5d, 0x8f, 0x93, 0x30,
+  0x86, 0x1e, 0xf0, 0x9b, 0x17, 0x48, 0x0f, 0x11, 0x7c, 0xf2, 0x1b, 0x39,
+  0xfe, 0x2e, 0xd7, 0xef, 0x66, 0x3a, 0x74, 0xbc, 0x23, 0xd0, 0x8f, 0x28,
+  0x1e, 0xd5, 0x6c, 0x04, 0xbf, 0x6f, 0x53, 0xdc, 0xfb, 0x06, 0x4c, 0x1f,
+  0x5e, 0xe9, 0xaa, 0x7a, 0x74, 0x70, 0x9f, 0xd4, 0xde, 0xae, 0x93, 0xf9,
+  0x60, 0x72, 0x3c, 0xf2, 0xf7, 0x01, 0xb9, 0x9c, 0x3f, 0xd2, 0xe2, 0x25,
+  0x5c, 0xdf, 0x64, 0x78, 0x33, 0xfc, 0x75, 0x66, 0x2a, 0x22, 0xbe, 0xf3,
+  0xbf, 0x00, 0x00, 0x00, 0xff, 0xff, 0xdc, 0x5d, 0x7b, 0x70, 0x5c, 0xd5,
   0x79, 0x3f, 0xf7, 0xee, 0xdd, 0xbb, 0x77, 0x57, 0xbb, 0xab, 0x95, 0x6c,
   0x6c, 0x21, 0xdb, 0xf1, 0xb5, 0xc1, 0x54, 0x18, 0x02, 0x02, 0x3c, 0xa9,
   0xc7, 0x75, 0xcc, 0x95, 0x01, 0xd7, 0x76, 0xa4, 0xc4, 0x71, 0x1b, 0x6a,
@@ -2115,9243 +2115,9243 @@ unsigned char ql83xx_firmware[] = {
   0xbb, 0x84, 0xeb, 0x8d, 0x3e, 0x42, 0x7a, 0xa0, 0x18, 0xd6, 0x34, 0xc6,
   0xdf, 0x0a, 0xe9, 0x0f, 0xbe, 0xb0, 0x27, 0x08, 0x7f, 0x78, 0x39, 0xf9,
   0xfc, 0x85, 0x7f, 0xbf, 0x04, 0xfe, 0xc1, 0x12, 0xde, 0x8f, 0xff, 0x03,
-  0x00, 0x00, 0xff, 0xff, 0xdc, 0x5d, 0x7b, 0x8c, 0x5c, 0x57, 0x79, 0x3f,
-  0xf7, 0x31, 0x33, 0x77, 0x66, 0x67, 0xd6, 0xb3, 0xe3, 0x4d, 0xf0, 0x63,
-  0x6d, 0xdf, 0x8d, 0x1d, 0xba, 0x81, 0x84, 0x6c, 0x82, 0x89, 0x9c, 0xc4,
-  0xd4, 0x77, 0x89, 0x13, 0xd6, 0xc6, 0x9b, 0x18, 0x28, 0x95, 0x11, 0x14,
-  0xc6, 0x28, 0xad, 0x4c, 0x5e, 0xd0, 0x8a, 0x56, 0x6b, 0x82, 0xd4, 0xbb,
-  0xf6, 0x7a, 0xed, 0x84, 0x5d, 0xd8, 0x14, 0xb5, 0x18, 0x43, 0xc9, 0x38,
-  0xd9, 0x04, 0xa3, 0xd2, 0xd6, 0xa2, 0x55, 0xe5, 0xaa, 0xa8, 0x1a, 0xdb,
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+  0xfe, 0xa6, 0x12, 0xd7, 0xd7, 0x9b, 0x02, 0x6f, 0x1b, 0x62, 0x48, 0x1c,
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+  0x81, 0xef, 0x2b, 0xfa, 0xab, 0xab, 0xef, 0x4c, 0xc7, 0x17, 0xd2, 0xec,
+  0x31, 0xf2, 0x1f, 0x65, 0xfc, 0x71, 0x3d, 0x0c, 0xc3, 0x43, 0xa9, 0x0c,
+  0x8f, 0x33, 0xfc, 0x45, 0xa1, 0xdf, 0x02, 0x0d, 0x5f, 0x03, 0x1b, 0xd5,
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+  0x34, 0x4b, 0x7e, 0xff, 0x43, 0x93, 0x82, 0x04, 0x62, 0x67, 0x26, 0x62,
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+  0x34, 0x22, 0xb0, 0xdf, 0x22, 0xb7, 0x39, 0xb7, 0x15, 0x93, 0x5d, 0x79,
+  0xb7, 0x91, 0xdf, 0x20, 0x8e, 0x22, 0x4e, 0xec, 0x62, 0xf5, 0x51, 0x73,
+  0x5c, 0xbe, 0x4f, 0xf3, 0xf5, 0xd6, 0x9b, 0x7c, 0x6f, 0xe1, 0x9f, 0x6a,
+  0x89, 0xb7, 0x98, 0xfb, 0x2d, 0x23, 0xe6, 0xd7, 0xea, 0xee, 0x3c, 0xc6,
+  0x3c, 0x5f, 0x95, 0x78, 0x48, 0xd6, 0xde, 0xf4, 0xf8, 0x4e, 0xa6, 0xad,
+  0x7f, 0x2f, 0xd7, 0x8b, 0x5e, 0x5f, 0x2c, 0x20, 0xed, 0xbd, 0xdd, 0x57,
+  0xda, 0xeb, 0xa2, 0x86, 0x2e, 0x9f, 0x0f, 0x5b, 0xed, 0xcf, 0xeb, 0x32,
+  0xf1, 0x7c, 0x26, 0xf6, 0xaf, 0x43, 0x7f, 0xe4, 0x79, 0x71, 0x72, 0x7e,
+  0x7a, 0x82, 0x7f, 0x96, 0xc1, 0xc5, 0xd8, 0x3f, 0xc3, 0xc0, 0x07, 0x42,
+  0xfb, 0xf7, 0x7d, 0x5e, 0xff, 0x55, 0x9e, 0x07, 0x6f, 0xa5, 0xfd, 0xb3,
+  0x2e, 0x5a, 0xb7, 0xfb, 0x3b, 0x7d, 0x39, 0xbf, 0xa9, 0xfd, 0x63, 0xf8,
+  0xde, 0x6e, 0xcf, 0x73, 0xbf, 0xd6, 0xe1, 0x7c, 0x16, 0xc2, 0x31, 0x8c,
+  0x7f, 0x4d, 0xe8, 0xc3, 0xea, 0x91, 0x36, 0xf3, 0x1f, 0xcd, 0xdf, 0x27,
+  0xf8, 0xf0, 0x65, 0xfc, 0x89, 0xf3, 0x8f, 0x72, 0x7f, 0x05, 0xf0, 0x00,
+  0xf5, 0xf4, 0x78, 0xe8, 0x6f, 0x2d, 0xc7, 0xf1, 0x20, 0x06, 0x8d, 0x71,
+  0x9b, 0x61, 0x80, 0xcf, 0xb4, 0xe2, 0x8d, 0xaf, 0x49, 0x7e, 0x49, 0xf4,
+  0x42, 0x87, 0xfc, 0x92, 0x60, 0x31, 0x2d, 0xde, 0xda, 0xd5, 0xfb, 0xd1,
+  0x37, 0xf9, 0xfb, 0xd3, 0xe2, 0x29, 0x66, 0x7b, 0xfe, 0xf0, 0xeb, 0xed,
+  0xf9, 0x09, 0xfe, 0xe9, 0x4b, 0x69, 0xed, 0x59, 0x36, 0xea, 0xe9, 0x9a,
+  0x78, 0xad, 0x82, 0xc1, 0x07, 0x72, 0xc1, 0xd0, 0x97, 0x39, 0x7d, 0x3d,
+  0xb7, 0xe4, 0xc7, 0xa6, 0xe1, 0x2b, 0x3a, 0xe4, 0xc3, 0x86, 0xaf, 0x74,
+  0xd2, 0x4f, 0x4e, 0xac, 0xff, 0x58, 0xbc, 0xfd, 0x20, 0x8d, 0xb7, 0xaf,
+  0x68, 0xfa, 0x11, 0x93, 0xf6, 0xf2, 0xfd, 0x91, 0xd1, 0xf7, 0x07, 0x9f,
+  0x7f, 0x6b, 0x79, 0x83, 0xe3, 0x39, 0x3d, 0x71, 0xde, 0x72, 0x7b, 0x41,
+  0x1d, 0x9f, 0x29, 0xb1, 0xff, 0xb7, 0xf5, 0xe2, 0xcf, 0x7e, 0x5c, 0xce,
+  0xbf, 0x39, 0x3e, 0xc9, 0xf3, 0xd3, 0x27, 0xf7, 0xd3, 0x59, 0xa4, 0xcb,
+  0xb3, 0x8b, 0x89, 0xfa, 0xeb, 0x6f, 0x16, 0xc4, 0x7a, 0x07, 0xfd, 0x05,
+  0xfc, 0xf1, 0x4c, 0x7f, 0x75, 0xbb, 0x5e, 0xfe, 0x58, 0xac, 0x17, 0xdf,
+  0x18, 0x5f, 0x89, 0x67, 0x37, 0xf9, 0x13, 0x13, 0xf7, 0x2f, 0xaf, 0x2f,
+  0x74, 0x6f, 0x2e, 0x3e, 0x7f, 0x90, 0xe7, 0x19, 0xb9, 0x54, 0xfe, 0x7a,
+  0x1e, 0xbf, 0xc0, 0x36, 0xea, 0xb8, 0x9f, 0x5b, 0xce, 0x93, 0xd2, 0xeb,
+  0x0b, 0xbf, 0xa5, 0xfd, 0xdc, 0xe8, 0xb0, 0x9f, 0x27, 0xde, 0xe2, 0x7e,
+  0x3e, 0x77, 0xd5, 0xfb, 0xb3, 0xb7, 0xf5, 0x05, 0xe3, 0x75, 0x7b, 0xe7,
+  0xf9, 0x47, 0xdf, 0x92, 0xed, 0x91, 0xcf, 0xfb, 0x46, 0x3d, 0x18, 0xdf,
+  0xa8, 0x07, 0x93, 0xd3, 0xeb, 0xc7, 0x6c, 0xf2, 0xeb, 0xab, 0xb3, 0x57,
+  0xa1, 0x5e, 0xe1, 0x37, 0x37, 0x92, 0xea, 0x17, 0x77, 0x69, 0xbf, 0xa6,
+  0xe5, 0xb7, 0xb4, 0xf0, 0x5f, 0xa2, 0x4c, 0xb3, 0x9f, 0xe5, 0x57, 0x89,
+  0xf3, 0x39, 0xce, 0x87, 0x4a, 0xf3, 0x05, 0xc4, 0xf8, 0x5c, 0x16, 0xf6,
+  0x60, 0x58, 0x5c, 0x0f, 0x87, 0x20, 0x3f, 0x61, 0xd3, 0x0a, 0x6b, 0xe9,
+  0xfb, 0xef, 0x1f, 0xe5, 0xfe, 0x23, 0xfa, 0xf7, 0x1c, 0xd9, 0x7f, 0x7b,
+  0x45, 0xfd, 0xf5, 0xff, 0xeb, 0xfc, 0x9e, 0x6e, 0xf1, 0x15, 0x4d, 0x54,
+  0x67, 0xf5, 0x65, 0x9c, 0xba, 0x82, 0xaf, 0x60, 0xe6, 0x45, 0x8d, 0xc6,
+  0x0f, 0x23, 0x88, 0xf7, 0xd9, 0x2b, 0x4e, 0xde, 0x45, 0x93, 0xa7, 0xcf,
+  0xb0, 0x7a, 0x98, 0x50, 0x9c, 0xcd, 0x06, 0x7b, 0x01, 0x3f, 0xc8, 0xed,
+  0xe3, 0x8b, 0xd6, 0x7e, 0x1a, 0x8f, 0x39, 0xee, 0x54, 0xc9, 0xf5, 0x12,
+  0x7a, 0xd1, 0xbe, 0x25, 0x7b, 0x43, 0x16, 0x85, 0xd3, 0x89, 0xf9, 0x59,
+  0x7e, 0xf8, 0x22, 0xe4, 0x5f, 0xf7, 0xc7, 0xf9, 0x60, 0x05, 0xa3, 0xbd,
+  0x7c, 0x3d, 0x45, 0x3f, 0xd4, 0xeb, 0x13, 0xf9, 0xaf, 0xe8, 0xf5, 0x87,
+  0xa2, 0x87, 0xe8, 0xb5, 0xc0, 0x67, 0x9f, 0x97, 0xeb, 0x97, 0x4f, 0xcf,
+  0xd2, 0x43, 0x79, 0x86, 0xff, 0x62, 0xdf, 0xff, 0x94, 0xb2, 0xde, 0x69,
+  0xe4, 0xb3, 0xa9, 0xc4, 0xef, 0x00, 0x9c, 0x10, 0x52, 0x51, 0x21, 0xf8,
+  0x71, 0xc2, 0x9d, 0x27, 0x68, 0xb3, 0xaa, 0xf0, 0x34, 0x05, 0xb9, 0x7a,
+  0x10, 0x69, 0x6c, 0x70, 0xec, 0xef, 0xb3, 0x9e, 0x94, 0x37, 0xf6, 0x49,
+  0xf2, 0xc1, 0xe7, 0x72, 0x28, 0x3c, 0x9e, 0x8f, 0xeb, 0x1d, 0x3d, 0x07,
+  0xf5, 0x8e, 0xd8, 0xb5, 0x7f, 0xd2, 0x66, 0xf9, 0x8f, 0xac, 0x5e, 0x9b,
+  0xcc, 0xe7, 0xb8, 0x4f, 0xc8, 0xb3, 0x97, 0xec, 0x7e, 0xca, 0xef, 0xcf,
+  0xea, 0x3f, 0x41, 0x7f, 0xe8, 0x75, 0x53, 0xcf, 0x47, 0x11, 0xf7, 0x0b,
+  0xf9, 0x24, 0xda, 0x27, 0xef, 0x47, 0xbb, 0xdb, 0xdd, 0xdf, 0xb8, 0x9e,
+  0xdf, 0xaf, 0xf1, 0x0f, 0x53, 0xfb, 0xf9, 0x02, 0xaf, 0x97, 0xfe, 0x90,
+  0x03, 0xf5, 0x84, 0x40, 0x7c, 0xdf, 0xea, 0xc4, 0xfa, 0xf8, 0xa3, 0x87,
+  0x66, 0x9d, 0x46, 0xff, 0x5c, 0xe6, 0x13, 0x8f, 0x85, 0xe8, 0xa8, 0xff,
+  0x85, 0xc8, 0x3f, 0x77, 0x33, 0x1d, 0xe0, 0x85, 0x29, 0xff, 0x57, 0xc7,
+  0x7e, 0x24, 0x17, 0xed, 0x78, 0xf1, 0x1d, 0x34, 0xbe, 0x6c, 0xbf, 0xc6,
+  0xf2, 0xdd, 0x01, 0x8d, 0x73, 0x38, 0x7b, 0xc6, 0x43, 0x0d, 0xb7, 0x39,
+  0xb2, 0x9d, 0xd9, 0x5b, 0x2c, 0x1f, 0x66, 0x04, 0xf2, 0x33, 0xc9, 0x7a,
+  0x82, 0xf1, 0x7a, 0xf2, 0xe4, 0xc1, 0xca, 0x34, 0xad, 0x17, 0x2a, 0xfc,
+  0x1b, 0x14, 0x2e, 0x22, 0x5a, 0xcf, 0xca, 0x87, 0x78, 0xca, 0x73, 0x64,
+  0xbc, 0x8e, 0x6f, 0x69, 0x9e, 0x81, 0xf6, 0xbc, 0x84, 0x28, 0x25, 0x51,
+  0x78, 0xbc, 0x00, 0xf5, 0x41, 0xc1, 0x05, 0xc7, 0x85, 0x45, 0x77, 0xfd,
+  0x93, 0xa5, 0xd7, 0xb6, 0xb2, 0x7a, 0x39, 0x85, 0xa8, 0x40, 0xeb, 0xe7,
+  0x38, 0x07, 0xe1, 0xda, 0x7e, 0xc9, 0xa6, 0xf5, 0xa7, 0xd0, 0xf1, 0xa0,
+  0x0a, 0xe3, 0x1f, 0x1c, 0xb2, 0x6f, 0x81, 0x78, 0x69, 0x63, 0xba, 0x9f,
+  0x8d, 0x6f, 0xce, 0x39, 0x40, 0x23, 0x8c, 0x97, 0xb7, 0xc2, 0xfb, 0x06,
+  0x1f, 0xad, 0xd6, 0xa6, 0xe8, 0xf3, 0x75, 0x67, 0x92, 0xbd, 0x2f, 0xd3,
+  0x50, 0xf2, 0x39, 0x6d, 0x74, 0xe1, 0x2c, 0xf3, 0x8f, 0x84, 0xfc, 0x48,
+  0xb3, 0x6f, 0x3a, 0xf8, 0x47, 0x28, 0x05, 0x2f, 0x1b, 0xaf, 0x7f, 0xaf,
+  0xd3, 0x7e, 0xc5, 0x62, 0xbf, 0xfa, 0xf1, 0x7e, 0x2d, 0xd4, 0x58, 0xbd,
+  0xde, 0xdf, 0x7c, 0x94, 0xe3, 0x67, 0x29, 0xb9, 0x77, 0x36, 0x07, 0xf5,
+  0x4d, 0xa1, 0x5e, 0x18, 0x72, 0x57, 0x9c, 0x7d, 0xdb, 0xe2, 0xfd, 0x89,
+  0xfc, 0xa2, 0x3d, 0x0a, 0xfb, 0x35, 0x64, 0x78, 0x11, 0x77, 0xe4, 0xac,
+  0xed, 0xd7, 0xf0, 0x8d, 0xc1, 0x99, 0xcd, 0xc4, 0xfd, 0xba, 0x14, 0xce,
+  0xdb, 0xc0, 0x87, 0xb5, 0x3a, 0xc3, 0xf6, 0xb3, 0x5c, 0x6f, 0x8d, 0xb6,
+  0xeb, 0xb3, 0x31, 0x2c, 0xd7, 0xdb, 0x11, 0x47, 0x3d, 0xaf, 0x48, 0x3a,
+  0x5f, 0xa3, 0xbe, 0x46, 0xf0, 0x62, 0x2e, 0x59, 0xdf, 0xbe, 0xbf, 0xad,
+  0xbf, 0x25, 0xe3, 0x63, 0x9c, 0xbf, 0x63, 0x10, 0xe2, 0x3d, 0x3e, 0xc8,
+  0x6b, 0xc6, 0xf7, 0x6d, 0xee, 0x5f, 0x9b, 0xb6, 0x07, 0xd8, 0x91, 0x2e,
+  0x7b, 0xc0, 0xef, 0x9e, 0x5f, 0x7f, 0x96, 0xbe, 0x68, 0x7c, 0xca, 0x07,
+  0x40, 0x68, 0x14, 0xa1, 0x7b, 0xc8, 0x3f, 0x6b, 0x59, 0x14, 0xf1, 0xfd,
+  0x1c, 0xeb, 0xbf, 0x3e, 0x26, 0x4f, 0xe0, 0xfa, 0x51, 0x0b, 0xed, 0x65,
+  0xfb, 0xb9, 0x84, 0x9b, 0x1b, 0x64, 0x3d, 0xd6, 0xd0, 0x6b, 0x63, 0x3c,
+  0x9e, 0xdd, 0x5c, 0x6c, 0x92, 0xeb, 0x71, 0x51, 0xcf, 0xcb, 0x85, 0xf5,
+  0xfe, 0x35, 0x62, 0x94, 0x5c, 0x46, 0xb0, 0x9e, 0x11, 0x3e, 0x69, 0xef,
+  0x87, 0x78, 0x41, 0x74, 0xdc, 0xa6, 0xeb, 0xd9, 0x3f, 0xe4, 0x50, 0xf9,
+  0x19, 0x1e, 0x77, 0xf8, 0xfa, 0xb6, 0xab, 0xc5, 0xc5, 0x9a, 0xe5, 0xef,
+  0x9d, 0x04, 0x3e, 0xbe, 0xfc, 0x06, 0x6b, 0xdf, 0xdc, 0x68, 0x69, 0x1c,
+  0xae, 0x5d, 0x04, 0xef, 0x5b, 0x23, 0xfd, 0xbb, 0xec, 0xc0, 0xfb, 0x02,
+  0xca, 0x3f, 0x7c, 0xca, 0x25, 0xcf, 0xbb, 0xd0, 0x5e, 0x4c, 0xe3, 0x2f,
+  0xa7, 0x88, 0x2c, 0xbd, 0xec, 0xb2, 0xf6, 0xa3, 0x4c, 0x9d, 0xad, 0x6f,
+  0xae, 0x4f, 0x78, 0x7f, 0xf6, 0x4e, 0xb3, 0x7a, 0xbf, 0x36, 0x5c, 0x3f,
+  0x96, 0x43, 0x78, 0x3a, 0x4f, 0xeb, 0xb7, 0x51, 0xf9, 0x45, 0xdb, 0x9b,
+  0x69, 0x72, 0xf9, 0xc5, 0xdb, 0xe7, 0x41, 0xfb, 0x42, 0x22, 0xaf, 0xf6,
+  0x17, 0xe9, 0xfe, 0xf1, 0x58, 0x7b, 0x51, 0xb6, 0x41, 0xdf, 0x1f, 0xa1,
+  0x25, 0xf2, 0x7e, 0x91, 0x3f, 0xb1, 0x30, 0x4a, 0xeb, 0x24, 0x45, 0xb0,
+  0xdf, 0x48, 0x7b, 0xc9, 0xff, 0x2f, 0x67, 0x9b, 0xb4, 0xfe, 0xdb, 0x4b,
+  0xe4, 0x3f, 0x9f, 0xb6, 0xc9, 0xfb, 0x7c, 0x2c, 0xdb, 0x7f, 0x9a, 0xd8,
+  0x0a, 0x97, 0xe9, 0x75, 0xfe, 0x8b, 0xc7, 0x96, 0x6b, 0x6c, 0x3f, 0xdb,
+  0x63, 0x7c, 0x3f, 0xd6, 0xfb, 0x3e, 0x9f, 0x70, 0xfe, 0x58, 0x75, 0xa6,
+  0xd8, 0xef, 0x5e, 0x43, 0xe1, 0xd7, 0xb4, 0x89, 0x7f, 0xc2, 0xea, 0x75,
+  0x5d, 0xea, 0xb0, 0x5f, 0xc5, 0x7e, 0xee, 0x11, 0xef, 0x2d, 0xe3, 0x65,
+  0xdf, 0xe7, 0xfb, 0x57, 0xbe, 0x6f, 0x6b, 0xca, 0xfe, 0xed, 0x67, 0xf8,
+  0x1f, 0xb2, 0x7f, 0x37, 0xf8, 0xfe, 0x2d, 0xb4, 0xee, 0x5f, 0xcb, 0xbf,
+  0x34, 0x7c, 0x1e, 0xea, 0x97, 0x0a, 0xfd, 0x1a, 0x1e, 0x37, 0xf4, 0xeb,
+  0xe5, 0x7e, 0xd8, 0xbf, 0x51, 0xf0, 0x12, 0x91, 0x67, 0xe9, 0xfa, 0xd5,
+  0x25, 0xe3, 0x4d, 0xeb, 0x45, 0x34, 0xd8, 0x7e, 0x6e, 0xc1, 0xdf, 0xcb,
+  0xfa, 0x35, 0xc7, 0x2d, 0x15, 0x1f, 0x13, 0xe3, 0xa1, 0x91, 0xc3, 0xea,
+  0xd5, 0x54, 0xd1, 0x79, 0x9a, 0xff, 0x12, 0xd9, 0x0d, 0x5a, 0x9f, 0x11,
+  0xa3, 0x2f, 0xb3, 0x7c, 0x18, 0x2b, 0xa2, 0xd7, 0x11, 0x5a, 0x25, 0xd7,
+  0xf9, 0x8d, 0x77, 0x30, 0x7f, 0x5d, 0xd6, 0xc3, 0x43, 0x76, 0xbd, 0x3f,
+  0x5b, 0x9b, 0x8d, 0xeb, 0xed, 0x65, 0x58, 0x7e, 0x03, 0xe3, 0x97, 0x8c,
+  0xeb, 0xeb, 0x35, 0xe8, 0xf5, 0x77, 0xc8, 0xf7, 0x1b, 0xc1, 0xdd, 0xb3,
+  0x67, 0xad, 0xd2, 0x1c, 0xe0, 0xdb, 0xb1, 0x98, 0x64, 0xce, 0x4f, 0x6c,
+  0xd6, 0xc3, 0xf8, 0x5f, 0x00, 0x00, 0x00, 0xff, 0xff, 0xcc, 0x5d, 0x7f,
   0x6c, 0x5d, 0xd5, 0x7d, 0x3f, 0xf7, 0xc7, 0x7b, 0xbe, 0xcf, 0x7e, 0xef,
   0xe5, 0xc6, 0x31, 0xce, 0x73, 0x7e, 0x34, 0x37, 0x40, 0xa9, 0x03, 0x0c,
   0x99, 0x28, 0xed, 0xd2, 0xd0, 0x8d, 0xeb, 0xc4, 0x49, 0x6d, 0x12, 0xab,
-  0x41, 0xa8, 0x28, 0xfc, 0xe8, 0xf4, 0x98, 0xe8, 0x96, 0x40, 0x81, 0x50,
-  0xad, 0xc8, 0x34, 0x54, 0xbb, 0x8e, 0x6d, 0x9c, 0xa4, 0x31, 0x98, 0xc1,
+  0x41, 0xa8, 0x28, 0xfc, 0xe8, 0xf4, 0x98, 0xe8, 0x96, 0x40, 0x81, 0x30,
+  0xad, 0xcc, 0x34, 0x54, 0xbb, 0x8e, 0x6d, 0x9c, 0xa4, 0x31, 0x98, 0xc1,
   0xda, 0x94, 0xb2, 0xf6, 0x39, 0x09, 0x2d, 0x93, 0xba, 0x29, 0x7f, 0x4d,
   0xa8, 0x7f, 0x3d, 0x3b, 0x14, 0x25, 0x53, 0x2c, 0x45, 0xea, 0x54, 0x05,
   0x54, 0xad, 0xaf, 0x85, 0xad, 0x51, 0x99, 0x20, 0x5b, 0xd1, 0x66, 0x04,
@@ -11364,8 +11364,8 @@ unsigned char ql83xx_firmware[] = {
   0x3e, 0x98, 0xfd, 0x3e, 0x00, 0x64, 0x3c, 0xa1, 0x6c, 0xaf, 0xdd, 0x68,
   0x1d, 0x2e, 0xc0, 0xf9, 0x85, 0xf3, 0xb5, 0x89, 0xf8, 0xf1, 0xc1, 0x70,
   0xbf, 0x6f, 0xbf, 0x0a, 0xdf, 0xf0, 0x78, 0xa1, 0xf5, 0x2e, 0x3f, 0x1f,
-  0x83, 0xf2, 0x04, 0x8d, 0x5f, 0xce, 0x12, 0x47, 0xff, 0xcf, 0x68, 0x3d,
-  0xbf, 0x5f, 0x74, 0xc2, 0xf9, 0xad, 0x4e, 0x16, 0xde, 0x0c, 0xeb, 0x17,
+  0x83, 0xf2, 0x04, 0x8d, 0x5f, 0xce, 0x12, 0x47, 0xff, 0x4f, 0x69, 0x3d,
+  0xbf, 0x9f, 0x77, 0xc2, 0xf9, 0xad, 0x4e, 0x16, 0xde, 0x0c, 0xeb, 0x17,
   0x5a, 0xc1, 0x0a, 0x54, 0xbf, 0x30, 0x30, 0x8e, 0xe0, 0xf5, 0x22, 0xd7,
   0xdb, 0x7e, 0xdb, 0x43, 0xf5, 0xe0, 0x26, 0x0b, 0x3b, 0xe8, 0x79, 0x79,
   0x23, 0x98, 0x82, 0xf3, 0xd9, 0x03, 0x6d, 0xdb, 0x11, 0x1b, 0xe9, 0x1f,
@@ -11390,7 +11390,7 @@ unsigned char ql83xx_firmware[] = {
   0xa4, 0xfe, 0x58, 0x59, 0xb4, 0x6f, 0xc2, 0x7c, 0x67, 0x8e, 0xbf, 0xac,
   0xe2, 0xf6, 0x15, 0x7f, 0x19, 0xd1, 0xb7, 0x26, 0x2d, 0xa9, 0x5e, 0x68,
   0x60, 0x55, 0x44, 0x79, 0xe5, 0x75, 0x8c, 0x15, 0xd0, 0x78, 0x38, 0x42,
-  0xfd, 0xd1, 0x3f, 0x41, 0xf9, 0x98, 0x70, 0xbe, 0x43, 0xbc, 0x38, 0xf1,
+  0xfd, 0xd1, 0x3f, 0x42, 0xf9, 0x98, 0x70, 0xbe, 0x43, 0xbc, 0x38, 0xf1,
   0x27, 0x0b, 0xf1, 0x4e, 0x9b, 0xc6, 0xab, 0xc2, 0xf9, 0xc3, 0xd7, 0xcd,
   0xd0, 0x5f, 0xa8, 0x89, 0xdf, 0x00, 0xb0, 0xb3, 0xc8, 0xfb, 0xa3, 0xc5,
   0x1f, 0x02, 0xb5, 0x7e, 0x31, 0x6d, 0xbf, 0x6c, 0xca, 0xd7, 0xc9, 0xfe,
@@ -11401,13 +11401,13 @@ unsigned char ql83xx_firmware[] = {
   0x6d, 0x29, 0xf8, 0x1a, 0x75, 0x3e, 0x92, 0xdb, 0x2b, 0xef, 0xdc, 0xc8,
   0x4c, 0x60, 0xe3, 0x0c, 0xee, 0x0f, 0xaf, 0xe7, 0x9a, 0x09, 0x4f, 0xd8,
   0xfd, 0x06, 0xe7, 0xa7, 0x30, 0x2e, 0xe1, 0xdf, 0x73, 0xfd, 0xa3, 0x9b,
-  0x7c, 0xcf, 0x71, 0x79, 0x7c, 0xa2, 0xf1, 0x8c, 0x36, 0xaf, 0xfc, 0x6d,
-  0x7c, 0x1e, 0xb9, 0x67, 0xeb, 0xa3, 0xd5, 0xc9, 0x5f, 0xcf, 0x9e, 0xad,
+  0x7c, 0xcf, 0x71, 0x79, 0x7c, 0xa2, 0xf1, 0x8c, 0x36, 0xaf, 0xfc, 0x2d,
+  0x7c, 0x1e, 0xb9, 0x67, 0xeb, 0xa3, 0xd5, 0xc9, 0x5f, 0xcd, 0x9e, 0xad,
   0x5a, 0xe3, 0xa3, 0x4c, 0xbe, 0x18, 0x18, 0xdf, 0x7b, 0x70, 0xc8, 0xde,
   0x4f, 0xda, 0xf3, 0xe6, 0xc1, 0x34, 0xb6, 0x5f, 0x9f, 0x28, 0xa0, 0xf3,
   0xa5, 0x93, 0xf0, 0x63, 0x04, 0x45, 0x50, 0xbb, 0xf1, 0x7f, 0x50, 0xbd,
   0x84, 0x75, 0xc3, 0xa6, 0xdf, 0x55, 0x2c, 0x4f, 0x57, 0xe0, 0xf9, 0xf3,
-  0x5b, 0xc4, 0x2f, 0x30, 0x90, 0x13, 0xff, 0x2a, 0xf3, 0x45, 0xab, 0xfe,
+  0x1b, 0xc4, 0x2f, 0x30, 0x90, 0x13, 0xff, 0x2a, 0xf3, 0x45, 0xab, 0xfe,
   0x34, 0xe1, 0xfc, 0xaa, 0xc4, 0xcd, 0x17, 0x57, 0x58, 0x4f, 0xc0, 0xed,
   0x01, 0xaf, 0xaf, 0xec, 0x0a, 0xf5, 0xd7, 0x26, 0xd4, 0x5f, 0x11, 0x0c,
   0xd2, 0xb7, 0xbd, 0x36, 0xea, 0x6f, 0x99, 0xb1, 0x7d, 0xa8, 0x33, 0xaf,
@@ -11455,7 +11455,7 @@ unsigned char ql83xx_firmware[] = {
   0xf0, 0x35, 0xc8, 0x85, 0x37, 0x56, 0x94, 0xdb, 0xbb, 0x9e, 0x8f, 0x5f,
   0x41, 0x92, 0x47, 0xa4, 0x1e, 0xf0, 0xfa, 0x52, 0x38, 0x9f, 0x9f, 0x37,
   0x92, 0xe6, 0x33, 0x6b, 0x7c, 0x74, 0x3e, 0x65, 0xbf, 0xdd, 0xa2, 0x9b,
-  0x4f, 0xbc, 0xde, 0xc5, 0xe7, 0xbf, 0xc9, 0x86, 0xce, 0xce, 0x82, 0x4f,
+  0x4f, 0xbc, 0xde, 0xc5, 0xe7, 0xbf, 0xc1, 0x86, 0xce, 0xce, 0x82, 0x4f,
   0x72, 0xe0, 0x79, 0x43, 0xfa, 0x97, 0x5c, 0x8f, 0xe0, 0xe2, 0x22, 0xcf,
   0x03, 0x41, 0x7f, 0xd6, 0xe1, 0x21, 0x8d, 0xe4, 0xf9, 0xdf, 0xb7, 0xac,
   0xf3, 0xef, 0x82, 0x0c, 0xeb, 0x1f, 0x9e, 0x4c, 0xe1, 0x7a, 0x90, 0xf1,
@@ -11463,7 +11463,7 @@ unsigned char ql83xx_firmware[] = {
   0x1d, 0x1e, 0x60, 0xb9, 0xe2, 0xaf, 0x57, 0xa9, 0x3e, 0x51, 0x28, 0x5f,
   0x39, 0x9e, 0x11, 0x0b, 0x41, 0xf8, 0x4f, 0xe0, 0x7b, 0x9e, 0x8a, 0xc7,
   0x72, 0xbc, 0xa0, 0x84, 0xe2, 0x15, 0xa6, 0x73, 0x1b, 0xf1, 0x87, 0xd8,
-  0xbf, 0x6e, 0x06, 0x2b, 0xac, 0xf1, 0x81, 0x7b, 0x46, 0xbc, 0x33, 0x88,
+  0xbf, 0x6a, 0x06, 0x2b, 0xac, 0xf1, 0x81, 0x7b, 0x46, 0xbc, 0x33, 0x88,
   0xcf, 0x11, 0xec, 0x4c, 0xe1, 0x4b, 0x48, 0x96, 0xd7, 0x6e, 0x30, 0x65,
   0x21, 0x79, 0xed, 0x6e, 0x5f, 0xa0, 0xf2, 0x9a, 0xf7, 0xc7, 0xf1, 0x0c,
   0xd8, 0x1f, 0x5f, 0xed, 0x0f, 0xc9, 0x83, 0x40, 0xfc, 0x6a, 0x2d, 0xf8,
@@ -11479,10 +11479,10 @@ unsigned char ql83xx_firmware[] = {
   0xcb, 0x5b, 0x8d, 0x64, 0xbc, 0x86, 0xa2, 0xcf, 0xa5, 0xef, 0x2f, 0xd3,
   0x2f, 0x8d, 0xa9, 0xf2, 0x30, 0x98, 0xe0, 0xfe, 0xc9, 0xf3, 0x72, 0x7e,
   0x9c, 0x07, 0xe5, 0xf9, 0x1a, 0xf1, 0xf7, 0x8f, 0x2d, 0xf3, 0xfe, 0xff,
-  0x03, 0xc5, 0x53, 0x69, 0xf5, 0xdb, 0x3d, 0x4a, 0xbd, 0x6b, 0x56, 0x9f,
+  0x3d, 0xc5, 0x53, 0x69, 0xf5, 0xdb, 0x3d, 0x4a, 0xbd, 0x6b, 0x56, 0x9f,
   0x90, 0xeb, 0xb7, 0x1d, 0xad, 0x76, 0x82, 0xff, 0x3d, 0x81, 0xe3, 0x8d,
   0xf3, 0x06, 0xce, 0x4f, 0xda, 0x3a, 0x42, 0xfc, 0x63, 0xe0, 0x69, 0x96,
-  0x7f, 0xf7, 0x47, 0x52, 0x3e, 0xb0, 0x1a, 0x7f, 0xe8, 0x1b, 0x31, 0x98,
+  0x7f, 0xf7, 0x07, 0x52, 0x3e, 0xb0, 0x1a, 0x7f, 0xe8, 0x1b, 0x31, 0x98,
   0xfd, 0x41, 0xfc, 0x99, 0x7d, 0xb1, 0xfd, 0x8d, 0xb3, 0xaf, 0xda, 0x31,
   0x73, 0x27, 0xb7, 0xaf, 0x94, 0x7c, 0xf0, 0x58, 0xfc, 0x21, 0xcf, 0x7f,
   0x75, 0x9f, 0xc5, 0xf9, 0x0e, 0xc0, 0x60, 0xf1, 0x0a, 0xce, 0xdf, 0xc7,
@@ -11501,11 +11501,11 @@ unsigned char ql83xx_firmware[] = {
   0xeb, 0x21, 0xa8, 0x2c, 0x6e, 0xbc, 0x83, 0x94, 0xf1, 0x3e, 0xb0, 0xfc,
   0xf6, 0x06, 0xda, 0x71, 0x35, 0xb1, 0x1e, 0xba, 0x3a, 0xde, 0x86, 0x60,
   0x6f, 0x15, 0x94, 0xf3, 0xec, 0xf8, 0x12, 0xf5, 0xe7, 0xfb, 0xaf, 0x89,
-  0xbe, 0xf9, 0xd6, 0x1f, 0xac, 0xbe, 0x99, 0xd6, 0xff, 0x8c, 0xf1, 0x3a,
-  0x5f, 0x8d, 0xd7, 0xea, 0xce, 0xcf, 0xc0, 0xcc, 0x12, 0xaf, 0xfb, 0xc9,
+  0xbe, 0xf9, 0xd6, 0xef, 0xad, 0xbe, 0x99, 0xd6, 0xff, 0x8c, 0xf1, 0x3a,
+  0x5f, 0x8d, 0xd7, 0xea, 0xce, 0xcf, 0xc0, 0xcc, 0x12, 0xaf, 0xfb, 0xf1,
   0x0b, 0x74, 0x7e, 0xec, 0x8a, 0x49, 0xe2, 0x75, 0x23, 0x16, 0xad, 0xc7,
   0x63, 0x90, 0x52, 0x3b, 0x24, 0xde, 0x03, 0x4a, 0xe7, 0xfb, 0x7d, 0xf7,
-  0xbb, 0x1d, 0x6a, 0xbc, 0x87, 0xc5, 0x63, 0x02, 0x70, 0x7e, 0x8e, 0xd7,
+  0x3b, 0x1d, 0x6a, 0xbc, 0x87, 0xc5, 0x63, 0x02, 0x70, 0x7e, 0x8e, 0xd7,
   0xdb, 0x6c, 0x48, 0xf1, 0x78, 0x8a, 0x87, 0xe1, 0xf9, 0xe2, 0x76, 0x6c,
   0x3e, 0x83, 0x8b, 0xee, 0x4f, 0xc2, 0xf3, 0x6e, 0xc1, 0xf6, 0xde, 0x35,
   0x1a, 0xaf, 0xdb, 0xac, 0x14, 0x7a, 0x60, 0xd5, 0x70, 0x3e, 0x16, 0xab,
@@ -11518,7 +11518,7 @@ unsigned char ql83xx_firmware[] = {
   0x5a, 0x0e, 0x30, 0x3e, 0xab, 0x69, 0xfa, 0xc8, 0xff, 0x87, 0xf1, 0x58,
   0x5e, 0x89, 0xd6, 0x0f, 0x40, 0xfe, 0x7b, 0xe6, 0x6d, 0x58, 0x47, 0xf9,
   0xf5, 0xad, 0x69, 0x77, 0xed, 0xa7, 0xa6, 0xef, 0xa0, 0xf9, 0x62, 0x34,
-  0x4f, 0xf8, 0xe7, 0xd4, 0x9e, 0x0f, 0xf1, 0x98, 0x5b, 0xc2, 0x78, 0x9d,
+  0x4f, 0xf8, 0x67, 0xd4, 0x9e, 0x0f, 0xf1, 0x98, 0x5b, 0xc2, 0x78, 0x9d,
   0x5f, 0x14, 0xfd, 0x3f, 0xa0, 0xde, 0x0e, 0x74, 0xf2, 0x2f, 0x46, 0x1e,
   0xae, 0x52, 0xec, 0x29, 0x8d, 0xbc, 0xd4, 0xe8, 0x67, 0x71, 0xfa, 0x18,
   0x66, 0x52, 0x3f, 0xc7, 0xe4, 0xcb, 0x85, 0xc4, 0x7a, 0xa1, 0x31, 0xf1,
@@ -11528,11 +11528,11 @@ unsigned char ql83xx_firmware[] = {
   0x32, 0x4c, 0x3f, 0x97, 0xae, 0x59, 0x7f, 0x6e, 0xc8, 0xd8, 0x1f, 0xce,
   0x57, 0xba, 0x57, 0xeb, 0xff, 0x0b, 0xfc, 0xf8, 0xfa, 0x6d, 0xf1, 0xe3,
   0xa3, 0x9e, 0x17, 0x60, 0x3c, 0xc4, 0x77, 0x0a, 0xf1, 0xe1, 0xc7, 0xc7,
-  0xf2, 0xc9, 0x8b, 0x3f, 0x3d, 0xa6, 0x7b, 0x7e, 0x79, 0xbe, 0xff, 0xf8,
+  0xf2, 0xc9, 0x8b, 0x3f, 0x3e, 0xa6, 0x7b, 0x7e, 0x79, 0xbe, 0xff, 0xf8,
   0xc1, 0x6c, 0xfd, 0x61, 0xcf, 0x7f, 0x7c, 0x34, 0x5f, 0xff, 0x07, 0xb5,
   0xfd, 0xcf, 0x2a, 0xef, 0xbe, 0x56, 0x6a, 0xcd, 0x18, 0xa7, 0xf8, 0x75,
   0x1f, 0x93, 0x77, 0x25, 0x76, 0x1e, 0x56, 0xe4, 0xe7, 0x17, 0xe4, 0x6b,
-  0x24, 0x2f, 0xe4, 0xfb, 0xf8, 0xfa, 0x37, 0x1e, 0x30, 0x9b, 0x2b, 0x18,
+  0x24, 0x2f, 0xe4, 0xfb, 0xf8, 0xfa, 0xd7, 0x1e, 0x30, 0x9b, 0x2b, 0x18,
   0xfe, 0x1c, 0xc9, 0xbf, 0x0b, 0x46, 0x26, 0x3c, 0x9a, 0x0e, 0xef, 0xed,
   0xce, 0x8f, 0x92, 0xf3, 0x67, 0xbf, 0xc2, 0x3f, 0xc9, 0xfd, 0xe5, 0x1d,
   0xa0, 0x84, 0xfc, 0x2f, 0x5b, 0xf7, 0x92, 0xf8, 0xc3, 0x90, 0xb4, 0xdf,
@@ -11550,7 +11550,7 @@ unsigned char ql83xx_firmware[] = {
   0x8d, 0x58, 0xf5, 0x71, 0x43, 0xc8, 0x07, 0x27, 0xf9, 0x7c, 0xde, 0xf6,
   0x8a, 0xd9, 0xdf, 0xb9, 0xb6, 0x3a, 0xbd, 0x99, 0xf2, 0xc7, 0xc0, 0xd6,
   0x95, 0xf8, 0x8a, 0x9d, 0xe6, 0xbf, 0x27, 0xfc, 0x3c, 0xcc, 0xdf, 0xf1,
-  0x79, 0xa9, 0xfd, 0xac, 0xe7, 0xc5, 0x0f, 0x35, 0xe7, 0x45, 0x58, 0xcf,
+  0x79, 0xa9, 0xfd, 0xac, 0xe7, 0xc5, 0x0f, 0x34, 0xe7, 0x45, 0x58, 0xcf,
   0x9c, 0xb5, 0xbf, 0x69, 0x59, 0xdb, 0x0f, 0xd7, 0xd3, 0x4d, 0x52, 0xfe,
   0x2c, 0x68, 0x16, 0x8d, 0xc6, 0x4a, 0x0f, 0xcb, 0xa3, 0xbb, 0x2c, 0x72,
   0xbf, 0x8e, 0xf9, 0xaf, 0x10, 0x3e, 0xfe, 0x05, 0x14, 0xef, 0xaf, 0x04,
@@ -11561,417 +11561,417 @@ unsigned char ql83xx_firmware[] = {
   0x8f, 0xf8, 0xd2, 0x84, 0xfa, 0x01, 0x1e, 0x6f, 0x1f, 0xf6, 0xdf, 0xf5,
   0xa8, 0xfd, 0xfa, 0xaa, 0xc5, 0xda, 0x27, 0xf8, 0xdf, 0x17, 0x4d, 0x7d,
   0xff, 0x8f, 0x02, 0x19, 0x4f, 0xc1, 0xcf, 0x6b, 0xcd, 0x79, 0x1b, 0x7f,
-  0x9e, 0x3c, 0xf2, 0xbd, 0xf0, 0x3c, 0xc1, 0xf3, 0xd7, 0xcb, 0xf9, 0x52,
+  0x9e, 0x3c, 0xf2, 0xdd, 0xf0, 0x3c, 0xc1, 0xf3, 0xd7, 0xcb, 0xf9, 0x52,
   0x24, 0xf9, 0x1a, 0x7d, 0x7e, 0xc8, 0x24, 0xf9, 0xdf, 0x24, 0x5f, 0x40,
-  0xad, 0x4f, 0x18, 0x7d, 0xfe, 0x3c, 0x79, 0xfe, 0xf5, 0x8f, 0xc8, 0xf3,
-  0x61, 0xff, 0x57, 0x48, 0xfd, 0x5d, 0x38, 0xb4, 0x42, 0x94, 0xc7, 0x6a,
-  0xfd, 0xe6, 0x5b, 0x69, 0x3c, 0x9b, 0xe3, 0x8d, 0x68, 0x7e, 0x32, 0x51,
-  0xe0, 0x4e, 0xb6, 0x89, 0xf5, 0xd3, 0xa1, 0x35, 0x5b, 0x01, 0xfe, 0x4d,
-  0x34, 0x7e, 0x3a, 0x2c, 0xc5, 0x5f, 0x61, 0xff, 0xad, 0x6d, 0x36, 0xc5,
-  0xeb, 0x64, 0x18, 0x9f, 0xe8, 0x7a, 0x65, 0xfd, 0xa7, 0xbf, 0xc7, 0x6d,
-  0xfd, 0x18, 0xaf, 0x0f, 0xcf, 0x4e, 0xca, 0xb7, 0x67, 0xef, 0x3f, 0x6f,
-  0x6c, 0xb1, 0xa9, 0x7f, 0x75, 0x49, 0xef, 0x67, 0xbf, 0xe7, 0xe3, 0xb7,
-  0x52, 0xbe, 0xfe, 0x78, 0x25, 0xf3, 0x27, 0x67, 0xc8, 0x47, 0x08, 0x6a,
-  0x6a, 0xbe, 0x4c, 0x72, 0x7e, 0x4d, 0xb3, 0xc6, 0xf3, 0x17, 0xe8, 0xfb,
-  0x7c, 0x68, 0xff, 0x36, 0x45, 0xfc, 0x74, 0x58, 0x4f, 0x2a, 0xee, 0xfd,
-  0x2f, 0x09, 0xf1, 0x39, 0x8c, 0x7f, 0xe4, 0x7c, 0x57, 0xac, 0xbd, 0xcb,
-  0x1d, 0x5e, 0x93, 0xe8, 0xd7, 0xf8, 0x3e, 0xf7, 0xd7, 0xca, 0xfc, 0x61,
-  0x6a, 0xfe, 0x12, 0xb3, 0x77, 0x2e, 0xa9, 0xf9, 0x7a, 0xfe, 0xd3, 0xf8,
-  0xbc, 0x0f, 0xdf, 0x27, 0xf7, 0x67, 0xe2, 0x7b, 0xaa, 0xfd, 0xbf, 0x60,
-  0x29, 0xf6, 0xfb, 0xd5, 0xc9, 0x4f, 0x73, 0x41, 0xd3, 0x97, 0xea, 0x5f,
-  0x1a, 0x6c, 0xfe, 0xa8, 0x3e, 0xc5, 0xae, 0x1f, 0x95, 0xaf, 0x6b, 0x4c,
-  0x1f, 0xd3, 0xc6, 0x7f, 0xc8, 0xfd, 0x69, 0x24, 0x7f, 0xd6, 0x94, 0x59,
-  0xfc, 0x83, 0xd9, 0x8b, 0xac, 0xfe, 0xb2, 0x50, 0x0f, 0x2d, 0xac, 0xaf,
-  0x06, 0x84, 0x78, 0x06, 0xaa, 0x6f, 0xb6, 0x0e, 0x9d, 0xe5, 0x23, 0xd8,
-  0x3e, 0xf3, 0x9d, 0x12, 0x08, 0xba, 0x11, 0x77, 0xd4, 0x88, 0x8b, 0xcf,
-  0x27, 0x93, 0x8c, 0xd7, 0x29, 0x7b, 0x01, 0xaf, 0x47, 0x64, 0xff, 0x1f,
-  0x46, 0xf6, 0xeb, 0xb9, 0x47, 0x4c, 0x1f, 0xbe, 0xaf, 0xb8, 0xc3, 0xab,
-  0xa2, 0x7c, 0x8f, 0xe6, 0x57, 0x6b, 0x33, 0x3d, 0x28, 0x1f, 0xc1, 0x43,
-  0xe7, 0xf3, 0x8b, 0x70, 0x12, 0x17, 0xaa, 0xa2, 0x3f, 0x20, 0xac, 0xf7,
-  0x3c, 0x24, 0xe3, 0xc5, 0xb4, 0xfa, 0xbe, 0xce, 0x1e, 0x72, 0x42, 0x3c,
-  0x3b, 0x1e, 0x9f, 0x41, 0x43, 0xd6, 0x37, 0xe4, 0xe7, 0xa9, 0x3f, 0x03,
-  0xfc, 0x23, 0xf5, 0x67, 0x74, 0x0d, 0x78, 0x2e, 0x8e, 0x87, 0xdc, 0x58,
-  0x9b, 0xbd, 0x1b, 0xe7, 0x4f, 0xf0, 0x78, 0x48, 0x95, 0xf6, 0x07, 0xc8,
-  0xe7, 0x23, 0xdd, 0x10, 0xb4, 0xfe, 0x34, 0x5a, 0x7f, 0x66, 0x9b, 0xe0,
-  0x2f, 0xa3, 0xf1, 0xf9, 0x51, 0xee, 0x8f, 0xe4, 0x78, 0x8d, 0xf5, 0x71,
-  0x78, 0x73, 0x1b, 0xbe, 0xfd, 0xae, 0x1e, 0x84, 0xc1, 0x64, 0xf9, 0xbe,
-  0xb7, 0xb2, 0x09, 0xed, 0xd2, 0xe5, 0xf7, 0x28, 0xfe, 0xb8, 0xa6, 0x25,
-  0xc5, 0x6b, 0x18, 0xbe, 0xb9, 0xbe, 0x57, 0xfc, 0x7e, 0xcb, 0x71, 0x68,
-  0x3d, 0x3b, 0xae, 0x6f, 0xc8, 0xf5, 0x0b, 0xfd, 0x3e, 0x0d, 0x1f, 0xd1,
-  0xfd, 0xd9, 0xf4, 0x0d, 0x1e, 0xbf, 0xda, 0xc6, 0xee, 0x75, 0xe4, 0xd1,
-  0x07, 0x3e, 0xfd, 0xed, 0x14, 0x7d, 0x83, 0xf3, 0x8b, 0x32, 0x7f, 0xad,
-  0xae, 0xfd, 0x73, 0xca, 0x7a, 0x70, 0x92, 0xd7, 0x83, 0xd7, 0x02, 0xdb,
-  0x9f, 0xac, 0x1d, 0x7e, 0xd5, 0x6d, 0x1a, 0xbd, 0xb5, 0x67, 0x83, 0x1f,
-  0xed, 0x20, 0x83, 0xf3, 0xe6, 0xc3, 0xb5, 0x59, 0xbc, 0x7e, 0x23, 0xfd,
-  0xe3, 0xeb, 0x95, 0xb6, 0xc7, 0xf9, 0x96, 0xd9, 0xfb, 0xac, 0xa4, 0xf7,
-  0x39, 0xf0, 0x7d, 0xbf, 0xf1, 0x6a, 0xe6, 0xbf, 0xdd, 0xdd, 0x30, 0xfa,
-  0xdc, 0x63, 0xc1, 0x2f, 0xb6, 0x93, 0xf7, 0xcd, 0xc1, 0xf5, 0x77, 0x5f,
-  0xfc, 0xfb, 0x94, 0xef, 0x39, 0xa7, 0xbc, 0x6f, 0x30, 0xf1, 0x7d, 0xf6,
-  0x18, 0x5d, 0xef, 0x64, 0xa4, 0x82, 0xea, 0x80, 0x87, 0x53, 0xda, 0xe7,
-  0xbe, 0x5a, 0x9b, 0xfd, 0x3c, 0x7e, 0x5f, 0x49, 0x6a, 0x1f, 0xe9, 0xfb,
-  0x26, 0x8a, 0xff, 0x22, 0xbe, 0xd7, 0x22, 0xc1, 0xdf, 0x6c, 0x5e, 0x45,
-  0xf4, 0x2d, 0x52, 0x2f, 0xf5, 0x00, 0xe3, 0x4f, 0xb9, 0x9c, 0xa7, 0x1e,
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+  0xe0, 0xfb, 0xbe, 0xe5, 0xe3, 0x7a, 0xe4, 0x53, 0x06, 0xa6, 0x5c, 0xad,
+  0x51, 0xbc, 0xb2, 0x1a, 0x7f, 0x74, 0x4b, 0xc0, 0xaa, 0x49, 0xf2, 0x27,
+  0x45, 0x1e, 0x3c, 0x70, 0x55, 0xe4, 0xc1, 0x3b, 0xa9, 0xe7, 0x5b, 0xd6,
+  0x78, 0xa3, 0x6a, 0x5f, 0x97, 0x7c, 0x42, 0x29, 0xcf, 0xfd, 0x4f, 0x7b,
+  0xfd, 0xa8, 0x3e, 0x0d, 0xae, 0x73, 0x80, 0x41, 0xf4, 0x69, 0xf5, 0x7b,
+  0x38, 0xbf, 0x58, 0x1b, 0xc6, 0x2b, 0x63, 0x7d, 0x1f, 0x71, 0x9c, 0xd0,
+  0xf8, 0x46, 0x24, 0x3e, 0xb8, 0x27, 0x31, 0xbe, 0xc1, 0xfd, 0x31, 0x3c,
+  0xbe, 0x71, 0x5f, 0x2e, 0xbc, 0x17, 0xfb, 0xcb, 0xab, 0xcf, 0xc7, 0x9f,
+  0x27, 0xfc, 0x3c, 0xe2, 0xf2, 0x88, 0xd7, 0x1f, 0xaa, 0x24, 0xef, 0x77,
+  0x9d, 0xff, 0x23, 0xb2, 0xdf, 0x3b, 0xe8, 0xf8, 0x59, 0x27, 0xe0, 0x7a,
+  0x63, 0xfb, 0xe9, 0xcb, 0x5f, 0xe7, 0xf2, 0x20, 0x11, 0xcf, 0xa4, 0xc1,
+  0x77, 0x34, 0x19, 0xbf, 0x32, 0x51, 0x6f, 0x4e, 0xf2, 0xf3, 0x8a, 0xcd,
+  0xe7, 0xc5, 0x7f, 0xf8, 0x49, 0x07, 0xbe, 0x0f, 0x7f, 0xf0, 0x6d, 0x7c,
+  0x5e, 0x7a, 0xa0, 0x65, 0xa1, 0xfc, 0x0a, 0xe6, 0xac, 0x8b, 0xaf, 0xcf,
+  0xce, 0xd4, 0x25, 0xf6, 0x7b, 0xe4, 0x8d, 0xc3, 0xa9, 0x29, 0x82, 0x7f,
+  0x51, 0x7c, 0x3f, 0xd9, 0x8f, 0xcf, 0xda, 0xe2, 0x7c, 0x01, 0x70, 0xba,
+  0x10, 0xf6, 0x27, 0x82, 0xdf, 0xf0, 0x27, 0x8b, 0xe9, 0xf3, 0xf5, 0xf7,
+  0xcf, 0x2f, 0x55, 0x1f, 0xd6, 0xf9, 0xa7, 0x73, 0xca, 0x9b, 0x34, 0x7b,
+  0x35, 0x36, 0x1e, 0xa2, 0xc4, 0x0b, 0xd1, 0x9f, 0x5e, 0xae, 0x3f, 0x26,
+  0xc6, 0x0b, 0x7d, 0x2c, 0xdf, 0x3c, 0x21, 0x9e, 0xca, 0xf9, 0xb0, 0xb0,
+  0xfd, 0x66, 0x62, 0x3e, 0x1e, 0x21, 0x9e, 0x18, 0xe9, 0x5f, 0x4f, 0xe2,
+  0x7e, 0x8a, 0xd6, 0x47, 0xe5, 0xfa, 0x6a, 0x21, 0xcf, 0x7e, 0xfa, 0xa5,
+  0x66, 0x7e, 0xa2, 0xfe, 0xd3, 0x07, 0x92, 0xed, 0xa7, 0x9c, 0xed, 0xab,
+  0xfc, 0xe6, 0xba, 0xfc, 0xdf, 0x19, 0x6e, 0x3f, 0x56, 0xe6, 0x48, 0xbe,
+  0x5c, 0x32, 0x5e, 0xef, 0x1d, 0xed, 0xfb, 0x54, 0xfb, 0x68, 0x5e, 0xc1,
+  0xff, 0xa9, 0x7c, 0xc0, 0x9c, 0x6f, 0xcb, 0x14, 0xf5, 0xbf, 0x7f, 0x12,
+  0xec, 0x59, 0xb1, 0x3e, 0x58, 0xee, 0xfe, 0x78, 0x64, 0xe5, 0x49, 0xfc,
+  0x0b, 0xe8, 0x06, 0x93, 0x87, 0x2e, 0x68, 0xb6, 0x4b, 0xe7, 0x2b, 0x68,
+  0x6b, 0x39, 0x98, 0xef, 0x07, 0x5c, 0x8c, 0xf2, 0xf7, 0x07, 0xe5, 0xc3,
+  0x1e, 0xdb, 0xd2, 0xc6, 0x60, 0x4c, 0x3c, 0x75, 0x8e, 0x67, 0x9f, 0x35,
+  0x0d, 0x67, 0xce, 0x18, 0x4d, 0x1f, 0xaf, 0xe5, 0x8a, 0x1f, 0x5d, 0x4e,
+  0xb1, 0x57, 0x99, 0x7f, 0x36, 0xa0, 0xf6, 0xaa, 0x9f, 0xa2, 0x4f, 0x50,
+  0xfc, 0xbb, 0x82, 0x4f, 0x8a, 0xf8, 0x97, 0x03, 0xdb, 0xa0, 0x78, 0x3c,
+  0x8a, 0x4f, 0x22, 0xf5, 0x98, 0xd0, 0x2d, 0x8c, 0x1f, 0xf2, 0xed, 0x78,
+  0xfc, 0xfb, 0x7e, 0x5d, 0x3c, 0x09, 0xca, 0x91, 0xca, 0x24, 0xe6, 0x57,
+  0x1a, 0xc4, 0xfc, 0xff, 0x6a, 0xbc, 0x5a, 0xe6, 0x0b, 0x17, 0xf8, 0xf6,
+  0x89, 0x7e, 0xa5, 0xd8, 0xa7, 0x3e, 0x95, 0x4c, 0x12, 0x9f, 0x9f, 0xc4,
+  0x2f, 0x9f, 0xd5, 0xbf, 0xac, 0x93, 0x9f, 0x8b, 0xd3, 0x47, 0xd4, 0xf5,
+  0xbb, 0x99, 0x64, 0x06, 0x1e, 0xfc, 0x3f, 0x00, 0x00, 0x00, 0xff, 0xff,
   0xcc, 0x5d, 0x6b, 0x70, 0x1d, 0x57, 0x7d, 0x3f, 0x7b, 0x76, 0xef, 0xbd,
   0x7b, 0x9f, 0xde, 0xd8, 0x42, 0x91, 0x1f, 0x89, 0x57, 0xb6, 0x6c, 0x2b,
   0xc4, 0x78, 0x94, 0xd8, 0x80, 0x06, 0x9b, 0xb2, 0x92, 0x15, 0x23, 0xc7,
@@ -11981,131379 +11981,131336 @@ unsigned char ql83xx_firmware[] = {
   0xc4, 0x33, 0x74, 0x3a, 0x99, 0xe9, 0x87, 0x5e, 0x3b, 0x0e, 0x09, 0xa9,
   0x05, 0xa6, 0xa5, 0xd0, 0x21, 0x30, 0x73, 0x43, 0xbf, 0xa8, 0x26, 0x09,
   0x6e, 0xa7, 0x05, 0x41, 0x03, 0xea, 0x79, 0x9f, 0x3d, 0x67, 0x1f, 0xf7,
-  0x5e, 0x39, 0x30, 0xf5, 0x07, 0xc8, 0x8e, 0xf6, 0xee, 0x9e, 0x3d, 0x8f,
-  0xff, 0xf3, 0xf7, 0xff, 0xfd, 0xaf, 0xd7, 0x3e, 0xd1, 0xfd, 0xa9, 0xa7,
-  0x81, 0xc0, 0xf3, 0xb6, 0x9d, 0xba, 0x18, 0xc6, 0xf3, 0x26, 0xe0, 0x2d,
-  0x88, 0x3d, 0x62, 0x11, 0x7e, 0x4b, 0x57, 0xf6, 0x9f, 0xb5, 0xd0, 0xb5,
-  0xe2, 0x4f, 0xbc, 0xb7, 0x45, 0x7b, 0xe4, 0xee, 0x45, 0xd9, 0x23, 0x9b,
-  0xa6, 0xa3, 0xcf, 0x8f, 0xd0, 0xb7, 0x42, 0x7e, 0xde, 0xdf, 0xc0, 0x1e,
-  0x69, 0x51, 0x9f, 0x69, 0x7c, 0x6e, 0x81, 0xfa, 0x9b, 0x54, 0x2b, 0xcf,
-  0xbf, 0xf0, 0x21, 0xe1, 0x3f, 0xa9, 0xf5, 0x2c, 0x2e, 0xf0, 0x83, 0xf9,
-  0x40, 0x7e, 0xff, 0xaf, 0xc5, 0xfd, 0x3b, 0x4d, 0x85, 0x5f, 0xae, 0xe1,
-  0xfe, 0x11, 0xfc, 0xb6, 0xa5, 0x24, 0xfd, 0xfd, 0xc6, 0xd6, 0xe8, 0xf1,
-  0xd8, 0x58, 0xa7, 0x46, 0xe0, 0xdf, 0x57, 0x6f, 0xe3, 0xf7, 0x7f, 0x07,
-  0x5c, 0xdf, 0x78, 0xae, 0x4f, 0xde, 0x45, 0xf4, 0xc3, 0x6d, 0xd0, 0x5f,
-  0xac, 0x21, 0x7e, 0x35, 0x9a, 0xbf, 0x55, 0xc8, 0x23, 0x76, 0x2d, 0xf0,
-  0xbc, 0xad, 0xf2, 0xbb, 0x36, 0xda, 0xdf, 0x0d, 0xf8, 0x5f, 0x35, 0xbc,
-  0x33, 0x37, 0x8f, 0x5e, 0x7f, 0x9c, 0x39, 0xb9, 0x5a, 0x3f, 0xbc, 0x11,
-  0x17, 0x59, 0x4d, 0x44, 0xfe, 0xfa, 0xb0, 0x97, 0xf6, 0xe7, 0xcd, 0x51,
-  0xbe, 0x3a, 0x40, 0xfb, 0x9b, 0xc1, 0x29, 0x93, 0xd8, 0x3f, 0xf3, 0x3c,
-  0xbe, 0xfa, 0x67, 0xe9, 0xe0, 0x79, 0x07, 0xa9, 0xac, 0xd7, 0xe7, 0xac,
-  0xc8, 0xc9, 0xfe, 0x39, 0xfa, 0x78, 0x73, 0xc9, 0xfe, 0x19, 0xb3, 0xe7,
-  0xfc, 0x81, 0x62, 0xc0, 0xde, 0x9e, 0xc8, 0x87, 0xf2, 0x7b, 0x73, 0x3c,
-  0xbf, 0x47, 0xff, 0x7d, 0x52, 0xec, 0x17, 0x4b, 0x89, 0x37, 0x0b, 0x43,
-  0x99, 0x3d, 0x8f, 0xea, 0xef, 0x09, 0x53, 0x7b, 0x5e, 0x55, 0xf2, 0xb3,
-  0x5a, 0x89, 0xf1, 0xea, 0x56, 0xaf, 0x21, 0xce, 0x73, 0x04, 0xd6, 0x07,
-  0x8b, 0x9a, 0xde, 0x4b, 0xae, 0x19, 0x90, 0xff, 0x7c, 0xff, 0xd1, 0x7a,
-  0x61, 0xe7, 0x3b, 0x06, 0xe5, 0x23, 0x3f, 0x58, 0xf0, 0x4e, 0x1b, 0x81,
-  0x7e, 0x1b, 0x47, 0x68, 0xbf, 0x0d, 0x88, 0xf5, 0xf5, 0x4c, 0x96, 0xf4,
-  0x83, 0x1e, 0xc7, 0xf5, 0x59, 0x3b, 0x61, 0x3f, 0x16, 0x29, 0xde, 0xa1,
-  0x1c, 0xe1, 0xbb, 0x30, 0x76, 0x1a, 0xfd, 0x78, 0x4b, 0xf8, 0x6f, 0x93,
-  0xeb, 0xd2, 0xb1, 0xf2, 0xd1, 0x14, 0xd1, 0x87, 0x75, 0xd8, 0x4b, 0xf9,
-  0x33, 0x04, 0x1e, 0x59, 0xeb, 0xaf, 0xb0, 0x48, 0xfc, 0xbc, 0xde, 0x7f,
-  0x30, 0xc4, 0x27, 0xcc, 0xf5, 0x39, 0xe9, 0xf7, 0x82, 0x54, 0xf9, 0xf4,
-  0x4f, 0x4c, 0x1c, 0x84, 0xac, 0x1b, 0x83, 0x2f, 0xb9, 0x15, 0x9b, 0xb6,
-  0x47, 0xf5, 0xe1, 0xc7, 0x79, 0x3f, 0x36, 0xe1, 0x6f, 0xd2, 0xfe, 0x8a,
-  0xc6, 0x6c, 0x5f, 0x9f, 0xb3, 0x3c, 0x23, 0xc7, 0x27, 0xec, 0x3d, 0xa5,
-  0x7f, 0xc7, 0xc1, 0x7b, 0x45, 0xbc, 0xcb, 0xeb, 0x53, 0xfc, 0x9d, 0xac,
-  0xec, 0x9f, 0x5e, 0x0d, 0xf7, 0x07, 0x84, 0xa0, 0x70, 0x91, 0xca, 0x03,
-  0x3e, 0xde, 0xdd, 0x6a, 0x3f, 0x42, 0xde, 0x1f, 0xdb, 0x7f, 0x18, 0x46,
-  0xf7, 0xc7, 0xd6, 0xfa, 0x55, 0xea, 0xfe, 0x08, 0x18, 0x90, 0xf5, 0xc7,
-  0x4d, 0x9d, 0xe7, 0xac, 0x8a, 0x17, 0x0e, 0xe1, 0xfb, 0xd8, 0xfb, 0xec,
-  0x11, 0xb0, 0x98, 0x7e, 0xa0, 0xf1, 0xeb, 0x37, 0xd7, 0xa0, 0x7f, 0xa4,
-  0x0f, 0xdc, 0xb0, 0x3d, 0x85, 0xf4, 0xe7, 0xac, 0x41, 0xf4, 0xa7, 0x73,
-  0x90, 0xf0, 0x3d, 0xe3, 0xcf, 0x67, 0xf5, 0xc0, 0x1e, 0xb6, 0x61, 0x01,
-  0xc4, 0xfd, 0xbf, 0xce, 0xa2, 0xfd, 0x7a, 0x88, 0xd4, 0xab, 0x07, 0xf8,
-  0xe6, 0xa8, 0xfd, 0x65, 0xef, 0xde, 0xee, 0x95, 0x56, 0xe6, 0xe3, 0xe2,
-  0x79, 0x7c, 0x7d, 0xfb, 0xa6, 0xf9, 0xfa, 0x0e, 0x99, 0xbd, 0x4d, 0xf8,
-  0x17, 0x27, 0xa7, 0xe3, 0xec, 0xe5, 0xa2, 0xb6, 0xfe, 0x4c, 0x7f, 0x4f,
-  0xf3, 0xf3, 0x39, 0x64, 0x7e, 0x60, 0x00, 0x9f, 0x4f, 0xde, 0xbf, 0xa5,
-  0xe9, 0x7e, 0x49, 0x4d, 0x9d, 0x1f, 0x34, 0x7e, 0xa6, 0x1f, 0x55, 0x7b,
-  0xd8, 0x1d, 0x96, 0x78, 0x1d, 0xfc, 0xef, 0x77, 0xac, 0x3e, 0xec, 0xe6,
-  0x1b, 0xcb, 0x3f, 0x18, 0xb5, 0x4d, 0xc6, 0x4f, 0x8a, 0xfd, 0x81, 0x59,
-  0x85, 0xff, 0xa3, 0x0a, 0x8e, 0xa2, 0xf9, 0xb3, 0xd0, 0xa6, 0x78, 0xc4,
-  0x02, 0xe3, 0x61, 0xbe, 0x20, 0x34, 0x73, 0x6a, 0x3d, 0x85, 0xc8, 0x0f,
-  0xdf, 0x97, 0xd5, 0xf2, 0xcb, 0x91, 0xf6, 0xa2, 0xa8, 0x67, 0x90, 0xfa,
-  0xa8, 0xb5, 0x7a, 0x06, 0x2d, 0x9e, 0x18, 0xee, 0x97, 0x21, 0xe4, 0x05,
-  0xdf, 0x7f, 0x36, 0x7d, 0xbe, 0x0b, 0xba, 0x91, 0xbc, 0x70, 0x48, 0xfc,
-  0x73, 0x3b, 0xba, 0xbe, 0xdf, 0xa2, 0x7c, 0x38, 0x00, 0xfa, 0xa4, 0xde,
-  0xa0, 0x0a, 0xce, 0x05, 0xf1, 0x65, 0x6e, 0xac, 0x3f, 0x00, 0xdc, 0xac,
-  0xcf, 0xfc, 0x15, 0xc2, 0xf7, 0xa0, 0xe1, 0x69, 0xb4, 0xfa, 0x7d, 0xe3,
-  0xf2, 0x05, 0x86, 0x2f, 0xcb, 0x24, 0xed, 0xc7, 0x93, 0xf7, 0x72, 0x7b,
-  0x06, 0x4f, 0x2f, 0xb6, 0x6f, 0x1f, 0xc1, 0x34, 0xb3, 0x32, 0xdf, 0x22,
-  0xfa, 0x01, 0x77, 0x18, 0xc9, 0xf6, 0xde, 0xac, 0xc6, 0xe7, 0x32, 0xa5,
-  0xe5, 0xdf, 0x2f, 0xcb, 0xfe, 0xbf, 0xb4, 0x9f, 0x9e, 0x32, 0x7e, 0x3e,
-  0x9e, 0x51, 0x71, 0x3e, 0x66, 0x21, 0xd9, 0x5f, 0xfe, 0x81, 0xc4, 0xfc,
-  0xe7, 0xeb, 0x31, 0xe7, 0xc3, 0x25, 0xf8, 0x32, 0x37, 0x25, 0xf1, 0x6c,
-  0x9f, 0xe1, 0xd2, 0xd4, 0xe6, 0x7c, 0x08, 0x81, 0xf3, 0x52, 0x0e, 0xc8,
-  0x8f, 0x26, 0xe3, 0x73, 0x85, 0x64, 0xfd, 0xcf, 0xbe, 0xb6, 0x16, 0xd4,
-  0xd7, 0x3a, 0x9f, 0xba, 0x6b, 0x16, 0xf5, 0xe7, 0xff, 0x6b, 0x8c, 0xfe,
-  0xe7, 0xfe, 0x5c, 0x9d, 0x3d, 0x2f, 0xd4, 0xcf, 0x30, 0xc4, 0x67, 0x09,
-  0x5a, 0xd4, 0xff, 0xa1, 0xf8, 0x04, 0x08, 0xae, 0x97, 0xae, 0xff, 0x2d,
-  0xb4, 0xbe, 0xcc, 0xfe, 0x35, 0xd4, 0xf5, 0x9d, 0x83, 0x8b, 0xb3, 0x37,
-  0x44, 0xfd, 0x72, 0xb2, 0xff, 0x24, 0xf0, 0x15, 0xfb, 0x32, 0x41, 0xfd,
-  0xfa, 0xae, 0xe5, 0xbf, 0x45, 0x3c, 0x61, 0x52, 0xf6, 0xbf, 0x53, 0xf0,
-  0xc7, 0xc3, 0x66, 0x94, 0xbe, 0x5a, 0x71, 0x98, 0xf6, 0x13, 0x1c, 0xfc,
-  0x3e, 0x53, 0x32, 0x64, 0x6e, 0x8c, 0x1c, 0xc7, 0x37, 0xeb, 0xf9, 0xac,
-  0x02, 0xc6, 0x43, 0xee, 0xc8, 0x40, 0x9e, 0x2f, 0x0b, 0xf0, 0xbb, 0x9b,
-  0x1a, 0xdf, 0x7a, 0xe4, 0xfb, 0xec, 0x23, 0xf4, 0x7d, 0x9d, 0x9c, 0x9f,
-  0x9b, 0xc4, 0x3f, 0x76, 0x41, 0x30, 0xff, 0x8b, 0x54, 0x7d, 0x82, 0xea,
-  0xaf, 0xf3, 0x54, 0x7f, 0xf9, 0x44, 0x7f, 0xd9, 0x84, 0x6f, 0x1a, 0xe9,
-  0xa7, 0x43, 0x29, 0xcc, 0x1f, 0xed, 0x1c, 0x2f, 0x8f, 0xef, 0xa7, 0xf6,
-  0x14, 0xf0, 0xa8, 0x3d, 0x65, 0x31, 0x79, 0x65, 0xd4, 0x9a, 0x89, 0x87,
-  0xe8, 0xfd, 0x18, 0x5d, 0x55, 0xfe, 0x8b, 0xf8, 0x25, 0x30, 0x5c, 0x7a,
-  0xbe, 0x00, 0xeb, 0x2f, 0x8c, 0xf1, 0xba, 0x46, 0xc5, 0x71, 0xeb, 0x8f,
-  0x5e, 0x40, 0xd7, 0xb0, 0xab, 0xe3, 0x29, 0x9c, 0x9f, 0xca, 0xb9, 0xd5,
-  0x57, 0x6a, 0xdf, 0xe8, 0x02, 0x63, 0x9d, 0xc3, 0x06, 0x9f, 0x3f, 0xd2,
-  0x8f, 0x51, 0xf8, 0xcb, 0x9f, 0xe5, 0xeb, 0x4d, 0xe5, 0xdb, 0xf2, 0x89,
-  0x8b, 0xde, 0xa9, 0xf4, 0xad, 0x8e, 0x45, 0xe5, 0xad, 0x08, 0x58, 0x94,
-  0x3f, 0x54, 0x5f, 0x58, 0x58, 0x78, 0x00, 0xd7, 0xeb, 0x64, 0x82, 0xfe,
-  0xaa, 0xa7, 0xcb, 0x6b, 0x4f, 0xed, 0xe7, 0x29, 0xf1, 0xeb, 0xc4, 0x1e,
-  0xb3, 0xdc, 0x2a, 0x21, 0xe0, 0xfa, 0x93, 0x6e, 0xb0, 0x66, 0x98, 0xe4,
-  0x2b, 0xb6, 0xf1, 0xfd, 0xb9, 0x24, 0x28, 0x3f, 0x88, 0xb9, 0x88, 0x24,
-  0x66, 0x60, 0xbf, 0xa4, 0x82, 0xfc, 0x20, 0x69, 0x74, 0xbf, 0x6b, 0xb8,
-  0x2e, 0xde, 0xa1, 0xde, 0xaa, 0x55, 0x29, 0x87, 0xd9, 0xe7, 0xcf, 0xff,
-  0x8e, 0xbc, 0xbe, 0x2d, 0xcd, 0xf8, 0x71, 0x56, 0xd1, 0xfe, 0x52, 0xe0,
-  0xec, 0xbf, 0xf0, 0xf8, 0x8b, 0x96, 0x9f, 0xd4, 0xd6, 0x3f, 0x54, 0xbf,
-  0xe1, 0x15, 0x8d, 0x34, 0x8e, 0x2f, 0xf9, 0xf7, 0x53, 0x79, 0x69, 0x23,
-  0xff, 0x06, 0x7f, 0x7f, 0xed, 0x6d, 0xc3, 0x0d, 0xe0, 0x63, 0xbe, 0x21,
-  0xe4, 0x2b, 0x93, 0xcf, 0xfb, 0x06, 0x60, 0xd9, 0x37, 0xce, 0x04, 0xf0,
-  0xf5, 0xa6, 0xd6, 0x5f, 0x20, 0x72, 0xff, 0xe1, 0x6f, 0x83, 0x4b, 0x24,
-  0x7e, 0xc9, 0xa2, 0xf9, 0xdb, 0xda, 0x5a, 0x83, 0xee, 0xe7, 0x15, 0x17,
-  0xd7, 0x91, 0x75, 0xec, 0x33, 0x08, 0xcf, 0xbc, 0xe8, 0x6f, 0xc5, 0x38,
-  0x99, 0x1f, 0x1c, 0x07, 0xc5, 0x9a, 0xf7, 0x5d, 0xa4, 0x6f, 0x7a, 0xe7,
-  0x13, 0xf3, 0x17, 0xef, 0xb7, 0x41, 0x30, 0x7f, 0xb1, 0x17, 0x42, 0x2e,
-  0xaf, 0xa3, 0xef, 0xff, 0xeb, 0x71, 0xe9, 0x9f, 0xf4, 0x58, 0xab, 0xcd,
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+  0x7c, 0xfd, 0xcb, 0xe1, 0x63, 0xad, 0xe1, 0x6f, 0x3e, 0x78, 0x4c, 0xc8,
+  0x3b, 0xe2, 0xbf, 0x5d, 0x1d, 0xec, 0x1f, 0xbb, 0xc0, 0xe8, 0x17, 0xec,
+  0x3f, 0x46, 0xc5, 0x85, 0xf7, 0xbd, 0xc3, 0x18, 0x67, 0x5c, 0xa6, 0xf4,
+  0x5b, 0x0b, 0xc1, 0xbe, 0xb7, 0x23, 0xfa, 0x01, 0x0c, 0x03, 0x45, 0x17,
+  0xc6, 0x6c, 0x07, 0xa4, 0x1d, 0x10, 0xa6, 0x57, 0x3e, 0x51, 0xbc, 0xe0,
+  0x0f, 0x23, 0xbe, 0x07, 0x49, 0x83, 0xeb, 0xd3, 0x61, 0x7e, 0x60, 0xf3,
+  0x33, 0xd5, 0xf9, 0x32, 0x7d, 0x3f, 0x6e, 0xaf, 0xaf, 0x93, 0xea, 0xa1,
+  0xa1, 0x7f, 0xd2, 0x7a, 0x07, 0x1e, 0x18, 0x22, 0xf6, 0xe3, 0xd2, 0x39,
+  0x1c, 0x1f, 0x7d, 0x71, 0x8a, 0xbc, 0xde, 0xb7, 0x4a, 0xbe, 0xe4, 0xd9,
+  0xdf, 0xe6, 0xbd, 0x63, 0x17, 0x30, 0xdc, 0x76, 0x73, 0xfc, 0x55, 0x1a,
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+  0xe7, 0xe9, 0xb1, 0xe1, 0x88, 0xf1, 0xae, 0x6f, 0x63, 0x04, 0xfb, 0xdf,
+  0xc2, 0x56, 0xf4, 0x3b, 0x9b, 0xff, 0xe1, 0x4d, 0x30, 0xe2, 0x7d, 0x78,
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+  0x78, 0xc9, 0xf7, 0xb4, 0xf9, 0x21, 0x34, 0xdf, 0xbc, 0x01, 0x9a, 0x62,
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+  0xf3, 0xbd, 0xf4, 0x3e, 0xa9, 0xfd, 0xff, 0x56, 0x3d, 0x5b, 0x5b, 0x5e,
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+  0x22, 0x3f, 0xb5, 0x15, 0xe2, 0xa9, 0x45, 0xe2, 0x4f, 0x21, 0xf5, 0x42,
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+  0x49, 0x4a, 0x3f, 0x67, 0xf2, 0x5b, 0xb5, 0xd7, 0xb8, 0x7a, 0x92, 0x3b,
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+  0xa2, 0xa2, 0xed, 0x97, 0x0c, 0xf8, 0xba, 0xb9, 0xf2, 0x28, 0xc2, 0x27,
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+  0xf8, 0xd1, 0xc1, 0xb3, 0xa4, 0x71, 0xbb, 0xa8, 0x4b, 0x3f, 0x2d, 0xf2,
+  0xff, 0xfb, 0x1f, 0xda, 0xc1, 0x1a, 0xf6, 0x84, 0x5f, 0xfb, 0xb6, 0xf4,
+  0xaf, 0xa9, 0x7e, 0x13, 0xe5, 0xb4, 0xf5, 0x61, 0x5c, 0xd9, 0xe0, 0x39,
+  0xbd, 0xbf, 0xc7, 0x55, 0xb2, 0xfe, 0x48, 0x09, 0xfa, 0x21, 0xa1, 0x7e,
+  0x0d, 0x7c, 0x38, 0xa7, 0x7a, 0x84, 0xbf, 0x6a, 0x31, 0xe6, 0x43, 0x90,
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+  0xf2, 0x5d, 0x62, 0xbe, 0x57, 0x61, 0x3d, 0xf5, 0xa2, 0xc6, 0xe2, 0x7a,
+  0xb6, 0x46, 0x7f, 0xbf, 0x64, 0x3d, 0xa0, 0x77, 0x75, 0xc8, 0x87, 0xc9,
+  0xec, 0xe7, 0x67, 0xf8, 0x13, 0xb6, 0x1f, 0xa1, 0x88, 0x2f, 0xba, 0x4a,
+  0xd3, 0xf9, 0x81, 0x99, 0xf6, 0x83, 0xb0, 0x27, 0x43, 0x61, 0xaf, 0x07,
+  0x56, 0x7e, 0x3e, 0xe5, 0x3b, 0x90, 0x7c, 0xcf, 0xc2, 0x27, 0x15, 0xc4,
+  0xd7, 0x32, 0xf1, 0x4a, 0x48, 0x2a, 0xa1, 0xc8, 0xbf, 0x4d, 0x8d, 0xe7,
+  0x62, 0x3c, 0xd1, 0xc9, 0x5f, 0x9c, 0xe4, 0x9b, 0x49, 0xbe, 0xfc, 0x2b,
+  0x36, 0x69, 0x1a, 0xeb, 0x97, 0xce, 0x3f, 0xd6, 0xfa, 0x03, 0x43, 0xfd,
+  0xe6, 0x61, 0x29, 0xea, 0x06, 0x32, 0xf3, 0x37, 0x2e, 0xcd, 0xf1, 0x3f,
+  0x4b, 0x82, 0xc1, 0x00, 0x2b, 0xb7, 0x0c, 0xfe, 0x67, 0xbf, 0x9c, 0xf4,
+  0x3f, 0xdf, 0xb0, 0xdf, 0xa3, 0xc8, 0xff, 0xdc, 0x97, 0x91, 0xaf, 0x85,
+  0xea, 0x65, 0x98, 0xef, 0xe3, 0xf5, 0xd1, 0xf8, 0x37, 0x19, 0xfe, 0x85,
+  0xa3, 0x31, 0xbe, 0x4f, 0xf1, 0x47, 0x3a, 0x48, 0x3f, 0x14, 0x66, 0x16,
+  0xf9, 0xdf, 0x7f, 0x27, 0x54, 0xf1, 0xe9, 0xb4, 0x7a, 0x6f, 0xe1, 0x93,
+  0xaa, 0x9e, 0x0a, 0xaa, 0x87, 0x62, 0x2d, 0x93, 0x32, 0x8b, 0x77, 0x84,
+  0x93, 0xb6, 0x6e, 0x7f, 0xdd, 0x32, 0xa7, 0xfc, 0x13, 0x67, 0x47, 0xf4,
+  0xfa, 0xe4, 0xfc, 0xf7, 0x13, 0xa5, 0x58, 0xde, 0x2a, 0xff, 0x6a, 0xc6,
+  0x7d, 0x2f, 0x1b, 0xf9, 0x2f, 0x9d, 0xe3, 0xff, 0x7f, 0xd4, 0xe1, 0xfe,
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+  0xf9, 0x23, 0x38, 0x53, 0xa7, 0xe7, 0xbf, 0x9d, 0x70, 0x79, 0xbf, 0xa1,
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+  0x1b, 0x35, 0x5e, 0xd8, 0x7c, 0xce, 0x8a, 0xf9, 0xf4, 0xc5, 0x99, 0x4f,
+  0xe7, 0xf6, 0xf2, 0xdd, 0x64, 0x3f, 0x2a, 0xf6, 0xf0, 0xec, 0xcd, 0xa3,
+  0xb5, 0xf5, 0xa0, 0x7a, 0x7c, 0xf6, 0x79, 0x43, 0xb5, 0x7f, 0xc2, 0xf6,
+  0x6b, 0x71, 0xfc, 0x5d, 0x39, 0xbc, 0xbf, 0xfe, 0xfd, 0xac, 0xbc, 0xb1,
+  0x09, 0x8e, 0x23, 0x7d, 0x35, 0x67, 0x10, 0xff, 0x8b, 0xe9, 0xdf, 0x67,
+  0x44, 0xbe, 0xc8, 0xdf, 0xdf, 0x8e, 0xe2, 0x2b, 0xc9, 0xa7, 0x51, 0xfd,
+  0x3d, 0xdf, 0xdf, 0xb4, 0x82, 0xff, 0x86, 0x03, 0xd9, 0xbc, 0xd7, 0xd2,
+  0xd9, 0x0c, 0xfa, 0x9e, 0x36, 0x2a, 0xa3, 0xe1, 0xfb, 0xbb, 0xfa, 0xd7,
+  0x22, 0xfe, 0x3d, 0x90, 0x90, 0xf4, 0xad, 0x7f, 0x3f, 0x32, 0xf8, 0x06,
+  0x5e, 0x4c, 0xe2, 0xe9, 0x2c, 0x3f, 0x3a, 0xd1, 0x4d, 0xe3, 0xeb, 0x4c,
+  0x3d, 0x8d, 0x70, 0x3c, 0x4d, 0xc5, 0x09, 0x8d, 0x6f, 0xf8, 0xf6, 0x0d,
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+  0x0a, 0xc5, 0x2b, 0x81, 0x6d, 0x59, 0x1e, 0xaf, 0x61, 0xf1, 0xb4, 0x9d,
+  0xc8, 0x1c, 0x41, 0xcf, 0x63, 0xf2, 0x3d, 0x9c, 0x7f, 0x5c, 0x5e, 0x2f,
+  0x5e, 0x4f, 0xf0, 0x2b, 0xb9, 0x1e, 0x66, 0x1b, 0xcf, 0xbf, 0x86, 0x9d,
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+  0xde, 0x0d, 0x34, 0x74, 0x23, 0xe8, 0xe1, 0x11, 0x1b, 0xce, 0x9b, 0xe6,
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+  0xcc, 0xbf, 0xbf, 0x5b, 0x48, 0xef, 0x16, 0x93, 0x5f, 0x5c, 0x5e, 0xf9,
+  0x0f, 0x66, 0xd4, 0xfc, 0x21, 0x80, 0x9e, 0xe1, 0xfc, 0xc1, 0xc0, 0x9f,
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+  0x7f, 0xd8, 0x9e, 0x6d, 0xe3, 0x6f, 0x38, 0xe4, 0x3e, 0x49, 0x17, 0x38,
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+  0xde, 0xd7, 0x93, 0x74, 0xff, 0x2f, 0xa5, 0x27, 0xb1, 0xfe, 0x20, 0x96,
+  0x6e, 0xd8, 0x3e, 0xa9, 0x3c, 0xab, 0xe2, 0x1b, 0x34, 0xa4, 0x5b, 0xa9,
+  0x69, 0xf3, 0x2b, 0xf0, 0x61, 0x1a, 0xf6, 0x22, 0xa8, 0x8c, 0x5b, 0xe9,
+  0xf5, 0x3f, 0xcf, 0xbe, 0x97, 0xf3, 0x03, 0xfe, 0x63, 0x7b, 0x46, 0xf3,
+  0x9f, 0xe8, 0xd7, 0xda, 0x7d, 0x3d, 0xa2, 0xbe, 0x97, 0xcb, 0x37, 0x42,
+  0x0f, 0x9b, 0x4a, 0x7a, 0x3c, 0xfd, 0xe3, 0x6d, 0xe6, 0x9b, 0x09, 0x7b,
+  0xf1, 0x15, 0x26, 0x8f, 0x79, 0x1d, 0xd4, 0x89, 0xc4, 0x7a, 0xb1, 0xe6,
+  0xc5, 0x36, 0xf7, 0x69, 0x98, 0xf9, 0x53, 0x8b, 0xd9, 0x56, 0x7a, 0xfc,
+  0x8d, 0x1c, 0xc1, 0x81, 0x5b, 0xd8, 0xb2, 0xd4, 0xdf, 0x5f, 0xa3, 0xfb,
+  0x87, 0xdb, 0xc4, 0xfd, 0x96, 0x3f, 0xd9, 0xc8, 0xfd, 0x43, 0x1a, 0x7f,
+  0xf1, 0xf5, 0xf8, 0x8b, 0xc2, 0x27, 0xaf, 0xe7, 0xf5, 0x7f, 0xf8, 0x97,
+  0x20, 0x56, 0xbf, 0xf6, 0x31, 0xfd, 0x8a, 0x4e, 0x59, 0xaa, 0x1e, 0xb5,
+  0x99, 0x07, 0x8e, 0xe5, 0x8e, 0x1c, 0xfe, 0xd3, 0xf7, 0xba, 0x68, 0xed,
+  0xd4, 0xf7, 0x9c, 0x1d, 0xd8, 0x9f, 0x9f, 0x68, 0x8c, 0x60, 0x8b, 0xcd,
+  0x43, 0xdf, 0xcd, 0x90, 0x79, 0xbd, 0x6c, 0x5e, 0xdd, 0x02, 0x97, 0xdf,
+  0xe4, 0x79, 0x25, 0x6f, 0x0f, 0x31, 0xfb, 0xf8, 0xdc, 0x48, 0xce, 0x7f,
+  0xd1, 0x7a, 0x06, 0x4e, 0xe0, 0xf5, 0xae, 0xab, 0x21, 0x6e, 0x75, 0xb0,
+  0x78, 0x52, 0x91, 0xcd, 0x87, 0x6c, 0x44, 0xf5, 0x03, 0xa6, 0x8f, 0x21,
+  0x8b, 0xd9, 0x2b, 0xf7, 0xe7, 0x1a, 0xdf, 0xb7, 0x8e, 0x3b, 0x93, 0x47,
+  0xa1, 0xbf, 0xa1, 0x06, 0xee, 0x95, 0xf4, 0x78, 0x67, 0x6a, 0xbf, 0xb7,
+  0xc0, 0xf7, 0x7a, 0x47, 0xf6, 0x6f, 0xb4, 0x8c, 0xfe, 0x8d, 0xc8, 0x7c,
+  0x29, 0x49, 0xcf, 0xe9, 0xf7, 0x65, 0x2d, 0xf3, 0xf3, 0x0f, 0xcf, 0x6b,
+  0xb6, 0x4c, 0x7a, 0x50, 0xf5, 0x97, 0x4b, 0x8f, 0x74, 0x36, 0x1f, 0x22,
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+  0xcb, 0x37, 0x0e, 0xca, 0xc3, 0xff, 0x72, 0xb2, 0x8f, 0xc7, 0xab, 0x06,
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+  0x71, 0x48, 0xfc, 0x97, 0xf1, 0x90, 0x5f, 0x1e, 0xa6, 0xf9, 0xda, 0x38,
+  0xde, 0x76, 0xfa, 0x7c, 0xba, 0x78, 0xdb, 0xc9, 0x80, 0x3d, 0x25, 0x7c,
+  0xbe, 0xa5, 0xc3, 0x37, 0xff, 0xf9, 0xb3, 0x29, 0xfb, 0xf9, 0x66, 0x2d,
+  0x6d, 0x72, 0xbe, 0x85, 0xe8, 0x69, 0xd0, 0xc0, 0xcc, 0x89, 0xeb, 0xc9,
+  0x5b, 0x81, 0x7e, 0x66, 0x68, 0xbf, 0xb7, 0xfb, 0xec, 0x6f, 0xe1, 0xfb,
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+  0xb7, 0x66, 0xa3, 0xfb, 0x0d, 0x7c, 0x7f, 0xab, 0xbc, 0xff, 0xc7, 0xb4,
+  0xf8, 0xfb, 0x59, 0x3d, 0x82, 0xc1, 0xba, 0xe6, 0xa0, 0xfb, 0x75, 0xd2,
+  0xbf, 0x9e, 0x7e, 0x0f, 0xce, 0xd7, 0x95, 0xc7, 0x63, 0xfb, 0x5e, 0x3f,
+  0xb6, 0xef, 0xc9, 0xf1, 0x8a, 0x0d, 0x4e, 0x2f, 0x53, 0x52, 0x3d, 0xe7,
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+  0x42, 0x57, 0x34, 0x97, 0xf8, 0x2f, 0xed, 0x5f, 0x97, 0xe8, 0x27, 0x67,
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+  0xbb, 0x84, 0xd7, 0xa7, 0xf7, 0xe6, 0x9f, 0x55, 0x1e, 0x38, 0xf4, 0x69,
+  0x29, 0x5f, 0xd2, 0x17, 0x9f, 0x18, 0xa8, 0xf7, 0xef, 0xe9, 0x3f, 0xad,
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+  0x55, 0xb3, 0x35, 0x1f, 0xe0, 0xcf, 0x1e, 0x76, 0x1f, 0x49, 0x5e, 0x68,
+  0xf7, 0x10, 0x7f, 0x5e, 0x3a, 0xbf, 0x90, 0x7e, 0xe2, 0xfd, 0x10, 0xbc,
+  0xb7, 0x48, 0xfc, 0xcb, 0xa8, 0x7e, 0x56, 0xa6, 0xa8, 0x3c, 0x7b, 0x5e,
+  0xde, 0x41, 0xfb, 0x61, 0xbd, 0x09, 0x35, 0x67, 0x00, 0x18, 0x93, 0xec,
+  0x7e, 0x1b, 0x98, 0x18, 0xaf, 0x9b, 0x27, 0xe7, 0x8d, 0xfb, 0x2c, 0x8c,
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+  0xc0, 0x80, 0xbf, 0xa5, 0xac, 0x83, 0xc0, 0x3a, 0x74, 0x17, 0xd9, 0x1f,
+  0x38, 0xa5, 0xb6, 0x7e, 0xba, 0xce, 0x7e, 0xf6, 0xe7, 0xcf, 0x72, 0x54,
+  0x02, 0x1e, 0xd8, 0x61, 0x1d, 0xd4, 0xd8, 0xf7, 0x2d, 0xab, 0x49, 0x8a,
+  0xb8, 0x1f, 0xd1, 0xc1, 0x5c, 0x44, 0x7f, 0x9c, 0x1b, 0xf4, 0x5c, 0x01,
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+  0x17, 0x81, 0xf1, 0x7e, 0xc9, 0xc7, 0x83, 0x45, 0x3a, 0xde, 0x09, 0xc9,
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+  0xf3, 0xb7, 0xaf, 0x82, 0xe3, 0xa5, 0xb2, 0x63, 0xa1, 0xe1, 0xec, 0xdb,
+  0x73, 0x39, 0x51, 0xcf, 0xa6, 0x82, 0xed, 0x3d, 0xee, 0xaf, 0xf2, 0x8a,
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+  0xbe, 0xdb, 0x78, 0xa1, 0x55, 0xfe, 0xc3, 0x0e, 0x23, 0x42, 0x3e, 0xe6,
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+  0xf4, 0x3f, 0x53, 0x79, 0xae, 0x99, 0x7f, 0x9e, 0xb1, 0x3c, 0x87, 0xc4,
+  0xfd, 0x48, 0xba, 0x98, 0x8f, 0x55, 0x03, 0xf7, 0x83, 0xc3, 0x6b, 0x59,
+  0xf4, 0xbc, 0x30, 0xf7, 0x7c, 0xb9, 0x8b, 0xc5, 0xf9, 0x04, 0x7f, 0x4b,
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+  0xff, 0x2f, 0x97, 0xbb, 0x8f, 0xcf, 0x10, 0x2a, 0x62, 0xff, 0xf9, 0x04,
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+  0x67, 0x8b, 0x6b, 0xcb, 0x3d, 0x4f, 0x8f, 0x01, 0x61, 0xa7, 0xf8, 0x7e,
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+  0x12, 0xcb, 0x4c, 0xe4, 0x77, 0xf2, 0xf1, 0xb8, 0x81, 0xd7, 0x8b, 0x25,
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+  0xd3, 0xf4, 0x55, 0x7a, 0xbd, 0x37, 0x89, 0x0f, 0x20, 0xf5, 0x55, 0x3b,
+  0x6e, 0x67, 0xff, 0xf2, 0x7b, 0xa2, 0x1f, 0x12, 0xf1, 0x59, 0xad, 0x8c,
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+  0xb5, 0xa0, 0x1b, 0xe9, 0xab, 0x7e, 0x59, 0x8c, 0x9f, 0x14, 0x7d, 0x95,
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+  0x7a, 0xc5, 0xa1, 0x78, 0x5a, 0x38, 0x6e, 0xb2, 0xfe, 0xa8, 0x6b, 0xfd,
+  0xcc, 0x1f, 0x62, 0xc9, 0xb2, 0x29, 0x7f, 0xe1, 0xb5, 0x12, 0xed, 0x0f,
+  0x66, 0x55, 0x4a, 0x7f, 0x4b, 0xfb, 0xab, 0x96, 0x3e, 0xf8, 0x39, 0xfc,
+  0xf7, 0xd0, 0x2e, 0x58, 0x7b, 0xfa, 0x1e, 0xc7, 0xe3, 0xed, 0xf5, 0xcd,
+  0x84, 0xaf, 0x62, 0x9b, 0xc7, 0xde, 0x65, 0x16, 0x0d, 0x7c, 0x2d, 0x6b,
+  0x9b, 0x58, 0xbf, 0xd3, 0x5b, 0xd4, 0x7e, 0xa8, 0xe0, 0x58, 0x8e, 0xf1,
+  0x0d, 0xd7, 0xfa, 0xcd, 0xb9, 0xf2, 0x69, 0xdd, 0xff, 0xec, 0x2d, 0xe0,
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+  0x40, 0xb0, 0x08, 0x6e, 0x2e, 0xc5, 0xbf, 0xaf, 0x6e, 0xc4, 0xf3, 0x77,
+  0x13, 0xc7, 0x7b, 0xcb, 0x14, 0xd4, 0x3c, 0x4a, 0xaf, 0x1f, 0x27, 0xab,
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+  0x51, 0x9f, 0xad, 0x68, 0x7a, 0x5f, 0x1e, 0x9a, 0xb0, 0x3c, 0xc6, 0x07,
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+  0x86, 0xf7, 0xbb, 0x95, 0xa1, 0x4b, 0xd1, 0xfe, 0xba, 0x21, 0xf7, 0x83,
+  0x95, 0xb1, 0xf8, 0xfd, 0xd3, 0x3f, 0x75, 0xf9, 0xfc, 0x31, 0x40, 0xc9,
+  0xf0, 0x97, 0x77, 0x84, 0xa6, 0x52, 0xf2, 0x45, 0xd9, 0x39, 0xc6, 0x0f,
+  0x4a, 0x9c, 0x58, 0xfe, 0x29, 0x85, 0x7f, 0x05, 0x0d, 0x5e, 0xb5, 0x82,
+  0x7e, 0x36, 0x25, 0x74, 0x23, 0x8b, 0x62, 0xfd, 0x9a, 0x11, 0xff, 0x0a,
+  0xeb, 0xaf, 0xb6, 0x43, 0xdb, 0xf2, 0x63, 0x5b, 0xe7, 0x5f, 0x99, 0xcd,
+  0x36, 0x3b, 0x2f, 0x58, 0x8e, 0xf1, 0x7f, 0xd4, 0xf2, 0xab, 0xa0, 0x60,
+  0x9c, 0xf3, 0xab, 0xc8, 0xfc, 0xd9, 0x95, 0x0b, 0xe3, 0xfd, 0x71, 0x7b,
+  0x27, 0xf3, 0xa3, 0x61, 0x3c, 0xc0, 0xe3, 0xf7, 0xcb, 0x32, 0x3e, 0x59,
+  0x64, 0xe7, 0x8f, 0xb1, 0x18, 0x64, 0x0f, 0x13, 0x0f, 0xd1, 0x3b, 0x45,
+  0x7e, 0xfc, 0x2d, 0xcd, 0xbf, 0x62, 0x7b, 0xe6, 0xc0, 0x3b, 0xdc, 0x1e,
+  0x4a, 0xfe, 0x14, 0x85, 0xff, 0xb2, 0xba, 0x1e, 0xba, 0xcc, 0x47, 0xac,
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+  0xc2, 0xaa, 0x90, 0x9f, 0xdb, 0xb3, 0x44, 0xb3, 0x98, 0xcf, 0x7f, 0xd2,
+  0xff, 0xee, 0x2b, 0xbc, 0x87, 0x4b, 0x36, 0xf0, 0x19, 0x2e, 0xe3, 0x28,
+  0xdf, 0x92, 0x45, 0x37, 0x59, 0x8b, 0xc5, 0x09, 0x99, 0x4d, 0xda, 0x6f,
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+  0x0b, 0xb0, 0xe4, 0x12, 0xd7, 0xdf, 0x23, 0xbc, 0xdc, 0x12, 0xe3, 0x3f,
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+  0xfd, 0x0b, 0x5c, 0x9f, 0x31, 0x79, 0xf4, 0xe5, 0x7c, 0x00, 0xff, 0x24,
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+  0x6b, 0xc9, 0xe7, 0x63, 0xeb, 0x7b, 0x36, 0xaa, 0x87, 0x0d, 0xda, 0x9a,
+  0xcf, 0xcb, 0xfb, 0xd1, 0x6e, 0x2e, 0x26, 0xe5, 0xd7, 0x9a, 0x39, 0xf1,
+  0x96, 0xdf, 0xde, 0x96, 0x3d, 0xa3, 0xf2, 0x6b, 0xcc, 0xdf, 0x24, 0xf7,
+  0xdf, 0x21, 0xe2, 0x7f, 0x01, 0x7d, 0x16, 0xf2, 0xad, 0x87, 0xe3, 0x21,
+  0x5c, 0xa2, 0x9b, 0x97, 0x5e, 0xc6, 0xbf, 0xb1, 0xc4, 0xe2, 0x3b, 0xe1,
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+  0xbb, 0xc3, 0x9f, 0x35, 0x84, 0xfc, 0x1c, 0x95, 0x6f, 0x36, 0x7a, 0x9e,
+  0xe6, 0x13, 0x17, 0xff, 0x6b, 0x57, 0x43, 0xb4, 0x47, 0x9c, 0xa5, 0x42,
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+  0x87, 0xbd, 0xe3, 0x02, 0x84, 0xa0, 0x23, 0x04, 0x89, 0x0b, 0x8a, 0xa2,
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+  0x43, 0x22, 0x29, 0x81, 0xb2, 0xa2, 0xa1, 0x7e, 0x34, 0x5e, 0xca, 0xaa,
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+  0x59, 0xe1, 0x62, 0x89, 0xaf, 0x6b, 0xfb, 0x79, 0x1a, 0xff, 0x2e, 0x1b,
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+  0xb9, 0xbf, 0xe0, 0xd2, 0x7a, 0x66, 0x08, 0xe6, 0xbf, 0x42, 0xf1, 0x3c,
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+  0x5f, 0xcf, 0x35, 0xc7, 0xcb, 0x6c, 0x29, 0x1e, 0x65, 0x31, 0x7f, 0x1c,
+  0x32, 0x3e, 0x6c, 0x90, 0xd6, 0xea, 0x2f, 0x7f, 0xc6, 0xf3, 0x71, 0x23,
+  0xc2, 0x7f, 0x3f, 0x6f, 0x73, 0x3c, 0x7d, 0xf5, 0xfc, 0x54, 0x13, 0x7f,
+  0x5c, 0xd6, 0x9f, 0x3a, 0xdc, 0x1f, 0x47, 0x4d, 0xf8, 0x7b, 0x84, 0x3f,
+  0xc5, 0xf8, 0x1a, 0x2c, 0xb2, 0x28, 0x17, 0xb8, 0x3e, 0x64, 0x7c, 0x0d,
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+  0xfe, 0x7f, 0x56, 0x5b, 0x4f, 0x8c, 0x0a, 0x13, 0xbc, 0x3f, 0xdb, 0xe0,
+  0x8b, 0x3b, 0x77, 0x09, 0xd6, 0x22, 0xf8, 0x71, 0xe5, 0x79, 0xf5, 0x92,
+  0x38, 0xaf, 0x02, 0xfe, 0x84, 0xe9, 0xc7, 0x04, 0x7e, 0xf4, 0xd9, 0x64,
+  0xbc, 0xe8, 0x19, 0x43, 0x1f, 0xb4, 0xb6, 0x9e, 0xe1, 0x7e, 0x4c, 0x2e,
+  0x2f, 0x6b, 0x94, 0xbf, 0x94, 0x2f, 0xf1, 0x7c, 0x1a, 0x97, 0x57, 0xd4,
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+  0x62, 0xec, 0x7c, 0x3c, 0xd3, 0xe2, 0x7c, 0x14, 0x12, 0xe7, 0x23, 0x7e,
+  0xfc, 0xef, 0x30, 0xc6, 0x2f, 0xfb, 0x67, 0xfd, 0x36, 0xc7, 0xdf, 0xd1,
+  0xda, 0xf8, 0x87, 0xe5, 0xf8, 0xcf, 0xe8, 0xfd, 0xaf, 0x30, 0x6e, 0xfc,
+  0xe7, 0x5b, 0x1d, 0xbf, 0xb5, 0xb8, 0xf1, 0xcb, 0xf1, 0x4e, 0x6b, 0xfd,
+  0x9a, 0x41, 0xfc, 0x3d, 0x86, 0xff, 0xd8, 0xa1, 0xfb, 0xef, 0x36, 0x62,
+  0xf4, 0xde, 0x4f, 0xf1, 0xdd, 0x0e, 0x37, 0xee, 0xb7, 0x07, 0x45, 0x7e,
+  0x71, 0x97, 0x38, 0x2f, 0xde, 0xe4, 0x79, 0xa4, 0xf0, 0xe3, 0x05, 0x3f,
+  0x66, 0xbb, 0xfd, 0x6c, 0x00, 0xe7, 0x78, 0xfc, 0x14, 0x49, 0xfe, 0x90,
+  0x1c, 0xe7, 0x0f, 0x29, 0xf3, 0x7e, 0x35, 0x67, 0xc6, 0x1a, 0x62, 0xf9,
+  0x3c, 0x89, 0xf7, 0x66, 0xe2, 0x05, 0x29, 0x79, 0xcd, 0x26, 0xed, 0xb7,
+  0xf5, 0x71, 0xfa, 0x15, 0xd1, 0xc0, 0xf4, 0x54, 0x27, 0xeb, 0x67, 0x21,
+  0xf6, 0x94, 0x72, 0x20, 0x04, 0xff, 0x13, 0x5d, 0x8a, 0x42, 0x98, 0x5f,
+  0x74, 0x62, 0x8e, 0xcd, 0xf7, 0xb7, 0xcb, 0xd3, 0x00, 0x6d, 0x71, 0xf1,
+  0x9f, 0x3a, 0x00, 0x7a, 0x70, 0x70, 0xe2, 0xf7, 0x1d, 0x04, 0x07, 0xdc,
+  0x87, 0x71, 0x4f, 0x75, 0x0e, 0xd6, 0x77, 0x7b, 0xf8, 0x87, 0x22, 0x3e,
+  0xd8, 0x97, 0xf2, 0x84, 0x49, 0x5c, 0x06, 0x48, 0xe0, 0x8b, 0xe9, 0xf9,
+  0x0b, 0xd7, 0x18, 0xcf, 0x9c, 0xdd, 0x4a, 0x3d, 0xc1, 0xf6, 0xeb, 0x17,
+  0xc7, 0x4f, 0x22, 0xf8, 0xd8, 0xc0, 0xec, 0x89, 0xdd, 0x82, 0xbf, 0x07,
+  0x04, 0xfe, 0x7d, 0x4d, 0xb3, 0x17, 0xb9, 0xff, 0x2a, 0x14, 0x80, 0xff,
+  0xc9, 0x4f, 0x65, 0xd8, 0x20, 0xac, 0xac, 0x05, 0x68, 0x0d, 0x41, 0x71,
+  0x9c, 0xf1, 0x83, 0x34, 0xf0, 0x93, 0xc8, 0x37, 0x97, 0xc5, 0x62, 0x8b,
+  0xbf, 0x50, 0x7c, 0xe8, 0x22, 0xf3, 0xaf, 0xea, 0xef, 0xe8, 0xed, 0x08,
+  0x16, 0x82, 0x7a, 0x20, 0xca, 0x57, 0x7a, 0x98, 0x3c, 0xec, 0xd2, 0xdb,
+  0x28, 0xdf, 0x45, 0xcf, 0xb1, 0xb9, 0x3f, 0x90, 0xf1, 0xd3, 0x73, 0x3e,
+  0xf1, 0x17, 0x10, 0x8d, 0x67, 0xde, 0xd6, 0x09, 0x16, 0x2e, 0x42, 0x6e,
+  0xff, 0x02, 0xe8, 0x33, 0x3e, 0x34, 0x72, 0xbe, 0x46, 0xf2, 0x45, 0x90,
+  0xff, 0xb3, 0x35, 0xf9, 0x32, 0x7e, 0x07, 0x90, 0xf3, 0x87, 0x94, 0x19,
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+  0x85, 0x0e, 0xe1, 0x71, 0xc1, 0x0a, 0x87, 0xe3, 0xe7, 0xb5, 0x67, 0xf7,
+  0x7f, 0x9c, 0x60, 0xb5, 0x26, 0x98, 0x24, 0x4f, 0x2d, 0x75, 0x0f, 0xb1,
+  0xc1, 0x11, 0xe2, 0xdf, 0x30, 0x7f, 0xef, 0x19, 0xca, 0xdf, 0xbb, 0x3f,
+  0x34, 0xfe, 0x94, 0x7a, 0x0a, 0x31, 0xfe, 0xbc, 0xfc, 0x18, 0xc2, 0xfe,
+  0x02, 0xc5, 0xec, 0xfa, 0xa0, 0x79, 0x23, 0xdf, 0xfd, 0x24, 0x7f, 0x72,
+  0x21, 0x9b, 0xcf, 0x60, 0x67, 0xce, 0xfb, 0x95, 0xb2, 0xeb, 0x4d, 0xa4,
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+  0x47, 0x93, 0xf1, 0x4d, 0x89, 0x8f, 0x2e, 0xa5, 0xe3, 0x1d, 0x5c, 0x3d,
+  0xf8, 0xfe, 0xad, 0x99, 0xf6, 0x87, 0xf4, 0x77, 0xa4, 0x7e, 0xda, 0xfe,
+  0xba, 0xf0, 0x02, 0x97, 0xdd, 0xd6, 0xa5, 0x3f, 0xab, 0xf4, 0x47, 0x46,
+  0x7a, 0x8c, 0xcf, 0x0a, 0x63, 0x0d, 0xf5, 0x5d, 0x88, 0xf7, 0x49, 0xc3,
+  0x6f, 0x0d, 0xdf, 0x16, 0xc3, 0x6f, 0x39, 0x51, 0x7b, 0x25, 0x19, 0x8f,
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+  0x15, 0xab, 0xa7, 0xc1, 0x66, 0x96, 0x3f, 0xed, 0xeb, 0x84, 0xf0, 0x3d,
+  0xc1, 0xf3, 0xca, 0x3d, 0xe2, 0x9d, 0x52, 0xe4, 0x65, 0x34, 0xe6, 0xdf,
+  0xf6, 0x67, 0xf6, 0x6f, 0xc1, 0x2f, 0xda, 0x8e, 0xf4, 0xdb, 0x09, 0xf4,
+  0xbb, 0xe0, 0x23, 0x66, 0x9f, 0x8b, 0xfe, 0x59, 0x7f, 0xda, 0x8f, 0xa2,
+  0xf1, 0xb6, 0xfe, 0x3c, 0xef, 0xeb, 0x68, 0xee, 0x15, 0xd4, 0x3e, 0x12,
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+  0x36, 0x9b, 0xbf, 0x51, 0xc1, 0x2b, 0x8b, 0xf8, 0x94, 0x1c, 0xef, 0x29,
+  0x90, 0x65, 0x0f, 0x8a, 0x78, 0xf6, 0x45, 0xc2, 0xbf, 0xd3, 0x27, 0x4b,
+  0xa8, 0x5f, 0x6f, 0x99, 0xdc, 0xbf, 0x7b, 0x3f, 0x87, 0xbf, 0x6d, 0x68,
+  0x6e, 0x6f, 0xd6, 0xe7, 0xbc, 0x89, 0x5f, 0x30, 0xac, 0x0f, 0x1a, 0x1b,
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+  0x8a, 0x8f, 0xa2, 0x6a, 0x52, 0xfd, 0xb2, 0x97, 0xa3, 0x7e, 0xb9, 0xf3,
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+  0x6c, 0x3c, 0x2e, 0x91, 0xff, 0x37, 0xbd, 0xdf, 0xd3, 0x58, 0x0a, 0xcd,
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+  0xcd, 0xb7, 0xbf, 0xfa, 0xb2, 0xb1, 0xf1, 0x4b, 0xa0, 0x4f, 0x81, 0xdf,
+  0xd7, 0x9b, 0x95, 0xf2, 0x73, 0x40, 0xff, 0x86, 0xef, 0x6f, 0x46, 0x5c,
+  0x3f, 0x30, 0xb5, 0x4a, 0x87, 0x53, 0x23, 0x54, 0x53, 0x20, 0xfc, 0xa6,
+  0xdb, 0x9b, 0x8a, 0xe1, 0xd4, 0x08, 0xea, 0x14, 0xd5, 0xb7, 0x1e, 0xd3,
+  0x1a, 0xd3, 0xde, 0xf8, 0x7f, 0xb3, 0x04, 0xd0, 0x88, 0xcd, 0xb7, 0xa6,
+  0x3b, 0x93, 0x05, 0x5c, 0xe3, 0xf2, 0x67, 0xb3, 0x56, 0xed, 0xb5, 0x70,
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+  0x1e, 0xf0, 0x57, 0xa3, 0x5f, 0xf7, 0xf3, 0xf7, 0x7b, 0xd4, 0x6e, 0xf9,
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+  0xf2, 0xae, 0x02, 0xf4, 0x00, 0xf5, 0x76, 0xb8, 0x3d, 0x0d, 0x3d, 0xb0,
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+  0xda, 0x7d, 0x79, 0x6c, 0xda, 0x7c, 0x3d, 0x84, 0x3e, 0x32, 0x4e, 0xad,
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+  0x48, 0xd3, 0x81, 0x09, 0x7e, 0x79, 0x3d, 0xf5, 0x27, 0x59, 0x17, 0xa0,
+  0xff, 0x8b, 0xa3, 0x29, 0xf6, 0xbe, 0xfa, 0x7d, 0xe8, 0xbf, 0xde, 0xa0,
+  0xcf, 0x3d, 0x7a, 0x15, 0xca, 0x6c, 0x7d, 0x66, 0x21, 0x9f, 0xb9, 0x21,
+  0xf9, 0x93, 0x38, 0xbd, 0xae, 0x35, 0xd2, 0xa4, 0x7d, 0x29, 0xed, 0x74,
+  0x9e, 0x62, 0xed, 0x2d, 0xda, 0x1e, 0xb5, 0xd9, 0x54, 0x7e, 0x0c, 0xae,
+  0x67, 0x78, 0xb3, 0x36, 0x1b, 0xf2, 0x41, 0xe8, 0x33, 0xd1, 0xf2, 0x97,
+  0xaf, 0x6f, 0x46, 0x91, 0x1f, 0x13, 0xad, 0x9c, 0xff, 0x43, 0x2a, 0x3f,
+  0x16, 0xfb, 0x19, 0x3f, 0xbb, 0x4d, 0xf1, 0xf3, 0x7b, 0xd5, 0xfd, 0x50,
+  0xea, 0x6f, 0x69, 0x3f, 0x7c, 0x40, 0xfd, 0xbe, 0xd5, 0xda, 0xf7, 0xcb,
+  0xea, 0xf7, 0x07, 0x5a, 0xfb, 0xfe, 0x06, 0xf5, 0xfb, 0x83, 0xad, 0x7d,
+  0xff, 0x43, 0xea, 0xf7, 0x87, 0x5a, 0xfb, 0xfe, 0x16, 0xf5, 0xfb, 0x9b,
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+  0xfc, 0xc5, 0xc7, 0x33, 0x22, 0xe6, 0xc3, 0xf6, 0xd7, 0xe8, 0xa5, 0x98,
+  0xfd, 0xc9, 0xf6, 0xc7, 0xbe, 0x4b, 0x06, 0xdf, 0x3f, 0x0e, 0xe5, 0x67,
+  0x17, 0x9d, 0x4c, 0xd4, 0xdf, 0x46, 0xa1, 0x7e, 0x38, 0x9f, 0xcf, 0x04,
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+  0x7c, 0x9a, 0xf1, 0x1a, 0x46, 0x4d, 0xe0, 0xff, 0xe9, 0xfc, 0xf1, 0x50,
+  0xe2, 0xf9, 0x15, 0xf5, 0xa0, 0xb6, 0xad, 0x45, 0x3e, 0x72, 0xf3, 0x7d,
+  0xa4, 0x9c, 0x4f, 0xd6, 0x77, 0x66, 0x73, 0x4e, 0x3a, 0x8f, 0x87, 0x2f,
+  0xe5, 0xf6, 0xf0, 0x79, 0xb3, 0x9c, 0x77, 0x4d, 0xe4, 0xed, 0x83, 0x78,
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+  0xe1, 0xe9, 0x12, 0xdd, 0xc4, 0x77, 0xbe, 0x30, 0x8b, 0x9c, 0x2b, 0xc0,
+  0x28, 0x69, 0x20, 0x8f, 0x81, 0x6e, 0x95, 0x87, 0xa9, 0x3e, 0x21, 0xe3,
+  0xb1, 0x83, 0xf5, 0xde, 0x2a, 0xd2, 0xfc, 0x42, 0x6a, 0x5f, 0x9a, 0xe3,
+  0xf3, 0xd7, 0xe2, 0x95, 0x92, 0xd9, 0x5f, 0x2d, 0xe5, 0xab, 0xdd, 0x11,
+  0x91, 0xa6, 0x0d, 0x3c, 0xf6, 0x07, 0x07, 0xb8, 0xbf, 0x67, 0xd4, 0xbc,
+  0x4e, 0xba, 0xef, 0x44, 0x3c, 0x4e, 0xa1, 0x45, 0xbd, 0x23, 0x7e, 0xbe,
+  0xf3, 0xac, 0xde, 0x91, 0x91, 0x5e, 0xef, 0x48, 0xc4, 0xe3, 0x72, 0x7a,
+  0x26, 0xe0, 0xed, 0xa8, 0xf8, 0x0e, 0x1c, 0x6f, 0xe7, 0xef, 0x00, 0x5f,
+  0x92, 0xc5, 0x77, 0x9b, 0xce, 0xb6, 0x00, 0xfc, 0xb1, 0xbb, 0xb8, 0x87,
+  0x2c, 0xc7, 0xe4, 0xa9, 0x03, 0x7a, 0xbc, 0x1d, 0xff, 0x1d, 0xed, 0xe5,
+  0xff, 0xb7, 0x17, 0x7f, 0x31, 0x7f, 0x73, 0x0b, 0x7c, 0x66, 0xff, 0x1e,
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+  0x87, 0x7f, 0xba, 0x45, 0xfc, 0x85, 0xf1, 0x5a, 0xc4, 0x5f, 0x3c, 0xde,
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+  0x11, 0xf5, 0xef, 0x74, 0xeb, 0x81, 0xa3, 0xf8, 0x9e, 0x95, 0x22, 0xf3,
+  0x87, 0xbe, 0x23, 0xe8, 0x84, 0x78, 0xb0, 0xb3, 0x75, 0xad, 0x7d, 0xae,
+  0xe0, 0x76, 0x50, 0xfb, 0x45, 0xa7, 0x0f, 0xf6, 0xd1, 0x3c, 0x36, 0x3f,
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+  0x50, 0x92, 0x5f, 0xcf, 0x96, 0xf2, 0xa1, 0xc6, 0xb7, 0x68, 0x8f, 0x62,
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+  0xdb, 0xed, 0xd0, 0x9d, 0xa6, 0x8e, 0xe2, 0x89, 0xe0, 0xfe, 0xdf, 0x68,
+  0x21, 0xbc, 0x72, 0x3b, 0xc6, 0x2b, 0x23, 0xeb, 0xa6, 0x44, 0xf7, 0x2b,
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+  0xe2, 0xf6, 0x32, 0x5e, 0x99, 0x8d, 0x4f, 0x4e, 0xc4, 0xfe, 0x81, 0x46,
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+  0xcd, 0x99, 0xe1, 0x93, 0x13, 0x0e, 0x3f, 0xbf, 0x6c, 0x7c, 0xf2, 0x2b,
+  0x19, 0xf9, 0x57, 0x27, 0x94, 0xe3, 0x9b, 0xe2, 0x93, 0xa6, 0xfa, 0x44,
+  0x16, 0x5e, 0xf9, 0xd0, 0x4d, 0xf3, 0x85, 0x57, 0xb2, 0xf3, 0x9f, 0x53,
+  0xe1, 0x95, 0x2d, 0xf8, 0x9f, 0xe6, 0xd3, 0xf6, 0xe3, 0x78, 0xd2, 0x1f,
+  0x26, 0x6f, 0x86, 0x67, 0xb2, 0xdf, 0x2f, 0xa4, 0xe9, 0x47, 0x1f, 0x24,
+  0x7f, 0xbf, 0x60, 0x86, 0x7f, 0x32, 0xfa, 0x2d, 0xce, 0x0d, 0xff, 0x64,
+  0xfe, 0x44, 0xc5, 0xb9, 0xe1, 0x9f, 0x2c, 0x7e, 0xaa, 0xcb, 0x10, 0xff,
+  0x94, 0xf0, 0x34, 0xe6, 0x1f, 0xd7, 0x65, 0x86, 0x7f, 0xca, 0xf8, 0x94,
+  0x1b, 0xd3, 0x87, 0x11, 0xfe, 0x29, 0xdb, 0x07, 0x1c, 0x3d, 0x1a, 0xe1,
+  0x9f, 0xd3, 0xf1, 0x79, 0x33, 0xc2, 0x3f, 0xb5, 0xfe, 0x42, 0x25, 0x43,
+  0xfc, 0x53, 0xd2, 0x7f, 0x19, 0x3f, 0x28, 0x99, 0xe1, 0x9f, 0x09, 0xff,
+  0x38, 0xba, 0x5f, 0x65, 0x33, 0xfc, 0x53, 0xb6, 0x87, 0xd8, 0x7a, 0x5d,
+  0x98, 0xe6, 0x5f, 0x77, 0x32, 0x79, 0x9e, 0x2f, 0x4c, 0xf5, 0x97, 0x4c,
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+  0xf0, 0x8b, 0xd6, 0xe9, 0x41, 0xe8, 0xff, 0x71, 0xeb, 0xf4, 0xc0, 0xe3,
+  0x9d, 0xc1, 0x99, 0x96, 0xfd, 0xd7, 0xa6, 0x3a, 0xd3, 0xf8, 0xcb, 0xaf,
+  0x93, 0xfc, 0x25, 0xd5, 0xfe, 0xb2, 0xcf, 0x24, 0xe2, 0x13, 0x96, 0x9a,
+  0xe1, 0xcf, 0x3a, 0x7a, 0x0b, 0x97, 0x1a, 0xe2, 0xdf, 0x73, 0x8a, 0x37,
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+  0xf0, 0xb0, 0xfe, 0x0f, 0x5d, 0x7a, 0xff, 0x5c, 0xb7, 0x44, 0xd7, 0xe3,
+  0x2c, 0xf1, 0x1f, 0xc5, 0x7e, 0xcb, 0xc6, 0x97, 0xe3, 0x13, 0xf8, 0xfb,
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+  0xb7, 0xa3, 0xaf, 0xc3, 0x23, 0x7a, 0x7e, 0xd4, 0x06, 0x4f, 0x18, 0x77,
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+  0x27, 0xe5, 0x4f, 0xa5, 0x3e, 0x7b, 0x4e, 0xd3, 0xeb, 0xce, 0xa9, 0x7a,
+  0xdd, 0xd1, 0xf9, 0x54, 0xfe, 0x97, 0x76, 0xc3, 0xfe, 0xe5, 0xa7, 0xad,
+  0x43, 0x48, 0xd6, 0xb7, 0x78, 0xbe, 0xf4, 0x09, 0xa8, 0xe4, 0x4b, 0xb9,
+  0x3e, 0xa0, 0xc8, 0x97, 0xde, 0x9b, 0x92, 0x2f, 0x55, 0xf3, 0xc3, 0xba,
+  0xbe, 0x75, 0x38, 0x5f, 0xba, 0x62, 0x64, 0xc9, 0x97, 0x1a, 0xec, 0xbc,
+  0xa4, 0x13, 0xfa, 0x68, 0x41, 0x9c, 0x77, 0xb0, 0x16, 0x79, 0x7d, 0x99,
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+  0x74, 0x37, 0xf3, 0x57, 0xe8, 0xfe, 0xba, 0x44, 0xf4, 0x0d, 0x1c, 0xae,
+  0x0f, 0xd2, 0x0d, 0xf0, 0xc5, 0xd2, 0xa0, 0x3d, 0xb2, 0x1f, 0x0c, 0x44,
+  0xf2, 0xd7, 0x0f, 0x69, 0xf5, 0xf7, 0x38, 0xfc, 0xd0, 0xf1, 0x9b, 0x32,
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+  0xbe, 0x4b, 0x3d, 0x1f, 0x68, 0xe4, 0x1d, 0x7f, 0xfd, 0x16, 0xdd, 0xaf,
+  0x76, 0x9f, 0x18, 0xa5, 0xd7, 0x77, 0x41, 0x3f, 0xcf, 0x4f, 0x7f, 0x2d,
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+  0x1b, 0x68, 0xf1, 0x3f, 0x39, 0x3e, 0x48, 0x10, 0xdf, 0x46, 0xee, 0x23,
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+  0x1a, 0xdf, 0x8c, 0x1d, 0xd9, 0xc2, 0xe8, 0xb9, 0x8a, 0x3e, 0x9f, 0x05,
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+  0xf8, 0xf0, 0x2a, 0xb2, 0xf6, 0xe3, 0xad, 0x69, 0x51, 0xf8, 0x47, 0x9c,
+  0xbf, 0x49, 0x78, 0x5f, 0xd6, 0xea, 0x6f, 0x56, 0x7f, 0x88, 0x5e, 0x9f,
+  0x4f, 0xa9, 0x37, 0x1a, 0x2f, 0x79, 0x99, 0xbf, 0x6e, 0xa8, 0xa1, 0x6b,
+  0x6e, 0xbb, 0x7c, 0x76, 0xc2, 0x55, 0xfc, 0x45, 0xfc, 0x5e, 0xce, 0x87,
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+  0x47, 0x9e, 0x14, 0xff, 0xef, 0x95, 0xe4, 0xfc, 0x9b, 0x1f, 0x27, 0xf7,
+  0x4b, 0xe6, 0x7c, 0x7f, 0x5e, 0xca, 0x5f, 0x63, 0xf2, 0x53, 0x29, 0x38,
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+  0xbe, 0x5d, 0x4b, 0xc2, 0xd5, 0x3f, 0x89, 0xa8, 0x5f, 0x00, 0x1f, 0x79,
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+  0xfc, 0x99, 0xe3, 0x77, 0xfd, 0xf2, 0x8b, 0xda, 0x5f, 0x58, 0x2a, 0x8f,
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+  0xce, 0xeb, 0x15, 0x78, 0xbe, 0x14, 0x37, 0x3b, 0x1f, 0xb2, 0x51, 0xcb,
+  0xb3, 0x15, 0xbf, 0x8c, 0x57, 0xc3, 0x2f, 0xf3, 0xd5, 0xc6, 0xd1, 0xfa,
+  0xfd, 0x7c, 0xa0, 0xe1, 0xfc, 0x08, 0xa9, 0xe3, 0x97, 0x43, 0x8a, 0x5f,
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+  0x2a, 0x14, 0x47, 0x6c, 0x1e, 0xba, 0x51, 0x30, 0x45, 0x7e, 0xc8, 0xdd,
+  0x6c, 0xe9, 0x7a, 0x96, 0x58, 0x80, 0x4f, 0xd6, 0x78, 0x51, 0xe7, 0x6b,
+  0x0a, 0x7e, 0xfe, 0x8b, 0xad, 0xd4, 0xe8, 0xba, 0x1a, 0x9f, 0xec, 0xc9,
+  0xcf, 0x6e, 0x95, 0xaf, 0x5d, 0xaf, 0xfb, 0xe7, 0x47, 0x63, 0xf6, 0xf5,
+  0x24, 0xc7, 0xd0, 0xbb, 0xcc, 0x82, 0x99, 0x54, 0x7c, 0xb2, 0xf7, 0xbc,
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+  0x96, 0x97, 0xc3, 0x39, 0xb8, 0xbf, 0xab, 0x66, 0x4f, 0xbd, 0xfe, 0xc3,
+  0x6d, 0xef, 0x4f, 0x37, 0xf4, 0x1f, 0xf2, 0xdd, 0x7f, 0x2e, 0x70, 0xff,
+  0x60, 0x43, 0xff, 0xa6, 0xef, 0xfe, 0xf3, 0x81, 0xfb, 0x87, 0x1a, 0xfa,
+  0x37, 0x7c, 0xf7, 0xbb, 0x3a, 0x1f, 0x00, 0xd4, 0xf9, 0x4e, 0xbd, 0xfd,
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+  0x89, 0xb5, 0xd0, 0xf7, 0x55, 0xf2, 0xc7, 0x63, 0xab, 0xe6, 0x8f, 0x47,
+  0x9f, 0xae, 0xe3, 0x8f, 0x99, 0x97, 0x75, 0x7a, 0xda, 0xd9, 0xbb, 0x87,
+  0xfe, 0x5f, 0xf8, 0xe4, 0x1d, 0x0f, 0xad, 0x8e, 0x4f, 0xde, 0xfa, 0xa0,
+  0xbe, 0x3f, 0xb0, 0x5f, 0x6a, 0xfc, 0x30, 0x34, 0xdd, 0x4f, 0x22, 0x7e,
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-  0xda, 0x83, 0xfb, 0x79, 0xfe, 0x35, 0x9f, 0x3d, 0xc4, 0x3c, 0xae, 0xf9,
-  0xf0, 0x14, 0xf1, 0x7f, 0x2e, 0xb8, 0xf5, 0x3e, 0xb9, 0xe4, 0x00, 0xf1,
-  0x5c, 0xea, 0x0c, 0x99, 0x5b, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1, 0x58,
+  0xe7, 0x0b, 0xf0, 0xaf, 0xe7, 0x7c, 0x01, 0xfe, 0xf5, 0x9c, 0x2f, 0xc0,
+  0xbf, 0x9e, 0xf3, 0x05, 0xf8, 0xd7, 0x73, 0xbe, 0x00, 0xff, 0x7a, 0xce,
+  0x17, 0xe0, 0x5f, 0xcf, 0xf9, 0x02, 0xfc, 0xeb, 0x39, 0x5f, 0x80, 0x7f,
+  0x3d, 0xe7, 0x0b, 0xf0, 0x1f, 0x78, 0x59, 0x80, 0x7f, 0xf5, 0xdc, 0x91,
+  0xfa, 0x17, 0x2e, 0xf0, 0xfb, 0xc1, 0x9a, 0xaf, 0x5f, 0xcc, 0xe7, 0xbc,
+  0xf0, 0xd5, 0x4b, 0xf9, 0x9c, 0x17, 0x5e, 0x1e, 0xe0, 0x73, 0x5e, 0xf8,
+  0xe8, 0x22, 0x3e, 0xf7, 0xa2, 0xfa, 0xbf, 0x06, 0xae, 0x5e, 0xb7, 0xc0,
+  0xef, 0x53, 0x6a, 0x3e, 0x3a, 0xca, 0xf3, 0x11, 0x3e, 0xbc, 0x81, 0xeb,
+  0xb4, 0x6a, 0x3e, 0xbb, 0x99, 0xeb, 0x08, 0xaf, 0x6e, 0xe1, 0xaf, 0x77,
+  0x35, 0x5f, 0xb9, 0x95, 0xbf, 0x5e, 0xf8, 0xe8, 0xb6, 0x2d, 0xf3, 0x74,
+  0x75, 0x9d, 0xd9, 0x3e, 0x9e, 0xe7, 0xf6, 0x3c, 0x6e, 0xe0, 0xae, 0x81,
+  0x47, 0xad, 0x86, 0xfa, 0x0d, 0x3c, 0x6e, 0xe0, 0xae, 0x81, 0x47, 0xf1,
+  0xf6, 0x7c, 0xcf, 0x9d, 0x0d, 0x7c, 0xa9, 0xa1, 0x4e, 0x54, 0x7f, 0x82,
+  0xec, 0xda, 0x83, 0xfb, 0x79, 0xfe, 0x35, 0x9f, 0x3d, 0xc4, 0x3c, 0xae,
+  0xf9, 0xf0, 0x14, 0xf1, 0x7f, 0x2e, 0xb8, 0xf5, 0x3e, 0xb9, 0xe4, 0x00,
+  0xf1, 0x5c, 0xea, 0x0c, 0x99, 0x5b, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1,
+  0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5,
+  0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1, 0x58, 0x2c, 0x16,
+  0x8b, 0xc5, 0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1, 0x58,
   0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62,
-  0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b,
-  0xc5, 0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1, 0x58, 0x2c,
-  0x16, 0x8b, 0xc5, 0x62, 0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1,
-  0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1, 0xfc, 0x3f, 0xb2, 0x59, 0x1c,
-  0xaa, 0xc7, 0xaa, 0x7b, 0xb0, 0x1e, 0x67, 0x0f, 0x5c, 0x5e, 0x8f, 0xa3,
-  0x6f, 0xe4, 0xe7, 0x3f, 0x94, 0x87, 0xaf, 0xa8, 0xc7, 0xd5, 0xfb, 0xfc,
-  0xcf, 0x83, 0x38, 0x7d, 0x25, 0x7c, 0xdf, 0xb9, 0x8e, 0x96, 0x9d, 0x4d,
-  0x75, 0xec, 0xd0, 0xb6, 0xe3, 0xf8, 0x84, 0xac, 0xf3, 0xf0, 0xda, 0xfd,
-  0xff, 0xfa, 0x75, 0xe7, 0x3a, 0x5a, 0x76, 0x36, 0x6b, 0x13, 0x59, 0xdf,
-  0xe9, 0xf5, 0x32, 0xae, 0xfb, 0xf5, 0x1e, 0xdf, 0x28, 0x63, 0x39, 0x95,
-  0x73, 0xa1, 0x1c, 0x1f, 0x34, 0x59, 0xe7, 0x61, 0xfe, 0x06, 0x00, 0x00,
-  0xff, 0xff, 0xec, 0xdd, 0xbf, 0x4a, 0x82, 0x51, 0x18, 0x07, 0x60, 0x3e,
-  0x49, 0xa7, 0x22, 0x11, 0x05, 0xc7, 0xc0, 0x1b, 0xf0, 0xb3, 0x84, 0x10,
-  0x1a, 0xed, 0x1e, 0x5c, 0xa5, 0x10, 0xc1, 0xd5, 0x0b, 0x88, 0x86, 0x52,
-  0x30, 0x6f, 0xc1, 0xa1, 0xcd, 0x1b, 0x71, 0xf1, 0x06, 0xdc, 0x9b, 0xbd,
-  0x04, 0xfb, 0xc3, 0xdb, 0x10, 0x88, 0x5b, 0x06, 0x9d, 0xe7, 0xe1, 0x1c,
-  0x7e, 0x7c, 0x9c, 0xed, 0xc7, 0x7b, 0xb6, 0x0f, 0xce, 0xf7, 0x5a, 0xbc,
-  0xba, 0x8f, 0x29, 0x1a, 0x74, 0x1b, 0xd9, 0x76, 0xbd, 0x9c, 0x68, 0x02,
-  0x20, 0x2d, 0xde, 0x7f, 0x86, 0x74, 0x2d, 0x2b, 0xab, 0xcd, 0x5b, 0xef,
-  0x54, 0x11, 0x89, 0x2a, 0xd7, 0x6f, 0xfe, 0x34, 0x01, 0x00, 0x80, 0xa3,
-  0x3a, 0x89, 0x2c, 0x46, 0x4e, 0x23, 0x4b, 0x91, 0xe7, 0x91, 0xf3, 0xc8,
-  0x27, 0x95, 0xfd, 0x2b, 0x85, 0xec, 0xe7, 0x1c, 0x54, 0xe3, 0xbb, 0x96,
-  0x1d, 0x9e, 0x8b, 0xc7, 0x38, 0x7f, 0x88, 0x9c, 0x44, 0x3e, 0x47, 0xce,
-  0xb2, 0xfd, 0xf3, 0xf3, 0xf2, 0xf9, 0x40, 0xda, 0x2e, 0xa8, 0x1f, 0x00,
-  0x00, 0x00, 0xe0, 0x77, 0x9d, 0x7d, 0x6d, 0x7f, 0x81, 0xa5, 0xea, 0xf6,
-  0xbe, 0x7f, 0xd1, 0x6a, 0x7e, 0xac, 0xbc, 0xad, 0x8c, 0x04, 0xe5, 0xd7,
-  0x9d, 0xab, 0xcb, 0x4e, 0xde, 0xd2, 0x44, 0x9a, 0xfa, 0xe3, 0xe1, 0xe8,
-  0x4e, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x14, 0xef, 0x00,
-  0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80,
-  0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00,
-  0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2,
-  0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff,
-  0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf,
-  0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03,
-  0x00, 0x00, 0xff, 0xff, 0xed, 0xc2, 0x31, 0x0d, 0x00, 0x00, 0x00, 0x80,
-  0xa0, 0xfe, 0xad, 0x8d, 0xe1, 0x03, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x16,
-  0x43, 0x8e, 0xfd, 0xea, 0x78, 0xda, 0xec, 0xc1, 0x01, 0x01, 0x00, 0x00,
-  0x00, 0x80, 0x90, 0xfe, 0xaf, 0xee, 0x08, 0x0a, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09,
-  0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec,
-  0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88,
-  0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00,
-  0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe,
-  0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
-  0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00,
+  0xb1, 0x58, 0x2c, 0x16, 0x8b, 0xc5, 0x62, 0xb1, 0xfc, 0x3f, 0xb2, 0x59,
+  0x1c, 0xaa, 0xc7, 0xaa, 0x7b, 0xb0, 0x1e, 0x67, 0x0f, 0x5c, 0x5e, 0x8f,
+  0xa3, 0x6f, 0xe4, 0xe7, 0x3f, 0x94, 0x87, 0xaf, 0xa8, 0xc7, 0xd5, 0xfb,
+  0xfc, 0xcf, 0x83, 0x38, 0x7d, 0x25, 0x7c, 0xdf, 0xb9, 0x8e, 0x96, 0x9d,
+  0x4d, 0x75, 0xec, 0xd0, 0xb6, 0xe3, 0xf8, 0x84, 0xac, 0xf3, 0xf0, 0xda,
+  0xfd, 0xff, 0xfa, 0x75, 0xe7, 0x3a, 0x5a, 0x76, 0x36, 0x6b, 0x13, 0x59,
+  0xdf, 0xe9, 0xf5, 0x32, 0xae, 0xfb, 0xf5, 0x1e, 0xdf, 0x28, 0x63, 0x39,
+  0x95, 0x73, 0xa1, 0x1c, 0x1f, 0x34, 0x59, 0xe7, 0x61, 0xfe, 0x06, 0x00,
+  0x00, 0xff, 0xff, 0xec, 0xdd, 0xb1, 0x4a, 0x42, 0x61, 0x18, 0x06, 0x60,
+  0x8e, 0x94, 0x93, 0xa1, 0x48, 0x82, 0xa3, 0xd0, 0x0d, 0xe8, 0x41, 0x17,
+  0xa1, 0xb1, 0xd9, 0xb9, 0x35, 0x83, 0x10, 0x1a, 0xed, 0x02, 0xc2, 0xa1,
+  0x14, 0xd2, 0x5b, 0x70, 0x68, 0xf3, 0x46, 0x5c, 0xbc, 0x81, 0xf6, 0x66,
+  0x2f, 0x21, 0x49, 0x3e, 0x07, 0x21, 0xda, 0x54, 0xf0, 0x7f, 0x1e, 0xce,
+  0xe1, 0xe5, 0x70, 0xb6, 0x97, 0xef, 0xdf, 0x7e, 0xf8, 0x76, 0xcf, 0xfc,
+  0xd3, 0x79, 0x4c, 0xd1, 0xd3, 0xdd, 0x4d, 0xb6, 0x5e, 0x2d, 0xc6, 0x9a,
+  0x00, 0x48, 0x8b, 0xfd, 0xcf, 0x90, 0xae, 0x45, 0x75, 0xf9, 0xf5, 0x7d,
+  0x5f, 0x52, 0x44, 0xa2, 0x2a, 0xf5, 0xdb, 0x93, 0x26, 0x00, 0x00, 0x70,
+  0x54, 0x17, 0x91, 0x97, 0x91, 0x93, 0xc8, 0x62, 0x64, 0x39, 0x72, 0x16,
+  0xf9, 0xa6, 0xb2, 0xb3, 0x52, 0xc8, 0xf6, 0xe7, 0xe0, 0x3a, 0xbe, 0x6b,
+  0xd9, 0xff, 0x73, 0x31, 0x8a, 0xff, 0xaf, 0x91, 0xe3, 0xc8, 0xf7, 0xc8,
+  0x8f, 0xec, 0xef, 0xf9, 0x99, 0xfe, 0x2e, 0x48, 0xfb, 0x09, 0xea, 0x07,
+  0x00, 0x00, 0x00, 0x38, 0xac, 0xab, 0xed, 0xeb, 0x16, 0x58, 0xaa, 0x7a,
+  0xfd, 0x61, 0xa3, 0xd5, 0x6e, 0xe4, 0xcd, 0x56, 0x47, 0x19, 0x09, 0x6a,
+  0xe6, 0xdd, 0xbc, 0xdd, 0xed, 0xe4, 0x9a, 0x48, 0xd3, 0xc3, 0xcb, 0xe0,
+  0xf9, 0x51, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x14, 0x1b,
+  0x00, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00,
   0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -143370,11 +143327,186 @@ unsigned char ql83xx_firmware[] = {
   0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
-  0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00,
-  0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x03, 0x00, 0x00, 0xff, 0xff, 0xed, 0xc2, 0x31, 0x0d, 0x00, 0x00, 0x00,
+  0x80, 0xa0, 0xfe, 0xad, 0x8d, 0xe1, 0x03, 0x43, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0,
+  0x16, 0x8a, 0xfc, 0xfe, 0xde, 0x78, 0xda, 0xec, 0xc1, 0x01, 0x01, 0x00,
+  0x00, 0x00, 0x80, 0x90, 0xfe, 0xaf, 0xee, 0x08, 0x0a, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09,
+  0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01,
+  0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff,
+  0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee,
+  0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00,
+  0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0,
+  0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00,
+  0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01,
+  0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff,
+  0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee,
+  0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+  0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0,
+  0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00,
+  0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+  0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01,
+  0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff,
+  0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee,
+  0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+  0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0,
+  0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00,
+  0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01,
+  0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff,
+  0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee,
+  0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00,
+  0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0,
+  0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00,
+  0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01,
+  0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff,
+  0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee,
+  0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00,
+  0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0,
+  0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00,
+  0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01,
+  0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff,
+  0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee,
+  0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00,
+  0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0,
+  0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00,
+  0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01,
+  0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff,
+  0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee,
+  0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00,
+  0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0,
+  0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00,
+  0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01,
+  0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff,
+  0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee,
+  0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00,
+  0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0,
+  0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00,
+  0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01,
+  0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff,
+  0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee,
+  0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00,
+  0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0,
+  0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00,
+  0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01,
+  0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff,
+  0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee,
+  0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00,
+  0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0,
+  0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xd2, 0xc1, 0x0d, 0x00, 0x30,
+  0x08, 0x03, 0x31, 0xf5, 0xc5, 0xfa, 0xdd, 0x18, 0xba, 0x44, 0x1f, 0x28,
+  0xb6, 0x98, 0xe0, 0x82, 0x03, 0x00, 0x80, 0x3c, 0x5d, 0x1a, 0xe8, 0x01,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6c, 0x74, 0x8f, 0x06, 0xc9,
+  0xfa, 0x51, 0x21, 0x7b, 0x7f, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0xf0, 0xdf, 0x00, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09,
   0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -143391,5574 +143523,5436 @@ unsigned char ql83xx_firmware[] = {
   0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09,
-  0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec,
-  0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88,
-  0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00,
-  0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe,
-  0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
-  0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00,
-  0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09,
-  0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec,
-  0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88,
-  0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00,
-  0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe,
-  0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
-  0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00,
-  0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09,
-  0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec,
-  0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88,
-  0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00,
-  0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe,
-  0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
-  0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00,
-  0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09,
-  0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec,
-  0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88,
-  0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00,
-  0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe,
-  0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
-  0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00,
-  0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09,
-  0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec,
-  0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88,
-  0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00,
-  0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe,
-  0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
-  0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00,
-  0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09,
-  0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec,
-  0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88,
-  0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00,
-  0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe,
-  0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
-  0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00,
-  0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09,
-  0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec,
-  0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88,
-  0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00,
-  0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe,
-  0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50,
-  0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xd2, 0xc1, 0x0d, 0x00, 0x30, 0x08,
-  0x03, 0x31, 0xf5, 0xc5, 0xfa, 0xdd, 0x18, 0xba, 0x44, 0x1f, 0x28, 0xb6,
-  0x98, 0xe0, 0x82, 0x03, 0x00, 0x80, 0x3c, 0x5d, 0x1a, 0xe8, 0x01, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6c, 0x74, 0x8f, 0x06, 0xc9, 0xfa,
-  0x51, 0x21, 0x7b, 0x7f, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0xf0, 0xdf, 0x00, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00,
-  0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xec, 0xc2,
-  0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03, 0x00, 0x00, 0xff,
-  0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80, 0xa0, 0xfe, 0xaf,
-  0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x03,
-  0x00, 0x00, 0xff, 0xff, 0xec, 0xc2, 0x01, 0x09, 0x00, 0x00, 0x00, 0x80,
-  0xa0, 0xfe, 0xaf, 0xee, 0x88, 0xa2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x50, 0x03, 0x00, 0x00, 0xff, 0xff, 0xed, 0xd4, 0x3b, 0x0e, 0x80,
-  0x20, 0x10, 0x45, 0xd1, 0xf8, 0xc1, 0x0f, 0xee, 0x7f, 0xbd, 0xda, 0x3c,
-  0x9b, 0x49, 0xac, 0x29, 0x3c, 0x27, 0x24, 0x37, 0x14, 0xc0, 0x54, 0x58,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x5f, 0xdc, 0xa5, 0x00, 0x0c,
-  0xfa, 0x8f, 0x63, 0xcd, 0x7e, 0x4e, 0x97, 0x74, 0x4b, 0xcf, 0xb4, 0x97,
-  0xf3, 0x2d, 0x3d, 0xd2, 0x29, 0xdd, 0x4b, 0xfb, 0xc7, 0xfd, 0x53, 0x39,
-  0xff, 0xce, 0x71, 0x95, 0x77, 0x5b, 0x99, 0x07, 0x00, 0x00, 0x60, 0x94,
-  0x07, 0xd9, 0x7d, 0x19, 0x01, 0x78, 0xda, 0xdc, 0x5d, 0x7d, 0x70, 0x5c,
-  0x57, 0x75, 0x3f, 0xef, 0x63, 0x3f, 0xb4, 0xde, 0x5d, 0xaf, 0x65, 0x59,
-  0x51, 0x14, 0x37, 0x79, 0x11, 0x4e, 0x50, 0x6c, 0x27, 0x23, 0x3b, 0x86,
-  0x88, 0xc4, 0x4d, 0x9e, 0x8c, 0x03, 0x4a, 0x6c, 0x83, 0x0b, 0x9d, 0x62,
-  0x3e, 0xd2, 0x6c, 0x70, 0xa0, 0xf2, 0xb7, 0x3a, 0xd0, 0x56, 0xe1, 0x63,
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+  0xf6, 0xf0, 0x29, 0x9d, 0xab, 0xca, 0xfa, 0x03, 0xb8, 0xfd, 0x75, 0xf7,
+  0x4b, 0x4c, 0xbf, 0xcd, 0xf7, 0x3a, 0xd3, 0xdf, 0x01, 0xef, 0x4d, 0xd3,
+  0xfe, 0x80, 0x6f, 0x06, 0x63, 0xe8, 0xd7, 0x9a, 0xad, 0xaa, 0xd6, 0x1b,
+  0x72, 0xf7, 0xf5, 0x26, 0x7b, 0x1e, 0x7b, 0x35, 0xcd, 0xf6, 0xaf, 0x3c,
+  0xdf, 0xd2, 0xef, 0xd7, 0x38, 0xf4, 0xbb, 0x28, 0x8b, 0xa7, 0x57, 0x04,
+  0xf2, 0x9b, 0xbc, 0xfc, 0x8b, 0xbf, 0x0d, 0xc6, 0x30, 0xff, 0xf6, 0x92,
+  0x4c, 0xfe, 0xc2, 0x54, 0x48, 0xfb, 0x37, 0x9a, 0x71, 0xd8, 0xff, 0x13,
+  0x55, 0xff, 0x32, 0xff, 0x1d, 0x08, 0xea, 0x6f, 0xfe, 0x6e, 0x52, 0x2d,
+  0x5f, 0x93, 0x3f, 0x95, 0xa2, 0xf2, 0xf6, 0x27, 0xe5, 0xf9, 0xa0, 0x07,
+  0x7f, 0x97, 0xd5, 0xbf, 0x12, 0xf9, 0x28, 0xbf, 0x32, 0xc3, 0xd7, 0x75,
+  0x49, 0x91, 0xaf, 0xf4, 0x2c, 0x7d, 0x1f, 0x9d, 0x0f, 0xed, 0xd4, 0x93,
+  0x52, 0x7b, 0x6c, 0x04, 0xf2, 0x15, 0xf0, 0xfa, 0xba, 0xf8, 0x4c, 0x1b,
+  0x83, 0x6d, 0xe0, 0x33, 0x7d, 0xfd, 0x0f, 0xc2, 0x5f, 0x80, 0xf9, 0x34,
+  0xa4, 0xf9, 0x86, 0xbf, 0x58, 0xbc, 0x18, 0x62, 0xfc, 0x15, 0xfe, 0xc2,
+  0xad, 0xb7, 0x9f, 0xa8, 0xbf, 0x1a, 0x3b, 0x71, 0xac, 0xb7, 0x1f, 0xab,
+  0x6a, 0xf3, 0xdb, 0x3d, 0xf7, 0x67, 0x66, 0x70, 0x3e, 0x70, 0x61, 0x55,
+  0x31, 0x1f, 0x08, 0xd6, 0x7c, 0xfd, 0x4d, 0x24, 0x8f, 0xaa, 0xff, 0x3d,
+  0xf9, 0xa7, 0xc0, 0xff, 0x84, 0xdf, 0x73, 0x2d, 0x70, 0x7d, 0xb6, 0xdb,
+  0xff, 0x7e, 0x5e, 0x17, 0xf8, 0x1f, 0x95, 0x6f, 0x2b, 0xac, 0x7c, 0x6d,
+  0xe1, 0xfb, 0xad, 0x6f, 0x88, 0xf8, 0x7e, 0xe3, 0xb1, 0xd7, 0x97, 0x1b,
+  0x12, 0x7b, 0x81, 0x4d, 0x76, 0xbf, 0x52, 0x9a, 0x62, 0xea, 0xd7, 0x7e,
+  0xc8, 0xb0, 0xf1, 0x64, 0x35, 0xe3, 0xad, 0x5f, 0x6b, 0x88, 0xeb, 0xd7,
+  0xe0, 0x5a, 0x26, 0xda, 0xf3, 0x46, 0x6e, 0x54, 0x12, 0x0f, 0xcd, 0x29,
+  0xa6, 0x7e, 0x90, 0xc8, 0x8f, 0xe1, 0x85, 0xca, 0x6f, 0xc5, 0xf3, 0x63,
+  0xe5, 0x18, 0xf2, 0xc3, 0xc5, 0x51, 0x35, 0x7c, 0x69, 0xb7, 0x7f, 0xec,
+  0xdb, 0x0c, 0x87, 0xe7, 0x7e, 0xeb, 0xa7, 0xbf, 0x0d, 0xf2, 0x3c, 0x8b,
+  0xe5, 0xb1, 0xe3, 0x81, 0xb9, 0x3f, 0x7e, 0x79, 0x3e, 0x15, 0xc9, 0xe3,
+  0xc9, 0xa7, 0x7f, 0x0d, 0xdc, 0xf7, 0x99, 0xe4, 0x7d, 0x03, 0x8a, 0x7c,
+  0x6e, 0xd7, 0xb6, 0x64, 0xf3, 0xa6, 0xb7, 0xfc, 0xf3, 0xf5, 0x1c, 0x3f,
+  0xaf, 0x0e, 0x16, 0xfb, 0xcb, 0x0c, 0x3f, 0xd0, 0xe2, 0xa3, 0xe5, 0x60,
+  0x7e, 0x20, 0xe0, 0x7b, 0xbe, 0xab, 0xe0, 0xf7, 0x71, 0xfc, 0x3d, 0x84,
+  0xef, 0xe6, 0xef, 0x16, 0x1e, 0xd8, 0xf3, 0x25, 0x92, 0x1a, 0x58, 0xb9,
+  0x88, 0xfb, 0xdd, 0x8c, 0x09, 0x3c, 0x0f, 0xa1, 0x86, 0xce, 0xc7, 0x38,
+  0xbe, 0x94, 0xb6, 0x27, 0xf1, 0x7c, 0xea, 0xdc, 0x44, 0xfe, 0x0d, 0xa2,
+  0xac, 0x47, 0x1e, 0x68, 0x9f, 0xdf, 0xba, 0x98, 0xfc, 0x9d, 0xf3, 0xfb,
+  0xe3, 0x8e, 0x3c, 0x06, 0xff, 0x7e, 0x4e, 0x3e, 0x4b, 0xdf, 0x81, 0x72,
+  0xe0, 0xbc, 0x1a, 0x9e, 0x1f, 0x6e, 0xa8, 0x95, 0x7f, 0x54, 0xe2, 0xab,
+  0x84, 0x9d, 0x76, 0x7e, 0xc6, 0x76, 0xbd, 0x23, 0x6e, 0xff, 0x13, 0xf1,
+  0xbd, 0x4f, 0x93, 0xef, 0x77, 0x83, 0xe3, 0x7f, 0xc9, 0xb4, 0xee, 0xc3,
+  0x9b, 0x36, 0xbf, 0x13, 0xfb, 0xfd, 0xc6, 0x0d, 0x08, 0x4c, 0xcb, 0x5e,
+  0x1a, 0x30, 0xe6, 0xa9, 0x7d, 0x3b, 0x2f, 0x9f, 0x87, 0x46, 0xf1, 0x20,
+  0x9a, 0x07, 0x61, 0xa2, 0x7c, 0x7e, 0xc3, 0x48, 0xb3, 0xfb, 0x51, 0x57,
+  0xfe, 0x81, 0xcd, 0xf7, 0x27, 0x20, 0xe6, 0x67, 0x7a, 0x08, 0xd8, 0xfe,
+  0x8b, 0x0a, 0x03, 0x0a, 0xe9, 0x34, 0x98, 0xe8, 0xb3, 0xd3, 0x18, 0xf6,
+  0xfd, 0x87, 0xce, 0xe4, 0xd3, 0x10, 0x80, 0x26, 0xba, 0x5c, 0xf9, 0x04,
+  0x45, 0x7b, 0xd1, 0xfa, 0xab, 0x9d, 0x03, 0xd8, 0x5e, 0x7d, 0x49, 0x1f,
+  0xfb, 0xac, 0xbc, 0xe2, 0xe6, 0x17, 0xe3, 0xe3, 0x8f, 0xdb, 0xdf, 0xc2,
+  0xc4, 0x1f, 0xa0, 0x67, 0xa3, 0x8d, 0x3f, 0xe7, 0x46, 0xc3, 0xf2, 0x29,
+  0x93, 0xef, 0x29, 0xaa, 0x0f, 0xa9, 0x05, 0xf2, 0x45, 0x52, 0x3c, 0xa6,
+  0x7c, 0x91, 0xe8, 0xbe, 0xdf, 0xc8, 0x94, 0xd3, 0x82, 0xfb, 0x7d, 0xe7,
+  0x5f, 0x75, 0x4b, 0x0d, 0x6f, 0x84, 0xcf, 0xd3, 0xfd, 0x01, 0x39, 0x7f,
+  0xd0, 0xf9, 0xf1, 0x88, 0x7f, 0x94, 0x9f, 0x7f, 0xc8, 0xf3, 0x1d, 0x67,
+  0xac, 0xe7, 0x51, 0xfe, 0xa9, 0xb0, 0x8c, 0xd7, 0x3b, 0xf9, 0x03, 0xdd,
+  0x79, 0x05, 0xbe, 0x17, 0x38, 0xeb, 0x4c, 0xcd, 0x80, 0x3c, 0xbf, 0x0b,
+  0xff, 0x7e, 0x11, 0xde, 0x3f, 0xfc, 0x42, 0x4a, 0xe9, 0xf9, 0xa7, 0x0f,
+  0x75, 0xd0, 0xfd, 0x7c, 0x6f, 0xd2, 0x9e, 0x0f, 0xd8, 0x67, 0xbb, 0x84,
+  0x50, 0xde, 0x5a, 0x4d, 0x8f, 0x04, 0xaf, 0x8b, 0xce, 0x7a, 0x77, 0xf1,
+  0x49, 0xb5, 0xf0, 0xba, 0xf8, 0x95, 0xef, 0xbc, 0xad, 0x8e, 0x40, 0xbc,
+  0x26, 0xe6, 0x2e, 0x11, 0xfb, 0x37, 0x48, 0x7e, 0x3e, 0x87, 0xd7, 0x2b,
+  0xca, 0xcf, 0x25, 0x41, 0x37, 0xc6, 0x6b, 0x98, 0x82, 0x2c, 0x7e, 0x6b,
+  0xe0, 0x2e, 0x67, 0x86, 0xe8, 0x74, 0xc2, 0x8b, 0xcf, 0x19, 0xcd, 0xc9,
+  0xdf, 0x15, 0x92, 0xfe, 0xf8, 0x8c, 0xf9, 0x3c, 0x5a, 0xeb, 0xd5, 0x10,
+  0xe3, 0xb3, 0x7f, 0x3c, 0xaa, 0x73, 0xf7, 0x41, 0xd7, 0x15, 0xf1, 0x86,
+  0xd6, 0x67, 0xe6, 0x08, 0x3e, 0x1f, 0x4d, 0xfa, 0xac, 0x2f, 0x21, 0x3e,
+  0xe7, 0xb9, 0x7c, 0xed, 0x50, 0xc2, 0x8d, 0xcf, 0x9d, 0xf8, 0x7b, 0x11,
+  0x7c, 0x3e, 0x69, 0xe1, 0x73, 0x23, 0xc7, 0xe1, 0xb3, 0x15, 0xff, 0xe6,
+  0x26, 0x8b, 0x07, 0xed, 0xfe, 0x8e, 0x02, 0xa9, 0x1f, 0xae, 0x1d, 0xef,
+  0x80, 0xbe, 0xf8, 0x9c, 0x67, 0xf3, 0xfb, 0x74, 0x9e, 0x4a, 0xb8, 0xfc,
+  0x30, 0xd4, 0x6a, 0x0e, 0x7e, 0x67, 0x5e, 0x03, 0x8d, 0x0b, 0xd6, 0x7e,
+  0xd5, 0xd2, 0xb5, 0x57, 0x37, 0x3a, 0x51, 0xbd, 0x0c, 0xf2, 0xdf, 0x63,
+  0x3e, 0x78, 0x0e, 0xa6, 0xb5, 0x34, 0xf9, 0x7b, 0xca, 0xf6, 0x25, 0xf8,
+  0xf6, 0xcf, 0x01, 0x1f, 0xfb, 0xca, 0xf0, 0x1c, 0x02, 0x31, 0x9e, 0x5f,
+  0xfd, 0x1f, 0xf1, 0xfc, 0xa6, 0x10, 0xcf, 0x4d, 0x6c, 0xff, 0xc5, 0x49,
+  0x3f, 0x7e, 0x64, 0xca, 0x37, 0x5d, 0xc0, 0xf7, 0x47, 0xad, 0xfb, 0x9a,
+  0x04, 0x50, 0xe0, 0x7b, 0x7e, 0x66, 0x0e, 0xbf, 0xdf, 0xd0, 0x70, 0x3d,
+  0xac, 0xb5, 0x5e, 0x3f, 0xd2, 0xe4, 0xcf, 0x73, 0x3f, 0xe7, 0xf3, 0xfd,
+  0xc4, 0x1e, 0xe7, 0xd7, 0xc3, 0xe1, 0x9f, 0x1c, 0xcf, 0xe2, 0x39, 0x4f,
+  0xbf, 0x3b, 0xa7, 0xef, 0xf6, 0x3c, 0xdd, 0x16, 0x79, 0x96, 0x42, 0xca,
+  0x73, 0xbb, 0xf1, 0x9f, 0xfa, 0x97, 0x27, 0xfe, 0x27, 0x02, 0xe3, 0xff,
+  0xfd, 0x35, 0x5d, 0x49, 0x1f, 0xe1, 0xf3, 0x7b, 0x84, 0x0f, 0xbb, 0x67,
+  0x5b, 0x6d, 0x3f, 0x23, 0x7c, 0x1e, 0xf2, 0x7c, 0x7a, 0x75, 0x2e, 0x9f,
+  0x46, 0xf2, 0x1f, 0xa7, 0x31, 0x5f, 0x49, 0x9d, 0xeb, 0x7f, 0x87, 0x09,
+  0x88, 0xe2, 0xa1, 0xf5, 0x9f, 0x6b, 0xa7, 0x66, 0x8b, 0xa0, 0x79, 0xdc,
+  0x89, 0xd7, 0xc6, 0x82, 0xc3, 0xcf, 0x02, 0x4e, 0x94, 0x99, 0xfb, 0xdc,
+  0x3a, 0xc3, 0xe7, 0x29, 0x9e, 0xcf, 0xb6, 0xd3, 0x11, 0x65, 0x7e, 0xe1,
+  0x81, 0x31, 0xc9, 0x7e, 0x04, 0x12, 0xfd, 0xf8, 0x78, 0x93, 0x67, 0xf2,
+  0x7f, 0x39, 0x47, 0x3f, 0xeb, 0xfc, 0x41, 0xf4, 0x83, 0x8f, 0x95, 0x5d,
+  0xf5, 0x45, 0x01, 0x7c, 0x2c, 0x91, 0xe6, 0x4b, 0x0e, 0x8b, 0xf4, 0x31,
+  0x01, 0x64, 0xf3, 0x03, 0x5d, 0x12, 0x7f, 0x7c, 0x33, 0xd0, 0x1f, 0xa9,
+  0xbc, 0xd4, 0x1f, 0x7b, 0xb0, 0x3f, 0xb2, 0xfd, 0xc6, 0x50, 0xd1, 0x1f,
+  0x43, 0x3f, 0x4f, 0xd7, 0xdb, 0x7a, 0xac, 0xf9, 0xcb, 0x6f, 0xb7, 0xc3,
+  0xe5, 0x2f, 0xbd, 0xf2, 0xb6, 0xf8, 0x63, 0xdc, 0xfc, 0xd0, 0x87, 0xb2,
+  0xec, 0xf9, 0xad, 0x27, 0xab, 0x76, 0x7e, 0x3b, 0x1c, 0x71, 0xbc, 0xaf,
+  0xc8, 0xd6, 0xc7, 0x7b, 0x2f, 0x33, 0xf7, 0x69, 0x44, 0x7e, 0xb2, 0x5f,
+  0x21, 0xf2, 0x27, 0x41, 0xe3, 0x89, 0x72, 0x0c, 0xfd, 0xc7, 0xcf, 0x8d,
+  0x29, 0xd6, 0xdb, 0xc2, 0x47, 0x38, 0xbc, 0xe3, 0xd6, 0xfb, 0xc4, 0x0c,
+  0x53, 0xff, 0x34, 0x80, 0xf5, 0xb3, 0x36, 0xcd, 0x95, 0x32, 0xea, 0xdf,
+  0x35, 0xde, 0x72, 0xf6, 0xb3, 0xc3, 0x32, 0xbe, 0x37, 0x47, 0xdf, 0x5e,
+  0x25, 0x7d, 0x27, 0x64, 0xfa, 0x9e, 0x19, 0x0b, 0xcb, 0x27, 0x2a, 0xe2,
+  0xd7, 0x12, 0xe9, 0x67, 0x8e, 0xec, 0x05, 0xfd, 0x66, 0x64, 0xfa, 0xc1,
+  0xcd, 0x60, 0xfd, 0xae, 0x3a, 0xf7, 0xd7, 0xe4, 0xb8, 0xf7, 0x78, 0x96,
+  0xd4, 0x43, 0x34, 0x9e, 0xe2, 0xf4, 0x03, 0xc1, 0xfa, 0xe1, 0xfb, 0xdf,
+  0x88, 0xf5, 0x9b, 0x1b, 0x0b, 0xcb, 0xf7, 0x86, 0xf5, 0x99, 0x7f, 0x11,
+  0xc7, 0xa7, 0x61, 0x36, 0x5f, 0xa5, 0xb1, 0xdf, 0x6f, 0x3f, 0x68, 0x8e,
+  0x3b, 0xfa, 0x55, 0xde, 0x71, 0xf4, 0x63, 0xeb, 0x07, 0x85, 0xf7, 0x85,
+  0x25, 0x25, 0xfd, 0xa6, 0x65, 0xfa, 0xbd, 0x2d, 0xd3, 0x0f, 0x70, 0xfa,
+  0x15, 0x59, 0xbe, 0xc8, 0x0b, 0x59, 0x96, 0x2f, 0x72, 0x80, 0xe2, 0x0b,
+  0xac, 0x94, 0xf1, 0xbc, 0x57, 0x1b, 0x5f, 0xec, 0xfe, 0xb5, 0x23, 0xe8,
+  0x47, 0x67, 0xb5, 0x66, 0x08, 0xfe, 0x6f, 0x97, 0xbf, 0x26, 0xa2, 0xfc,
+  0x9e, 0x1f, 0x87, 0xc4, 0x9f, 0xff, 0x00, 0xd5, 0x62, 0x9c, 0xa8, 0x20,
+  0x0a, 0x20, 0x42, 0x55, 0x49, 0x4c, 0x44, 0x5f, 0x53, 0x54, 0x52, 0x3d,
+  0x57, 0x65, 0x64, 0x20, 0x4f, 0x63, 0x74, 0x20, 0x31, 0x34, 0x20, 0x30,
+  0x32, 0x3a, 0x30, 0x38, 0x3a, 0x32, 0x36, 0x20, 0x50, 0x44, 0x54, 0x20,
+  0x32, 0x30, 0x31, 0x35, 0x20, 0x62, 0x79, 0x20, 0x62, 0x74, 0x30, 0x34,
+  0x3a, 0x62, 0x75, 0x69, 0x6c, 0x64, 0x20, 0x69, 0x6e, 0x20, 0x2f, 0x75,
+  0x73, 0x72, 0x2f, 0x71, 0x6c, 0x63, 0x2f, 0x70, 0x72, 0x6f, 0x6a, 0x2f,
+  0x62, 0x75, 0x69, 0x6c, 0x64, 0x2f, 0x63, 0x68, 0x65, 0x63, 0x6b, 0x69,
+  0x6e, 0x5f, 0x62, 0x75, 0x69, 0x6c, 0x64, 0x2f, 0x70, 0x65, 0x67, 0x6e,
+  0x65, 0x74, 0x5f, 0x6e, 0x69, 0x63, 0x2d, 0x52, 0x5f, 0x35, 0x5f, 0x34,
+  0x5f, 0x35, 0x78, 0x2f, 0x73, 0x77, 0x2e, 0x68, 0x69, 0x6c, 0x64, 0x61,
+  0x20, 0x0a, 0x20, 0x42, 0x55, 0x49, 0x4c, 0x44, 0x5f, 0x4f, 0x50, 0x54,
+  0x53, 0x3d, 0x4d, 0x4e, 0x3a, 0x30, 0x2c, 0x20, 0x4d, 0x53, 0x5f, 0x31,
+  0x32, 0x38, 0x4d, 0x42, 0x3a, 0x31, 0x20, 0x0a, 0x20, 0x46, 0x43, 0x4f,
+  0x45, 0x3d, 0x30, 0x20, 0x0a, 0x20, 0x49, 0x53, 0x43, 0x53, 0x49, 0x3d,
+  0x31, 0x20, 0x0a, 0x20, 0x49, 0x53, 0x43, 0x53, 0x49, 0x5f, 0x4d, 0x4f,
+  0x44, 0x45, 0x3d, 0x69, 0x6e, 0x69, 0x74, 0x69, 0x61, 0x74, 0x6f, 0x72,
+  0x20, 0x0a, 0x20, 0x43, 0x48, 0x49, 0x50, 0x5f, 0x52, 0x45, 0x56, 0x49,
+  0x53, 0x49, 0x4f, 0x4e, 0x3d, 0x30, 0x78, 0x36, 0x30, 0x20, 0x0a, 0x20,
+  0x54, 0x4e, 0x49, 0x43, 0x5f, 0x52, 0x45, 0x56, 0x3d, 0x31, 0x2e, 0x31,
+  0x2e, 0x30, 0x20, 0x0a, 0x20, 0x52, 0x45, 0x56, 0x3d, 0x35, 0x2e, 0x34,
+  0x2e, 0x35, 0x36, 0x20, 0x0a, 0xff, 0xff, 0xff
 };
-unsigned int ql83xx_firmware_len = 1787044;
+unsigned int ql83xx_firmware_len = 1786976;
 
diff --git a/sys/dev/qlxgbe/ql_ver.h b/sys/dev/qlxgbe/ql_ver.h
index 0d86db943efc..34051fc3a19a 100644
--- a/sys/dev/qlxgbe/ql_ver.h
+++ b/sys/dev/qlxgbe/ql_ver.h
@@ -36,6 +36,6 @@
 
 #define QLA_VERSION_MAJOR 	3
 #define QLA_VERSION_MINOR	10
-#define QLA_VERSION_BUILD       25
+#define QLA_VERSION_BUILD       26
 
 #endif /* #ifndef _QL_VER_H_ */

From c2c3ad006ac12e752c7e8691b95ffaedaf325ac1 Mon Sep 17 00:00:00 2001
From: luigi <luigi@FreeBSD.org>
Date: Tue, 26 Jan 2016 22:45:05 +0000
Subject: [PATCH 046/113] avoid warnings for signed/unsigned comparison and
 unused arguments

---
 sys/netpfil/ipfw/dn_heap.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/sys/netpfil/ipfw/dn_heap.c b/sys/netpfil/ipfw/dn_heap.c
index 42431b00a72c..b533d6d7982d 100644
--- a/sys/netpfil/ipfw/dn_heap.c
+++ b/sys/netpfil/ipfw/dn_heap.c
@@ -81,7 +81,7 @@ heap_resize(struct dn_heap *h, unsigned int new_size)
 {
 	struct dn_heap_entry *p;
 
-	if (h->size >= new_size )	/* have enough room */
+	if ((unsigned int)h->size >= new_size )	/* have enough room */
 		return 0;
 #if 1  /* round to the next power of 2 */
 	new_size |= new_size >> 1;
@@ -419,6 +419,8 @@ dn_ht_init(struct dn_ht *ht, int buckets, int ofs,
 static int
 do_del(void *obj, void *arg)
 {
+	(void)obj;
+	(void)arg;
 	return DNHT_SCAN_DEL;
 }
 

From 3043ee5984d99c40baf7dd38bf39ffdf2495bf47 Mon Sep 17 00:00:00 2001
From: luigi <luigi@FreeBSD.org>
Date: Tue, 26 Jan 2016 22:45:45 +0000
Subject: [PATCH 047/113] prevent warning for unused argument

---
 sys/netpfil/ipfw/dn_sched_fifo.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sys/netpfil/ipfw/dn_sched_fifo.c b/sys/netpfil/ipfw/dn_sched_fifo.c
index e2aa60826eb8..e3e0cfe04330 100644
--- a/sys/netpfil/ipfw/dn_sched_fifo.c
+++ b/sys/netpfil/ipfw/dn_sched_fifo.c
@@ -61,6 +61,7 @@ fifo_enqueue(struct dn_sch_inst *si, struct dn_queue *q, struct mbuf *m)
 	 * re-enqueue from an existing scheduler, which we should
 	 * handle.
 	 */
+	(void)q;
 	return dn_enqueue((struct dn_queue *)(si+1), m, 0);
 }
 

From 17af12dfee178c781ceb88ace4ccddb8595478bb Mon Sep 17 00:00:00 2001
From: luigi <luigi@FreeBSD.org>
Date: Tue, 26 Jan 2016 22:46:58 +0000
Subject: [PATCH 048/113] prevent warnings for signed/unsigned comparisons and
 unused arguments. Add checks for parameters overflowing 32 bit.

---
 sys/netpfil/ipfw/dn_sched_rr.c | 20 ++++++++++++++------
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/sys/netpfil/ipfw/dn_sched_rr.c b/sys/netpfil/ipfw/dn_sched_rr.c
index dd608d7fbd48..63e525a2b7a0 100644
--- a/sys/netpfil/ipfw/dn_sched_rr.c
+++ b/sys/netpfil/ipfw/dn_sched_rr.c
@@ -52,8 +52,8 @@
 struct rr_queue {
 	struct dn_queue q;		/* Standard queue */
 	int status;			/* 1: queue is in the list */
-	int credit;			/* Number of bytes to transmit */
-	int quantum;			/* quantum * C */
+	uint32_t credit;		/* max bytes we can transmit */
+	uint32_t quantum;		/* quantum * weight */
 	struct rr_queue *qnext;		/* */
 };
 
@@ -61,9 +61,9 @@ struct rr_queue {
  * and is right after dn_schk
  */
 struct rr_schk {
-	int min_q;		/* Min quantum */
-	int max_q;		/* Max quantum */
-	int q_bytes;		/* Bytes per quantum */
+	uint32_t min_q;		/* Min quantum */
+	uint32_t max_q;		/* Max quantum */
+	uint32_t q_bytes;	/* default quantum in bytes */
 };
 
 /* per-instance round robin list, right after dn_sch_inst */
@@ -227,6 +227,7 @@ rr_new_sched(struct dn_sch_inst *_si)
 static int
 rr_free_sched(struct dn_sch_inst *_si)
 {
+	(void)_si;
 	ND("called");
 	/* Nothing to do? */
 	return 0;
@@ -237,6 +238,7 @@ rr_new_fsk(struct dn_fsk *fs)
 {
 	struct rr_schk *schk = (struct rr_schk *)(fs->sched + 1);
 	/* par[0] is the weight, par[1] is the quantum step */
+	/* make sure the product fits an uint32_t */
 	ipdn_bound_var(&fs->fs.par[0], 1,
 		1, 65536, "RR weight");
 	ipdn_bound_var(&fs->fs.par[1], schk->q_bytes,
@@ -248,10 +250,16 @@ static int
 rr_new_queue(struct dn_queue *_q)
 {
 	struct rr_queue *q = (struct rr_queue *)_q;
+	uint64_t quantum;
 
 	_q->ni.oid.subtype = DN_SCHED_RR;
 
-	q->quantum = _q->fs->fs.par[0] * _q->fs->fs.par[1];
+	quantum = (uint64_t)_q->fs->fs.par[0] * _q->fs->fs.par[1];
+	if (quantum >= (1ULL<< 32)) {
+		D("quantum too large, truncating to 4G - 1");
+		quantum = (1ULL<< 32) - 1;
+	}
+	q->quantum = quantum;
 	ND("called, q->quantum %d", q->quantum);
 	q->credit = q->quantum;
 	q->status = 0;

From 5e7533603b9c96251039bf574fbaff037ebb2d8b Mon Sep 17 00:00:00 2001
From: luigi <luigi@FreeBSD.org>
Date: Tue, 26 Jan 2016 23:36:18 +0000
Subject: [PATCH 049/113] fix various warnings (signed/unsigned, printf types,
 unused arguments)

---
 sys/netpfil/ipfw/dn_sched_qfq.c | 29 ++++++++++++++++-------------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/sys/netpfil/ipfw/dn_sched_qfq.c b/sys/netpfil/ipfw/dn_sched_qfq.c
index b5f4bbad3bbb..02e2d8e5a2bd 100644
--- a/sys/netpfil/ipfw/dn_sched_qfq.c
+++ b/sys/netpfil/ipfw/dn_sched_qfq.c
@@ -48,6 +48,7 @@
 #endif
 
 #ifdef QFQ_DEBUG
+#define _P64	unsigned long long	/* cast for printing uint64_t */
 struct qfq_sched;
 static void dump_sched(struct qfq_sched *q, const char *msg);
 #define	NO(x)	x
@@ -84,19 +85,19 @@ static inline unsigned long __fls(unsigned long word)
 
 #if !defined(_KERNEL) || !defined(__linux__)
 #ifdef QFQ_DEBUG
-int test_bit(int ix, bitmap *p)
+static int test_bit(int ix, bitmap *p)
 {
 	if (ix < 0 || ix > 31)
 		D("bad index %d", ix);
 	return *p & (1<<ix);
 }
-void __set_bit(int ix, bitmap *p)
+static void __set_bit(int ix, bitmap *p)
 {
 	if (ix < 0 || ix > 31)
 		D("bad index %d", ix);
 	*p |= (1<<ix);
 }
-void __clear_bit(int ix, bitmap *p)
+static void __clear_bit(int ix, bitmap *p)
 {
 	if (ix < 0 || ix > 31)
 		D("bad index %d", ix);
@@ -230,9 +231,9 @@ struct qfq_sched {
 	uint64_t	V;		/* Precise virtual time. */
 	uint32_t	wsum;		/* weight sum */
 	uint32_t	iwsum;		/* inverse weight sum */
-	NO(uint32_t	i_wsum;		/* ONE_FP/w_sum */
-	uint32_t	_queued;	/* debugging */
-	uint32_t	loops;	/* debugging */)
+	NO(uint32_t	i_wsum;)	/* ONE_FP/w_sum */
+	NO(uint32_t	queued;)	/* debugging */
+	NO(uint32_t	loops;)		/* debugging */
 	bitmap bitmaps[QFQ_MAX_STATE];	/* Group bitmaps. */
 	struct qfq_group groups[QFQ_MAX_INDEX + 1]; /* The groups. */
 };
@@ -486,6 +487,7 @@ qfq_slot_rotate(struct qfq_sched *q, struct qfq_group *grp, uint64_t roundedS)
 {
 	unsigned int i = (grp->S - roundedS) >> grp->slot_shift;
 
+	(void)q;
 	grp->full_slots <<= i;
 	grp->front = (grp->front - i) % QFQ_MAX_SLOTS;
 }
@@ -516,6 +518,7 @@ qfq_update_class(struct qfq_sched *q, struct qfq_group *grp,
 	    struct qfq_class *cl)
 {
 
+	(void)q;
 	cl->S = cl->F;
 	if (cl->_q.mq.head == NULL)  {
 		qfq_front_slot_remove(grp);
@@ -853,9 +856,9 @@ dump_groups(struct qfq_sched *q, uint32_t mask)
 			if (g->slots[j])
 				D("    bucket %d %p", j, g->slots[j]);
 		}
-		D("full_slots 0x%x", g->full_slots);
+		D("full_slots 0x%llx", (_P64)g->full_slots);
 		D("        %2d S 0x%20llx F 0x%llx %c", i,
-			g->S, g->F,
+			(_P64)g->S, (_P64)g->F,
 			mask & (1<<i) ? '1' : '0');
 	}
 }
@@ -864,11 +867,11 @@ static void
 dump_sched(struct qfq_sched *q, const char *msg)
 {
 	D("--- in %s: ---", msg);
-	ND("loops %d queued %d V 0x%llx", q->loops, q->queued, q->V);
-	D("    ER 0x%08x", q->bitmaps[ER]);
-	D("    EB 0x%08x", q->bitmaps[EB]);
-	D("    IR 0x%08x", q->bitmaps[IR]);
-	D("    IB 0x%08x", q->bitmaps[IB]);
+	D("loops %d queued %d V 0x%llx", q->loops, q->queued, (_P64)q->V);
+	D("    ER 0x%08x", (unsigned)q->bitmaps[ER]);
+	D("    EB 0x%08x", (unsigned)q->bitmaps[EB]);
+	D("    IR 0x%08x", (unsigned)q->bitmaps[IR]);
+	D("    IB 0x%08x", (unsigned)q->bitmaps[IB]);
 	dump_groups(q, 0xffffffff);
 };
 #endif /* QFQ_DEBUG */

From 156e03004c23e540f5680a1ae0c57e55cc26cf05 Mon Sep 17 00:00:00 2001
From: luigi <luigi@FreeBSD.org>
Date: Tue, 26 Jan 2016 23:37:07 +0000
Subject: [PATCH 050/113] fix various warnings to compile the test code with
 -Wextra

---
 sys/netpfil/ipfw/test/Makefile        | 2 +-
 sys/netpfil/ipfw/test/main.c          | 4 ++--
 sys/netpfil/ipfw/test/test_dn_sched.c | 6 ++++++
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/sys/netpfil/ipfw/test/Makefile b/sys/netpfil/ipfw/test/Makefile
index c556a4bf3d51..529306e495ab 100644
--- a/sys/netpfil/ipfw/test/Makefile
+++ b/sys/netpfil/ipfw/test/Makefile
@@ -20,7 +20,7 @@ HEAP_OBJS=$(HEAP_SRCS:.c=.o)
 
 VPATH=	.:..
 
-CFLAGS = -I.. -I. -Wall -Werror -O3 -DIPFW
+CFLAGS = -I.. -I. -Wall -Werror -O3 -DIPFW -Wextra
 TARGETS= test_sched # no test_heap by default
 
 all:	$(TARGETS)
diff --git a/sys/netpfil/ipfw/test/main.c b/sys/netpfil/ipfw/test/main.c
index ce86f49615e7..0dd575c94d3c 100644
--- a/sys/netpfil/ipfw/test/main.c
+++ b/sys/netpfil/ipfw/test/main.c
@@ -594,9 +594,9 @@ controller(struct cfg_s *c)
 	int flow_id;
 
 	/* histeresis between max and min */
-	if (c->state == 0 && c->pending >= c->th_max)
+	if (c->state == 0 && c->pending >= (uint32_t)c->th_max)
 		c->state = 1;
-	else if (c->state == 1 && c->pending <= c->th_min)
+	else if (c->state == 1 && c->pending <= (uint32_t)c->th_min)
 		c->state = 0;
 	ND(1, "state %d pending %2d", c->state, c->pending);
 	c->can_dequeue = c->state;
diff --git a/sys/netpfil/ipfw/test/test_dn_sched.c b/sys/netpfil/ipfw/test/test_dn_sched.c
index ee46c95ed868..2fcc310b2f63 100644
--- a/sys/netpfil/ipfw/test/test_dn_sched.c
+++ b/sys/netpfil/ipfw/test/test_dn_sched.c
@@ -15,6 +15,9 @@ m_freem(struct mbuf *m)
 int
 dn_sched_modevent(module_t mod, int cmd, void *arg)
 {
+	(void)mod;
+	(void)cmd;
+	(void)arg;
 	return 0;
 }
 
@@ -32,6 +35,8 @@ int
 dn_delete_queue(void *_q, void *do_free)
 {
 	struct dn_queue *q = _q;
+
+	(void)do_free;
         if (q->mq.head)
                 dn_free_pkts(q->mq.head);
         free(q);
@@ -66,6 +71,7 @@ dn_enqueue(struct dn_queue *q, struct mbuf* m, int drop)
 int
 ipdn_bound_var(int *v, int dflt, int lo, int hi, const char *msg)
 {
+	(void)msg;
         if (*v < lo) {
                 *v = dflt;
         } else if (*v > hi) {

From 2bb5907f9e92cdeab69dee43a47aabe94d109f03 Mon Sep 17 00:00:00 2001
From: dteske <dteske@FreeBSD.org>
Date: Tue, 26 Jan 2016 23:56:27 +0000
Subject: [PATCH 051/113] Add keep_tite configuration option

Similar to dialog(3) keep_tite option used to prevent visually disturbing
initialization or exit that could occur when run from a script using
dpv(3) by way of dpv(1) in sequence with other dialog(1) invocations.
---
 lib/libdpv/dpv.3         | 5 +++--
 lib/libdpv/dpv.c         | 5 ++++-
 lib/libdpv/dpv.h         | 1 +
 lib/libdpv/dpv_private.h | 1 +
 sys/sys/param.h          | 2 +-
 5 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/lib/libdpv/dpv.3 b/lib/libdpv/dpv.3
index 8581279e1dc6..011ab8208d14 100644
--- a/lib/libdpv/dpv.3
+++ b/lib/libdpv/dpv.3
@@ -1,4 +1,4 @@
-.\" Copyright (c) 2013-2015 Devin Teske
+.\" Copyright (c) 2013-2016 Devin Teske
 .\" All rights reserved.
 .\"
 .\" Redistribution and use in source and binary forms, with or without
@@ -24,7 +24,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd Oct 22, 2015
+.Dd Jan 26, 2016
 .Dt DPV 3
 .Os
 .Sh NAME
@@ -64,6 +64,7 @@ argument contains the following properties for configuring global display
 features:
 .Bd -literal -offset indent
 struct dpv_config {
+    uint8_t          keep_tite;     /* Cleaner exit for scripts */
     enum dpv_display display_type;  /* Def. DPV_DISPLAY_LIBDIALOG */
     enum dpv_output  output_type;   /* Default DPV_OUTPUT_NONE */
     int              debug;         /* Enable debug on stderr */
diff --git a/lib/libdpv/dpv.c b/lib/libdpv/dpv.c
index d3506ca9d82d..edf75bd1dfe7 100644
--- a/lib/libdpv/dpv.c
+++ b/lib/libdpv/dpv.c
@@ -69,6 +69,7 @@ long long dpv_overall_read = 0;
 static char pathbuf[PATH_MAX];
 
 /* Extra display information */
+uint8_t keep_tite = FALSE;	/* dpv_config.keep_tite */
 uint8_t no_labels = FALSE;	/* dpv_config.options & DPV_NO_LABELS */
 uint8_t wide = FALSE;		/* dpv_config.options & DPV_WIDE_MODE */
 char *aprompt = NULL;		/* dpv_config.aprompt */
@@ -150,6 +151,7 @@ dpv(struct dpv_config *config, struct dpv_file_node *file_list)
 	dialog_updates_per_second = DIALOG_UPDATES_PER_SEC;
 	display_limit	= DISPLAY_LIMIT_DEFAULT;
 	display_type	= DPV_DISPLAY_LIBDIALOG;
+	keep_tite	= FALSE;
 	label_size	= LABEL_SIZE_DEFAULT;
 	msg_done	= NULL;
 	msg_fail	= NULL;
@@ -193,6 +195,7 @@ dpv(struct dpv_config *config, struct dpv_file_node *file_list)
 		dialog_updates_per_second = config->dialog_updates_per_second;
 		display_limit	= config->display_limit;
 		display_type	= config->display_type;
+		keep_tite	= config->keep_tite;
 		label_size	= config->label_size;
 		msg_done	= (char *)config->msg_done;
 		msg_fail	= (char *)config->msg_fail;
@@ -695,7 +698,7 @@ dpv(struct dpv_config *config, struct dpv_file_node *file_list)
 			close(dialog_out);
 			waitpid(pid, (int *)NULL, 0);	
 		}
-		if (!dpv_interrupt)
+		if (!keep_tite && !dpv_interrupt)
 			printf("\n");
 	} else
 		warnx("%s: %lli overall read", __func__, dpv_overall_read);
diff --git a/lib/libdpv/dpv.h b/lib/libdpv/dpv.h
index 03768a7ced40..67d7bc11e9a8 100644
--- a/lib/libdpv/dpv.h
+++ b/lib/libdpv/dpv.h
@@ -97,6 +97,7 @@ struct dpv_file_node {
  * Anatomy of config option to pass as dpv() config argument
  */
 struct dpv_config {
+	uint8_t	keep_tite;		/* Prevent visually distracting exit */
 	enum dpv_display display_type;	/* Display (default TYPE_LIBDIALOG) */
 	enum dpv_output  output_type;	/* Output (default TYPE_NONE) */
 	int	debug;			/* Enable debugging output on stderr */
diff --git a/lib/libdpv/dpv_private.h b/lib/libdpv/dpv_private.h
index 5164eb321ed2..1bebba643f18 100644
--- a/lib/libdpv/dpv_private.h
+++ b/lib/libdpv/dpv_private.h
@@ -38,6 +38,7 @@ extern uint8_t debug;
 extern unsigned int dpv_nfiles;
 
 /* Extra display information */
+extern uint8_t keep_tite;
 extern uint8_t no_labels;
 extern uint8_t wide;
 extern char *msg_done, *msg_fail, *msg_pending;
diff --git a/sys/sys/param.h b/sys/sys/param.h
index 7c03f3374d4c..c383c432e43f 100644
--- a/sys/sys/param.h
+++ b/sys/sys/param.h
@@ -58,7 +58,7 @@
  *		in the range 5 to 9.
  */
 #undef __FreeBSD_version
-#define __FreeBSD_version 1100096	/* Master, propagated to newvers */
+#define __FreeBSD_version 1100097	/* Master, propagated to newvers */
 
 /*
  * __FreeBSD_kernel__ indicates that this system uses the kernel of FreeBSD,

From d08ad3f736078451711e1347dabd1d64e255b033 Mon Sep 17 00:00:00 2001
From: dteske <dteske@FreeBSD.org>
Date: Tue, 26 Jan 2016 23:59:30 +0000
Subject: [PATCH 052/113] Add `-k' for dpv(3) `keep_tite' config option

For scripts using dialog(1) several times, it can be visually distracting
running dpv(1) several times amidst other dialogs. The `-k' option, similar
to dialog(1) `--keep-tite', enables the same functionality to smooth ti/te.
---
 usr.bin/dpv/dpv.1 | 9 +++++++--
 usr.bin/dpv/dpv.c | 8 ++++++--
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/usr.bin/dpv/dpv.1 b/usr.bin/dpv/dpv.1
index 5a64af934404..6af3752cb02a 100644
--- a/usr.bin/dpv/dpv.1
+++ b/usr.bin/dpv/dpv.1
@@ -1,4 +1,4 @@
-.\" Copyright (c) 2013-2015 Devin Teske
+.\" Copyright (c) 2013-2016 Devin Teske
 .\" All rights reserved.
 .\"
 .\" Redistribution and use in source and binary forms, with or without
@@ -24,7 +24,7 @@
 .\"
 .\" $FreeBSD$
 .\"
-.Dd Oct 22, 2015
+.Dd Jan 26, 2016
 .Dt DPV 1
 .Os
 .Sh NAME
@@ -138,6 +138,11 @@ Default value
 is
 .Dq Li %'10lli bytes read @ %'9.1f bytes/sec. [%i/%i busy/wait] .
 This format is used when handling more than one file.
+.It Fl k
+Keep tite.
+Prevent visually distracting initialization/exit routines for scripts running
+.Xr dialog 1
+several times.
 .It Fl l
 Line mode. Read lines from input instead of bytes.
 .It Fl L Ar size
diff --git a/usr.bin/dpv/dpv.c b/usr.bin/dpv/dpv.c
index 4e006f6c12d5..2bab727ed0cc 100644
--- a/usr.bin/dpv/dpv.c
+++ b/usr.bin/dpv/dpv.c
@@ -271,7 +271,7 @@ main(int argc, char *argv[])
 	 * Process command-line options
 	 */
 	while ((ch = getopt(argc, argv,
-	    "a:b:dDhi:I:lL:mn:No:p:P:t:TU:wx:X")) != -1) {
+	    "a:b:dDhi:I:klL:mn:No:p:P:t:TU:wx:X")) != -1) {
 		switch(ch) {
 		case 'a': /* additional message text to append */
 			if (config->aprompt == NULL) {
@@ -307,6 +307,9 @@ main(int argc, char *argv[])
 		case 'I': /* status line format string for many-files */
 			config->status_many = optarg;
 			break;
+		case 'k': /* keep tite */
+			config->keep_tite = TRUE;
+			break;
 		case 'l': /* Line mode */
 			line_mode = TRUE;
 			break;
@@ -467,7 +470,8 @@ main(int argc, char *argv[])
 	if (dpv(config, file_list) != 0 && debug)
 		warnx("dpv(3) returned error!?");
 
-	end_dialog();
+	if (!config->keep_tite)
+		end_dialog();
 	dpv_free();
 
 	exit(EXIT_SUCCESS);

From 0967d3b5ae954ee4cb64b3f09f60aff80ec5a733 Mon Sep 17 00:00:00 2001
From: dteske <dteske@FreeBSD.org>
Date: Wed, 27 Jan 2016 00:02:51 +0000
Subject: [PATCH 053/113] Bump copyrights

---
 lib/libdpv/dpv.c         | 2 +-
 lib/libdpv/dpv.h         | 2 +-
 lib/libdpv/dpv_private.h | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/lib/libdpv/dpv.c b/lib/libdpv/dpv.c
index edf75bd1dfe7..8ac39b10f86c 100644
--- a/lib/libdpv/dpv.c
+++ b/lib/libdpv/dpv.c
@@ -1,5 +1,5 @@
 /*-
- * Copyright (c) 2013-2014 Devin Teske <dteske@FreeBSD.org>
+ * Copyright (c) 2013-2016 Devin Teske <dteske@FreeBSD.org>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/lib/libdpv/dpv.h b/lib/libdpv/dpv.h
index 67d7bc11e9a8..a79962b3a624 100644
--- a/lib/libdpv/dpv.h
+++ b/lib/libdpv/dpv.h
@@ -1,5 +1,5 @@
 /*-
- * Copyright (c) 2013-2014 Devin Teske <dteske@FreeBSD.org>
+ * Copyright (c) 2013-2016 Devin Teske <dteske@FreeBSD.org>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/lib/libdpv/dpv_private.h b/lib/libdpv/dpv_private.h
index 1bebba643f18..fd4734c330da 100644
--- a/lib/libdpv/dpv_private.h
+++ b/lib/libdpv/dpv_private.h
@@ -1,5 +1,5 @@
 /*-
- * Copyright (c) 2013-2014 Devin Teske <dteske@FreeBSD.org>
+ * Copyright (c) 2013-2016 Devin Teske <dteske@FreeBSD.org>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without

From cd5415338986676c397649b838a9c56aadf2f8bf Mon Sep 17 00:00:00 2001
From: dteske <dteske@FreeBSD.org>
Date: Wed, 27 Jan 2016 00:03:43 +0000
Subject: [PATCH 054/113] Bump copyright

---
 usr.bin/dpv/dpv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/usr.bin/dpv/dpv.c b/usr.bin/dpv/dpv.c
index 2bab727ed0cc..440b5ab6de0f 100644
--- a/usr.bin/dpv/dpv.c
+++ b/usr.bin/dpv/dpv.c
@@ -1,5 +1,5 @@
 /*-
- * Copyright (c) 2013-2014 Devin Teske <dteske@FreeBSD.org>
+ * Copyright (c) 2013-2016 Devin Teske <dteske@FreeBSD.org>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without

From 51896ff64b61a7a87ec30d4615aa9e9a83179955 Mon Sep 17 00:00:00 2001
From: dteske <dteske@FreeBSD.org>
Date: Wed, 27 Jan 2016 00:08:23 +0000
Subject: [PATCH 055/113] Change incorrect path

---
 usr.sbin/bsdconfig/share/packages/index.subr | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/usr.sbin/bsdconfig/share/packages/index.subr b/usr.sbin/bsdconfig/share/packages/index.subr
index f3c171355ba5..4f222784fd51 100644
--- a/usr.sbin/bsdconfig/share/packages/index.subr
+++ b/usr.sbin/bsdconfig/share/packages/index.subr
@@ -1,6 +1,6 @@
 if [ ! "$_PACKAGES_INDEX_SUBR" ]; then _PACKAGES_INDEX_SUBR=1
 #
-# Copyright (c) 2013 Devin Teske
+# Copyright (c) 2013-2016 Devin Teske
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -47,7 +47,7 @@ _INDEX_INITTED=
 #
 # Default path to pkg(8) repo-packagesite.sqlite database
 #
-SQLITE_REPO="/var/db/pkg/repo-packagesite.sqlite"
+SQLITE_REPO="/var/db/pkg/repo-FreeBSD.sqlite"
 
 #
 # Default path to on-disk cache INDEX file

From ebabb0bf02ef0ad6a3725ca2d8250f678285d943 Mon Sep 17 00:00:00 2001
From: dteske <dteske@FreeBSD.org>
Date: Wed, 27 Jan 2016 00:09:53 +0000
Subject: [PATCH 056/113] Fix ABI parsing

---
 usr.sbin/bsdconfig/share/packages/musthavepkg.subr | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/usr.sbin/bsdconfig/share/packages/musthavepkg.subr b/usr.sbin/bsdconfig/share/packages/musthavepkg.subr
index 929823e4f21e..b336d26d9c2e 100644
--- a/usr.sbin/bsdconfig/share/packages/musthavepkg.subr
+++ b/usr.sbin/bsdconfig/share/packages/musthavepkg.subr
@@ -1,6 +1,6 @@
 if [ ! "$_PACKAGES_MUSTHAVEPKG_SUBR" ]; then _PACKAGES_MUSTHAVEPKG_SUBR=1
 #
-# Copyright (c) 2014 Devin Teske
+# Copyright (c) 2014-2016 Devin Teske
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -45,7 +45,11 @@ f_include $BSDCFG_SHARE/mustberoot.subr
 f_musthavepkg_init()
 {
 	local funcname=f_musthavepkg_init
-	local pkg_abi_awk='$1~/^ABI/{print $NF; exit}'
+	local pkg_abi_awk=' # BEGIN-AWK
+		$1 ~ /^ABI/ && $0 = $NF, sub(/^"/, "") && sub(/".*/, "") {
+			print; found = 1; exit
+		} END { exit ! found }
+	' # END-AWK
 
 	if [ "$PKG_ABI" ]; then # Already set
 		f_dprintf "PKG_ABI=[%s]" "$PKG_ABI"

From 2e623b340f634c5363b749d9a07efcf5c1c59163 Mon Sep 17 00:00:00 2001
From: dteske <dteske@FreeBSD.org>
Date: Wed, 27 Jan 2016 00:12:58 +0000
Subject: [PATCH 057/113] Use dpv(1) in `bsdconfig packages'

---
 usr.sbin/bsdconfig/include/messages.subr        |  5 +++--
 usr.sbin/bsdconfig/share/packages/index.subr    | 14 ++++++++------
 usr.sbin/bsdconfig/share/packages/packages.subr |  4 +++-
 3 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/usr.sbin/bsdconfig/include/messages.subr b/usr.sbin/bsdconfig/include/messages.subr
index 04f44854f5ea..66b1ba1c447f 100644
--- a/usr.sbin/bsdconfig/include/messages.subr
+++ b/usr.sbin/bsdconfig/include/messages.subr
@@ -1,5 +1,5 @@
 # Copyright (c) 2012 Ron McDowell
-# Copyright (c) 2012-2013 Devin Teske
+# Copyright (c) 2012-2016 Devin Teske
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -60,6 +60,7 @@ msg_biology_desc="Software related to biology."
 msg_bootstrapping_pkg="Bootstrapping pkg(8)..."
 msg_brazil="Brazil"
 msg_building_package_menus="Building package menu(s)..."
+msg_building_package_main_menu="Building package main menu..."
 msg_cad_desc="Computer Aided Design utilities."
 msg_canada="Canada"
 msg_cancel="Cancel"
@@ -201,7 +202,6 @@ msg_linux_desc="Linux programs that can run under binary compatibility."
 msg_lisp_desc="Software related to the Lisp language."
 msg_lithuania="Lithuania"
 msg_loading_of_dependent_package_failed="Loading of dependent package %s failed"
-msg_located_index_now_reading_package_data_from_it="Located INDEX, now reading package data from it..."
 msg_logging_in_to_user_at_host="Logging in to %s@%s.."
 msg_looking_for_keymap_files="Looking for keymap files..."
 msg_looking_up_host="Looking up host %s"
@@ -313,6 +313,7 @@ msg_proceed="Proceed"
 msg_processing_selection="Processing selection..."
 msg_python_desc="Software related to the Python language."
 msg_quick_start_how_to_use_this_menu_system="Quick start - How to use this menu system"
+msg_reading_package_index_data="Reading package index data"
 msg_reinstall="Reinstall"
 msg_reinstall_desc="Mark this package for reinstall"
 msg_release_name="Release Name"
diff --git a/usr.sbin/bsdconfig/share/packages/index.subr b/usr.sbin/bsdconfig/share/packages/index.subr
index 4f222784fd51..de81656f73fb 100644
--- a/usr.sbin/bsdconfig/share/packages/index.subr
+++ b/usr.sbin/bsdconfig/share/packages/index.subr
@@ -162,8 +162,6 @@ f_index_initialize()
 				fi
 			) < "$PACKAGES_INDEX_CACHEFILE" 2> /dev/null
 		)'; then
-			f_show_info \
-			  "$msg_located_index_now_reading_package_data_from_it"
 			if ! f_index_read "$__var_to_set"; then
 				f_show_err \
 					"$msg_io_or_format_error_on_index_file"
@@ -179,8 +177,11 @@ f_index_initialize()
 	# If we reach this point, we need to generate the data from scratch
 	#
 
-	f_show_info "$msg_generating_index_from_pkg_database"
-	eval "$__var_to_set"='$( pkg rquery -I | sort )'
+	eval "$__var_to_set"='$( pkg rquery -I | (
+		exec 2<&1; dpv -ko /dev/stderr >&$TERMINAL_STDOUT_PASSTHRU \
+			-b "$DIALOG_BACKTITLE" \
+			-- "$msg_generating_index_from_pkg_database"
+	) | sort )'
 
 	#
 	# Attempt to create the persistant on-disk cache
@@ -204,7 +205,6 @@ f_index_initialize()
 			"$__tmpfile" "$PACKAGES_INDEX_CACHEFILE"
 	fi
 
-	f_show_info "$msg_located_index_now_reading_package_data_from_it"
 	if ! f_index_read "$__var_to_set"; then
 		f_show_err "$msg_io_or_format_error_on_index_file"
 		return $FAILURE
@@ -329,7 +329,9 @@ f_index_read()
 		sub(/^ /, "", category_list)
 		print "PACKAGE_CATEGORIES=\"" category_list "\""
 
-	}' )" # End-Quote
+	}' | ( exec 2<&1; dpv -ko /dev/stderr >&$TERMINAL_STDOUT_PASSTHRU \
+		-b "$DIALOG_BACKTITLE" -- "$msg_reading_package_index_data"
+	) )" # End-Quote
 }
 
 # f_index_extract_pages $var_to_get $var_basename $pagesize [$category]
diff --git a/usr.sbin/bsdconfig/share/packages/packages.subr b/usr.sbin/bsdconfig/share/packages/packages.subr
index f3ec70773878..37801856ff28 100644
--- a/usr.sbin/bsdconfig/share/packages/packages.subr
+++ b/usr.sbin/bsdconfig/share/packages/packages.subr
@@ -1,6 +1,6 @@
 if [ ! "$_PACKAGES_PACKAGES_SUBR" ]; then _PACKAGES_PACKAGES_SUBR=1
 #
-# Copyright (c) 2013 Devin Teske
+# Copyright (c) 2013-2016 Devin Teske
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -668,6 +668,8 @@ f_package_config()
 		#   CATEGORY_MENU_LIST _categories_{varpkg} _rundeps_{varpkg}
 		#   PACKAGE_CATEGORIES _npkgs
 
+	f_show_info "$msg_building_package_main_menu"
+
 	# Detect installed packages (updates marks/SELECTED_PACKAGES)
 	f_package_detect_installed
 	export PACKAGES_DETECTED=1 # exported for awk(1) ENVIRON[]

From 2f1de40ae4b267274d3f5ed990e642f42a26b013 Mon Sep 17 00:00:00 2001
From: glebius <glebius@FreeBSD.org>
Date: Wed, 27 Jan 2016 00:20:07 +0000
Subject: [PATCH 058/113] Provide TCPSTAT_DEC() and TCPSTAT_FETCH() macros.

---
 sys/net/vnet.h        | 3 +++
 sys/netinet/tcp_var.h | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/sys/net/vnet.h b/sys/net/vnet.h
index 7b43f83b96ec..75bb728bc17c 100644
--- a/sys/net/vnet.h
+++ b/sys/net/vnet.h
@@ -101,6 +101,9 @@ struct vnet {
 #define	VNET_PCPUSTAT_ADD(type, name, f, v)	\
     counter_u64_add(VNET(name)[offsetof(type, f) / sizeof(uint64_t)], (v))
 
+#define	VNET_PCPUSTAT_FETCH(type, name, f)	\
+    counter_u64_fetch(VNET(name)[offsetof(type, f) / sizeof(uint64_t)])
+
 #define	VNET_PCPUSTAT_SYSINIT(name)	\
 static void				\
 vnet_##name##_init(const void *unused)	\
diff --git a/sys/netinet/tcp_var.h b/sys/netinet/tcp_var.h
index 6cd4cf05874a..4712c6b2d51d 100644
--- a/sys/netinet/tcp_var.h
+++ b/sys/netinet/tcp_var.h
@@ -605,6 +605,9 @@ VNET_PCPUSTAT_DECLARE(struct tcpstat, tcpstat);	/* tcp statistics */
 #define	TCPSTAT_ADD(name, val)	\
     VNET_PCPUSTAT_ADD(struct tcpstat, tcpstat, name, (val))
 #define	TCPSTAT_INC(name)	TCPSTAT_ADD(name, 1)
+#define	TCPSTAT_DEC(name)	TCPSTAT_ADD(name, -1)
+#define	TCPSTAT_FETCH(name)	VNET_PCPUSTAT_FETCH(struct tcpstat, tcpstat, \
+				    name)
 
 /*
  * Kernel module consumers must use this accessor macro.

From 1a12f8d9a17a94b40aad848fb3fa61b3f0eb1acf Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 00:24:24 +0000
Subject: [PATCH 059/113] Remove excess whitespace

---
 lib/libc/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/libc/Makefile b/lib/libc/Makefile
index a48b3e5ca881..707fc1a46a18 100644
--- a/lib/libc/Makefile
+++ b/lib/libc/Makefile
@@ -173,7 +173,7 @@ CFLAGS+= -I${SRCTOP}/lib/libutil
 # Same issue with libm
 MSUN_ARCH_SUBDIR != ${MAKE} -B -C ${SRCTOP}/lib/msun -V ARCH_SUBDIR
 # unfortunately msun/src contains both private and public headers
-CFLAGS+= -I${SRCTOP}/lib/msun/${MSUN_ARCH_SUBDIR} 
+CFLAGS+= -I${SRCTOP}/lib/msun/${MSUN_ARCH_SUBDIR}
 .if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64"
 CFLAGS+= -I${SRCTOP}/lib/msun/x86
 .endif

From 9487eaf98f45a433931bad91a3463694f5423688 Mon Sep 17 00:00:00 2001
From: glebius <glebius@FreeBSD.org>
Date: Wed, 27 Jan 2016 00:45:46 +0000
Subject: [PATCH 060/113] Augment struct tcpstat with tcps_states[], which is
 used for book-keeping the amount of TCP connections by state.  Provides a
 cheap way to get connection count without traversing the whole pcb list.

Sponsored by:	Netflix
---
 sys/dev/cxgbe/tom/t4_cpl_io.c |  2 +-
 sys/netinet/tcp_offload.c     |  2 +-
 sys/netinet/tcp_subr.c        |  3 +++
 sys/netinet/tcp_syncache.c    | 13 ++++++++++++-
 sys/netinet/tcp_timewait.c    |  1 +
 sys/netinet/tcp_usrreq.c      |  1 +
 sys/netinet/tcp_var.h         |  4 ++++
 usr.bin/systat/netstat.c      |  2 +-
 8 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/sys/dev/cxgbe/tom/t4_cpl_io.c b/sys/dev/cxgbe/tom/t4_cpl_io.c
index f18f115c3202..43e4d611cf7e 100644
--- a/sys/dev/cxgbe/tom/t4_cpl_io.c
+++ b/sys/dev/cxgbe/tom/t4_cpl_io.c
@@ -45,10 +45,10 @@ __FBSDID("$FreeBSD$");
 #include <netinet/in_pcb.h>
 #include <netinet/ip.h>
 #include <netinet/ip6.h>
-#include <netinet/tcp_var.h>
 #define TCPSTATES
 #include <netinet/tcp_fsm.h>
 #include <netinet/tcp_seq.h>
+#include <netinet/tcp_var.h>
 #include <netinet/toecore.h>
 
 #include "common/common.h"
diff --git a/sys/netinet/tcp_offload.c b/sys/netinet/tcp_offload.c
index 683e2121c170..60fd7e9761c2 100644
--- a/sys/netinet/tcp_offload.c
+++ b/sys/netinet/tcp_offload.c
@@ -42,10 +42,10 @@ __FBSDID("$FreeBSD$");
 #include <netinet/in.h>
 #include <netinet/in_pcb.h>
 #include <netinet/tcp.h>
-#include <netinet/tcp_var.h>
 #include <netinet/tcp_offload.h>
 #define	TCPOUTFLAGS
 #include <netinet/tcp_fsm.h>
+#include <netinet/tcp_var.h>
 #include <netinet/toecore.h>
 
 int registered_toedevs;
diff --git a/sys/netinet/tcp_subr.c b/sys/netinet/tcp_subr.c
index 6358e8173283..b16f54009aab 100644
--- a/sys/netinet/tcp_subr.c
+++ b/sys/netinet/tcp_subr.c
@@ -1468,6 +1468,7 @@ tcp_close(struct tcpcb *tp)
 #endif
 	in_pcbdrop(inp);
 	TCPSTAT_INC(tcps_closed);
+	TCPSTAT_DEC(tcps_states[tp->t_state]);
 	KASSERT(inp->inp_socket != NULL, ("tcp_close: inp_socket NULL"));
 	so = inp->inp_socket;
 	soisdisconnected(so);
@@ -2910,6 +2911,8 @@ tcp_state_change(struct tcpcb *tp, int newstate)
 	int pstate = tp->t_state;
 #endif
 
+	TCPSTAT_DEC(tcps_states[tp->t_state]);
+	TCPSTAT_INC(tcps_states[newstate]);
 	tp->t_state = newstate;
 	TCP_PROBE6(state__change, NULL, tp, NULL, tp, NULL, pstate);
 }
diff --git a/sys/netinet/tcp_syncache.c b/sys/netinet/tcp_syncache.c
index 940d3de237ce..45e00e97083a 100644
--- a/sys/netinet/tcp_syncache.c
+++ b/sys/netinet/tcp_syncache.c
@@ -351,6 +351,7 @@ syncache_insert(struct syncache *sc, struct syncache_head *sch)
 
 	SCH_UNLOCK(sch);
 
+	TCPSTAT_INC(tcps_states[TCPS_SYN_RECEIVED]);
 	TCPSTAT_INC(tcps_sc_added);
 }
 
@@ -364,6 +365,7 @@ syncache_drop(struct syncache *sc, struct syncache_head *sch)
 
 	SCH_LOCK_ASSERT(sch);
 
+	TCPSTAT_DEC(tcps_states[TCPS_SYN_RECEIVED]);
 	TAILQ_REMOVE(&sch->sch_bucket, sc, sc_hash);
 	sch->sch_length--;
 
@@ -992,7 +994,16 @@ syncache_expand(struct in_conninfo *inc, struct tcpopt *to, struct tcphdr *th,
 			goto failed;
 		}
 	} else {
-		/* Pull out the entry to unlock the bucket row. */
+		/*
+		 * Pull out the entry to unlock the bucket row.
+		 * 
+		 * NOTE: We must decrease TCPS_SYN_RECEIVED count here, not
+		 * tcp_state_change().  The tcpcb is not existent at this
+		 * moment.  A new one will be allocated via syncache_socket->
+		 * sonewconn->tcp_usr_attach in TCPS_CLOSED state, then
+		 * syncache_socket() will change it to TCPS_SYN_RECEIVED.
+		 */
+		TCPSTAT_DEC(tcps_states[TCPS_SYN_RECEIVED]);
 		TAILQ_REMOVE(&sch->sch_bucket, sc, sc_hash);
 		sch->sch_length--;
 #ifdef TCP_OFFLOAD
diff --git a/sys/netinet/tcp_timewait.c b/sys/netinet/tcp_timewait.c
index 4685fe734f5e..c98de24f29e9 100644
--- a/sys/netinet/tcp_timewait.c
+++ b/sys/netinet/tcp_timewait.c
@@ -660,6 +660,7 @@ tcp_tw_2msl_stop(struct tcptw *tw, int reuse)
 
 	if (!reuse)
 		uma_zfree(V_tcptw_zone, tw);
+	TCPSTAT_DEC(tcps_states[TCPS_TIME_WAIT]);
 }
 
 struct tcptw *
diff --git a/sys/netinet/tcp_usrreq.c b/sys/netinet/tcp_usrreq.c
index 4b3150bad82a..0a87a6219b7b 100644
--- a/sys/netinet/tcp_usrreq.c
+++ b/sys/netinet/tcp_usrreq.c
@@ -1883,6 +1883,7 @@ tcp_attach(struct socket *so)
 	tp->t_state = TCPS_CLOSED;
 	INP_WUNLOCK(inp);
 	INP_INFO_RUNLOCK(&V_tcbinfo);
+	TCPSTAT_INC(tcps_states[TCPS_CLOSED]);
 	return (0);
 }
 
diff --git a/sys/netinet/tcp_var.h b/sys/netinet/tcp_var.h
index 4712c6b2d51d..32aa0bbf912c 100644
--- a/sys/netinet/tcp_var.h
+++ b/sys/netinet/tcp_var.h
@@ -34,6 +34,7 @@
 #define _NETINET_TCP_VAR_H_
 
 #include <netinet/tcp.h>
+#include <netinet/tcp_fsm.h>
 
 #ifdef _KERNEL
 #include <net/vnet.h>
@@ -587,6 +588,9 @@ struct	tcpstat {
 	uint64_t tcps_sig_err_sigopt;	/* No signature expected by socket */
 	uint64_t tcps_sig_err_nosigopt;	/* No signature provided by segment */
 
+	/* Running connection count. */
+	uint64_t tcps_states[TCP_NSTATES];
+
 	uint64_t _pad[12];		/* 6 UTO, 6 TBD */
 };
 
diff --git a/usr.bin/systat/netstat.c b/usr.bin/systat/netstat.c
index 3f994e8707cd..56bc34ea3021 100644
--- a/usr.bin/systat/netstat.c
+++ b/usr.bin/systat/netstat.c
@@ -59,10 +59,10 @@ static const char sccsid[] = "@(#)netstat.c	8.1 (Berkeley) 6/6/93";
 #include <netinet/tcp.h>
 #include <netinet/tcpip.h>
 #include <netinet/tcp_seq.h>
-#include <netinet/tcp_var.h>
 #define TCPSTATES
 #include <netinet/tcp_fsm.h>
 #include <netinet/tcp_timer.h>
+#include <netinet/tcp_var.h>
 #include <netinet/tcp_debug.h>
 #include <netinet/udp.h>
 #include <netinet/udp_var.h>

From ccaed9e02be515e0496ee4dc90e02aac28c3485a Mon Sep 17 00:00:00 2001
From: glebius <glebius@FreeBSD.org>
Date: Wed, 27 Jan 2016 00:48:05 +0000
Subject: [PATCH 061/113] Grab a snap amount of TCP connections in syncache
 from tcpstat.

---
 sys/netinet/tcp_subr.c     |  5 +++--
 sys/netinet/tcp_syncache.c | 19 -------------------
 sys/netinet/tcp_syncache.h |  1 -
 3 files changed, 3 insertions(+), 22 deletions(-)

diff --git a/sys/netinet/tcp_subr.c b/sys/netinet/tcp_subr.c
index b16f54009aab..0d16330bee84 100644
--- a/sys/netinet/tcp_subr.c
+++ b/sys/netinet/tcp_subr.c
@@ -1590,7 +1590,8 @@ tcp_pcblist(SYSCTL_HANDLER_ARGS)
 	 * resource-intensive to repeat twice on every request.
 	 */
 	if (req->oldptr == NULL) {
-		n = V_tcbinfo.ipi_count + syncache_pcbcount();
+		n = V_tcbinfo.ipi_count +
+		    TCPSTAT_FETCH(tcps_states[TCPS_SYN_RECEIVED]);
 		n += imax(n / 8, 10);
 		req->oldidx = 2 * (sizeof xig) + n * sizeof(struct xtcpcb);
 		return (0);
@@ -1607,7 +1608,7 @@ tcp_pcblist(SYSCTL_HANDLER_ARGS)
 	n = V_tcbinfo.ipi_count;
 	INP_LIST_RUNLOCK(&V_tcbinfo);
 
-	m = syncache_pcbcount();
+	m = TCPSTAT_FETCH(tcps_states[TCPS_SYN_RECEIVED]);
 
 	error = sysctl_wire_old_buffer(req, 2 * (sizeof xig)
 		+ (n + m) * sizeof(struct xtcpcb));
diff --git a/sys/netinet/tcp_syncache.c b/sys/netinet/tcp_syncache.c
index 45e00e97083a..0ff731833716 100644
--- a/sys/netinet/tcp_syncache.c
+++ b/sys/netinet/tcp_syncache.c
@@ -2099,25 +2099,6 @@ syncookie_reseed(void *arg)
 	callout_schedule(&sc->secret.reseed, SYNCOOKIE_LIFETIME * hz);
 }
 
-/*
- * Returns the current number of syncache entries.  This number
- * will probably change before you get around to calling 
- * syncache_pcblist.
- */
-int
-syncache_pcbcount(void)
-{
-	struct syncache_head *sch;
-	int count, i;
-
-	for (count = 0, i = 0; i < V_tcp_syncache.hashsize; i++) {
-		/* No need to lock for a read. */
-		sch = &V_tcp_syncache.hashbase[i];
-		count += sch->sch_length;
-	}
-	return count;
-}
-
 /*
  * Exports the syncache entries to userland so that netstat can display
  * them alongside the other sockets.  This function is intended to be
diff --git a/sys/netinet/tcp_syncache.h b/sys/netinet/tcp_syncache.h
index 9fcbbec6414a..6b12c13ab3b7 100644
--- a/sys/netinet/tcp_syncache.h
+++ b/sys/netinet/tcp_syncache.h
@@ -46,7 +46,6 @@ int	 syncache_add(struct in_conninfo *, struct tcpopt *,
 	     void *, void *);
 void	 syncache_chkrst(struct in_conninfo *, struct tcphdr *);
 void	 syncache_badack(struct in_conninfo *);
-int	 syncache_pcbcount(void);
 int	 syncache_pcblist(struct sysctl_req *req, int max_pcbs, int *pcbs_exported);
 
 struct syncache {

From 6c4255a1e633d69e779125ce66e6032a1abca475 Mon Sep 17 00:00:00 2001
From: glebius <glebius@FreeBSD.org>
Date: Wed, 27 Jan 2016 00:50:27 +0000
Subject: [PATCH 062/113] Grab value for LEAF_tcpCurrEstab from
 net.inet.tcp.stats instead of net.inet.tcp.pcblist, which is much cheaper.

---
 contrib/bsnmp/snmp_mibII/mibII_tcp.c | 34 ++++++++++++++++------------
 1 file changed, 20 insertions(+), 14 deletions(-)

diff --git a/contrib/bsnmp/snmp_mibII/mibII_tcp.c b/contrib/bsnmp/snmp_mibII/mibII_tcp.c
index a61052d2eb92..c798bae1fa17 100644
--- a/contrib/bsnmp/snmp_mibII/mibII_tcp.c
+++ b/contrib/bsnmp/snmp_mibII/mibII_tcp.c
@@ -45,10 +45,10 @@ struct tcp_index {
 };
 
 static uint64_t tcp_tick;
+static uint64_t tcp_stats_tick;
 static struct tcpstat tcpstat;
 static struct xinpgen *xinpgen;
 static size_t xinpgen_len;
-static u_int tcp_count;
 static u_int tcp_total;
 
 static u_int oidnum;
@@ -64,13 +64,9 @@ tcp_compare(const void *p1, const void *p2)
 }
 
 static int
-fetch_tcp(void)
+fetch_tcp_stats(void)
 {
 	size_t len;
-	struct xinpgen *ptr;
-	struct xtcpcb *tp;
-	struct tcp_index *oid;
-	in_addr_t inaddr;
 
 	len = sizeof(tcpstat);
 	if (sysctlbyname("net.inet.tcp.stats", &tcpstat, &len, NULL, 0) == -1) {
@@ -82,6 +78,20 @@ fetch_tcp(void)
 		return (-1);
 	}
 
+	tcp_stats_tick = get_ticks();
+
+	return (0);
+}
+
+static int
+fetch_tcp(void)
+{
+	size_t len;
+	struct xinpgen *ptr;
+	struct xtcpcb *tp;
+	struct tcp_index *oid;
+	in_addr_t inaddr;
+
 	len = 0;
 	if (sysctlbyname("net.inet.tcp.pcblist", NULL, &len, NULL, 0) == -1) {
 		syslog(LOG_ERR, "net.inet.tcp.pcblist: %m");
@@ -102,7 +112,6 @@ fetch_tcp(void)
 
 	tcp_tick = get_ticks();
 
-	tcp_count = 0;
 	tcp_total = 0;
 	for (ptr = (struct xinpgen *)(void *)((char *)xinpgen + xinpgen->xig_len);
 	     ptr->xig_len > sizeof(struct xinpgen);
@@ -114,10 +123,6 @@ fetch_tcp(void)
 
 		if (tp->xt_inp.inp_vflag & INP_IPV4)
 			tcp_total++;
-
-		if (tp->xt_tp.t_state == TCPS_ESTABLISHED ||
-		    tp->xt_tp.t_state == TCPS_CLOSE_WAIT)
-			tcp_count++;
 	}
 
 	if (oidnum < tcp_total) {
@@ -184,8 +189,8 @@ op_tcp(struct snmp_context *ctx __unused, struct snmp_value *value,
 		abort();
 	}
 
-	if (tcp_tick < this_tick)
-		if (fetch_tcp() == -1)
+	if (tcp_stats_tick < this_tick)
+		if (fetch_tcp_stats() == -1)
 			return (SNMP_ERR_GENERR);
 
 	switch (value->var.subs[sub - 1]) {
@@ -226,7 +231,8 @@ op_tcp(struct snmp_context *ctx __unused, struct snmp_value *value,
 		break;
 
 	  case LEAF_tcpCurrEstab:
-		value->v.uint32 = tcp_count;
+		value->v.uint32 = tcpstat.tcps_states[TCPS_ESTABLISHED] +
+		    tcpstat.tcps_states[TCPS_CLOSE_WAIT];
 		break;
 
 	  case LEAF_tcpInSegs:

From 64d0bd295160c8cef670f9b055df3535eb015a7a Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 01:24:05 +0000
Subject: [PATCH 063/113] Fix DIRDEPS_BUILD after r294752.

DIRDEPS_BUILD does not yet support PROGS having their own dependency
file.

Overriding .MAKE.DEPENDFILE here causes major problems with the meta
mode logic since it creates the Makefile.depend as '.depend' resulting
in infinite loops in make due to dirdeps.mk including .depend endlessly.

X-MFC-With:	r294752
MFC after:	1 week
Sponsored by:	EMC / Isilon Storage Division
---
 share/mk/bsd.dep.mk | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/share/mk/bsd.dep.mk b/share/mk/bsd.dep.mk
index d31dc8b5d96b..f7f475e6ecfc 100644
--- a/share/mk/bsd.dep.mk
+++ b/share/mk/bsd.dep.mk
@@ -56,7 +56,9 @@ _MKDEPCC+=	${DEPFLAGS}
 .endif
 MKDEPCMD?=	CC='${_MKDEPCC}' mkdep
 DEPENDFILE?=	.depend
+.if ${MK_DIRDEPS_BUILD} == "no"
 .MAKE.DEPENDFILE= ${DEPENDFILE}
+.endif
 DEPENDFILES=	${DEPENDFILE}
 
 # Keep `tags' here, before SRCS are mangled below for `depend'.

From 55fac9c2d304bb7ea0cc3fa6ed8469a81ab3b6db Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 01:24:08 +0000
Subject: [PATCH 064/113] Set a value for _RECURSING_PROGS for debugging.

MFC after:	3 days
Sponsored by:	EMC / Isilon Storage Division
---
 share/mk/bsd.progs.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/share/mk/bsd.progs.mk b/share/mk/bsd.progs.mk
index 92a5eea56b08..cba0b5936a17 100644
--- a/share/mk/bsd.progs.mk
+++ b/share/mk/bsd.progs.mk
@@ -119,7 +119,7 @@ x.$p= PROG_CXX=$p
 $p ${p}_p: .PHONY .MAKE
 	(cd ${.CURDIR} && \
 	    DEPENDFILE=.depend.$p \
-	    NO_SUBDIR=1 ${MAKE} -f ${MAKEFILE} _RECURSING_PROGS= \
+	    NO_SUBDIR=1 ${MAKE} -f ${MAKEFILE} _RECURSING_PROGS=t \
 	    PROG=$p ${x.$p})
 
 # Pseudo targets for PROG, such as 'install'.
@@ -127,7 +127,7 @@ $p ${p}_p: .PHONY .MAKE
 $p.$t: .PHONY .MAKE
 	(cd ${.CURDIR} && \
 	    DEPENDFILE=.depend.$p \
-	    NO_SUBDIR=1 ${MAKE} -f ${MAKEFILE} _RECURSING_PROGS= \
+	    NO_SUBDIR=1 ${MAKE} -f ${MAKEFILE} _RECURSING_PROGS=t \
 	    PROG=$p ${x.$p} ${@:E})
 .endfor
 .endfor

From 1896d0ccd1d4ad7c450d45ed43e3ccc61316939d Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 01:24:11 +0000
Subject: [PATCH 065/113] FAST_DEPEND: Apply missed nofilemon fix from r294351.

Sponsored by:	EMC / Isilon Storage Division
---
 sys/conf/kern.post.mk | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sys/conf/kern.post.mk b/sys/conf/kern.post.mk
index 63aeab164f7e..65d162b81a48 100644
--- a/sys/conf/kern.post.mk
+++ b/sys/conf/kern.post.mk
@@ -200,7 +200,8 @@ SRCS=	assym.s vnode_if.h ${BEFORE_DEPEND} ${CFILES} \
 	${SYSTEM_CFILES} ${GEN_CFILES} ${SFILES} \
 	${MFILES:T:S/.m$/.h/}
 DEPENDFILES=	.depend
-.if ${MK_FAST_DEPEND} == "yes" && ${.MAKE.MODE:Unormal:Mmeta*} == ""
+.if ${MK_FAST_DEPEND} == "yes" && \
+    (${.MAKE.MODE:Unormal:Mmeta} == "" || ${.MAKE.MODE:Unormal:Mnofilemon} != "")
 DEPENDFILES+=	.depend.*
 DEPEND_CFLAGS+=	-MD -MP -MF.depend.${.TARGET}
 DEPEND_CFLAGS+=	-MT${.TARGET}

From 5aa5255644b8d653636e4d06bf3a49d9579083ee Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 01:24:14 +0000
Subject: [PATCH 066/113] FAST_DEPEND: Mark some unneeded code for later
 removal.

Sponsored by:	EMC / Isilon Storage Division
---
 sys/conf/kern.pre.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/conf/kern.pre.mk b/sys/conf/kern.pre.mk
index 007e66553114..7860701e8440 100644
--- a/sys/conf/kern.pre.mk
+++ b/sys/conf/kern.pre.mk
@@ -64,7 +64,7 @@ NOSTDINC= -nostdinc
 
 INCLUDES= ${NOSTDINC} ${INCLMAGIC} -I. -I$S
 
-.if make(depend) || make(kernel-depend)
+.if ${MK_FAST_DEPEND} == "no" && (make(depend) || make(kernel-depend))
 
 # This hack lets us use the ipfilter code without spamming a new
 # include path into contrib'ed source files.

From 46307c6f50aa27e604086cfcd78d7ee2fc110f4b Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 01:33:19 +0000
Subject: [PATCH 067/113] nslexer.c does not depend on nsparser.h.

nslexer.o depends on nsparser.h, which is already added by bsd.lib.mk
and .depend.

This reverts r237402.

MFC after:	2 weeks
Sponsored by:	EMC / Isilon Storage Division
---
 lib/libc/net/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/libc/net/Makefile.inc b/lib/libc/net/Makefile.inc
index c6307afc1d53..ed1d75f29ce4 100644
--- a/lib/libc/net/Makefile.inc
+++ b/lib/libc/net/Makefile.inc
@@ -36,7 +36,7 @@ LFLAGS+=-P_nsyy
 
 CLEANFILES+=nslexer.c nslexer.c.*
 
-nslexer.c: nslexer.l nsparser.h
+nslexer.c: nslexer.l
 	${LEX} ${LFLAGS} -o${.TARGET}.tmp1 ${.IMPSRC}
 	sed -e '/YY_BUF_SIZE/s/16384/1024/' ${.TARGET}.tmp1 >${.TARGET}.tmp2
 	rm -f ${.TARGET}.tmp1

From 273b2d98ab2ca59155970f71a9edc9d7c79d0e68 Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 01:33:23 +0000
Subject: [PATCH 068/113] Replace nslexer.l->nslexer.c custom rule with a -D
 CFLAG.

This avoids reproducing the lex logic which had dependencies set wrong
and used an intermediate file for modifying the YY_BUF_SIZE.

This has only been possible since flex 2.5.37 was imported in r250873,
which uses #ifndef YY_BUF_SIZE.

MFC after:	2 weeks
Sponsored by:	EMC / Isilon Storage Division
---
 lib/libc/net/Makefile.inc | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/lib/libc/net/Makefile.inc b/lib/libc/net/Makefile.inc
index ed1d75f29ce4..6f51f08f236b 100644
--- a/lib/libc/net/Makefile.inc
+++ b/lib/libc/net/Makefile.inc
@@ -12,7 +12,7 @@ SRCS+=	base64.c ether_addr.c eui64.c \
 	getproto.c getprotoent.c getprotoname.c getservent.c \
 	if_indextoname.c if_nameindex.c if_nametoindex.c \
 	ip6opt.c linkaddr.c map_v4v6.c name6.c ntoh.c \
-	nsdispatch.c nslexer.c nsparser.y nss_compat.c \
+	nsdispatch.c nslexer.l nsparser.y nss_compat.c \
 	rcmd.c rcmdsh.c recv.c rthdr.c sctp_sys_calls.c send.c \
         sockatmark.c sourcefilter.c vars.c
 
@@ -34,13 +34,8 @@ CFLAGS+=-I${LIBC_SRCTOP}/resolv
 YFLAGS+=-p_nsyy
 LFLAGS+=-P_nsyy
 
-CLEANFILES+=nslexer.c nslexer.c.*
-
-nslexer.c: nslexer.l
-	${LEX} ${LFLAGS} -o${.TARGET}.tmp1 ${.IMPSRC}
-	sed -e '/YY_BUF_SIZE/s/16384/1024/' ${.TARGET}.tmp1 >${.TARGET}.tmp2
-	rm -f ${.TARGET}.tmp1
-	mv -f ${.TARGET}.tmp2 ${.TARGET}
+CFLAGS.nslexer.c= -DYY_BUF_SIZE=1024
+CFLAGS+=	${CFLAGS.${.IMPSRC:T}}
 
 MAN+=	byteorder.3 ethers.3 eui64.3 \
 	getaddrinfo.3 gai_strerror.3 gethostbyname.3 \

From bda9fd0b43dbaa6b84cf8ec8e36f97987ab92249 Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 01:33:26 +0000
Subject: [PATCH 069/113] Revert yacc dependency back to pre-r241298.

Several attempts to fix this logic was done after r241298, which were
all reverted, yet this change was not.

The .h file does not depend on the .c file, so do not impose such a
dependency on it.  They are generated by the same command but do not
depend on each other.  Restore the .ORDER which should handle parallel build
issues.  This fixes an actual bug where the .h file is not recreated
when missing [1].  For example:
  cd lib/libc
  make cleanobj
  make nsparser.h
  rm nsparser.h
  make nsparser.h # will not rebuild nsparser.h

I have been trying to track down a build problem where nsparser.h is
missing when nslexer.o is built.  It is possible this is related.

Reported by:	bde [1]
		https://lists.freebsd.org/pipermail/svn-src-all/2012-October/059481.html
		https://lists.freebsd.org/pipermail/svn-src-all/2012-October/060038.html
MFC after:	3 weeks
Sponsored by:	EMC / Isilon Storage Division
---
 share/mk/bsd.dep.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/share/mk/bsd.dep.mk b/share/mk/bsd.dep.mk
index f7f475e6ecfc..948f31008a71 100644
--- a/share/mk/bsd.dep.mk
+++ b/share/mk/bsd.dep.mk
@@ -110,8 +110,8 @@ ${_YC} y.tab.h: ${_YSRC}
 CLEANFILES+= y.tab.c y.tab.h
 .elif !empty(YFLAGS:M-d)
 .for _YH in ${_YC:R}.h
-${_YH}: ${_YC}
-${_YC}: ${_YSRC}
+.ORDER: ${_YC} ${_YH}
+${_YC} ${_YH}: ${_YSRC}
 	${YACC} ${YFLAGS} -o ${_YC} ${.ALLSRC}
 SRCS+=	${_YH}
 CLEANFILES+= ${_YH}

From 7860e04138c66d208ac2fa347703113261c0b120 Mon Sep 17 00:00:00 2001
From: luigi <luigi@FreeBSD.org>
Date: Wed, 27 Jan 2016 02:08:30 +0000
Subject: [PATCH 070/113] bugfix: the scheduler template (dn_schk) for the
 round robin scheduler is followed by another structure (rr_schk) whose size
 must be set in the schk_datalen field of the descriptor. Not allocating the
 memory may cause other memory to be overwritten (though dn_schk is 192 bytes
 and rr_schk only 12 so we may be lucky and end up in the padding after the
 dn_schk).

This is a merge candidate for stable and 10.3

MFC after:	3 days
---
 sys/netpfil/ipfw/dn_sched_rr.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sys/netpfil/ipfw/dn_sched_rr.c b/sys/netpfil/ipfw/dn_sched_rr.c
index 63e525a2b7a0..16649a82e638 100644
--- a/sys/netpfil/ipfw/dn_sched_rr.c
+++ b/sys/netpfil/ipfw/dn_sched_rr.c
@@ -294,7 +294,7 @@ static struct dn_alg rr_desc = {
 	_SI( .name = ) "RR",
 	_SI( .flags = ) DN_MULTIQUEUE,
 
-	_SI( .schk_datalen = ) 0,
+	_SI( .schk_datalen = ) sizeof(struct rr_schk),
 	_SI( .si_datalen = ) sizeof(struct rr_si),
 	_SI( .q_datalen = ) sizeof(struct rr_queue) - sizeof(struct dn_queue),
 
@@ -311,5 +311,6 @@ static struct dn_alg rr_desc = {
 	_SI( .free_queue = ) rr_free_queue,
 };
 
+_Static_assert(sizeof(struct dn_schk) < 193, "a");
 
 DECLARE_DNSCHED_MODULE(dn_rr, &rr_desc);

From e0376f17e2eedb799a522253baa1d17351c097f4 Mon Sep 17 00:00:00 2001
From: dteske <dteske@FreeBSD.org>
Date: Wed, 27 Jan 2016 02:11:58 +0000
Subject: [PATCH 071/113] Replace awk with more efficient builtins-only algo

---
 usr.sbin/bsdconfig/share/strings.subr | 64 +++++++++++++++++++++++----
 1 file changed, 55 insertions(+), 9 deletions(-)

diff --git a/usr.sbin/bsdconfig/share/strings.subr b/usr.sbin/bsdconfig/share/strings.subr
index e624fb5c7cd7..e0cd7e0a1d5a 100644
--- a/usr.sbin/bsdconfig/share/strings.subr
+++ b/usr.sbin/bsdconfig/share/strings.subr
@@ -70,17 +70,63 @@ f_substr()
 #
 f_snprintf()
 {
+	local __funcname=f_snprintf
 	local __var_to_set="$1" __size="$2"
 	shift 2 # var_to_set size
-	eval "$__var_to_set"=\$\( printf -- \"\$@\" \| \
-		awk -v max=\"\$__size\" \''
-	{
-		len = length($0)
-		max -= len
-		print substr($0,0,(max > 0 ? len : max + len))
-		if ( max < 0 ) exit
-		max--
-	}'\' \)
+
+	if [ "$__size" -eq 0 ] 2> /dev/null; then
+		setvar "$__var_to_set" ""
+		return ${SUCCESS:-0}
+	elif [ $? -ge 2 ] || [ $__size -lt 0 ]; then
+		setvar "$__var_to_set" ""
+		echo "$__funcname: invalid size argument \`__size'" >&2
+		return ${FAILURE:-1}
+	fi
+
+	local __f_snprintf_tmp
+	f_sprintf __f_snprintf_tmp "$@"
+
+	local __tmp_size=${#__f_snprintf_tmp}
+	local __trim=$(( $__tmp_size - $__size )) __trimq
+	local __tbuf __tbuf_len
+	local __mask __mask_len
+	while [ $__trim -gt 0 ]; do
+		__tbuf="?"
+		__tbuf_len=1
+		if [ $__trim -le $__size ]; then
+			while [ $__tbuf_len -lt $(( $__trim / $__tbuf_len )) ]
+			do
+				__tbuf="$__tbuf?"
+				__tbuf_len=$(( $__tbuf_len + 1 ))
+			done
+			__trimq=$(( $__trim / $__tbuf_len ))
+			__trim=$(( $__trim - $__tbuf_len * $__trimq ))
+			while [ $__trimq -gt 0 ]; do
+				__f_snprintf_tmp="${__f_snprintf_tmp%$__tbuf}"
+				__trimq=$(( $__trimq - 1 ))
+			done
+		else
+			__mask="$__f_snprintf_tmp"
+			while [ $__tbuf_len -lt $(( $__size / $__tbuf_len )) ]
+			do
+				__tbuf="$__tbuf?"
+				__tbuf_len=$(( $__tbuf_len + 1 ))
+			done
+			__trimq=$(( $__size / $__tbuf_len ))
+			if [ $(( $__trimq * $__tbuf_len )) -ne $__size ]; then
+				__tbuf="$__tbuf?"
+				__tbuf_len=$(( $__tbuf_len + 1 ))
+			fi
+			__mask_len=$(( $__tmp_size - $__tbuf_len * $__trimq ))
+			__trim=$(( $__tmp_size - $__mask_len - $__size ))
+			while [ $__trimq -gt 0 ]; do
+				__mask="${__mask#$__tbuf}"
+				__trimq=$(( $__trimq - 1 ))
+			done
+			__f_snprintf_tmp="${__f_snprintf_tmp%"$__mask"}"
+		fi
+	done
+	setvar "$__var_to_set" "$__f_snprintf_tmp"
 }
 
 # f_sprintf $var_to_set $format [$arguments ...]

From 94957acd2f6a3553dd12ba30f83867a5e129d2f5 Mon Sep 17 00:00:00 2001
From: luigi <luigi@FreeBSD.org>
Date: Wed, 27 Jan 2016 02:14:08 +0000
Subject: [PATCH 072/113] the _Static_assert was not supposed to be in the
 commit.

---
 sys/netpfil/ipfw/dn_sched_rr.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/sys/netpfil/ipfw/dn_sched_rr.c b/sys/netpfil/ipfw/dn_sched_rr.c
index 16649a82e638..a4ec9b66e3fc 100644
--- a/sys/netpfil/ipfw/dn_sched_rr.c
+++ b/sys/netpfil/ipfw/dn_sched_rr.c
@@ -311,6 +311,5 @@ static struct dn_alg rr_desc = {
 	_SI( .free_queue = ) rr_free_queue,
 };
 
-_Static_assert(sizeof(struct dn_schk) < 193, "a");
 
 DECLARE_DNSCHED_MODULE(dn_rr, &rr_desc);

From d2ca0a07825355904475b1fe585efdd49eeae0b3 Mon Sep 17 00:00:00 2001
From: luigi <luigi@FreeBSD.org>
Date: Wed, 27 Jan 2016 02:22:31 +0000
Subject: [PATCH 073/113] cleanup and document in some detail the internals of
 the testing code for dummynet schedulers

---
 sys/netpfil/ipfw/test/Makefile        |   2 +-
 sys/netpfil/ipfw/test/dn_test.h       |  72 +++----
 sys/netpfil/ipfw/test/main.c          | 266 ++++++++++++++++----------
 sys/netpfil/ipfw/test/mylist.h        |   1 +
 sys/netpfil/ipfw/test/test_dn_sched.c |   1 +
 5 files changed, 199 insertions(+), 143 deletions(-)

diff --git a/sys/netpfil/ipfw/test/Makefile b/sys/netpfil/ipfw/test/Makefile
index 529306e495ab..f76e636932ba 100644
--- a/sys/netpfil/ipfw/test/Makefile
+++ b/sys/netpfil/ipfw/test/Makefile
@@ -20,7 +20,7 @@ HEAP_OBJS=$(HEAP_SRCS:.c=.o)
 
 VPATH=	.:..
 
-CFLAGS = -I.. -I. -Wall -Werror -O3 -DIPFW -Wextra
+CFLAGS = -I.. -I. -Wall -Werror -O3 -Wextra
 TARGETS= test_sched # no test_heap by default
 
 all:	$(TARGETS)
diff --git a/sys/netpfil/ipfw/test/dn_test.h b/sys/netpfil/ipfw/test/dn_test.h
index 3b309cce082f..77704690f6f3 100644
--- a/sys/netpfil/ipfw/test/dn_test.h
+++ b/sys/netpfil/ipfw/test/dn_test.h
@@ -23,8 +23,8 @@ extern "C" {
 extern int debug;
 #define ND(fmt, args...) do {} while (0)
 #define D1(fmt, args...) do {} while (0)
-#define D(fmt, args...) fprintf(stderr, "%-8s " fmt "\n",      \
-        __FUNCTION__, ## args)
+#define D(fmt, args...) fprintf(stderr, "%-10s %4d %-8s " fmt "\n",      \
+        __FILE__, __LINE__, __FUNCTION__, ## args)
 #define DX(lev, fmt, args...) do {              \
         if (debug > lev) D(fmt, ## args); } while (0)
 
@@ -53,11 +53,24 @@ enum	{
 	DN_SCHED_WF2QP,
 };
 
+/* from ip_dummynet.h, fields used in ip_dn_private.h */
 struct dn_id {
-	int type, subtype, len, id;
+	uint16_t 	len; /* total len inc. this header */
+	uint8_t		type;
+	uint8_t		subtype;
+//	uint32_t	id;	/* generic id */
 };
 
+/* (from ip_dummynet.h)
+ * A flowset, which is a template for flows. Contains parameters
+ * from the command line: id, target scheduler, queue sizes, plr,
+ * flow masks, buckets for the flow hash, and possibly scheduler-
+ * specific parameters (weight, quantum and so on).
+ */
 struct dn_fs {
+        /* generic scheduler parameters. Leave them at -1 if unset.
+         * Now we use 0: weight, 1: lmax, 2: priority
+         */
 	int par[4];	/* flowset parameters */
 
 	/* simulation entries.
@@ -78,16 +91,29 @@ struct dn_fs {
 	int	cur;
 };
 
+/* (ip_dummynet.h)
+ * scheduler template, indicating nam, number, mask and buckets
+ */
 struct dn_sch {
 };
 
+/* (from ip_dummynet.h)
+ * dn_flow collects flow_id and stats for queues and scheduler
+ * instances, and is used to pass these info to userland.
+ * oid.type/oid.subtype describe the object, oid.id is number
+ * of the parent object.
+ */
 struct dn_flow {
 	struct dn_id oid;
-	int length;
-	int len_bytes;
-	int drops;
+	uint64_t tot_pkts;
 	uint64_t tot_bytes;
-	uint32_t flow_id;
+	uint32_t length;	/* Queue length, in packets */
+	uint32_t len_bytes;	/* Queue length, in bytes */
+	uint32_t drops;
+	//uint32_t flow_id;
+
+	/* the following fields are used by the traffic generator.
+	 */
 	struct list_head h;	/* used by the generator */
 
 	/* bytes served by the flow since the last backlog time */
@@ -96,6 +122,7 @@ struct dn_flow {
 	uint64_t sch_bytes;
 };
 
+/* the link */
 struct dn_link {
 };
 
@@ -107,9 +134,9 @@ struct mbuf {
                 int len;
         } m_pkthdr;
         struct mbuf *m_nextpkt;
-	int flow_id;	/* for testing, index of a flow */
+	uint32_t flow_id;	/* for testing, index of a flow */
 	//int flowset_id;	/* for testing, index of a flowset */
-	void *cfg;	/* config args */
+	//void *cfg;	/* config args */
 };
 
 #define MALLOC_DECLARE(x)	extern volatile int __dummy__ ## x
@@ -131,36 +158,9 @@ typedef struct _md_t moduledata_t;
 	moduledata_t *_g_##name = & b
 #define MODULE_DEPEND(a, b, c, d, e)
 
-#ifdef IPFW
 #include <dn_heap.h>
 #include <ip_dn_private.h>
 #include <dn_sched.h>
-#else
-struct dn_queue {
-        struct dn_fsk *fs;             /* parent flowset. */
-        struct dn_sch_inst *_si;	/* parent sched instance. */
-};
-struct dn_schk {
-};
-struct dn_fsk {
-	struct dn_fs fs;
-	struct dn_schk *sched;
-};
-struct dn_sch_inst {
-	struct dn_schk *sched;
-};
-struct dn_alg {
-	int type;
-	const char *name;
-	void *enqueue, *dequeue;
-	int q_datalen, si_datalen, schk_datalen;
-	int (*config)(struct dn_schk *);
-	int (*new_sched)(struct dn_sch_inst *);
-	int (*new_fsk)(struct dn_fsk *);
-        int (*new_queue)(struct dn_queue *q);
-};
-
-#endif
 
 #ifndef __FreeBSD__
 int fls(int);
diff --git a/sys/netpfil/ipfw/test/main.c b/sys/netpfil/ipfw/test/main.c
index 0dd575c94d3c..71fa2744db6c 100644
--- a/sys/netpfil/ipfw/test/main.c
+++ b/sys/netpfil/ipfw/test/main.c
@@ -9,11 +9,9 @@
  * keeping track of statistics.
  */
 
-#include "dn_test.h"
+// #define USE_BURST	// what is this for ?
 
-struct q_list {
-	struct list_head h;
-};
+#include "dn_test.h"
 
 struct cfg_s {
 	int ac;
@@ -30,14 +28,19 @@ struct cfg_s {
 	uint32_t	dequeue;
 
 	/* generator parameters */
-	int th_min, th_max;
+	int32_t th_min, th_max;	/* thresholds for hysteresis; negative means per flow */
+#ifdef USE_BURST
 	int maxburst;
+#endif /* USE_BURST */
 	int lmin, lmax;	/* packet len */
 	int flows;	/* number of flows */
 	int flowsets;	/* number of flowsets */
 	int wsum;	/* sum of weights of all flows */
+#ifdef USE_CUR
 	int max_y;	/* max random number in the generation */
-	int cur_y, cur_fs;	/* used in generation, between 0 and max_y - 1 */
+	int cur_y
+	int cur_fs;	/* used in generation, between 0 and max_y - 1 */
+#endif /* USE_CUR */
 	const char *fs_config; /* flowset config */
 	int can_dequeue;
 	int burst;	/* count of packets sent in a burst */
@@ -52,17 +55,26 @@ struct cfg_s {
 		struct mbuf *);
 	struct mbuf * (*deq)(struct dn_sch_inst *);
 	/* size of the three fields including sched-specific areas */
-	int schk_len;
-	int q_len; /* size of a queue including sched-fields */
-	int si_len; /* size of a sch_inst including sched-fields */
+	uint32_t schk_len;
+	uint32_t q_len; /* size of a queue including sched-fields */
+	uint32_t si_len; /* size of a sch_inst including sched-fields */
 	char *q;	/* array of flow queues */
 		/* use a char* because size is variable */
-	struct dn_fsk *fs;	/* array of flowsets */
-	struct dn_sch_inst *si;
+	/*
+	 * The scheduler template (one) followd by schk_datalen bytes
+	 * for scheduler-specific parameters, total size is schk_len
+	 */
 	struct dn_schk *sched;
+	/*
+	 * one scheduler instance, followed by si_datalen bytes
+	 * for scheduler specific parameters of this instance,
+	 * total size is si_len. si->sched points to sched
+	 */
+	struct dn_sch_inst *si;
+	struct dn_fsk *fs;	/* array of flowsets */
 
 	/* generator state */
-	int state;		/* 0 = going up, 1: going down */
+	int state;	/* 0 = going up (enqueue), 1: going down (dequeue) */
 
 	/*
 	 * We keep lists for each backlog level, and always serve
@@ -72,17 +84,18 @@ struct cfg_s {
 	 * XXX to optimize things, entry i could contain queues with
 	 * 2^{i-1}+1 .. 2^i entries.
 	 */
-#define BACKLOG	30
-	uint32_t	llmask;
+#define BACKLOG	30 /* this many backlogged classes, we only need BACKLOG+1 */
+	uint64_t	llmask;
 	struct list_head ll[BACKLOG + 10];
 
 	double *q_wfi;	/* (byte) Worst-case Fair Index of the flows  */
 	double wfi;	/* (byte) Worst-case Fair Index of the system */
 };
 
-/* FI2Q and Q2FI converts from flow_id to dn_queue and back.
- * We cannot easily use pointer arithmetic because it is variable size.
-  */
+/* FI2Q and Q2FI converts from flow_id (i.e. queue index)
+ * to dn_queue and back. We cannot simply use pointer arithmetic
+ * because the queu has variable size, q_len
+ */
 #define FI2Q(c, i)	((struct dn_queue *)((c)->q + (c)->q_len * (i)))
 #define Q2FI(c, q)	(((char *)(q) - (c)->q)/(c)->q_len)
 
@@ -92,10 +105,11 @@ struct dn_parms dn_cfg;
 
 static void controller(struct cfg_s *c);
 
-/* release a packet: put the mbuf in the freelist, and the queue in
- * the bucket.
+/* release a packet for a given flow_id.
+ * Put the mbuf in the freelist, and in case move the
+ * flow to the end of the bucket.
  */
-int
+static int
 drop(struct cfg_s *c, struct mbuf *m)
 {
 	struct dn_queue *q;
@@ -118,31 +132,36 @@ drop(struct cfg_s *c, struct mbuf *m)
 	return 0;
 }
 
-/* dequeue returns NON-NULL when a packet is dropped */
+
+/*
+ * dn_sch_inst does not have a queue, for the RR we
+ * allocate a mq right after si
+ */
 static int
-enqueue(struct cfg_s *c, void *_m)
+default_enqueue(struct dn_sch_inst *si, struct dn_queue *q, struct mbuf *m)
 {
-	struct mbuf *m = _m;
-	if (c->enq)
-		return c->enq(c->si, FI2Q(c, m->flow_id), m);
-	if (c->head == NULL)
-		c->head = m;
+	struct mq *mq = (struct mq *)si;
+
+	(void)q;
+	/* this is the default function if no scheduler is provided */
+	if (mq->head == NULL)
+		mq->head = m;
 	else
-		c->tail->m_nextpkt = m;
-	c->tail = m;
+		mq->tail->m_nextpkt = m;
+	mq->tail = m;
 	return 0; /* default - success */
 }
 
-/* dequeue returns NON-NULL when a packet is available */
-static void *
-dequeue(struct cfg_s *c)
+
+static struct mbuf *
+default_dequeue(struct dn_sch_inst *si)
 {
+	struct mq *mq = (struct mq *)si;
 	struct mbuf *m;
-	if (c->deq)
-		return c->deq(c->si);
-	if ((m = c->head)) {
-		m = c->head;
-		c->head = m->m_nextpkt;
+	/* this is the default function if no scheduler is provided */
+	if ((m = mq->head)) {
+		m = mq->head;
+		mq->head = m->m_nextpkt;
 		m->m_nextpkt = NULL;
 	}
 	return m;
@@ -193,23 +212,34 @@ mainloop(struct cfg_s *c)
 		DX(3, "loop %d enq %d send %p rx %d",
 			i, c->_enqueue, c->tosend, c->can_dequeue);
 		if ( (m = c->tosend) ) {
+			int ret;
+			struct dn_queue *q = FI2Q(c, m->flow_id);
 			c->_enqueue++;
-			if (enqueue(c, m)) {
+			ret = c->enq(c->si, q, m);
+			if (ret) {
 				drop(c, m);
-				ND("loop %d enqueue fail", i );
+				D("loop %d enqueue fail", i );
+				/*
+				 * XXX do not insist; rather, try dequeue
+				 */
+				goto do_dequeue;
 			} else {
 				ND("enqueue ok");
 				c->pending++;
 				gnet_stats_enq(c, m);
 			}
-		}
-		if (c->can_dequeue) {
+		} else if (c->can_dequeue) {
+do_dequeue:
 			c->dequeue++;
-			if ((m = dequeue(c))) {
+			m = c->deq(c->si);
+			if (m) {
 				c->pending--;
 				drop(c, m);
 				c->drop--;	/* compensate */
 				gnet_stats_deq(c, m);
+			} else {
+				D("--- ouch, cannot operate on iteration %d, pending %d", i, c->pending);
+				break;
 			}
 		}
 	}
@@ -221,11 +251,10 @@ int
 dump(struct cfg_s *c)
 {
 	int i;
-	struct dn_queue *q;
 
 	for (i=0; i < c->flows; i++) {
-		q = FI2Q(c, i);
-		DX(1, "queue %4d tot %10llu", i,
+		//struct dn_queue *q = FI2Q(c, i);
+		ND(1, "queue %4d tot %10llu", i,
 		    (unsigned long long)q->ni.tot_bytes);
 	}
 	DX(1, "done %d loops\n", c->loops);
@@ -284,20 +313,25 @@ getnum(const char *s, char **next, const char *key)
  *     weight:maxlen:flows
  * indicating how many flows are hooked to that fs.
  * Both weight and range can be min-max-steps.
- * In a first pass we just count the number of flowsets and flows,
- * in a second pass we complete the setup.
+ * The first pass (fs != NULL) justs count the number of flowsets and flows,
+ * the second pass (fs == NULL) we complete the setup.
  */
 static void
-parse_flowsets(struct cfg_s *c, const char *fs, int pass)
+parse_flowsets(struct cfg_s *c, const char *fs)
 {
 	char *s, *cur, *next;
 	int n_flows = 0, n_fs = 0, wsum = 0;
 	int i, j;
 	struct dn_fs *prev = NULL;
+	int pass = (fs == NULL);
 
 	DX(3, "--- pass %d flows %d flowsets %d", pass, c->flows, c->flowsets);
-	if (pass == 0)
+	if (fs != NULL) { /* first pass */
+		if (c->fs_config)
+			D("warning, overwriting fs %s with %s",
+				c->fs_config, fs);
 		c->fs_config = fs;
+	}
 	s = c->fs_config ? strdup(c->fs_config) : NULL;
 	if (s == NULL) {
 		if (pass == 0)
@@ -327,7 +361,7 @@ parse_flowsets(struct cfg_s *c, const char *fs, int pass)
 			w, w_h, w_steps, len, len_h, l_steps, flows);
 		if (w == 0 || w_h < w || len == 0 || len_h < len ||
 				flows == 0) {
-			DX(4,"wrong parameters %s", fs);
+			DX(4,"wrong parameters %s", s);
 			return;
 		}
 		n_flows += flows * w_steps * l_steps;
@@ -361,7 +395,6 @@ parse_flowsets(struct cfg_s *c, const char *fs, int pass)
 			}
 		}
 	}
-	c->max_y = prev ? prev->base_y + prev->y : 0;
 	c->flows = n_flows;
 	c->flowsets = n_fs;
 	c->wsum = wsum;
@@ -369,7 +402,11 @@ parse_flowsets(struct cfg_s *c, const char *fs, int pass)
 		return;
 
 	/* now link all flows to their parent flowsets */
+	DX(1,"%d flows on %d flowsets", c->flows, c->flowsets);
+#ifdef USE_CUR
+	c->max_y = prev ? prev->base_y + prev->y : 0;
 	DX(1,"%d flows on %d flowsets max_y %d", c->flows, c->flowsets, c->max_y);
+#endif /* USE_CUR */
 	for (i=0; i < c->flowsets; i++) {
 		struct dn_fs *fs = &c->fs[i].fs;
 		DX(1, "fs %3d w %5d l %4d flow %5d .. %5d y %6d .. %6d",
@@ -383,6 +420,18 @@ parse_flowsets(struct cfg_s *c, const char *fs, int pass)
 	}
 }
 
+/* available schedulers */
+extern moduledata_t *_g_dn_fifo;
+extern moduledata_t *_g_dn_wf2qp;
+extern moduledata_t *_g_dn_rr;
+extern moduledata_t *_g_dn_qfq;
+#ifdef WITH_QFQP
+extern moduledata_t *_g_dn_qfqp;
+#endif
+#ifdef WITH_KPS
+extern moduledata_t *_g_dn_kps;
+#endif
+
 static int
 init(struct cfg_s *c)
 {
@@ -395,7 +444,7 @@ init(struct cfg_s *c)
 	moduledata_t *mod = NULL;
 	struct dn_alg *p = NULL;
 
-	c->th_min = 0;
+	c->th_min = -1; /* 1 packet per flow */
 	c->th_max = -20;/* 20 packets per flow */
 	c->lmin = c->lmax = 1280;	/* packet len */
 	c->flows = 1;
@@ -408,16 +457,6 @@ init(struct cfg_s *c)
 		} else if (!strcmp(*av, "-d")) {
 			debug = atoi(av[1]);
 		} else if (!strcmp(*av, "-alg")) {
-			extern moduledata_t *_g_dn_fifo;
-			extern moduledata_t *_g_dn_wf2qp;
-			extern moduledata_t *_g_dn_rr;
-			extern moduledata_t *_g_dn_qfq;
-#ifdef WITH_QFQP
-			extern moduledata_t *_g_dn_qfqp;
-#endif
-#ifdef WITH_KPS
-			extern moduledata_t *_g_dn_kps;
-#endif
 			if (!strcmp(av[1], "rr"))
 				mod = _g_dn_rr;
 			else if (!strcmp(av[1], "wf2qp"))
@@ -443,9 +482,11 @@ init(struct cfg_s *c)
 			c->lmin = getnum(av[1], NULL, av[0]);
 			c->lmax = c->lmin;
 			DX(3, "setting max to %d", c->th_max);
+#ifdef USE_BURST
 		} else if (!strcmp(*av, "-burst")) {
 			c->maxburst = getnum(av[1], NULL, av[0]);
 			DX(3, "setting max to %d", c->th_max);
+#endif /* USE_BURST */
 		} else if (!strcmp(*av, "-qmax")) {
 			c->th_max = getnum(av[1], NULL, av[0]);
 			DX(3, "setting max to %d", c->th_max);
@@ -456,15 +497,17 @@ init(struct cfg_s *c)
 			c->flows = getnum(av[1], NULL, av[0]);
 			DX(3, "setting flows to %d", c->flows);
 		} else if (!strcmp(*av, "-flowsets")) {
-			parse_flowsets(c, av[1], 0);
+			parse_flowsets(c, av[1]); /* first pass */
 			DX(3, "setting flowsets to %d", c->flowsets);
 		} else {
 			D("option %s not recognised, ignore", *av);
 		}
 		ac -= 2; av += 2;
 	}
+#ifdef USE_BURST
 	if (c->maxburst <= 0)
 		c->maxburst = 1;
+#endif /* USE_BURST */
 	if (c->loops <= 0)
 		c->loops = 1;
 	if (c->flows <= 0)
@@ -482,45 +525,61 @@ init(struct cfg_s *c)
 		c->th_max = c->flows * -c->th_max;
 	if (c->th_max <= c->th_min)
 		c->th_max = c->th_min + 1;
+
+	/* now load parameters from the module */
 	if (mod) {
 		p = mod->p;
 		DX(3, "using module %s f %p p %p", mod->name, mod->f, mod->p);
 		DX(3, "modname %s ty %d", p->name, p->type);
+		// XXX check enq and deq not null
 		c->enq = p->enqueue;
 		c->deq = p->dequeue;
 		c->si_len += p->si_datalen;
 		c->q_len += p->q_datalen;
 		c->schk_len += p->schk_datalen;
+	} else {
+		/* make sure c->si has room for a queue */
+		c->enq = default_enqueue;
+		c->deq = default_dequeue;
 	}
+
 	/* allocate queues, flowsets and one scheduler */
-	c->q = calloc(c->flows, c->q_len);
-	c->q_wfi = (double *)calloc(c->flows, sizeof(double));
+	D("using %d flows, %d flowsets", c->flows, c->flowsets);
+	D("q_len %d dn_fsk %d si %d sched %d",
+		c->q_len, (int)sizeof(struct dn_fsk),
+		c->si_len, c->schk_len);
+	c->sched = calloc(1, c->schk_len); /* one parent scheduler */
+	c->si = calloc(1, c->si_len); /* one scheduler instance */
 	c->fs = calloc(c->flowsets, sizeof(struct dn_fsk));
-	c->si = calloc(1, c->si_len);
-	c->sched = calloc(c->flows, c->schk_len);
-	if (c->q == NULL || c->fs == NULL || !c->q_wfi) {
-		D("error allocating memory for flows");
+	c->q = calloc(c->flows, c->q_len);	/* one queue per flow */
+	c->q_wfi = calloc(c->flows, sizeof(double)); /* stats, one per flow */
+	if (!c->sched || !c->si || !c->fs || !c->q || !c->q_wfi) {
+		D("error allocating memory");
 		exit(1);
 	}
-	c->si->sched = c->sched;
+	c->si->sched = c->sched; /* link scheduler instance to template */
 	if (p) {
+		/* run initialization code if needed */
 		if (p->config)
-			p->config(c->sched);
+			p->config(c->si->sched);
 		if (p->new_sched)
 			p->new_sched(c->si);
 	}
 	/* parse_flowsets links queues to their flowsets */
-	parse_flowsets(c, av[1], 1);
+	parse_flowsets(c, NULL); /* second pass */
 	/* complete the work calling new_fsk */
 	for (i = 0; i < c->flowsets; i++) {
-		if (c->fs[i].fs.par[1] == 0)
-			c->fs[i].fs.par[1] = 1000;	/* default pkt len */
-		c->fs[i].sched = c->sched;
+		struct dn_fsk *fsk = &c->fs[i];
+		if (fsk->fs.par[1] == 0)
+			fsk->fs.par[1] = 1000;	/* default pkt len */
+		fsk->sched = c->si->sched;
 		if (p && p->new_fsk)
-			p->new_fsk(&c->fs[i]);
+			p->new_fsk(fsk);
 	}
+	/* --- now the scheduler is initialized --- */
 
-	/* initialize the lists for the generator, and put
+	/*
+	 * initialize the lists for the generator, and put
 	 * all flows in the list for backlog = 0
 	 */
 	for (i=0; i <= BACKLOG+5; i++)
@@ -536,7 +595,7 @@ init(struct cfg_s *c)
 		INIT_LIST_HEAD(&q->ni.h);
 		list_add_tail(&q->ni.h, &c->ll[0]);
 	}
-	c->llmask = 1;
+	c->llmask = 1; /* all flows are in the first list */
 	return 0;
 }
 
@@ -545,7 +604,6 @@ int
 main(int ac, char *av[])
 {
 	struct cfg_s c;
-	struct timeval end;
 	double ll;
 	int i;
 	char msg[40];
@@ -555,16 +613,15 @@ main(int ac, char *av[])
 	c.av = av;
 	init(&c);
 	gettimeofday(&c.time, NULL);
+	D("th_min %d th_max %d", c.th_min, c.th_max);
+
 	mainloop(&c);
-	gettimeofday(&end, NULL);
-	end.tv_sec -= c.time.tv_sec;
-	end.tv_usec -= c.time.tv_usec;
-	if (end.tv_usec < 0) {
-		end.tv_usec += 1000000;
-		end.tv_sec--;
+	{
+		struct timeval end;
+		gettimeofday(&end, NULL);
+		timersub(&end, &c.time, &c.time);
 	}
-	c.time = end;
-	ll = end.tv_sec*1000000 + end.tv_usec;
+	ll = c.time.tv_sec*1000000 + c.time.tv_usec;
 	ll *= 1000;	/* convert to nanoseconds */
 	ll /= c._enqueue;
 	sprintf(msg, "1::%d", c.flows);
@@ -572,8 +629,10 @@ main(int ac, char *av[])
 		if (c.wfi < c.q_wfi[i])
 			c.wfi = c.q_wfi[i];
 	}
-	D("sched=%-12s\ttime=%d.%03d sec (%.0f nsec)\twfi=%.02f\tflow=%-16s",
-	   c.name, (int)c.time.tv_sec, (int)c.time.tv_usec / 1000, ll, c.wfi,
+	D("sched=%-12s\ttime=%d.%03d sec (%.0f nsec) enq %lu %lu deq\n"
+	   "\twfi=%.02f\tflow=%-16s",
+	   c.name, (int)c.time.tv_sec, (int)c.time.tv_usec / 1000, ll,
+	   (unsigned long)c._enqueue, (unsigned long)c.dequeue, c.wfi,
 	   c.fs_config ? c.fs_config : msg);
 	dump(&c);
 	DX(1, "done ac %d av %p", ac, av);
@@ -593,7 +652,7 @@ controller(struct cfg_s *c)
 	struct dn_fs *fs;
 	int flow_id;
 
-	/* histeresis between max and min */
+	/* hysteresis between max and min */
 	if (c->state == 0 && c->pending >= (uint32_t)c->th_max)
 		c->state = 1;
 	else if (c->state == 1 && c->pending <= (uint32_t)c->th_min)
@@ -601,9 +660,14 @@ controller(struct cfg_s *c)
 	ND(1, "state %d pending %2d", c->state, c->pending);
 	c->can_dequeue = c->state;
 	c->tosend = NULL;
-	if (c->state)
+	if (c->can_dequeue)
 		return;
 
+	/*
+	 * locate the flow to use for enqueueing
+	 * We take the queue with the lowest number of queued packets,
+	 * generate a packet for it, and put the queue in the next highest.
+	 */
     if (1) {
 	int i;
 	struct dn_queue *q;
@@ -611,7 +675,7 @@ controller(struct cfg_s *c)
 
 	i = ffs(c->llmask) - 1;
 	if (i < 0) {
-		DX(2, "no candidate");
+		D("no candidate");
 		c->can_dequeue = 1;
 		return;
 	}
@@ -633,8 +697,9 @@ controller(struct cfg_s *c)
 		c->llmask |= 1<<(1+i);
 	}
 	fs = &q->fs->fs;
-	c->cur_fs = q->fs - c->fs;
 	fs->cur = flow_id;
+#ifdef USE_CUR
+	c->cur_fs = q->fs - c->fs;
     } else {
 	/* XXX this does not work ? */
 	/* now decide whom to send the packet, and the length */
@@ -650,6 +715,7 @@ controller(struct cfg_s *c)
 	c->cur_y++;
 	if (c->cur_y >= fs->next_y)
 		c->cur_fs++;
+#endif /* USE_CUR */
     }
 
 	/* construct a packet */
@@ -662,7 +728,7 @@ controller(struct cfg_s *c)
 	if (m == NULL)
 		return;
 
-	m->cfg = c;
+	//m->cfg = c;
 	m->m_nextpkt = NULL;
 	m->m_pkthdr.len = fs->par[1]; // XXX maxlen
 	m->flow_id = flow_id;
@@ -672,15 +738,3 @@ controller(struct cfg_s *c)
 		fs->par[0], m->m_pkthdr.len);
 
 }
-
-/*
-Packet allocation:
-to achieve a distribution that matches weights, for each X=w/lmax class
-we should generate a number of packets proportional to Y = X times the number
-of flows in the class.
-So we construct an array with the cumulative distribution of Y's,
-and use it to identify the flow via inverse mapping (if the Y's are
-not too many we can use an array for the lookup). In practice,
-each flow will have X entries [virtually] pointing to it.
-
-*/
diff --git a/sys/netpfil/ipfw/test/mylist.h b/sys/netpfil/ipfw/test/mylist.h
index 6247f32ea4e4..109592256f47 100644
--- a/sys/netpfil/ipfw/test/mylist.h
+++ b/sys/netpfil/ipfw/test/mylist.h
@@ -6,6 +6,7 @@
 
 #ifndef _MYLIST_H
 #define _MYLIST_H
+/* not just a head, also the link field for a list entry */
 struct list_head {
         struct list_head *prev, *next;
 };
diff --git a/sys/netpfil/ipfw/test/test_dn_sched.c b/sys/netpfil/ipfw/test/test_dn_sched.c
index 2fcc310b2f63..e610019630b1 100644
--- a/sys/netpfil/ipfw/test/test_dn_sched.c
+++ b/sys/netpfil/ipfw/test/test_dn_sched.c
@@ -61,6 +61,7 @@ dn_enqueue(struct dn_queue *q, struct mbuf* m, int drop)
         mq_append(&q->mq, m);
         q->ni.length++;
         q->ni.tot_bytes += m->m_pkthdr.len;
+        q->ni.tot_pkts++;
         return 0;
 
 drop:

From 31bb8ee5bdf9a6332a86e4774ebdccba877ce42e Mon Sep 17 00:00:00 2001
From: jhibbits <jhibbits@FreeBSD.org>
Date: Wed, 27 Jan 2016 02:23:54 +0000
Subject: [PATCH 074/113] Convert rman to use rman_res_t instead of u_long

Summary:
Migrate to using the semi-opaque type rman_res_t to specify rman resources.  For
now, this is still compatible with u_long.

This is step one in migrating rman to use uintmax_t for resources instead of
u_long.

Going forward, this could feasibly be used to specify architecture-specific
definitions of resource ranges, rather than baking a specific integer type into
the API.

This change has been broken out to facilitate MFC'ing drivers back to 10 without
breaking ABI.

Reviewed By: jhb
Sponsored by:	Alex Perez/Inertial Computing
Differential Revision: https://reviews.freebsd.org/D5075
---
 lib/libdevinfo/devinfo.3             |  8 ++---
 lib/libdevinfo/devinfo.h             |  8 ++---
 share/man/man9/bus_adjust_resource.9 |  3 +-
 share/man/man9/bus_alloc_resource.9  |  5 ++-
 share/man/man9/bus_get_resource.9    |  2 +-
 share/man/man9/bus_set_resource.9    |  2 +-
 share/man/man9/rman.9                | 20 +++++------
 sys/arm/arm/nexus.c                  |  4 +--
 sys/arm/at91/at91.c                  |  4 +--
 sys/arm/cavium/cns11xx/econa.c       |  2 +-
 sys/arm/mv/mv_localbus.c             |  4 +--
 sys/arm/mv/mv_pci.c                  |  4 +--
 sys/arm/versatile/versatile_pci.c    |  2 +-
 sys/arm/xscale/i8134x/i81342.c       |  2 +-
 sys/arm/xscale/i8134x/i81342_pci.c   |  4 +--
 sys/arm/xscale/i8134x/obio.c         |  2 +-
 sys/arm/xscale/ixp425/avila_ata.c    |  2 +-
 sys/arm/xscale/ixp425/ixp425.c       |  2 +-
 sys/arm/xscale/ixp425/ixp425_pci.c   |  2 +-
 sys/arm/xscale/pxa/pxa_obio.c        |  8 ++---
 sys/arm/xscale/pxa/pxa_smi.c         |  4 +--
 sys/arm64/arm64/gic_v3_fdt.c         |  4 +--
 sys/arm64/arm64/nexus.c              |  9 ++---
 sys/arm64/cavium/thunder_pcie.c      |  6 ++--
 sys/arm64/cavium/thunder_pcie_pem.c  |  6 ++--
 sys/dev/acpica/acpi.c                | 20 +++++------
 sys/dev/acpica/acpi_hpet.c           |  2 +-
 sys/dev/acpica/acpi_pcib_acpi.c      | 12 +++----
 sys/dev/acpica/acpi_resource.c       |  2 +-
 sys/dev/acpica/acpi_timer.c          |  2 +-
 sys/dev/acpica/acpivar.h             |  3 +-
 sys/dev/advansys/adv_isa.c           |  2 +-
 sys/dev/ahci/ahci.c                  |  2 +-
 sys/dev/ahci/ahci.h                  |  2 +-
 sys/dev/ata/ata-cbus.c               |  5 +--
 sys/dev/ata/ata-isa.c                |  4 +--
 sys/dev/ata/ata-pci.c                |  3 +-
 sys/dev/ata/ata-pci.h                |  2 +-
 sys/dev/atkbdc/atkbdc_ebus.c         |  4 +--
 sys/dev/atkbdc/atkbdc_isa.c          | 10 +++---
 sys/dev/atkbdc/atkbdc_subr.c         |  2 +-
 sys/dev/cs/if_cs.c                   |  2 +-
 sys/dev/ctau/if_ct.c                 | 10 +++---
 sys/dev/cx/if_cx.c                   | 10 +++---
 sys/dev/ed/if_ed_3c503.c             |  2 +-
 sys/dev/ed/if_ed_cbus.c              | 12 +++----
 sys/dev/ed/if_ed_hpp.c               |  2 +-
 sys/dev/ed/if_ed_wd80x3.c            |  2 +-
 sys/dev/eisa/eisaconf.c              |  2 +-
 sys/dev/fdt/simplebus.c              |  4 +--
 sys/dev/fe/if_fe_cbus.c              | 14 ++++----
 sys/dev/fe/if_fe_isa.c               | 12 +++----
 sys/dev/gpio/gpiobus.c               |  4 +--
 sys/dev/mca/mca_bus.c                |  2 +-
 sys/dev/mvs/mvs_pci.c                |  3 +-
 sys/dev/mvs/mvs_soc.c                |  2 +-
 sys/dev/ncv/ncr53c500_pccard.c       |  2 +-
 sys/dev/nsp/nsp_pccard.c             |  2 +-
 sys/dev/ofw/ofwbus.c                 |  4 +--
 sys/dev/pccard/pccard.c              | 20 +++++------
 sys/dev/pccard/pccardvarp.h          | 10 +++---
 sys/dev/pccbb/pccbb.c                | 12 +++----
 sys/dev/pccbb/pccbb_pci.c            |  4 +--
 sys/dev/pccbb/pccbbvar.h             |  2 +-
 sys/dev/pcf/pcf_isa.c                |  2 +-
 sys/dev/pci/hostb_pci.c              |  2 +-
 sys/dev/pci/isa_pci.c                |  6 ++--
 sys/dev/pci/pci.c                    | 14 ++++----
 sys/dev/pci/pci_host_generic.c       |  8 ++---
 sys/dev/pci/pci_iov.c                |  8 ++---
 sys/dev/pci/pci_pci.c                | 47 +++++++++++++-------------
 sys/dev/pci/pci_private.h            | 12 +++----
 sys/dev/pci/pci_subr.c               | 16 ++++-----
 sys/dev/pci/pcib_private.h           | 21 ++++++------
 sys/dev/pci/pcivar.h                 |  4 +--
 sys/dev/pci/vga_pci.c                |  5 +--
 sys/dev/ppc/ppc.c                    |  4 +--
 sys/dev/ppc/ppcvar.h                 |  2 +-
 sys/dev/puc/puc.c                    |  8 ++---
 sys/dev/puc/puc_bfe.h                |  6 ++--
 sys/dev/quicc/quicc_bfe.h            |  5 +--
 sys/dev/quicc/quicc_core.c           |  6 ++--
 sys/dev/scc/scc_bfe.h                |  4 +--
 sys/dev/scc/scc_core.c               |  6 ++--
 sys/dev/siba/siba.c                  |  6 ++--
 sys/dev/siba/siba_bwn.c              |  2 +-
 sys/dev/siba/siba_pcib.c             |  4 +--
 sys/dev/siis/siis.c                  |  2 +-
 sys/dev/snc/if_snc_cbus.c            |  2 +-
 sys/dev/sound/isa/gusc.c             |  4 +--
 sys/dev/sound/isa/sbc.c              |  4 +--
 sys/dev/sound/pci/csa.c              |  5 +--
 sys/dev/sound/pci/fm801.c            |  3 +-
 sys/dev/sound/pci/vibes.c            |  3 +-
 sys/dev/stg/tmc18c30_subr.c          |  2 +-
 sys/dev/wl/if_wl.c                   |  2 +-
 sys/isa/isa_common.c                 |  2 +-
 sys/isa/isa_common.h                 |  3 +-
 sys/kern/bus_if.m                    | 22 ++++++------
 sys/kern/subr_bus.c                  | 42 ++++++++++++-----------
 sys/kern/subr_rman.c                 | 32 +++++++++---------
 sys/mips/adm5120/admpci.c            |  2 +-
 sys/mips/adm5120/obio.c              |  6 ++--
 sys/mips/alchemy/obio.c              |  6 ++--
 sys/mips/atheros/apb.c               |  6 ++--
 sys/mips/atheros/ar71xx_pci.c        |  2 +-
 sys/mips/atheros/ar724x_pci.c        |  2 +-
 sys/mips/atheros/qca955x_pci.c       |  2 +-
 sys/mips/beri/beri_simplebus.c       |  4 +--
 sys/mips/cavium/ciu.c                |  5 +--
 sys/mips/cavium/obio.c               |  2 +-
 sys/mips/cavium/octopci.c            |  5 +--
 sys/mips/idt/idtpci.c                |  2 +-
 sys/mips/idt/obio.c                  |  6 ++--
 sys/mips/malta/gt.c                  |  2 +-
 sys/mips/malta/gt_pci.c              |  4 +--
 sys/mips/malta/obio.c                |  2 +-
 sys/mips/mips/cpu.c                  |  5 +--
 sys/mips/mips/nexus.c                | 18 +++++-----
 sys/mips/nlm/xlp_simplebus.c         |  4 +--
 sys/mips/rmi/iodi.c                  |  4 +--
 sys/mips/rmi/xlr_pci.c               |  2 +-
 sys/mips/rt305x/obio.c               |  6 ++--
 sys/mips/rt305x/rt305x_gpio.c        |  2 +-
 sys/mips/rt305x/rt305x_pci.c         |  2 +-
 sys/mips/sentry5/obio.c              |  2 +-
 sys/mips/sibyte/sb_zbbus.c           |  2 +-
 sys/mips/sibyte/sb_zbpci.c           |  2 +-
 sys/pc98/pc98/canbus.c               |  9 ++---
 sys/powerpc/mpc85xx/lbc.c            |  4 +--
 sys/powerpc/ofw/ofw_pci.c            | 12 +++----
 sys/powerpc/powermac/macgpio.c       |  5 +--
 sys/powerpc/powermac/macio.c         |  6 ++--
 sys/powerpc/powermac/uninorth.c      |  6 ++--
 sys/powerpc/psim/ata_iobus.c         |  6 ++--
 sys/powerpc/psim/iobus.c             |  6 ++--
 sys/sparc64/central/central.c        |  6 ++--
 sys/sparc64/ebus/ebus.c              |  6 ++--
 sys/sparc64/fhc/fhc.c                |  6 ++--
 sys/sparc64/isa/isa.c                |  2 +-
 sys/sparc64/pci/apb.c                |  8 ++---
 sys/sparc64/pci/fire.c               |  2 +-
 sys/sparc64/pci/ofw_pci.c            |  4 +--
 sys/sparc64/pci/psycho.c             |  2 +-
 sys/sparc64/pci/sbbc.c               |  6 ++--
 sys/sparc64/pci/schizo.c             |  2 +-
 sys/sparc64/sbus/sbus.c              |  4 +--
 sys/sparc64/sparc64/nexus.c          |  4 +--
 sys/sparc64/sparc64/upa.c            |  8 ++---
 sys/sys/_types.h                     |  2 ++
 sys/sys/bus.h                        | 50 ++++++++++++++--------------
 sys/sys/rman.h                       | 40 +++++++++++-----------
 sys/sys/types.h                      |  2 ++
 sys/x86/include/legacyvar.h          |  5 +--
 sys/x86/include/pci_cfgreg.h         |  2 +-
 sys/x86/isa/atrtc.c                  |  2 +-
 sys/x86/isa/clock.c                  |  2 +-
 sys/x86/isa/isa.c                    |  2 +-
 sys/x86/pci/pci_bus.c                |  8 ++---
 sys/x86/pci/qpi.c                    |  2 +-
 sys/x86/x86/mptable_pci.c            |  8 ++---
 sys/x86/x86/nexus.c                  | 22 +++++++-----
 162 files changed, 538 insertions(+), 491 deletions(-)

diff --git a/lib/libdevinfo/devinfo.3 b/lib/libdevinfo/devinfo.3
index ee094dd62f86..9628a9ac9c20 100644
--- a/lib/libdevinfo/devinfo.3
+++ b/lib/libdevinfo/devinfo.3
@@ -110,8 +110,8 @@ struct devinfo_dev {
 
 struct devinfo_rman {
     devinfo_handle_t	dm_handle;	/* resource manager handle */
-    u_long		dm_start;	/* resource start */
-    u_long		dm_size;	/* resource size */
+    rman_res_t		dm_start;	/* resource start */
+    rman_res_t		dm_size;	/* resource size */
     char		*dm_desc;	/* resource description */
 };
 
@@ -119,8 +119,8 @@ struct devinfo_res {
     devinfo_handle_t	dr_handle;	/* resource handle */
     devinfo_handle_t	dr_rman;	/* resource manager handle */
     devinfo_handle_t	dr_device;	/* owning device */
-    u_long		dr_start;	/* region start */
-    u_long		dr_size;	/* region size */
+    rman_res_t		dr_start;	/* region start */
+    rman_res_t		dr_size;	/* region size */
 };
 .Ed
 .Pp
diff --git a/lib/libdevinfo/devinfo.h b/lib/libdevinfo/devinfo.h
index b0b8cec49f36..f94644600aeb 100644
--- a/lib/libdevinfo/devinfo.h
+++ b/lib/libdevinfo/devinfo.h
@@ -56,8 +56,8 @@ struct devinfo_dev {
 struct devinfo_rman {
 	devinfo_handle_t	dm_handle;	/* resource manager handle */
 
-	unsigned long		dm_start;	/* resource start */
-	unsigned long		dm_size;	/* resource size */
+	rman_res_t		dm_start;	/* resource start */
+	rman_res_t		dm_size;	/* resource size */
     
 	char			*dm_desc;	/* resource description */
 };
@@ -67,8 +67,8 @@ struct devinfo_res {
 	devinfo_handle_t	dr_rman;	/* resource manager handle */
 	devinfo_handle_t	dr_device;	/* owning device */
 
-	unsigned long		dr_start;	/* region start */
-	unsigned long		dr_size;	/* region size */
+	rman_res_t		dr_start;	/* region start */
+	rman_res_t		dr_size;	/* region size */
 	/* XXX add flags */
 };
 
diff --git a/share/man/man9/bus_adjust_resource.9 b/share/man/man9/bus_adjust_resource.9
index b7c477a8be23..6f561b938f37 100644
--- a/share/man/man9/bus_adjust_resource.9
+++ b/share/man/man9/bus_adjust_resource.9
@@ -41,7 +41,8 @@
 .In sys/rman.h
 .In machine/resource.h
 .Ft int
-.Fn bus_adjust_resource "device_t dev" "int type" "struct resource *r" "u_long start" "u_long end"
+.Fo bus_adjust_resource
+.Fa "device_t dev" "int type" "struct resource *r" "rman_res_t start" "rman_res_t end"
 .Sh DESCRIPTION
 This function is used to ask the parent bus to adjust the resource range
 assigned to an allocated resource.
diff --git a/share/man/man9/bus_alloc_resource.9 b/share/man/man9/bus_alloc_resource.9
index 78959a02a1cf..d579f9a7eee7 100644
--- a/share/man/man9/bus_alloc_resource.9
+++ b/share/man/man9/bus_alloc_resource.9
@@ -43,7 +43,10 @@
 .In sys/rman.h
 .In machine/resource.h
 .Ft struct resource *
-.Fn bus_alloc_resource "device_t dev" "int type" "int *rid" "u_long start" "u_long end" "u_long count" "u_int flags"
+.Fo bus_alloc_resource
+.Fa "device_t dev" "int type" "int *rid" "rman_res_t start" "rman_res_t end"
+.Fa "rman_res_t count" "u_int flags"
+.Fc
 .Ft struct resource *
 .Fn bus_alloc_resource_any "device_t dev" "int type" "int *rid" "u_int flags"
 .Sh DESCRIPTION
diff --git a/share/man/man9/bus_get_resource.9 b/share/man/man9/bus_get_resource.9
index 2f6898a748c8..33fc2e24ca74 100644
--- a/share/man/man9/bus_get_resource.9
+++ b/share/man/man9/bus_get_resource.9
@@ -44,7 +44,7 @@
 .In sys/rman.h
 .Ft int
 .Fo bus_get_resource
-.Fa "device_t dev" "int type" "int rid" "u_long *startp" "u_long *countp"
+.Fa "device_t dev" "int type" "int rid" "rman_res_t *startp" "rman_res_t *countp"
 .Fc
 .Sh DESCRIPTION
 The
diff --git a/share/man/man9/bus_set_resource.9 b/share/man/man9/bus_set_resource.9
index 2eb24bf5db1e..b8d8409098a7 100644
--- a/share/man/man9/bus_set_resource.9
+++ b/share/man/man9/bus_set_resource.9
@@ -43,7 +43,7 @@
 .In machine/resource.h
 .Ft int
 .Fo bus_set_resource
-.Fa "device_t dev" "int type" "int rid" "u_long start" "u_long count"
+.Fa "device_t dev" "int type" "int rid" "rman_res_t start" "rman_res_t count"
 .Fc
 .Sh DESCRIPTION
 The
diff --git a/share/man/man9/rman.9 b/share/man/man9/rman.9
index a14f68680f7e..6787cea5a732 100644
--- a/share/man/man9/rman.9
+++ b/share/man/man9/rman.9
@@ -65,7 +65,7 @@
 .Ft int
 .Fn rman_activate_resource "struct resource *r"
 .Ft int
-.Fn rman_adjust_resource "struct resource *r" "u_long start" "u_long end"
+.Fn rman_adjust_resource "struct resource *r" "rman_res_t start" "rman_res_t end"
 .Ft int
 .Fn rman_await_resource "struct resource *r" "int pri2" "int timo"
 .Ft int
@@ -79,32 +79,32 @@
 .Ft int
 .Fn rman_is_region_manager "struct resource *r" "struct rman *rm"
 .Ft int
-.Fn rman_manage_region "struct rman *rm" "u_long start" "u_long end"
+.Fn rman_manage_region "struct rman *rm" "rman_res_t start" "rman_res_t end"
 .Ft int
-.Fn rman_first_free_region "struct rman *rm" "u_long *start" "u_long *end"
+.Fn rman_first_free_region "struct rman *rm" "rman_res_t *start" "rman_res_t *end"
 .Ft int
-.Fn rman_last_free_region "struct rman *rm" "u_long *start" "u_long *end"
+.Fn rman_last_free_region "struct rman *rm" "rman_res_t *start" "rman_res_t *end"
 .Ft int
 .Fn rman_release_resource "struct resource *r"
 .Ft "struct resource *"
 .Fo rman_reserve_resource
-.Fa "struct rman *rm" "u_long start" "u_long end" "u_long count"
+.Fa "struct rman *rm" "rman_res_t start" "rman_res_t end" "rman_res_t count"
 .Fa "u_int flags" "struct device *dev"
 .Fc
 .Ft "struct resource *"
 .Fo rman_reserve_resource_bound
-.Fa "struct rman *rm" "u_long start" "u_long end" "u_long count"
-.Fa "u_long bound" "u_int flags" "struct device *dev"
+.Fa "struct rman *rm" "rman_res_t start" "rman_res_t end" "rman_res_t count"
+.Fa "rman_res_t bound" "u_int flags" "struct device *dev"
 .Fc
 .Ft uint32_t
 .Fn rman_make_alignment_flags "uint32_t size"
-.Ft u_long
+.Ft rman_res_t
 .Fn rman_get_start "struct resource *r"
-.Ft u_long
+.Ft rman_res_t
 .Fn rman_get_end "struct resource *r"
 .Ft "struct device *"
 .Fn rman_get_device "struct resource *r"
-.Ft u_long
+.Ft rman_res_t
 .Fn rman_get_size "struct resource *r"
 .Ft u_int
 .Fn rman_get_flags "struct resource *r"
diff --git a/sys/arm/arm/nexus.c b/sys/arm/arm/nexus.c
index 8dce36c99900..97e9e2595335 100644
--- a/sys/arm/arm/nexus.c
+++ b/sys/arm/arm/nexus.c
@@ -82,7 +82,7 @@ static	int nexus_attach(device_t);
 static	int nexus_print_child(device_t, device_t);
 static	device_t nexus_add_child(device_t, u_int, const char *, int);
 static	struct resource *nexus_alloc_resource(device_t, device_t, int, int *,
-    u_long, u_long, u_long, u_int);
+    rman_res_t, rman_res_t, rman_res_t, u_int);
 static	int nexus_activate_resource(device_t, device_t, int, int,
     struct resource *);
 #ifdef ARM_INTRNG
@@ -212,7 +212,7 @@ nexus_add_child(device_t bus, u_int order, const char *name, int unit)
  */
 static struct resource *
 nexus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *rv;
 	struct rman *rm;
diff --git a/sys/arm/at91/at91.c b/sys/arm/at91/at91.c
index 8b94dc627a77..0b0d9118c9f0 100644
--- a/sys/arm/at91/at91.c
+++ b/sys/arm/at91/at91.c
@@ -147,7 +147,7 @@ at91_attach(device_t dev)
 
 static struct resource *
 at91_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct at91_softc *sc = device_get_softc(dev);
 	struct resource_list_entry *rle;
@@ -255,7 +255,7 @@ at91_activate_resource(device_t bus, device_t child, int type, int rid,
     struct resource *r)
 {
 #if 0
-	u_long p;
+	rman_res_t p;
 	int error;
 	
 	if (type == SYS_RES_MEMORY) {
diff --git a/sys/arm/cavium/cns11xx/econa.c b/sys/arm/cavium/cns11xx/econa.c
index b9446f09606d..29f09044d2ce 100644
--- a/sys/arm/cavium/cns11xx/econa.c
+++ b/sys/arm/cavium/cns11xx/econa.c
@@ -408,7 +408,7 @@ econa_attach(device_t dev)
 
 static struct resource *
 econa_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct econa_softc *sc = device_get_softc(dev);
 	struct resource_list_entry *rle;
diff --git a/sys/arm/mv/mv_localbus.c b/sys/arm/mv/mv_localbus.c
index 59cccc475fb8..cb1fbcc5287e 100644
--- a/sys/arm/mv/mv_localbus.c
+++ b/sys/arm/mv/mv_localbus.c
@@ -100,7 +100,7 @@ static int localbus_attach(device_t);
 static int localbus_print_child(device_t, device_t);
 
 static struct resource *localbus_alloc_resource(device_t, device_t, int,
-    int *, u_long, u_long, u_long, u_int);
+    int *, rman_res_t, rman_res_t, rman_res_t, u_int);
 static struct resource_list *localbus_get_resource_list(device_t, device_t);
 
 static ofw_bus_get_devinfo_t localbus_get_devinfo;
@@ -332,7 +332,7 @@ localbus_print_child(device_t dev, device_t child)
 
 static struct resource *
 localbus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct localbus_devinfo *di;
 	struct resource_list_entry *rle;
diff --git a/sys/arm/mv/mv_pci.c b/sys/arm/mv/mv_pci.c
index 05dcbbc60b10..2dd45eb70528 100644
--- a/sys/arm/mv/mv_pci.c
+++ b/sys/arm/mv/mv_pci.c
@@ -332,7 +332,7 @@ static int mv_pcib_probe(device_t);
 static int mv_pcib_attach(device_t);
 
 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
-    u_long, u_long, u_long, u_int);
+    rman_res_t, rman_res_t, rman_res_t, u_int);
 static int mv_pcib_release_resource(device_t, device_t, int, int,
     struct resource *);
 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
@@ -830,7 +830,7 @@ mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
 
 static struct resource *
 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct mv_pcib_softc *sc = device_get_softc(dev);
 	struct rman *rm = NULL;
diff --git a/sys/arm/versatile/versatile_pci.c b/sys/arm/versatile/versatile_pci.c
index 8a5c0105aeb1..0bc49264c7e1 100644
--- a/sys/arm/versatile/versatile_pci.c
+++ b/sys/arm/versatile/versatile_pci.c
@@ -305,7 +305,7 @@ versatile_pci_write_ivar(device_t dev, device_t child, int which,
 
 static struct resource *
 versatile_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 
 	struct versatile_pci_softc *sc = device_get_softc(bus);
diff --git a/sys/arm/xscale/i8134x/i81342.c b/sys/arm/xscale/i8134x/i81342.c
index 49d658ae2d53..7a6b315661fc 100644
--- a/sys/arm/xscale/i8134x/i81342.c
+++ b/sys/arm/xscale/i8134x/i81342.c
@@ -409,7 +409,7 @@ i81342_attach(device_t dev)
 
 static struct resource *
 i81342_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct i81342_softc *sc = device_get_softc(dev);
 	struct resource *rv;
diff --git a/sys/arm/xscale/i8134x/i81342_pci.c b/sys/arm/xscale/i8134x/i81342_pci.c
index d9d978c8a4bc..d17fb1409ef5 100644
--- a/sys/arm/xscale/i8134x/i81342_pci.c
+++ b/sys/arm/xscale/i8134x/i81342_pci.c
@@ -328,7 +328,7 @@ i81342_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
 
 static struct resource *
 i81342_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-   u_long start, u_long end, u_long count, u_int flags)
+   rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct i81342_pci_softc *sc = device_get_softc(bus);	
 	struct resource *rv;
@@ -383,7 +383,7 @@ static int
 i81342_pci_activate_resource(device_t bus, device_t child, int type, int rid,
     struct resource *r)
 {
-	u_long p;
+	bus_space_handle_t p;
 	int error;
 	
 	if (type == SYS_RES_MEMORY) {
diff --git a/sys/arm/xscale/i8134x/obio.c b/sys/arm/xscale/i8134x/obio.c
index 5aa3c477d2e2..f61893befdac 100644
--- a/sys/arm/xscale/i8134x/obio.c
+++ b/sys/arm/xscale/i8134x/obio.c
@@ -91,7 +91,7 @@ obio_attach(device_t dev)
 
 static struct resource *
 obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *rv;
 	struct rman *rm;
diff --git a/sys/arm/xscale/ixp425/avila_ata.c b/sys/arm/xscale/ixp425/avila_ata.c
index 217cfc8d405d..e3a9a520c6c5 100644
--- a/sys/arm/xscale/ixp425/avila_ata.c
+++ b/sys/arm/xscale/ixp425/avila_ata.c
@@ -282,7 +282,7 @@ ata_avila_intr(void *xsc)
 
 static struct resource *
 ata_avila_alloc_resource(device_t dev, device_t child, int type, int *rid,
-		       u_long start, u_long end, u_long count, u_int flags)
+		   rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct ata_avila_softc *sc = device_get_softc(dev);
 
diff --git a/sys/arm/xscale/ixp425/ixp425.c b/sys/arm/xscale/ixp425/ixp425.c
index 07c491aa573f..017d56750fb4 100644
--- a/sys/arm/xscale/ixp425/ixp425.c
+++ b/sys/arm/xscale/ixp425/ixp425.c
@@ -496,7 +496,7 @@ getvbase(uint32_t hwbase, uint32_t size, uint32_t *vbase)
 
 static struct resource *
 ixp425_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct ixp425_softc *sc = device_get_softc(dev);
 	const struct hwvtrans *vtrans;
diff --git a/sys/arm/xscale/ixp425/ixp425_pci.c b/sys/arm/xscale/ixp425/ixp425_pci.c
index 9bda385cf8fd..d9878783b40e 100644
--- a/sys/arm/xscale/ixp425/ixp425_pci.c
+++ b/sys/arm/xscale/ixp425/ixp425_pci.c
@@ -269,7 +269,7 @@ ixppcib_teardown_intr(device_t dev, device_t child, struct resource *vec,
 
 static struct resource *
 ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct ixppcib_softc *sc = device_get_softc(bus);
 	struct rman *rmanp;
diff --git a/sys/arm/xscale/pxa/pxa_obio.c b/sys/arm/xscale/pxa/pxa_obio.c
index 8b3591093ad3..6761ca37ba93 100644
--- a/sys/arm/xscale/pxa/pxa_obio.c
+++ b/sys/arm/xscale/pxa/pxa_obio.c
@@ -50,14 +50,14 @@ static int	pxa_read_ivar(device_t, device_t, int, uintptr_t *);
 
 static struct resource_list *	pxa_get_resource_list(device_t, device_t);
 static struct resource *	pxa_alloc_resource(device_t, device_t, int,
-				    int *, u_long, u_long, u_long, u_int);
+				    int *, rman_res_t, rman_res_t, rman_res_t, u_int);
 static int			pxa_release_resource(device_t, device_t, int,
 				    int, struct resource *);
 static int			pxa_activate_resource(device_t, device_t,
 				    int, int, struct resource *);
 
 static struct resource *	pxa_alloc_gpio_irq(device_t, device_t, int,
-				    int *, u_long, u_long, u_long, u_int);
+				    int *, rman_res_t, rman_res_t, rman_res_t, u_int);
 
 struct obio_device {
 	const char	*od_name;
@@ -224,7 +224,7 @@ pxa_get_resource_list(device_t dev, device_t child)
 
 static struct resource *
 pxa_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct	obio_softc *sc;
 	struct	obio_device *od;
@@ -351,7 +351,7 @@ DRIVER_MODULE(pxa, nexus, pxa_driver, pxa_devclass, 0, 0);
 
 static struct resource *
 pxa_alloc_gpio_irq(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct	obio_softc *sc;
 	struct	obio_device *od;
diff --git a/sys/arm/xscale/pxa/pxa_smi.c b/sys/arm/xscale/pxa/pxa_smi.c
index f25dac771234..4c49e75f6d53 100644
--- a/sys/arm/xscale/pxa/pxa_smi.c
+++ b/sys/arm/xscale/pxa/pxa_smi.c
@@ -70,7 +70,7 @@ static int	pxa_smi_print_child(device_t, device_t);
 static int	pxa_smi_read_ivar(device_t, device_t, int, uintptr_t *);
 
 static struct resource *	pxa_smi_alloc_resource(device_t, device_t,
-				    int, int *, u_long, u_long, u_long, u_int);
+				    int, int *, rman_res_t, rman_res_t, rman_res_t, u_int);
 static int			pxa_smi_release_resource(device_t, device_t,
 				    int, int, struct resource *);
 static int			pxa_smi_activate_resource(device_t, device_t,
@@ -176,7 +176,7 @@ pxa_smi_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 
 static struct resource *
 pxa_smi_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct	pxa_smi_softc *sc;
 	struct	smi_ivars *smid;
diff --git a/sys/arm64/arm64/gic_v3_fdt.c b/sys/arm64/arm64/gic_v3_fdt.c
index 79075f2a4239..6c8de4929caf 100644
--- a/sys/arm64/arm64/gic_v3_fdt.c
+++ b/sys/arm64/arm64/gic_v3_fdt.c
@@ -54,7 +54,7 @@ static int gic_v3_fdt_probe(device_t);
 static int gic_v3_fdt_attach(device_t);
 
 static struct resource *gic_v3_ofw_bus_alloc_res(device_t, device_t, int, int *,
-    u_long, u_long, u_long, u_int);
+    rman_res_t, rman_res_t, rman_res_t, u_int);
 static const struct ofw_bus_devinfo *gic_v3_ofw_get_devinfo(device_t, device_t);
 
 static device_method_t gic_v3_fdt_methods[] = {
@@ -174,7 +174,7 @@ gic_v3_ofw_get_devinfo(device_t bus __unused, device_t child)
 
 static struct resource *
 gic_v3_ofw_bus_alloc_res(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct gic_v3_ofw_devinfo *di;
 	struct resource_list_entry *rle;
diff --git a/sys/arm64/arm64/nexus.c b/sys/arm64/arm64/nexus.c
index ec1fe84117c7..8290cffca792 100644
--- a/sys/arm64/arm64/nexus.c
+++ b/sys/arm64/arm64/nexus.c
@@ -99,13 +99,14 @@ static device_attach_t	nexus_acpi_attach;
 static	int nexus_print_child(device_t, device_t);
 static	device_t nexus_add_child(device_t, u_int, const char *, int);
 static	struct resource *nexus_alloc_resource(device_t, device_t, int, int *,
-    u_long, u_long, u_long, u_int);
+    rman_res_t, rman_res_t, rman_res_t, u_int);
 static	int nexus_activate_resource(device_t, device_t, int, int,
     struct resource *);
 static int nexus_config_intr(device_t dev, int irq, enum intr_trigger trig,
     enum intr_polarity pol);
 static struct resource_list *nexus_get_reslist(device_t, device_t);
-static	int nexus_set_resource(device_t, device_t, int, int, u_long, u_long);
+static	int nexus_set_resource(device_t, device_t, int, int,
+    rman_res_t, rman_res_t);
 static	int nexus_deactivate_resource(device_t, device_t, int, int,
     struct resource *);
 
@@ -201,7 +202,7 @@ nexus_add_child(device_t bus, u_int order, const char *name, int unit)
  */
 static struct resource *
 nexus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct nexus_device *ndev = DEVTONX(child);
 	struct resource *rv;
@@ -332,7 +333,7 @@ nexus_get_reslist(device_t dev, device_t child)
 
 static int
 nexus_set_resource(device_t dev, device_t child, int type, int rid,
-    u_long start, u_long count)
+    rman_res_t start, rman_res_t count)
 {
 	struct nexus_device	*ndev = DEVTONX(child);
 	struct resource_list	*rl = &ndev->nx_resources;
diff --git a/sys/arm64/cavium/thunder_pcie.c b/sys/arm64/cavium/thunder_pcie.c
index 20aab1e09866..9785739a858f 100644
--- a/sys/arm64/cavium/thunder_pcie.c
+++ b/sys/arm64/cavium/thunder_pcie.c
@@ -110,7 +110,7 @@ SYSCTL_INT(_hw, OID_AUTO, thunder_pcie_max_vfs, CTLFLAG_RWTUN,
 
 /* Forward prototypes */
 static struct resource *thunder_pcie_alloc_resource(device_t,
-    device_t, int, int *, u_long, u_long, u_long, u_int);
+    device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int);
 static int thunder_pcie_attach(device_t);
 static int thunder_pcie_identify_pcib(device_t);
 static int thunder_pcie_maxslots(device_t);
@@ -431,7 +431,7 @@ thunder_pcie_release_resource(device_t dev, device_t child, int type, int rid,
 
 static struct resource *
 thunder_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct thunder_pcie_softc *sc = device_get_softc(dev);
 	struct rman *rm = NULL;
@@ -519,7 +519,7 @@ static int
 thunder_pcie_identify_pcib(device_t dev)
 {
 	struct thunder_pcie_softc *sc;
-	u_long start;
+	rman_res_t start;
 
 	sc = device_get_softc(dev);
 	start = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);
diff --git a/sys/arm64/cavium/thunder_pcie_pem.c b/sys/arm64/cavium/thunder_pcie_pem.c
index e5007ac7716a..e4406c3e3673 100644
--- a/sys/arm64/cavium/thunder_pcie_pem.c
+++ b/sys/arm64/cavium/thunder_pcie_pem.c
@@ -126,7 +126,7 @@ struct thunder_pem_softc {
 };
 
 static struct resource * thunder_pem_alloc_resource(device_t, device_t, int,
-    int *, u_long, u_long, u_long, u_int);
+    int *, rman_res_t, rman_res_t, rman_res_t, u_int);
 static int thunder_pem_attach(device_t);
 static int thunder_pem_detach(device_t);
 static uint64_t thunder_pem_config_reg_read(struct thunder_pem_softc *, int);
@@ -230,7 +230,7 @@ static int
 thunder_pem_identify(device_t dev)
 {
 	struct thunder_pem_softc *sc;
-	u_long start;
+	rman_res_t start;
 
 	sc = device_get_softc(dev);
 	start = rman_get_start(sc->reg);
@@ -426,7 +426,7 @@ thunder_pem_write_config(device_t dev, u_int bus, u_int slot,
 
 static struct resource *
 thunder_pem_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct thunder_pem_softc *sc = device_get_softc(dev);
 	struct rman *rm = NULL;
diff --git a/sys/dev/acpica/acpi.c b/sys/dev/acpica/acpi.c
index 0593235c97df..686bbc834b77 100644
--- a/sys/dev/acpica/acpi.c
+++ b/sys/dev/acpica/acpi.c
@@ -121,12 +121,12 @@ static struct resource_list *acpi_get_rlist(device_t dev, device_t child);
 static void	acpi_reserve_resources(device_t dev);
 static int	acpi_sysres_alloc(device_t dev);
 static int	acpi_set_resource(device_t dev, device_t child, int type,
-			int rid, u_long start, u_long count);
+			int rid, rman_res_t start, rman_res_t count);
 static struct resource *acpi_alloc_resource(device_t bus, device_t child,
-			int type, int *rid, u_long start, u_long end,
-			u_long count, u_int flags);
+			int type, int *rid, rman_res_t start, rman_res_t end,
+			rman_res_t count, u_int flags);
 static int	acpi_adjust_resource(device_t bus, device_t child, int type,
-			struct resource *r, u_long start, u_long end);
+			struct resource *r, rman_res_t start, rman_res_t end);
 static int	acpi_release_resource(device_t bus, device_t child, int type,
 			int rid, struct resource *r);
 static void	acpi_delete_resource(device_t bus, device_t child, int type,
@@ -1247,13 +1247,13 @@ acpi_reserve_resources(device_t dev)
 
 static int
 acpi_set_resource(device_t dev, device_t child, int type, int rid,
-    u_long start, u_long count)
+    rman_res_t start, rman_res_t count)
 {
     struct acpi_softc *sc = device_get_softc(dev);
     struct acpi_device *ad = device_get_ivars(child);
     struct resource_list *rl = &ad->ad_rl;
     ACPI_DEVICE_INFO *devinfo;
-    u_long end;
+    rman_res_t end;
     
     /* Ignore IRQ resources for PCI link devices. */
     if (type == SYS_RES_IRQ && ACPI_ID_PROBE(dev, child, pcilink_ids) != NULL)
@@ -1323,7 +1323,7 @@ acpi_set_resource(device_t dev, device_t child, int type, int rid,
 
 static struct resource *
 acpi_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
     ACPI_RESOURCE ares;
     struct acpi_device *ad;
@@ -1399,8 +1399,8 @@ acpi_alloc_resource(device_t bus, device_t child, int type, int *rid,
  * system resources.
  */
 struct resource *
-acpi_alloc_sysres(device_t child, int type, int *rid, u_long start, u_long end,
-    u_long count, u_int flags)
+acpi_alloc_sysres(device_t child, int type, int *rid, rman_res_t start,
+    rman_res_t end, rman_res_t count, u_int flags)
 {
     struct rman *rm;
     struct resource *res;
@@ -1450,7 +1450,7 @@ acpi_is_resource_managed(int type, struct resource *r)
 
 static int
 acpi_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
-    u_long start, u_long end)
+    rman_res_t start, rman_res_t end)
 {
 
     if (acpi_is_resource_managed(type, r))
diff --git a/sys/dev/acpica/acpi_hpet.c b/sys/dev/acpica/acpi_hpet.c
index 0da8bae30716..1b5a161eabba 100644
--- a/sys/dev/acpica/acpi_hpet.c
+++ b/sys/dev/acpica/acpi_hpet.c
@@ -322,7 +322,7 @@ hpet_find(ACPI_HANDLE handle, UINT32 level, void *context,
 static int
 hpet_find_irq_rid(device_t dev, u_long start, u_long end)
 {
-	u_long irq;
+	rman_res_t irq;
 	int error, rid;
 
 	for (rid = 0;; rid++) {
diff --git a/sys/dev/acpica/acpi_pcib_acpi.c b/sys/dev/acpica/acpi_pcib_acpi.c
index 490f2779512f..ef909549c88d 100644
--- a/sys/dev/acpica/acpi_pcib_acpi.c
+++ b/sys/dev/acpica/acpi_pcib_acpi.c
@@ -91,12 +91,12 @@ static int		acpi_pcib_alloc_msix(device_t pcib, device_t dev,
 			    int *irq);
 static struct resource *acpi_pcib_acpi_alloc_resource(device_t dev,
 			    device_t child, int type, int *rid,
-			    u_long start, u_long end, u_long count,
+			    rman_res_t start, rman_res_t end, rman_res_t count,
 			    u_int flags);
 #ifdef NEW_PCIB
 static int		acpi_pcib_acpi_adjust_resource(device_t dev,
 			    device_t child, int type, struct resource *r,
-			    u_long start, u_long end);
+			    rman_res_t start, rman_res_t end);
 #ifdef PCI_RES_BUS
 static int		acpi_pcib_acpi_release_resource(device_t dev,
 			    device_t child, int type, int rid,
@@ -283,7 +283,7 @@ acpi_pcib_producer_handler(ACPI_RESOURCE *res, void *context)
 
 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
 static int
-first_decoded_bus(struct acpi_hpcib_softc *sc, u_long *startp)
+first_decoded_bus(struct acpi_hpcib_softc *sc, rman_res_t *startp)
 {
 	struct resource_list_entry *rle;
 
@@ -304,7 +304,7 @@ acpi_pcib_acpi_attach(device_t dev)
     u_int slot, func, busok;
 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
     struct resource *bus_res;
-    u_long start;
+    rman_res_t start;
     int rid;
 #endif
     uint8_t busno;
@@ -584,7 +584,7 @@ acpi_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
 
 struct resource *
 acpi_pcib_acpi_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 #ifdef NEW_PCIB
     struct acpi_hpcib_softc *sc;
@@ -625,7 +625,7 @@ acpi_pcib_acpi_alloc_resource(device_t dev, device_t child, int type, int *rid,
 #ifdef NEW_PCIB
 int
 acpi_pcib_acpi_adjust_resource(device_t dev, device_t child, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 	struct acpi_hpcib_softc *sc;
 
diff --git a/sys/dev/acpica/acpi_resource.c b/sys/dev/acpica/acpi_resource.c
index f8936a53c572..078ecce1eb0a 100644
--- a/sys/dev/acpica/acpi_resource.c
+++ b/sys/dev/acpica/acpi_resource.c
@@ -671,7 +671,7 @@ acpi_sysres_attach(device_t dev)
     struct resource_list_entry *bus_rle, *dev_rle;
     struct resource_list *bus_rl, *dev_rl;
     int done, type;
-    u_long start, end, count;
+    rman_res_t start, end, count;
 
     /*
      * Loop through all current resources to see if the new one overlaps
diff --git a/sys/dev/acpica/acpi_timer.c b/sys/dev/acpica/acpi_timer.c
index 296e38f273a7..2cdf90805d2c 100644
--- a/sys/dev/acpica/acpi_timer.c
+++ b/sys/dev/acpica/acpi_timer.c
@@ -122,7 +122,7 @@ static void
 acpi_timer_identify(driver_t *driver, device_t parent)
 {
     device_t dev;
-    u_long rlen, rstart;
+    rman_res_t rlen, rstart;
     int rid, rtype;
 
     ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
diff --git a/sys/dev/acpica/acpivar.h b/sys/dev/acpica/acpivar.h
index cbd4bd97b9d8..4f601c96fef0 100644
--- a/sys/dev/acpica/acpivar.h
+++ b/sys/dev/acpica/acpivar.h
@@ -383,7 +383,8 @@ ACPI_STATUS	acpi_lookup_irq_resource(device_t dev, int rid,
 ACPI_STATUS	acpi_parse_resources(device_t dev, ACPI_HANDLE handle,
 		    struct acpi_parse_resource_set *set, void *arg);
 struct resource *acpi_alloc_sysres(device_t child, int type, int *rid,
-		    u_long start, u_long end, u_long count, u_int flags);
+		    rman_res_t start, rman_res_t end, rman_res_t count,
+		    u_int flags);
 
 /* ACPI event handling */
 UINT32		acpi_event_power_button_sleep(void *context);
diff --git a/sys/dev/advansys/adv_isa.c b/sys/dev/advansys/adv_isa.c
index 8afa05d69310..00381a3a4de7 100644
--- a/sys/dev/advansys/adv_isa.c
+++ b/sys/dev/advansys/adv_isa.c
@@ -109,7 +109,7 @@ adv_isa_probe(device_t dev)
 {
 	int	port_index;
 	int	max_port_index;
-	u_long	iobase, iocount, irq;
+	rman_res_t	iobase, iocount, irq;
 	int	user_iobase = 0;
 	int	rid = 0;
 	void	*ih;
diff --git a/sys/dev/ahci/ahci.c b/sys/dev/ahci/ahci.c
index 7fe3da880575..25ebbf716a1c 100644
--- a/sys/dev/ahci/ahci.c
+++ b/sys/dev/ahci/ahci.c
@@ -523,7 +523,7 @@ ahci_intr_one_edge(void *data)
 
 struct resource *
 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct ahci_controller *ctlr = device_get_softc(dev);
 	struct resource *res;
diff --git a/sys/dev/ahci/ahci.h b/sys/dev/ahci/ahci.h
index 5953425e2d9e..86bdf2b7050d 100644
--- a/sys/dev/ahci/ahci.h
+++ b/sys/dev/ahci/ahci.h
@@ -626,7 +626,7 @@ int ahci_detach(device_t dev);
 int ahci_setup_interrupt(device_t dev);
 int ahci_print_child(device_t dev, device_t child);
 struct resource *ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags);
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags);
 int ahci_release_resource(device_t dev, device_t child, int type, int rid,
     struct resource *r);
 int ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 
diff --git a/sys/dev/ata/ata-cbus.c b/sys/dev/ata/ata-cbus.c
index 489391dd2cf6..793601d092e4 100644
--- a/sys/dev/ata/ata-cbus.c
+++ b/sys/dev/ata/ata-cbus.c
@@ -67,7 +67,7 @@ ata_cbus_probe(device_t dev)
 {
     struct resource *io;
     int rid;
-    u_long tmp;
+    rman_res_t tmp;
 
     /* dont probe PnP devices */
     if (isa_get_vendorid(dev))
@@ -168,7 +168,8 @@ ata_cbus_attach(device_t dev)
 
 static struct resource *
 ata_cbus_alloc_resource(device_t dev, device_t child, int type, int *rid,
-			u_long start, u_long end, u_long count, u_int flags)
+			rman_res_t start, rman_res_t end, rman_res_t count,
+			u_int flags)
 {
     struct ata_cbus_controller *ctlr = device_get_softc(dev);
 
diff --git a/sys/dev/ata/ata-isa.c b/sys/dev/ata/ata-isa.c
index c94d2623f932..43b8533bcfc9 100644
--- a/sys/dev/ata/ata-isa.c
+++ b/sys/dev/ata/ata-isa.c
@@ -60,7 +60,7 @@ static int
 ata_isa_probe(device_t dev)
 {
     struct resource *io = NULL, *ctlio = NULL;
-    u_long tmp;
+    rman_res_t tmp;
     int rid;
 
     /* check isapnp ids */
@@ -100,7 +100,7 @@ ata_isa_attach(device_t dev)
 {
     struct ata_channel *ch = device_get_softc(dev);
     struct resource *io = NULL, *ctlio = NULL;
-    u_long tmp;
+    rman_res_t tmp;
     int i, rid;
 
     if (ch->attached)
diff --git a/sys/dev/ata/ata-pci.c b/sys/dev/ata/ata-pci.c
index 00ad6c73c3e5..74df04458c7b 100644
--- a/sys/dev/ata/ata-pci.c
+++ b/sys/dev/ata/ata-pci.c
@@ -217,7 +217,8 @@ ata_pci_write_config(device_t dev, device_t child, int reg,
 
 struct resource *
 ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
-		       u_long start, u_long end, u_long count, u_int flags)
+		       rman_res_t start, rman_res_t end, rman_res_t count,
+		       u_int flags)
 {
 	struct ata_pci_controller *controller = device_get_softc(dev);
 	struct resource *res = NULL;
diff --git a/sys/dev/ata/ata-pci.h b/sys/dev/ata/ata-pci.h
index 7872e9523f4d..101d6c6ddef4 100644
--- a/sys/dev/ata/ata-pci.h
+++ b/sys/dev/ata/ata-pci.h
@@ -535,7 +535,7 @@ void ata_pci_write_config(device_t dev, device_t child, int reg,
 int ata_pci_print_child(device_t dev, device_t child);
 int ata_pci_child_location_str(device_t dev, device_t child, char *buf,
     size_t buflen);
-struct resource * ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
+struct resource * ata_pci_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags);
 int ata_pci_release_resource(device_t dev, device_t child, int type, int rid, struct resource *r);
 int ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags, driver_filter_t *filter, driver_intr_t *function, void *argument, void **cookiep);
  int ata_pci_teardown_intr(device_t dev, device_t child, struct resource *irq, void *cookie);
diff --git a/sys/dev/atkbdc/atkbdc_ebus.c b/sys/dev/atkbdc/atkbdc_ebus.c
index 0dcb0a71e792..fd6443e8bf32 100644
--- a/sys/dev/atkbdc/atkbdc_ebus.c
+++ b/sys/dev/atkbdc/atkbdc_ebus.c
@@ -91,7 +91,7 @@ static int
 atkbdc_ebus_probe(device_t dev)
 {
 	struct resource *port0, *port1;
-	u_long count, start;
+	rman_res_t count, start;
 	int error, rid;
 
 	if (strcmp(ofw_bus_get_name(dev), "8042") != 0)
@@ -176,7 +176,7 @@ atkbdc_ebus_attach(device_t dev)
 	atkbdc_device_t *adi;
 	device_t cdev;
 	phandle_t child;
-	u_long count, intr, start;
+	rman_res_t count, intr, start;
 	int children, error, rid, unit;
 	char *cname, *dname;
 
diff --git a/sys/dev/atkbdc/atkbdc_isa.c b/sys/dev/atkbdc/atkbdc_isa.c
index c55e3562724b..2f863fce8347 100644
--- a/sys/dev/atkbdc/atkbdc_isa.c
+++ b/sys/dev/atkbdc/atkbdc_isa.c
@@ -50,8 +50,8 @@ static int	atkbdc_isa_attach(device_t dev);
 static device_t	atkbdc_isa_add_child(device_t bus, u_int order, const char *name,
 		    int unit);
 static struct resource *atkbdc_isa_alloc_resource(device_t dev, device_t child,
-		    int type, int *rid, u_long start, u_long end,
-		    u_long count, u_int flags);
+		    int type, int *rid, rman_res_t start, rman_res_t end,
+		    rman_res_t count, u_int flags);
 static int	atkbdc_isa_release_resource(device_t dev, device_t child,
 		    int type, int rid, struct resource *r);
 
@@ -97,8 +97,8 @@ atkbdc_isa_probe(device_t dev)
 {
 	struct resource	*port0;
 	struct resource	*port1;
-	u_long		start;
-	u_long		count;
+	rman_res_t	start;
+	rman_res_t	count;
 	int		error;
 	int		rid;
 #if defined(__i386__) || defined(__amd64__)
@@ -295,7 +295,7 @@ atkbdc_isa_add_child(device_t bus, u_int order, const char *name, int unit)
 
 struct resource *
 atkbdc_isa_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	atkbdc_softc_t	*sc;
 	
diff --git a/sys/dev/atkbdc/atkbdc_subr.c b/sys/dev/atkbdc/atkbdc_subr.c
index b97b592bafa9..28730c6bbcf4 100644
--- a/sys/dev/atkbdc/atkbdc_subr.c
+++ b/sys/dev/atkbdc/atkbdc_subr.c
@@ -51,7 +51,7 @@ int
 atkbdc_print_child(device_t bus, device_t dev)
 {
 	atkbdc_device_t *kbdcdev;
-	u_long irq;
+	rman_res_t irq;
 	int flags;
 	int retval = 0;
 
diff --git a/sys/dev/cs/if_cs.c b/sys/dev/cs/if_cs.c
index a9b0d088ab6d..770efe8c1e3f 100644
--- a/sys/dev/cs/if_cs.c
+++ b/sys/dev/cs/if_cs.c
@@ -258,7 +258,7 @@ cs_cs89x0_probe(device_t dev)
 {
 	int i;
 	int error;
-	u_long irq, junk;
+	rman_res_t irq, junk;
 	struct cs_softc *sc = device_get_softc(dev);
 	unsigned rev_type = 0;
 	uint16_t id;
diff --git a/sys/dev/ctau/if_ct.c b/sys/dev/ctau/if_ct.c
index e7b892794bc5..da8d32c11022 100644
--- a/sys/dev/ctau/if_ct.c
+++ b/sys/dev/ctau/if_ct.c
@@ -317,8 +317,8 @@ static	short porttab [] = {
 static	char dmatab [] = { 7, 6, 5, 0 };
 static	char irqtab [] = { 5, 10, 11, 7, 3, 15, 12, 0 };
 
-static int ct_is_free_res (device_t dev, int rid, int type, u_long start,
-	u_long end, u_long count)
+static int ct_is_free_res (device_t dev, int rid, int type, rman_res_t start,
+	rman_res_t end, rman_res_t count)
 {
 	struct resource *res;
 	
@@ -332,7 +332,7 @@ static int ct_is_free_res (device_t dev, int rid, int type, u_long start,
 
 static void ct_identify (driver_t *driver, device_t dev)
 {
-	u_long iobase, rescount;
+	rman_res_t iobase, rescount;
 	int devcount;
 	device_t *devices;
 	device_t child;
@@ -440,7 +440,7 @@ static void ct_identify (driver_t *driver, device_t dev)
 static int ct_probe (device_t dev)
 {
 	int unit = device_get_unit (dev);
-	u_long iobase, rescount;
+	rman_res_t iobase, rescount;
 
 	if (!device_get_desc (dev) ||
 	    strcmp (device_get_desc (dev), "Cronyx Tau-ISA"))
@@ -529,7 +529,7 @@ ct_bus_dma_mem_free (ct_dma_mem_t *dmem)
 static int ct_attach (device_t dev)
 {
 	bdrv_t *bd = device_get_softc (dev);
-	u_long iobase, drq, irq, rescount;
+	rman_res_t iobase, drq, irq, rescount;
 	int unit = device_get_unit (dev);
 	char *ct_ln = CT_LOCK_NAME;
 	ct_board_t *b;
diff --git a/sys/dev/cx/if_cx.c b/sys/dev/cx/if_cx.c
index cac69ab209f6..d513161e0fd5 100644
--- a/sys/dev/cx/if_cx.c
+++ b/sys/dev/cx/if_cx.c
@@ -405,8 +405,8 @@ static short porttab [] = {
 static char dmatab [] = { 7, 6, 5, 0 };
 static char irqtab [] = { 5, 10, 11, 7, 3, 15, 12, 0 };
 
-static int cx_is_free_res (device_t dev, int rid, int type, u_long start,
-	u_long end, u_long count)
+static int cx_is_free_res (device_t dev, int rid, int type, rman_res_t start,
+	rman_res_t end, rman_res_t count)
 {
 	struct resource *res;
 	
@@ -420,7 +420,7 @@ static int cx_is_free_res (device_t dev, int rid, int type, u_long start,
 
 static void cx_identify (driver_t *driver, device_t dev)
 {
-	u_long iobase, rescount;
+	rman_res_t iobase, rescount;
 	int devcount;
 	device_t *devices;
 	device_t child;
@@ -530,7 +530,7 @@ static int cx_probe (device_t dev)
 {
 	int unit = device_get_unit (dev);
 	int i;
-	u_long iobase, rescount;
+	rman_res_t iobase, rescount;
 
 	if (!device_get_desc (dev) ||
 	    strcmp (device_get_desc (dev), "Cronyx Sigma"))
@@ -629,7 +629,7 @@ cx_bus_dma_mem_free (cx_dma_mem_t *dmem)
 static int cx_attach (device_t dev)
 {
 	bdrv_t *bd = device_get_softc (dev);
-	u_long iobase, drq, irq, rescount;
+	rman_res_t iobase, drq, irq, rescount;
 	int unit = device_get_unit (dev);
 	char *cx_ln = CX_LOCK_NAME;
 	cx_board_t *b;
diff --git a/sys/dev/ed/if_ed_3c503.c b/sys/dev/ed/if_ed_3c503.c
index d7ab2f2941aa..353fbbf232a5 100644
--- a/sys/dev/ed/if_ed_3c503.c
+++ b/sys/dev/ed/if_ed_3c503.c
@@ -74,7 +74,7 @@ ed_probe_3Com(device_t dev, int port_rid, int flags)
 	int     i;
 	u_int   memsize;
 	u_char  isa16bit;
-	u_long	conf_maddr, conf_msize, irq, junk, pmem;
+	rman_res_t	conf_maddr, conf_msize, irq, junk, pmem;
 
 	error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
 	if (error)
diff --git a/sys/dev/ed/if_ed_cbus.c b/sys/dev/ed/if_ed_cbus.c
index c3660a73b0a9..f9672accabad 100644
--- a/sys/dev/ed/if_ed_cbus.c
+++ b/sys/dev/ed/if_ed_cbus.c
@@ -607,7 +607,7 @@ ed98_alloc_memory(dev, rid)
 {
 	struct ed_softc *sc = device_get_softc(dev);
 	int error;
-	u_long conf_maddr, conf_msize;
+	rman_res_t conf_maddr, conf_msize;
 
 	error = bus_get_resource(dev, SYS_RES_MEMORY, 0, &conf_maddr,
 	    &conf_msize);
@@ -1001,7 +1001,7 @@ ed_probe_CNET98(device_t dev, int port_rid, int flags)
 	struct ed_softc *sc = device_get_softc(dev);
 	int error;
 	u_char tmp;
-	u_long conf_irq, junk;
+	rman_res_t conf_irq, junk;
 #ifdef DIAGNOSTIC
 	u_char tmp_s;
 #endif
@@ -1157,7 +1157,7 @@ ed_probe_CNET98EL(device_t dev, int port_rid, int flags)
 	int error;
 	int i;
 	u_char romdata[ETHER_ADDR_LEN * 2], tmp;
-	u_long conf_irq, junk;
+	rman_res_t conf_irq, junk;
 
 	error = ed98_alloc_port(dev, port_rid);
 	if (error)
@@ -1251,7 +1251,7 @@ ed_probe_NEC77(device_t dev, int port_rid, int flags)
 	struct ed_softc *sc = device_get_softc(dev);
 	int error;
 	u_char tmp;
-	u_long conf_irq, junk;
+	rman_res_t conf_irq, junk;
 
 	error = ed98_probe_Novell(dev, port_rid, flags);
 	if (error)
@@ -1303,7 +1303,7 @@ ed_probe_NW98X(device_t dev, int port_rid, int flags)
 	struct ed_softc *sc = device_get_softc(dev);
 	int error;
 	u_char tmp;
-	u_long conf_irq, junk;
+	rman_res_t conf_irq, junk;
 
 	error = ed98_probe_Novell(dev, port_rid, flags);
 	if (error)
@@ -1427,7 +1427,7 @@ ed_probe_SB98(device_t dev, int port_rid, int flags)
 	struct ed_softc *sc = device_get_softc(dev);
 	int error;
 	u_char tmp;
-	u_long conf_irq, junk;
+	rman_res_t conf_irq, junk;
 
 	error = ed98_alloc_port(dev, port_rid);
 	if (error)
diff --git a/sys/dev/ed/if_ed_hpp.c b/sys/dev/ed/if_ed_hpp.c
index f16cd0118dcd..ec5c8db268bd 100644
--- a/sys/dev/ed/if_ed_hpp.c
+++ b/sys/dev/ed/if_ed_hpp.c
@@ -126,7 +126,7 @@ ed_probe_HP_pclanp(device_t dev, int port_rid, int flags)
 	u_char irq;			/* board configured IRQ */
 	uint8_t test_pattern[ED_HPP_TEST_SIZE];	/* read/write areas for */
 	uint8_t test_buffer[ED_HPP_TEST_SIZE];	/* probing card */
-	u_long conf_maddr, conf_msize, conf_irq, junk;
+	rman_res_t conf_maddr, conf_msize, conf_irq, junk;
 
 	error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
 	if (error)
diff --git a/sys/dev/ed/if_ed_wd80x3.c b/sys/dev/ed/if_ed_wd80x3.c
index 4ff2286ab137..ccaa46e883df 100644
--- a/sys/dev/ed/if_ed_wd80x3.c
+++ b/sys/dev/ed/if_ed_wd80x3.c
@@ -97,7 +97,7 @@ ed_probe_WD80x3_generic(device_t dev, int flags, uint16_t *intr_vals[])
 	int     i;
 	u_int   memsize;
 	u_char  iptr, isa16bit, sum, totalsum;
-	u_long	irq, junk, pmem;
+	rman_res_t	irq, junk, pmem;
 
 	sc->chip_type = ED_CHIP_TYPE_DP8390;
 
diff --git a/sys/dev/eisa/eisaconf.c b/sys/dev/eisa/eisaconf.c
index 8ec3419a36dc..ada184676401 100644
--- a/sys/dev/eisa/eisaconf.c
+++ b/sys/dev/eisa/eisaconf.c
@@ -352,7 +352,7 @@ eisa_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
 
 static struct resource *
 eisa_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	int isdefault;
 	struct eisa_device *e_dev = device_get_ivars(child);
diff --git a/sys/dev/fdt/simplebus.c b/sys/dev/fdt/simplebus.c
index 4e5bdd25b976..42096d28fe0d 100644
--- a/sys/dev/fdt/simplebus.c
+++ b/sys/dev/fdt/simplebus.c
@@ -46,7 +46,7 @@ __FBSDID("$FreeBSD$");
 static int		simplebus_probe(device_t dev);
 static int		simplebus_attach(device_t dev);
 static struct resource *simplebus_alloc_resource(device_t, device_t, int,
-    int *, u_long, u_long, u_long, u_int);
+    int *, rman_res_t, rman_res_t, rman_res_t, u_int);
 static void		simplebus_probe_nomatch(device_t bus, device_t child);
 static int		simplebus_print_child(device_t bus, device_t child);
 static device_t		simplebus_add_child(device_t dev, u_int order,
@@ -322,7 +322,7 @@ simplebus_get_resource_list(device_t bus __unused, device_t child)
 
 static struct resource *
 simplebus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct simplebus_softc *sc;
 	struct simplebus_devinfo *di;
diff --git a/sys/dev/fe/if_fe_cbus.c b/sys/dev/fe/if_fe_cbus.c
index dc10952e0ecc..c083cdda87a1 100644
--- a/sys/dev/fe/if_fe_cbus.c
+++ b/sys/dev/fe/if_fe_cbus.c
@@ -298,7 +298,7 @@ fe_probe_re1000(device_t dev)
 {
 	struct fe_softc *sc = device_get_softc(dev);
 	int i, n;
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 	u_char sum;
 
 	static struct fe_simple_probe_struct probe_table [] = {
@@ -398,7 +398,7 @@ fe_probe_jli(device_t dev)
 {
 	struct fe_softc *sc = device_get_softc(dev);
 	int i, n, xirq, error;
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 	u_char eeprom [JLI_EEPROM_SIZE];
 	u_short const * irqmap;
 
@@ -524,7 +524,7 @@ static int
 fe_probe_cnet9ne (device_t dev)
 {
 	struct fe_softc *sc = device_get_softc(dev);
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 
 	static struct fe_simple_probe_struct probe_table [] = {
 		{ FE_DLCR2, 0x58, 0x00 },
@@ -598,7 +598,7 @@ static int
 fe_probe_ssi(device_t dev)
 {
 	struct fe_softc *sc = device_get_softc(dev);
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 
 	u_char eeprom [SSI_EEPROM_SIZE];
 	static struct fe_simple_probe_struct probe_table [] = {
@@ -676,7 +676,7 @@ fe_probe_lnx(device_t dev)
 {
 	struct fe_softc *sc = device_get_softc(dev);
 
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 	u_char eeprom [LNX_EEPROM_SIZE];
 
 	static struct fe_simple_probe_struct probe_table [] = {
@@ -804,7 +804,7 @@ fe_probe_ubn(device_t dev)
 	struct fe_softc *sc = device_get_softc(dev);
 
 	u_char sum, save7;
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 	int i;
 	static struct fe_simple_probe_struct const probe_table [] = {
 		{ FE_DLCR2, 0x58, 0x00 },
@@ -949,7 +949,7 @@ fe_probe_rex(device_t dev)
 	struct fe_softc *sc = device_get_softc(dev);
 
 	int i;
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 	u_char eeprom [REX_EEPROM_SIZE];
 
 	static struct fe_simple_probe_struct probe_table [] = {
diff --git a/sys/dev/fe/if_fe_isa.c b/sys/dev/fe/if_fe_isa.c
index 53046e9a9a16..8dc7cba0488a 100644
--- a/sys/dev/fe/if_fe_isa.c
+++ b/sys/dev/fe/if_fe_isa.c
@@ -203,7 +203,7 @@ fe_probe_fmv(device_t dev)
 {
 	struct fe_softc *sc = device_get_softc(dev);
 	int n;
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 
 	static u_short const irqmap [ 4 ] = { 3, 7, 10, 15 };
 
@@ -698,7 +698,7 @@ fe_probe_jli(device_t dev)
 {
 	struct fe_softc *sc = device_get_softc(dev);
 	int i, n, error, xirq;
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 	u_char eeprom [JLI_EEPROM_SIZE];
 	u_short const * irqmap;
 
@@ -816,7 +816,7 @@ static int
 fe_probe_ssi(device_t dev)
 {
 	struct fe_softc *sc = device_get_softc(dev);
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 
 	u_char eeprom [SSI_EEPROM_SIZE];
 	static struct fe_simple_probe_struct probe_table [] = {
@@ -878,7 +878,7 @@ static int
 fe_probe_lnx(device_t dev)
 {
 	struct fe_softc *sc = device_get_softc(dev);
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 
 	u_char eeprom [LNX_EEPROM_SIZE];
 	static struct fe_simple_probe_struct probe_table [] = {
@@ -946,7 +946,7 @@ static int
 fe_probe_gwy(device_t dev)
 {
 	struct fe_softc *sc = device_get_softc(dev);
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 
 	static struct fe_simple_probe_struct probe_table [] = {
 	    /*	{ FE_DLCR2, 0x70, 0x00 }, */
@@ -999,7 +999,7 @@ static int
 fe_probe_ubn(device_t dev)
 {
 	struct fe_softc *sc = device_get_softc(dev);
-	u_long iobase, irq;
+	rman_res_t iobase, irq;
 #if 0
 	u_char sum;
 #endif
diff --git a/sys/dev/gpio/gpiobus.c b/sys/dev/gpio/gpiobus.c
index 4a7994ead3a1..e3755de29599 100644
--- a/sys/dev/gpio/gpiobus.c
+++ b/sys/dev/gpio/gpiobus.c
@@ -488,7 +488,7 @@ gpiobus_hinted_child(device_t bus, const char *dname, int dunit)
 
 static int
 gpiobus_set_resource(device_t dev, device_t child, int type, int rid,
-    u_long start, u_long count)
+    rman_res_t start, rman_res_t count)
 {
 	struct gpiobus_ivar *devi;
 	struct resource_list_entry *rle;
@@ -506,7 +506,7 @@ gpiobus_set_resource(device_t dev, device_t child, int type, int rid,
 
 static struct resource *
 gpiobus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct gpiobus_softc *sc;
 	struct resource *rv;
diff --git a/sys/dev/mca/mca_bus.c b/sys/dev/mca/mca_bus.c
index 2b4a0b52d2c2..f97fd24ac2dc 100644
--- a/sys/dev/mca/mca_bus.c
+++ b/sys/dev/mca/mca_bus.c
@@ -456,7 +456,7 @@ mca_read_ivar (device_t dev, device_t child, int which, uintptr_t * result)
 
 static struct resource *
 mca_alloc_resource (device_t dev, device_t child, int type, int *rid,
-		    u_long start, u_long end, u_long count, u_int flags)
+		    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct mca_device *		m_dev = device_get_ivars(child);
 	struct resource_list_entry *	rle;
diff --git a/sys/dev/mvs/mvs_pci.c b/sys/dev/mvs/mvs_pci.c
index 11c1dd3cfa7b..316ac0008dd1 100644
--- a/sys/dev/mvs/mvs_pci.c
+++ b/sys/dev/mvs/mvs_pci.c
@@ -389,7 +389,8 @@ mvs_intr(void *data)
 
 static struct resource *
 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid,
-		       u_long start, u_long end, u_long count, u_int flags)
+		       rman_res_t start, rman_res_t end, rman_res_t count,
+		       u_int flags)
 {
 	struct mvs_controller *ctlr = device_get_softc(dev);
 	int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
diff --git a/sys/dev/mvs/mvs_soc.c b/sys/dev/mvs/mvs_soc.c
index 8ed7df4fcdd7..d4ecd8fdb207 100644
--- a/sys/dev/mvs/mvs_soc.c
+++ b/sys/dev/mvs/mvs_soc.c
@@ -336,7 +336,7 @@ mvs_intr(void *data)
 
 static struct resource *
 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid,
-		       u_long start, u_long end, u_long count, u_int flags)
+		   rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct mvs_controller *ctlr = device_get_softc(dev);
 	int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
diff --git a/sys/dev/ncv/ncr53c500_pccard.c b/sys/dev/ncv/ncr53c500_pccard.c
index a7a2b5b7d7d5..55f0ef98d49e 100644
--- a/sys/dev/ncv/ncr53c500_pccard.c
+++ b/sys/dev/ncv/ncr53c500_pccard.c
@@ -142,7 +142,7 @@ ncv_alloc_resource(device_t dev)
 {
 	struct ncv_softc	*sc = device_get_softc(dev);
 	u_int32_t		flags = device_get_flags(dev);
-	u_long			ioaddr, iosize, maddr, msize;
+	rman_res_t		ioaddr, iosize, maddr, msize;
 	int			error;
 	bus_addr_t		offset = 0;
 
diff --git a/sys/dev/nsp/nsp_pccard.c b/sys/dev/nsp/nsp_pccard.c
index aed82af21942..75fc07603869 100644
--- a/sys/dev/nsp/nsp_pccard.c
+++ b/sys/dev/nsp/nsp_pccard.c
@@ -115,7 +115,7 @@ static int
 nsp_alloc_resource(device_t dev)
 {
 	struct nsp_softc	*sc = device_get_softc(dev);
-	u_long			ioaddr, iosize, maddr, msize;
+	rman_res_t		ioaddr, iosize, maddr, msize;
 	int			error;
 
 	error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &ioaddr, &iosize);
diff --git a/sys/dev/ofw/ofwbus.c b/sys/dev/ofw/ofwbus.c
index 670abff7e6f8..142ee1aa3706 100644
--- a/sys/dev/ofw/ofwbus.c
+++ b/sys/dev/ofw/ofwbus.c
@@ -178,7 +178,7 @@ ofwbus_attach(device_t dev)
 
 static struct resource *
 ofwbus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct ofwbus_softc *sc;
 	struct rman *rm;
@@ -239,7 +239,7 @@ ofwbus_alloc_resource(device_t bus, device_t child, int type, int *rid,
 
 static int
 ofwbus_adjust_resource(device_t bus, device_t child __unused, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 	struct ofwbus_softc *sc;
 	struct rman *rm;
diff --git a/sys/dev/pccard/pccard.c b/sys/dev/pccard/pccard.c
index 87ab53abcf4a..b3c2e32e61eb 100644
--- a/sys/dev/pccard/pccard.c
+++ b/sys/dev/pccard/pccard.c
@@ -97,9 +97,9 @@ static void	pccard_print_resources(struct resource_list *rl,
 		    const char *name, int type, int count, const char *format);
 static int	pccard_print_child(device_t dev, device_t child);
 static int	pccard_set_resource(device_t dev, device_t child, int type,
-		    int rid, u_long start, u_long count);
+		    int rid, rman_res_t start, rman_res_t count);
 static int	pccard_get_resource(device_t dev, device_t child, int type,
-		    int rid, u_long *startp, u_long *countp);
+		    int rid, rman_res_t *startp, rman_res_t *countp);
 static void	pccard_delete_resource(device_t dev, device_t child, int type,
 		    int rid);
 static int	pccard_set_res_flags(device_t dev, device_t child, int type,
@@ -113,8 +113,8 @@ static int	pccard_read_ivar(device_t bus, device_t child, int which,
 		    uintptr_t *result);
 static void	pccard_driver_added(device_t dev, driver_t *driver);
 static struct resource *pccard_alloc_resource(device_t dev,
-		    device_t child, int type, int *rid, u_long start,
-		    u_long end, u_long count, u_int flags);
+		    device_t child, int type, int *rid, rman_res_t start,
+		    rman_res_t end, rman_res_t count, u_int flags);
 static int	pccard_release_resource(device_t dev, device_t child, int type,
 		    int rid, struct resource *r);
 static void	pccard_child_detached(device_t parent, device_t dev);
@@ -474,7 +474,7 @@ pccard_function_init(struct pccard_function *pf, int entry)
 	struct pccard_ce_iospace *ios;
 	struct pccard_ce_memspace *mems;
 	device_t bus;
-	u_long start, end, len;
+	rman_res_t start, end, len;
 	int i, rid, spaces;
 
 	if (pf->pf_flags & PFF_ENABLED) {
@@ -614,8 +614,8 @@ pccard_function_free(struct pccard_function *pf)
 }
 
 static void
-pccard_mfc_adjust_iobase(struct pccard_function *pf, bus_addr_t addr,
-    bus_addr_t offset, bus_size_t size)
+pccard_mfc_adjust_iobase(struct pccard_function *pf, rman_res_t addr,
+    rman_res_t offset, rman_res_t size)
 {
 	bus_size_t iosize, tmp;
 
@@ -923,7 +923,7 @@ pccard_print_child(device_t dev, device_t child)
 
 static int
 pccard_set_resource(device_t dev, device_t child, int type, int rid,
-    u_long start, u_long count)
+    rman_res_t start, rman_res_t count)
 {
 	struct pccard_ivar *devi = PCCARD_IVAR(child);
 	struct resource_list *rl = &devi->resources;
@@ -952,7 +952,7 @@ pccard_set_resource(device_t dev, device_t child, int type, int rid,
 
 static int
 pccard_get_resource(device_t dev, device_t child, int type, int rid,
-    u_long *startp, u_long *countp)
+    rman_res_t *startp, rman_res_t *countp)
 {
 	struct pccard_ivar *devi = PCCARD_IVAR(child);
 	struct resource_list *rl = &devi->resources;
@@ -1132,7 +1132,7 @@ pccard_driver_added(device_t dev, driver_t *driver)
 
 static struct resource *
 pccard_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct pccard_ivar *dinfo;
 	struct resource_list_entry *rle = 0;
diff --git a/sys/dev/pccard/pccardvarp.h b/sys/dev/pccard/pccardvarp.h
index 54d7f7501aeb..9478c8f03e3e 100644
--- a/sys/dev/pccard/pccardvarp.h
+++ b/sys/dev/pccard/pccardvarp.h
@@ -48,14 +48,14 @@
 #define PCCARD_CFE_AUDIO		0x0800
 
 struct pccard_ce_iospace {
-	u_long	length;
-	u_long	start;
+	rman_res_t	length;
+	rman_res_t	start;
 };
 
 struct pccard_ce_memspace {
-	u_long	length;
-	u_long	cardaddr;
-	u_long	hostaddr;
+	rman_res_t	length;
+	rman_res_t	cardaddr;
+	rman_res_t	hostaddr;
 };
 
 struct pccard_config_entry {
diff --git a/sys/dev/pccbb/pccbb.c b/sys/dev/pccbb/pccbb.c
index c5cf16de16d4..93987715fdee 100644
--- a/sys/dev/pccbb/pccbb.c
+++ b/sys/dev/pccbb/pccbb.c
@@ -166,8 +166,8 @@ static int	cbb_cardbus_activate_resource(device_t brdev, device_t child,
 static int	cbb_cardbus_deactivate_resource(device_t brdev,
 		    device_t child, int type, int rid, struct resource *res);
 static struct resource	*cbb_cardbus_alloc_resource(device_t brdev,
-		    device_t child, int type, int *rid, u_long start,
-		    u_long end, u_long count, u_int flags);
+		    device_t child, int type, int *rid, rman_res_t start,
+		    rman_res_t end, rman_res_t count, u_int flags);
 static int	cbb_cardbus_release_resource(device_t brdev, device_t child,
 		    int type, int rid, struct resource *res);
 static int	cbb_cardbus_power_enable_socket(device_t brdev,
@@ -1230,12 +1230,12 @@ cbb_cardbus_deactivate_resource(device_t brdev, device_t child, int type,
 
 static struct resource *
 cbb_cardbus_alloc_resource(device_t brdev, device_t child, int type,
-    int *rid, u_long start, u_long end, u_long count, u_int flags)
+    int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct cbb_softc *sc = device_get_softc(brdev);
 	int tmp;
 	struct resource *res;
-	u_long align;
+	rman_res_t align;
 
 	switch (type) {
 	case SYS_RES_IRQ:
@@ -1395,7 +1395,7 @@ cbb_pcic_deactivate_resource(device_t brdev, device_t child, int type,
 
 static struct resource *
 cbb_pcic_alloc_resource(device_t brdev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *res = NULL;
 	struct cbb_softc *sc = device_get_softc(brdev);
@@ -1538,7 +1538,7 @@ cbb_deactivate_resource(device_t brdev, device_t child, int type,
 
 struct resource *
 cbb_alloc_resource(device_t brdev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct cbb_softc *sc = device_get_softc(brdev);
 
diff --git a/sys/dev/pccbb/pccbb_pci.c b/sys/dev/pccbb/pccbb_pci.c
index a82afa271ed0..e739027dc885 100644
--- a/sys/dev/pccbb/pccbb_pci.c
+++ b/sys/dev/pccbb/pccbb_pci.c
@@ -783,7 +783,7 @@ cbb_pci_filt(void *arg)
 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
 static struct resource *
 cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct cbb_softc *sc;
 
@@ -797,7 +797,7 @@ cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
 
 static int
 cbb_pci_adjust_resource(device_t bus, device_t child, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 	struct cbb_softc *sc;
 
diff --git a/sys/dev/pccbb/pccbbvar.h b/sys/dev/pccbb/pccbbvar.h
index f19b933ba2de..196f154fe077 100644
--- a/sys/dev/pccbb/pccbbvar.h
+++ b/sys/dev/pccbb/pccbbvar.h
@@ -113,7 +113,7 @@ extern devclass_t cbb_devclass;
 int	cbb_activate_resource(device_t brdev, device_t child,
 	    int type, int rid, struct resource *r);
 struct resource	*cbb_alloc_resource(device_t brdev, device_t child,
-	    int type, int *rid, u_long start, u_long end, u_long count,
+	    int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count,
 	    u_int flags);
 void	cbb_child_detached(device_t brdev, device_t child);
 int	cbb_child_present(device_t parent, device_t child);
diff --git a/sys/dev/pcf/pcf_isa.c b/sys/dev/pcf/pcf_isa.c
index e8116359db44..70c3efe8f707 100644
--- a/sys/dev/pcf/pcf_isa.c
+++ b/sys/dev/pcf/pcf_isa.c
@@ -100,7 +100,7 @@ pcf_isa_identify(driver_t *driver, device_t parent)
 static int
 pcf_isa_probe(device_t dev)
 {
-	u_long		start, count;
+	rman_res_t	start, count;
 	u_int		rid = 0, port, error;
 
 	/* skip PnP probes */
diff --git a/sys/dev/pci/hostb_pci.c b/sys/dev/pci/hostb_pci.c
index 4e28691d31f9..84878caf900d 100644
--- a/sys/dev/pci/hostb_pci.c
+++ b/sys/dev/pci/hostb_pci.c
@@ -102,7 +102,7 @@ pci_hostb_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
 
 static struct resource *
 pci_hostb_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 
 	return (bus_alloc_resource(dev, type, rid, start, end, count, flags));
diff --git a/sys/dev/pci/isa_pci.c b/sys/dev/pci/isa_pci.c
index 7819b7e4cc83..950920da0c82 100644
--- a/sys/dev/pci/isa_pci.c
+++ b/sys/dev/pci/isa_pci.c
@@ -52,8 +52,8 @@ __FBSDID("$FreeBSD$");
 static int	isab_pci_probe(device_t dev);
 static int	isab_pci_attach(device_t dev);
 static struct resource *	isab_pci_alloc_resource(device_t dev,
-    device_t child, int type, int *rid, u_long start, u_long end, u_long count,
-    u_int flags);
+    device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
+    rman_res_t count, u_int flags);
 static int	isab_pci_release_resource(device_t dev, device_t child,
     int type, int rid, struct resource *r);
 
@@ -169,7 +169,7 @@ isab_pci_attach(device_t dev)
 
 static struct resource *
 isab_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct isab_pci_softc *sc;
 	int bar;
diff --git a/sys/dev/pci/pci.c b/sys/dev/pci/pci.c
index 261aa0cd96d9..81caa48daa7f 100644
--- a/sys/dev/pci/pci.c
+++ b/sys/dev/pci/pci.c
@@ -3353,7 +3353,7 @@ pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg,
 {
 	struct resource *res;
 	char *cp;
-	u_long start, end, count;
+	rman_res_t start, end, count;
 	int rid, sec_bus, sec_reg, sub_bus, sub_reg, sup_bus;
 
 	switch (cfg->hdrtype & PCIM_HDRTYPE) {
@@ -3453,8 +3453,8 @@ pci_reserve_secbus(device_t bus, device_t dev, pcicfgregs *cfg,
 }
 
 static struct resource *
-pci_alloc_secbus(device_t dev, device_t child, int *rid, u_long start,
-    u_long end, u_long count, u_int flags)
+pci_alloc_secbus(device_t dev, device_t child, int *rid, rman_res_t start,
+    rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct pci_devinfo *dinfo;
 	pcicfgregs *cfg;
@@ -4618,7 +4618,8 @@ DB_SHOW_COMMAND(pciregs, db_pci_dump)
 
 static struct resource *
 pci_reserve_map(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int num, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int num,
+    u_int flags)
 {
 	struct pci_devinfo *dinfo = device_get_ivars(child);
 	struct resource_list *rl = &dinfo->resources;
@@ -4716,7 +4717,8 @@ pci_reserve_map(device_t dev, device_t child, int type, int *rid,
 
 struct resource *
 pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_long num, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_long num,
+    u_int flags)
 {
 	struct pci_devinfo *dinfo;
 	struct resource_list *rl;
@@ -4791,7 +4793,7 @@ pci_alloc_multi_resource(device_t dev, device_t child, int type, int *rid,
 
 struct resource *
 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 #ifdef PCI_IOV
 	struct pci_devinfo *dinfo;
diff --git a/sys/dev/pci/pci_host_generic.c b/sys/dev/pci/pci_host_generic.c
index e4260e0355f4..d6d21257eb34 100644
--- a/sys/dev/pci/pci_host_generic.c
+++ b/sys/dev/pci/pci_host_generic.c
@@ -124,8 +124,8 @@ static int generic_pcie_read_ivar(device_t dev, device_t child, int index,
 static int generic_pcie_write_ivar(device_t dev, device_t child, int index,
     uintptr_t value);
 static struct resource *generic_pcie_alloc_resource(device_t dev,
-    device_t child, int type, int *rid, u_long start, u_long end,
-    u_long count, u_int flags);
+    device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
+    rman_res_t count, u_int flags);
 static int generic_pcie_release_resource(device_t dev, device_t child,
     int type, int rid, struct resource *res);
 
@@ -482,7 +482,7 @@ generic_pcie_release_resource(device_t dev, device_t child, int type,
 
 static struct resource *
 generic_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct generic_pcie_softc *sc;
 	struct resource *res;
@@ -527,7 +527,7 @@ generic_pcie_alloc_resource(device_t dev, device_t child, int type, int *rid,
 
 static int
 generic_pcie_adjust_resource(device_t dev, device_t child, int type,
-    struct resource *res, u_long start, u_long end)
+    struct resource *res, rman_res_t start, rman_res_t end)
 {
 	struct generic_pcie_softc *sc;
 	struct rman *rm;
diff --git a/sys/dev/pci/pci_iov.c b/sys/dev/pci/pci_iov.c
index 58e692649df5..85ddc319e68f 100644
--- a/sys/dev/pci/pci_iov.c
+++ b/sys/dev/pci/pci_iov.c
@@ -320,7 +320,7 @@ pci_iov_alloc_bar(struct pci_devinfo *dinfo, int bar, pci_addr_t bar_shift)
 	struct resource *res;
 	struct pcicfg_iov *iov;
 	device_t dev, bus;
-	u_long start, end;
+	rman_res_t start, end;
 	pci_addr_t bar_size;
 	int rid;
 
@@ -890,15 +890,15 @@ pci_iov_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
 }
 
 struct resource *
-pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid, u_long start,
-    u_long end, u_long count, u_int flags)
+pci_vf_alloc_mem_resource(device_t dev, device_t child, int *rid,
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct pci_devinfo *dinfo;
 	struct pcicfg_iov *iov;
 	struct pci_map *map;
 	struct resource *res;
 	struct resource_list_entry *rle;
-	u_long bar_start, bar_end;
+	rman_res_t bar_start, bar_end;
 	pci_addr_t bar_length;
 	int error;
 
diff --git a/sys/dev/pci/pci_pci.c b/sys/dev/pci/pci_pci.c
index f5a5b7415f0b..a6c69311dbee 100644
--- a/sys/dev/pci/pci_pci.c
+++ b/sys/dev/pci/pci_pci.c
@@ -212,9 +212,10 @@ pcib_write_windows(struct pcib_softc *sc, int mask)
  * ISA alias range.
  */
 static int
-pcib_is_isa_range(struct pcib_softc *sc, u_long start, u_long end, u_long count)
+pcib_is_isa_range(struct pcib_softc *sc, rman_res_t start, rman_res_t end,
+    rman_res_t count)
 {
-	u_long next_alias;
+	rman_res_t next_alias;
 
 	if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
 		return (0);
@@ -275,13 +276,13 @@ pcib_add_window_resources(struct pcib_window *w, struct resource **res,
 	}
 }
 
-typedef void (nonisa_callback)(u_long start, u_long end, void *arg);
+typedef void (nonisa_callback)(rman_res_t start, rman_res_t end, void *arg);
 
 static void
-pcib_walk_nonisa_ranges(u_long start, u_long end, nonisa_callback *cb,
+pcib_walk_nonisa_ranges(rman_res_t start, rman_res_t end, nonisa_callback *cb,
     void *arg)
 {
-	u_long next_end;
+	rman_res_t next_end;
 
 	/*
 	 * If start is within an ISA alias range, move up to the start
@@ -309,7 +310,7 @@ pcib_walk_nonisa_ranges(u_long start, u_long end, nonisa_callback *cb,
 }
 
 static void
-count_ranges(u_long start, u_long end, void *arg)
+count_ranges(rman_res_t start, rman_res_t end, void *arg)
 {
 	int *countp;
 
@@ -324,7 +325,7 @@ struct alloc_state {
 };
 
 static void
-alloc_ranges(u_long start, u_long end, void *arg)
+alloc_ranges(rman_res_t start, rman_res_t end, void *arg)
 {
 	struct alloc_state *as;
 	struct pcib_window *w;
@@ -348,7 +349,7 @@ alloc_ranges(u_long start, u_long end, void *arg)
 }
 
 static int
-pcib_alloc_nonisa_ranges(struct pcib_softc *sc, u_long start, u_long end)
+pcib_alloc_nonisa_ranges(struct pcib_softc *sc, rman_res_t start, rman_res_t end)
 {
 	struct alloc_state as;
 	int i, new_count;
@@ -609,7 +610,7 @@ pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
 
 static struct resource *
 pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *res;
 
@@ -633,9 +634,9 @@ pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
  * subbus.
  */
 static int
-pcib_grow_subbus(struct pcib_secbus *bus, u_long new_end)
+pcib_grow_subbus(struct pcib_secbus *bus, rman_res_t new_end)
 {
-	u_long old_end;
+	rman_res_t old_end;
 	int error;
 
 	old_end = rman_get_end(bus->res);
@@ -658,10 +659,10 @@ pcib_grow_subbus(struct pcib_secbus *bus, u_long new_end)
 
 struct resource *
 pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *res;
-	u_long start_free, end_free, new_end;
+	rman_res_t start_free, end_free, new_end;
 
 	/*
 	 * First, see if the request can be satisified by the existing
@@ -1158,8 +1159,8 @@ pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
  */
 static struct resource *
 pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
-    device_t child, int type, int *rid, u_long start, u_long end, u_long count,
-    u_int flags)
+    device_t child, int type, int *rid, rman_res_t start, rman_res_t end,
+    rman_res_t count, u_int flags)
 {
 	struct resource *res;
 
@@ -1196,10 +1197,10 @@ pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
 /* Allocate a fresh resource range for an unconfigured window. */
 static int
 pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *res;
-	u_long base, limit, wmask;
+	rman_res_t base, limit, wmask;
 	int rid;
 
 	/*
@@ -1269,7 +1270,7 @@ pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
 /* Try to expand an existing window to the requested base and limit. */
 static int
 pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
-    u_long base, u_long limit)
+    rman_res_t base, rman_res_t limit)
 {
 	struct resource *res;
 	int error, i, force_64k_base;
@@ -1367,9 +1368,9 @@ pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
  */
 static int
 pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
-	u_long align, start_free, end_free, front, back, wmask;
+	rman_res_t align, start_free, end_free, front, back, wmask;
 	int error;
 
 	/*
@@ -1534,7 +1535,7 @@ pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
  */
 struct resource *
 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct pcib_softc *sc;
 	struct resource *r;
@@ -1623,7 +1624,7 @@ pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
 
 int
 pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
-    u_long start, u_long end)
+    rman_res_t start, rman_res_t end)
 {
 	struct pcib_softc *sc;
 
@@ -1658,7 +1659,7 @@ pcib_release_resource(device_t dev, device_t child, int type, int rid,
  */
 struct resource *
 pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct pcib_softc	*sc = device_get_softc(dev);
 	const char *name, *suffix;
diff --git a/sys/dev/pci/pci_private.h b/sys/dev/pci/pci_private.h
index 7795747bd219..a49435e03562 100644
--- a/sys/dev/pci/pci_private.h
+++ b/sys/dev/pci/pci_private.h
@@ -105,8 +105,8 @@ int		pci_msix_count_method(device_t dev, device_t child);
 int		pci_msix_pba_bar_method(device_t dev, device_t child);
 int		pci_msix_table_bar_method(device_t dev, device_t child);
 struct resource	*pci_alloc_resource(device_t dev, device_t child, 
-		    int type, int *rid, u_long start, u_long end, u_long count,
-		    u_int flags);
+		    int type, int *rid, rman_res_t start, rman_res_t end,
+		    rman_res_t count, u_int flags);
 int		pci_release_resource(device_t dev, device_t child, int type,
 		    int rid, struct resource *r);
 int		pci_activate_resource(device_t dev, device_t child, int type,
@@ -151,8 +151,8 @@ struct pci_map *pci_add_bar(device_t dev, int reg, pci_addr_t value,
 		    pci_addr_t size);
 
 struct resource *pci_alloc_multi_resource(device_t dev, device_t child,
-		    int type, int *rid, u_long start, u_long end, u_long count,
-		    u_long num, u_int flags);
+		    int type, int *rid, rman_res_t start, rman_res_t end,
+		    rman_res_t count, u_long num, u_int flags);
 
 int		pci_iov_attach_method(device_t bus, device_t dev,
 		    struct nvlist *pf_schema, struct nvlist *vf_schema);
@@ -162,8 +162,8 @@ device_t	pci_create_iov_child_method(device_t bus, device_t pf,
 		    uint16_t rid, uint16_t vid, uint16_t did);
 
 struct resource *pci_vf_alloc_mem_resource(device_t dev, device_t child,
-		    int *rid, u_long start, u_long end, u_long count,
-		    u_int flags);
+		    int *rid, rman_res_t start, rman_res_t end,
+		    rman_res_t count, u_int flags);
 int		pci_vf_release_mem_resource(device_t dev, device_t child,
 		    int rid, struct resource *r);
 #endif /* _PCI_PRIVATE_H_ */
diff --git a/sys/dev/pci/pci_subr.c b/sys/dev/pci/pci_subr.c
index 03bcdc088b9f..77c60c3baab8 100644
--- a/sys/dev/pci/pci_subr.c
+++ b/sys/dev/pci/pci_subr.c
@@ -178,8 +178,8 @@ pcib_host_res_free(device_t pcib, struct pcib_host_resources *hr)
 }
 
 int
-pcib_host_res_decodes(struct pcib_host_resources *hr, int type, u_long start,
-    u_long end, u_int flags)
+pcib_host_res_decodes(struct pcib_host_resources *hr, int type, rman_res_t start,
+    rman_res_t end, u_int flags)
 {
 	struct resource_list_entry *rle;
 	int rid;
@@ -201,11 +201,11 @@ pcib_host_res_decodes(struct pcib_host_resources *hr, int type, u_long start,
 
 struct resource *
 pcib_host_res_alloc(struct pcib_host_resources *hr, device_t dev, int type,
-    int *rid, u_long start, u_long end, u_long count, u_int flags)
+    int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource_list_entry *rle;
 	struct resource *r;
-	u_long new_start, new_end;
+	rman_res_t new_start, new_end;
 
 	if (flags & RF_PREFETCHABLE)
 		KASSERT(type == SYS_RES_MEMORY,
@@ -261,7 +261,7 @@ pcib_host_res_alloc(struct pcib_host_resources *hr, device_t dev, int type,
 
 int
 pcib_host_res_adjust(struct pcib_host_resources *hr, device_t dev, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 	struct resource_list_entry *rle;
 
@@ -329,8 +329,8 @@ pci_find_domain(int domain)
 }
 
 struct resource *
-pci_domain_alloc_bus(int domain, device_t dev, int *rid, u_long start,
-    u_long end, u_long count, u_int flags)
+pci_domain_alloc_bus(int domain, device_t dev, int *rid, rman_res_t start,
+    rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct pci_domain *d;
 	struct resource *res;
@@ -349,7 +349,7 @@ pci_domain_alloc_bus(int domain, device_t dev, int *rid, u_long start,
 
 int
 pci_domain_adjust_bus(int domain, device_t dev, struct resource *r,
-    u_long start, u_long end)
+    rman_res_t start, rman_res_t end)
 {
 #ifdef INVARIANTS
 	struct pci_domain *d;
diff --git a/sys/dev/pci/pcib_private.h b/sys/dev/pci/pcib_private.h
index bba4ce290926..417c107925e3 100644
--- a/sys/dev/pci/pcib_private.h
+++ b/sys/dev/pci/pcib_private.h
@@ -49,13 +49,13 @@ int		pcib_host_res_init(device_t pcib,
 int		pcib_host_res_free(device_t pcib,
 		    struct pcib_host_resources *hr);
 int		pcib_host_res_decodes(struct pcib_host_resources *hr, int type,
-		    u_long start, u_long end, u_int flags);
+		    rman_res_t start, rman_res_t end, u_int flags);
 struct resource *pcib_host_res_alloc(struct pcib_host_resources *hr,
-		    device_t dev, int type, int *rid, u_long start, u_long end,
-		    u_long count, u_int flags);
+		    device_t dev, int type, int *rid, rman_res_t start,
+		    rman_res_t end, rman_res_t count, u_int flags);
 int		pcib_host_res_adjust(struct pcib_host_resources *hr,
-		    device_t dev, int type, struct resource *r, u_long start,
-		    u_long end);
+		    device_t dev, int type, struct resource *r, rman_res_t start,
+		    rman_res_t end);
 #endif
 
 /*
@@ -132,13 +132,13 @@ int		host_pcib_get_busno(pci_read_config_fn read_config, int bus,
     int slot, int func, uint8_t *busnum);
 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
 struct resource *pci_domain_alloc_bus(int domain, device_t dev, int *rid,
-		    u_long start, u_long end, u_long count, u_int flags);
+		    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags);
 int		pci_domain_adjust_bus(int domain, device_t dev,
-		    struct resource *r, u_long start, u_long end);
+		    struct resource *r, rman_res_t start, rman_res_t end);
 int		pci_domain_release_bus(int domain, device_t dev, int rid,
 		    struct resource *r);
 struct resource *pcib_alloc_subbus(struct pcib_secbus *bus, device_t child,
-		    int *rid, u_long start, u_long end, u_long count,
+		    int *rid, rman_res_t start, rman_res_t end, rman_res_t count,
 		    u_int flags);
 void		pcib_setup_secbus(device_t dev, struct pcib_secbus *bus,
     int min_count);
@@ -152,10 +152,11 @@ const char	*pcib_child_name(device_t child);
 int		pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
 int		pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
 struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 
-					    u_long start, u_long end, u_long count, u_int flags);
+					    rman_res_t start, rman_res_t end,
+					    rman_res_t count, u_int flags);
 #ifdef NEW_PCIB
 int		pcib_adjust_resource(device_t bus, device_t child, int type,
-    struct resource *r, u_long start, u_long end);
+    struct resource *r, rman_res_t start, rman_res_t end);
 int		pcib_release_resource(device_t dev, device_t child, int type, int rid,
     struct resource *r);
 #endif
diff --git a/sys/dev/pci/pcivar.h b/sys/dev/pci/pcivar.h
index d8df42fea2e1..7c1403522191 100644
--- a/sys/dev/pci/pcivar.h
+++ b/sys/dev/pci/pcivar.h
@@ -397,7 +397,7 @@ pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
  * Check if the address range falls within the VGA defined address range(s)
  */
 static __inline int
-pci_is_vga_ioport_range(u_long start, u_long end)
+pci_is_vga_ioport_range(rman_res_t start, rman_res_t end)
 {
  
 	return (((start >= 0x3b0 && end <= 0x3bb) ||
@@ -405,7 +405,7 @@ pci_is_vga_ioport_range(u_long start, u_long end)
 }
 
 static __inline int
-pci_is_vga_memory_range(u_long start, u_long end)
+pci_is_vga_memory_range(rman_res_t start, rman_res_t end)
 {
 
 	return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
diff --git a/sys/dev/pci/vga_pci.c b/sys/dev/pci/vga_pci.c
index 0c49ca09c324..048bc91cecc4 100644
--- a/sys/dev/pci/vga_pci.c
+++ b/sys/dev/pci/vga_pci.c
@@ -68,7 +68,8 @@ SYSCTL_DECL(_hw_pci);
 
 static struct vga_resource *lookup_res(struct vga_pci_softc *sc, int rid);
 static struct resource *vga_pci_alloc_resource(device_t dev, device_t child,
-    int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
+    int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count,
+    u_int flags);
 static int	vga_pci_release_resource(device_t dev, device_t child, int type,
     int rid, struct resource *r);
 
@@ -333,7 +334,7 @@ lookup_res(struct vga_pci_softc *sc, int rid)
 
 static struct resource *
 vga_pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct vga_resource *vr;
 
diff --git a/sys/dev/ppc/ppc.c b/sys/dev/ppc/ppc.c
index e1edc4d87ae2..17a4a0420f4b 100644
--- a/sys/dev/ppc/ppc.c
+++ b/sys/dev/ppc/ppc.c
@@ -1674,7 +1674,7 @@ ppc_probe(device_t dev, int rid)
 #endif
 	struct ppc_data *ppc;
 	int error;
-	u_long port;
+	rman_res_t port;
 
 	/*
 	 * Allocate the ppc_data structure.
@@ -2015,7 +2015,7 @@ ppc_write_ivar(device_t bus, device_t dev, int index, uintptr_t val)
  */
 struct resource *
 ppc_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct ppc_data *ppc = DEVTOSOFTC(bus);
 
diff --git a/sys/dev/ppc/ppcvar.h b/sys/dev/ppc/ppcvar.h
index faff75ac69e6..792111e8e23d 100644
--- a/sys/dev/ppc/ppcvar.h
+++ b/sys/dev/ppc/ppcvar.h
@@ -41,7 +41,7 @@ u_char ppc_io(device_t, int, u_char *, int, u_char);
 int ppc_exec_microseq(device_t, struct ppb_microseq **);
 
 struct resource *ppc_alloc_resource(device_t bus, device_t child, int type,
-    int *rid, u_long start, u_long end, u_long count, u_int flags);
+    int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags);
 int ppc_release_resource(device_t bus, device_t child, int type, int rid,
     struct resource *r);
 int ppc_reset_epp(device_t);
diff --git a/sys/dev/puc/puc.c b/sys/dev/puc/puc.c
index 2b320ca405a7..75736d1caef0 100644
--- a/sys/dev/puc/puc.c
+++ b/sys/dev/puc/puc.c
@@ -78,7 +78,7 @@ puc_get_bar(struct puc_softc *sc, int rid)
 {
 	struct puc_bar *bar;
 	struct rman *rm;
-	u_long end, start;
+	rman_res_t end, start;
 	int error, i;
 
 	/* Find the BAR entry with the given RID. */
@@ -474,7 +474,7 @@ puc_bfe_probe(device_t dev, const struct puc_cfg *cfg)
 
 struct resource *
 puc_bus_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct puc_port *port;
 	struct resource *res;
@@ -567,11 +567,11 @@ puc_bus_release_resource(device_t dev, device_t child, int type, int rid,
 
 int
 puc_bus_get_resource(device_t dev, device_t child, int type, int rid,
-    u_long *startp, u_long *countp)
+    rman_res_t *startp, rman_res_t *countp)
 {
 	struct puc_port *port;
 	struct resource *res;
-	u_long start;
+	rman_res_t start;
 
 	/* Get our immediate child. */
 	while (child != NULL && device_get_parent(child) != dev)
diff --git a/sys/dev/puc/puc_bfe.h b/sys/dev/puc/puc_bfe.h
index 9f2f3fbd16fc..912958b3becb 100644
--- a/sys/dev/puc/puc_bfe.h
+++ b/sys/dev/puc/puc_bfe.h
@@ -85,9 +85,9 @@ int puc_bfe_probe(device_t, const struct puc_cfg *);
 
 int puc_bus_child_location_str(device_t, device_t, char *, size_t);
 int puc_bus_child_pnpinfo_str(device_t, device_t, char *, size_t);
-struct resource *puc_bus_alloc_resource(device_t, device_t, int, int *, u_long,
-    u_long, u_long, u_int);
-int puc_bus_get_resource(device_t, device_t, int, int, u_long *, u_long *);
+struct resource *puc_bus_alloc_resource(device_t, device_t, int, int *,
+    rman_res_t, rman_res_t, rman_res_t, u_int);
+int puc_bus_get_resource(device_t, device_t, int, int, rman_res_t *, rman_res_t *);
 int puc_bus_print_child(device_t, device_t);
 int puc_bus_read_ivar(device_t, device_t, int, uintptr_t *);
 int puc_bus_release_resource(device_t, device_t, int, int, struct resource *);
diff --git a/sys/dev/quicc/quicc_bfe.h b/sys/dev/quicc/quicc_bfe.h
index 5c589146ac47..a08e4cf3f8d0 100644
--- a/sys/dev/quicc/quicc_bfe.h
+++ b/sys/dev/quicc/quicc_bfe.h
@@ -61,8 +61,9 @@ int quicc_bfe_detach(device_t);
 int quicc_bfe_probe(device_t, u_int);
 
 struct resource *quicc_bus_alloc_resource(device_t, device_t, int, int *,
-    u_long, u_long, u_long, u_int);
-int quicc_bus_get_resource(device_t, device_t, int, int, u_long *, u_long *);
+    rman_res_t, rman_res_t, rman_res_t, u_int);
+int quicc_bus_get_resource(device_t, device_t, int, int,
+    rman_res_t *, rman_res_t *);
 int quicc_bus_read_ivar(device_t, device_t, int, uintptr_t *);
 int quicc_bus_release_resource(device_t, device_t, int, int, struct resource *);
 int quicc_bus_setup_intr(device_t, device_t, struct resource *, int,
diff --git a/sys/dev/quicc/quicc_core.c b/sys/dev/quicc/quicc_core.c
index 532bb8e3dfe2..16525d63e28a 100644
--- a/sys/dev/quicc/quicc_core.c
+++ b/sys/dev/quicc/quicc_core.c
@@ -101,7 +101,7 @@ quicc_bfe_attach(device_t dev)
 	struct quicc_softc *sc;
 	struct resource_list_entry *rle;
 	const char *sep;
-	u_long size, start;
+	rman_res_t size, start;
 	int error;
 
 	sc = device_get_softc(dev);
@@ -254,7 +254,7 @@ quicc_bfe_probe(device_t dev, u_int clock)
 
 struct resource *
 quicc_bus_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct quicc_device *qd;
 	struct resource_list_entry *rle;
@@ -284,7 +284,7 @@ quicc_bus_alloc_resource(device_t dev, device_t child, int type, int *rid,
 
 int
 quicc_bus_get_resource(device_t dev, device_t child, int type, int rid,
-    u_long *startp, u_long *countp)
+    rman_res_t *startp, rman_res_t *countp)
 {
 	struct quicc_device *qd;
 	struct resource_list_entry *rle;
diff --git a/sys/dev/scc/scc_bfe.h b/sys/dev/scc/scc_bfe.h
index 33acdc52d152..be52707bd110 100644
--- a/sys/dev/scc/scc_bfe.h
+++ b/sys/dev/scc/scc_bfe.h
@@ -143,8 +143,8 @@ int scc_bfe_detach(device_t dev);
 int scc_bfe_probe(device_t dev, u_int regshft, u_int rclk, u_int rid);
 
 struct resource *scc_bus_alloc_resource(device_t, device_t, int, int *,
-    u_long, u_long, u_long, u_int);
-int scc_bus_get_resource(device_t, device_t, int, int, u_long *, u_long *);
+    rman_res_t, rman_res_t, rman_res_t, u_int);
+int scc_bus_get_resource(device_t, device_t, int, int, rman_res_t *, rman_res_t *);
 int scc_bus_read_ivar(device_t, device_t, int, uintptr_t *);
 int scc_bus_release_resource(device_t, device_t, int, int, struct resource *);
 int scc_bus_setup_intr(device_t, device_t, struct resource *, int,
diff --git a/sys/dev/scc/scc_core.c b/sys/dev/scc/scc_core.c
index 7c96426e768d..6b0558a95fe9 100644
--- a/sys/dev/scc/scc_core.c
+++ b/sys/dev/scc/scc_core.c
@@ -103,7 +103,7 @@ scc_bfe_attach(device_t dev, u_int ipc)
 	struct scc_softc *sc, *sc0;
 	const char *sep;
 	bus_space_handle_t bh;
-	u_long base, size, start, sz;
+	rman_res_t base, size, start, sz;
 	int c, error, mode, sysdev;
 
 	/*
@@ -407,7 +407,7 @@ scc_bfe_probe(device_t dev, u_int regshft, u_int rclk, u_int rid)
 
 struct resource *
 scc_bus_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource_list_entry *rle;
 	struct scc_chan *ch;
@@ -431,7 +431,7 @@ scc_bus_alloc_resource(device_t dev, device_t child, int type, int *rid,
 
 int
 scc_bus_get_resource(device_t dev, device_t child, int type, int rid,
-    u_long *startp, u_long *countp)
+    rman_res_t *startp, rman_res_t *countp)
 {
 	struct resource_list_entry *rle;
 	struct scc_chan *ch;
diff --git a/sys/dev/siba/siba.c b/sys/dev/siba/siba.c
index ebe7190166ce..8c3898c7b8bd 100644
--- a/sys/dev/siba/siba.c
+++ b/sys/dev/siba/siba.c
@@ -92,8 +92,8 @@ static int	siba_activate_resource(device_t, device_t, int, int,
 		    struct resource *);
 static device_t	siba_add_child(device_t, u_int, const char *, int);
 static struct resource *
-		siba_alloc_resource(device_t, device_t, int, int *, u_long,
-		    u_long, u_long, u_int);
+		siba_alloc_resource(device_t, device_t, int, int *, rman_res_t,
+		    rman_res_t, rman_res_t, u_int);
 static int	siba_attach(device_t);
 #ifdef notyet
 static void	siba_destroy_devinfo(struct siba_devinfo *);
@@ -371,7 +371,7 @@ siba_print_child(device_t bus, device_t child)
 
 static struct resource *
 siba_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource			*rv;
 	struct resource_list		*rl;
diff --git a/sys/dev/siba/siba_bwn.c b/sys/dev/siba/siba_bwn.c
index 2cd3d4a2786e..3cb784e56e80 100644
--- a/sys/dev/siba/siba_bwn.c
+++ b/sys/dev/siba/siba_bwn.c
@@ -242,7 +242,7 @@ siba_bwn_resume(device_t dev)
 /* proxying to the parent */
 static struct resource *
 siba_bwn_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 
 	return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
diff --git a/sys/dev/siba/siba_pcib.c b/sys/dev/siba/siba_pcib.c
index 6236aedcbe0a..cd755c030187 100644
--- a/sys/dev/siba/siba_pcib.c
+++ b/sys/dev/siba/siba_pcib.c
@@ -92,7 +92,7 @@ static int	siba_pcib_activate_resource(device_t, device_t, int,
 		    int, struct resource *);
 static struct resource *
 		siba_pcib_alloc_resource(device_t, device_t, int, int *,
-		    u_long , u_long, u_long, u_int);
+		    rman_res_t , rman_res_t, rman_res_t, u_int);
 static int	siba_pcib_attach(device_t);
 static int	siba_pcib_deactivate_resource(device_t, device_t, int,
 		    int, struct resource *);
@@ -249,7 +249,7 @@ siba_pcib_teardown_intr(device_t dev, device_t child, struct resource *vec,
 
 static struct resource *
 siba_pcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 #if 1
 
diff --git a/sys/dev/siis/siis.c b/sys/dev/siis/siis.c
index 301b9e9d8377..9ceb444c5966 100644
--- a/sys/dev/siis/siis.c
+++ b/sys/dev/siis/siis.c
@@ -314,7 +314,7 @@ siis_intr(void *data)
 
 static struct resource *
 siis_alloc_resource(device_t dev, device_t child, int type, int *rid,
-		       u_long start, u_long end, u_long count, u_int flags)
+		    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct siis_controller *ctlr = device_get_softc(dev);
 	int unit = ((struct siis_channel *)device_get_softc(child))->unit;
diff --git a/sys/dev/snc/if_snc_cbus.c b/sys/dev/snc/if_snc_cbus.c
index c3c7946a4b65..eea025034e61 100644
--- a/sys/dev/snc/if_snc_cbus.c
+++ b/sys/dev/snc/if_snc_cbus.c
@@ -72,7 +72,7 @@ snc_isapnp_reconfig(device_t dev)
 {
 	struct isa_device *idev = DEVTOISA(dev);
         struct isa_config config;
-	u_long start, count;
+	rman_res_t start, count;
 	int rid;
 
 	bzero(&config, sizeof(config));
diff --git a/sys/dev/sound/isa/gusc.c b/sys/dev/sound/isa/gusc.c
index a45e7e693fb0..d6fd90f73417 100644
--- a/sys/dev/sound/isa/gusc.c
+++ b/sys/dev/sound/isa/gusc.c
@@ -91,7 +91,7 @@ static int gusc_attach(device_t dev);
 static int gusisa_probe(device_t dev);
 static void gusc_intr(void *);
 static struct resource *gusc_alloc_resource(device_t bus, device_t child, int type, int *rid,
-					      u_long start, u_long end, u_long count, u_int flags);
+					    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags);
 static int gusc_release_resource(device_t bus, device_t child, int type, int rid,
 				   struct resource *r);
 
@@ -350,7 +350,7 @@ gusc_intr(void *arg)
 
 static struct resource *
 gusc_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		      u_long start, u_long end, u_long count, u_int flags)
+		    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	sc_p scp;
 	int *alloced, rid_max, alloced_max;
diff --git a/sys/dev/sound/isa/sbc.c b/sys/dev/sound/isa/sbc.c
index 6f8f64e084c5..3a323651b116 100644
--- a/sys/dev/sound/isa/sbc.c
+++ b/sys/dev/sound/isa/sbc.c
@@ -80,7 +80,7 @@ static int sbc_attach(device_t dev);
 static void sbc_intr(void *p);
 
 static struct resource *sbc_alloc_resource(device_t bus, device_t child, int type, int *rid,
-					   u_long start, u_long end, u_long count, u_int flags);
+					   rman_res_t start, rman_res_t end, rman_res_t count, u_int flags);
 static int sbc_release_resource(device_t bus, device_t child, int type, int rid,
 				struct resource *r);
 static int sbc_setup_intr(device_t dev, device_t child, struct resource *irq,
@@ -573,7 +573,7 @@ sbc_teardown_intr(device_t dev, device_t child, struct resource *irq,
 
 static struct resource *
 sbc_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		      u_long start, u_long end, u_long count, u_int flags)
+		   rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct sbc_softc *scp;
 	int *alloced, rid_max, alloced_max;
diff --git a/sys/dev/sound/pci/csa.c b/sys/dev/sound/pci/csa.c
index e40641066f3c..5dbc7be0c586 100644
--- a/sys/dev/sound/pci/csa.c
+++ b/sys/dev/sound/pci/csa.c
@@ -81,7 +81,8 @@ typedef struct csa_softc *sc_p;
 static int csa_probe(device_t dev);
 static int csa_attach(device_t dev);
 static struct resource *csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
-					      u_long start, u_long end, u_long count, u_int flags);
+					      rman_res_t start, rman_res_t end,
+					      rman_res_t count, u_int flags);
 static int csa_release_resource(device_t bus, device_t child, int type, int rid,
 				   struct resource *r);
 static int csa_setup_intr(device_t bus, device_t child,
@@ -396,7 +397,7 @@ csa_resume(device_t dev)
 
 static struct resource *
 csa_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		      u_long start, u_long end, u_long count, u_int flags)
+		   rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	sc_p scp;
 	csa_res *resp;
diff --git a/sys/dev/sound/pci/fm801.c b/sys/dev/sound/pci/fm801.c
index 969d53261ea9..82b1d7780bcb 100644
--- a/sys/dev/sound/pci/fm801.c
+++ b/sys/dev/sound/pci/fm801.c
@@ -716,7 +716,8 @@ fm801_pci_probe( device_t dev )
 
 static struct resource *
 fm801_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		     u_long start, u_long end, u_long count, u_int flags)
+		     rman_res_t start, rman_res_t end, rman_res_t count,
+		     u_int flags)
 {
 	struct fm801_info *fm801;
 
diff --git a/sys/dev/sound/pci/vibes.c b/sys/dev/sound/pci/vibes.c
index f0cb57fbaacc..2c7453604471 100644
--- a/sys/dev/sound/pci/vibes.c
+++ b/sys/dev/sound/pci/vibes.c
@@ -721,9 +721,10 @@ sv_probe(device_t dev)
 static int
 sv_attach(device_t dev) {
 	struct sc_info	*sc;
+	rman_res_t	count, midi_start, games_start;
 	u_int32_t	data;
 	char		status[SND_STATUSLEN];
-	u_long		midi_start, games_start, count, sdmaa, sdmac, ml, mu;
+	u_long		sdmaa, sdmac, ml, mu;
 
 	sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
 	sc->dev = dev;
diff --git a/sys/dev/stg/tmc18c30_subr.c b/sys/dev/stg/tmc18c30_subr.c
index 8c686d673563..98cf1b424096 100644
--- a/sys/dev/stg/tmc18c30_subr.c
+++ b/sys/dev/stg/tmc18c30_subr.c
@@ -65,7 +65,7 @@ int
 stg_alloc_resource(device_t dev)
 {
 	struct stg_softc *	sc = device_get_softc(dev);
-	u_long			maddr, msize;
+	rman_res_t		maddr, msize;
 	int			error;
 
 	mtx_init(&sc->sc_sclow.sl_lock, "stg", NULL, MTX_DEF);
diff --git a/sys/dev/wl/if_wl.c b/sys/dev/wl/if_wl.c
index 23835c6079b2..b3b92d6c2798 100644
--- a/sys/dev/wl/if_wl.c
+++ b/sys/dev/wl/if_wl.c
@@ -388,7 +388,7 @@ wlprobe(device_t device)
     struct wl_softc	*sc;
     char		*str = "wl%d: board out of range [0..%d]\n";
     u_char		inbuf[100];
-    unsigned long	junk, sirq;
+    rman_res_t		junk, sirq;
     int			error, irq;
 
     error = ISA_PNP_PROBE(device_get_parent(device), device, wl_ids);
diff --git a/sys/isa/isa_common.c b/sys/isa/isa_common.c
index 9e10320a5ae7..7c114594f56f 100644
--- a/sys/isa/isa_common.c
+++ b/sys/isa/isa_common.c
@@ -928,7 +928,7 @@ isa_driver_added(device_t dev, driver_t *driver)
 
 static int
 isa_set_resource(device_t dev, device_t child, int type, int rid,
-    u_long start, u_long count)
+    rman_res_t start, rman_res_t count)
 {
 	struct isa_device* idev = DEVTOISA(child);
 	struct resource_list *rl = &idev->id_resources;
diff --git a/sys/isa/isa_common.h b/sys/isa/isa_common.h
index a6702f492af3..977e222e6776 100644
--- a/sys/isa/isa_common.h
+++ b/sys/isa/isa_common.h
@@ -69,7 +69,8 @@ struct isa_device {
  */
 extern void isa_init(device_t dev);
 extern struct resource *isa_alloc_resource(device_t bus, device_t child,
-    int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
+    int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count,
+    u_int flags);
 extern int isa_release_resource(device_t bus, device_t child,
     int type, int rid, struct resource *r);
 
diff --git a/sys/kern/bus_if.m b/sys/kern/bus_if.m
index bafa448488cf..e55b1ce9ea6b 100644
--- a/sys/kern/bus_if.m
+++ b/sys/kern/bus_if.m
@@ -44,8 +44,8 @@ INTERFACE bus;
 CODE {
 	static struct resource *
 	null_alloc_resource(device_t dev, device_t child,
-	    int type, int *rid, u_long start, u_long end,
-	    u_long count, u_int flags)
+	    int type, int *rid, rman_res_t start, rman_res_t end,
+	    rman_res_t count, u_int flags)
 	{
 	    return (0);
 	}
@@ -264,9 +264,9 @@ METHOD struct resource * alloc_resource {
 	device_t	_child;
 	int		_type;
 	int	       *_rid;
-	u_long		_start;
-	u_long		_end;
-	u_long		_count;
+	rman_res_t	_start;
+	rman_res_t	_end;
+	rman_res_t	_count;
 	u_int		_flags;
 } DEFAULT null_alloc_resource;
 
@@ -332,8 +332,8 @@ METHOD int adjust_resource {
 	device_t	_child;
 	int		_type;
 	struct resource *_res;
-	u_long		_start;
-	u_long		_end;
+	rman_res_t	_start;
+	rman_res_t	_end;
 };
 
 /**
@@ -433,8 +433,8 @@ METHOD int set_resource {
 	device_t	_child;
 	int		_type;
 	int		_rid;
-	u_long		_start;
-	u_long		_count;
+	rman_res_t	_start;
+	rman_res_t	_count;
 };
 
 /**
@@ -457,8 +457,8 @@ METHOD int get_resource {
 	device_t	_child;
 	int		_type;
 	int		_rid;
-	u_long		*_startp;
-	u_long		*_countp;
+	rman_res_t	*_startp;
+	rman_res_t	*_countp;
 };
 
 /**
diff --git a/sys/kern/subr_bus.c b/sys/kern/subr_bus.c
index b1159b606ce8..6aca991954c3 100644
--- a/sys/kern/subr_bus.c
+++ b/sys/kern/subr_bus.c
@@ -3063,8 +3063,8 @@ resource_list_free(struct resource_list *rl)
  * @param count		XXX end-start+1
  */
 int
-resource_list_add_next(struct resource_list *rl, int type, u_long start,
-    u_long end, u_long count)
+resource_list_add_next(struct resource_list *rl, int type, rman_res_t start,
+    rman_res_t end, rman_res_t count)
 {
 	int rid;
 
@@ -3092,7 +3092,7 @@ resource_list_add_next(struct resource_list *rl, int type, u_long start,
  */
 struct resource_list_entry *
 resource_list_add(struct resource_list *rl, int type, int rid,
-    u_long start, u_long end, u_long count)
+    rman_res_t start, rman_res_t end, rman_res_t count)
 {
 	struct resource_list_entry *rle;
 
@@ -3250,7 +3250,7 @@ resource_list_delete(struct resource_list *rl, int type, int rid)
  */
 struct resource *
 resource_list_reserve(struct resource_list *rl, device_t bus, device_t child,
-    int type, int *rid, u_long start, u_long end, u_long count, u_int flags)
+    int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource_list_entry *rle = NULL;
 	int passthrough = (device_get_parent(child) != bus);
@@ -3307,7 +3307,7 @@ resource_list_reserve(struct resource_list *rl, device_t bus, device_t child,
  */
 struct resource *
 resource_list_alloc(struct resource_list *rl, device_t bus, device_t child,
-    int type, int *rid, u_long start, u_long end, u_long count, u_int flags)
+    int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource_list_entry *rle = NULL;
 	int passthrough = (device_get_parent(child) != bus);
@@ -3949,7 +3949,7 @@ bus_generic_teardown_intr(device_t dev, device_t child, struct resource *irq,
  */
 int
 bus_generic_adjust_resource(device_t dev, device_t child, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 	/* Propagate up the bus hierarchy until someone handles it. */
 	if (dev->parent)
@@ -3966,7 +3966,7 @@ bus_generic_adjust_resource(device_t dev, device_t child, int type,
  */
 struct resource *
 bus_generic_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	/* Propagate up the bus hierarchy until someone handles it. */
 	if (dev->parent)
@@ -4104,7 +4104,7 @@ bus_generic_get_dma_tag(device_t dev, device_t child)
  */
 int
 bus_generic_rl_get_resource(device_t dev, device_t child, int type, int rid,
-    u_long *startp, u_long *countp)
+    rman_res_t *startp, rman_res_t *countp)
 {
 	struct resource_list *		rl = NULL;
 	struct resource_list_entry *	rle = NULL;
@@ -4135,7 +4135,7 @@ bus_generic_rl_get_resource(device_t dev, device_t child, int type, int rid,
  */
 int
 bus_generic_rl_set_resource(device_t dev, device_t child, int type, int rid,
-    u_long start, u_long count)
+    rman_res_t start, rman_res_t count)
 {
 	struct resource_list *		rl = NULL;
 
@@ -4203,7 +4203,7 @@ bus_generic_rl_release_resource(device_t dev, device_t child, int type,
  */
 struct resource *
 bus_generic_rl_alloc_resource(device_t dev, device_t child, int type,
-    int *rid, u_long start, u_long end, u_long count, u_int flags)
+    int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource_list *		rl = NULL;
 
@@ -4289,8 +4289,8 @@ bus_release_resources(device_t dev, const struct resource_spec *rs,
  * parent of @p dev.
  */
 struct resource *
-bus_alloc_resource(device_t dev, int type, int *rid, u_long start, u_long end,
-    u_long count, u_int flags)
+bus_alloc_resource(device_t dev, int type, int *rid, rman_res_t start, rman_res_t end,
+    rman_res_t count, u_int flags)
 {
 	if (dev->parent == NULL)
 		return (NULL);
@@ -4305,8 +4305,8 @@ bus_alloc_resource(device_t dev, int type, int *rid, u_long start, u_long end,
  * parent of @p dev.
  */
 int
-bus_adjust_resource(device_t dev, int type, struct resource *r, u_long start,
-    u_long end)
+bus_adjust_resource(device_t dev, int type, struct resource *r, rman_res_t start,
+    rman_res_t end)
 {
 	if (dev->parent == NULL)
 		return (EINVAL);
@@ -4436,7 +4436,7 @@ bus_describe_intr(device_t dev, struct resource *irq, void *cookie,
  */
 int
 bus_set_resource(device_t dev, int type, int rid,
-    u_long start, u_long count)
+    rman_res_t start, rman_res_t count)
 {
 	return (BUS_SET_RESOURCE(device_get_parent(dev), dev, type, rid,
 	    start, count));
@@ -4450,7 +4450,7 @@ bus_set_resource(device_t dev, int type, int rid,
  */
 int
 bus_get_resource(device_t dev, int type, int rid,
-    u_long *startp, u_long *countp)
+    rman_res_t *startp, rman_res_t *countp)
 {
 	return (BUS_GET_RESOURCE(device_get_parent(dev), dev, type, rid,
 	    startp, countp));
@@ -4462,10 +4462,11 @@ bus_get_resource(device_t dev, int type, int rid,
  * This function simply calls the BUS_GET_RESOURCE() method of the
  * parent of @p dev and returns the start value.
  */
-u_long
+rman_res_t
 bus_get_resource_start(device_t dev, int type, int rid)
 {
-	u_long start, count;
+	rman_res_t start;
+	rman_res_t count;
 	int error;
 
 	error = BUS_GET_RESOURCE(device_get_parent(dev), dev, type, rid,
@@ -4481,10 +4482,11 @@ bus_get_resource_start(device_t dev, int type, int rid)
  * This function simply calls the BUS_GET_RESOURCE() method of the
  * parent of @p dev and returns the count value.
  */
-u_long
+rman_res_t
 bus_get_resource_count(device_t dev, int type, int rid)
 {
-	u_long start, count;
+	rman_res_t start;
+	rman_res_t count;
 	int error;
 
 	error = BUS_GET_RESOURCE(device_get_parent(dev), dev, type, rid,
diff --git a/sys/kern/subr_rman.c b/sys/kern/subr_rman.c
index 310bd5e521ec..3050e443d62a 100644
--- a/sys/kern/subr_rman.c
+++ b/sys/kern/subr_rman.c
@@ -90,8 +90,8 @@ struct resource_i {
 	TAILQ_ENTRY(resource_i)	r_link;
 	LIST_ENTRY(resource_i)	r_sharelink;
 	LIST_HEAD(, resource_i)	*r_sharehead;
-	u_long	r_start;	/* index of the first entry in this resource */
-	u_long	r_end;		/* index of the last entry (inclusive) */
+	rman_res_t	r_start;	/* index of the first entry in this resource */
+	rman_res_t	r_end;		/* index of the last entry (inclusive) */
 	u_int	r_flags;
 	void	*r_virtual;	/* virtual address of this resource */
 	struct device *r_dev;	/* device which has allocated this resource */
@@ -154,7 +154,7 @@ rman_init(struct rman *rm)
 }
 
 int
-rman_manage_region(struct rman *rm, u_long start, u_long end)
+rman_manage_region(struct rman *rm, rman_res_t start, rman_res_t end)
 {
 	struct resource_i *r, *s, *t;
 	int rv = 0;
@@ -274,7 +274,7 @@ rman_fini(struct rman *rm)
 }
 
 int
-rman_first_free_region(struct rman *rm, u_long *start, u_long *end)
+rman_first_free_region(struct rman *rm, rman_res_t *start, rman_res_t *end)
 {
 	struct resource_i *r;
 
@@ -292,7 +292,7 @@ rman_first_free_region(struct rman *rm, u_long *start, u_long *end)
 }
 
 int
-rman_last_free_region(struct rman *rm, u_long *start, u_long *end)
+rman_last_free_region(struct rman *rm, rman_res_t *start, rman_res_t *end)
 {
 	struct resource_i *r;
 
@@ -311,7 +311,7 @@ rman_last_free_region(struct rman *rm, u_long *start, u_long *end)
 
 /* Shrink or extend one or both ends of an allocated resource. */
 int
-rman_adjust_resource(struct resource *rr, u_long start, u_long end)
+rman_adjust_resource(struct resource *rr, rman_res_t start, rman_res_t end)
 {
 	struct resource_i *r, *s, *t, *new;
 	struct rman *rm;
@@ -434,13 +434,13 @@ rman_adjust_resource(struct resource *rr, u_long start, u_long end)
 #define	SHARE_TYPE(f)	(f & (RF_SHAREABLE | RF_PREFETCHABLE))
 
 struct resource *
-rman_reserve_resource_bound(struct rman *rm, u_long start, u_long end,
-			    u_long count, u_long bound, u_int flags,
+rman_reserve_resource_bound(struct rman *rm, rman_res_t start, rman_res_t end,
+			    rman_res_t count, rman_res_t bound, u_int flags,
 			    struct device *dev)
 {
 	u_int new_rflags;
 	struct resource_i *r, *s, *rv;
-	u_long rstart, rend, amask, bmask;
+	rman_res_t rstart, rend, amask, bmask;
 
 	rv = NULL;
 
@@ -641,8 +641,8 @@ rman_reserve_resource_bound(struct rman *rm, u_long start, u_long end,
 }
 
 struct resource *
-rman_reserve_resource(struct rman *rm, u_long start, u_long end, u_long count,
-		      u_int flags, struct device *dev)
+rman_reserve_resource(struct rman *rm, rman_res_t start, rman_res_t end,
+		      rman_res_t count, u_int flags, struct device *dev)
 {
 
 	return (rman_reserve_resource_bound(rm, start, end, count, 0, flags,
@@ -803,13 +803,13 @@ rman_make_alignment_flags(uint32_t size)
 }
 
 void
-rman_set_start(struct resource *r, u_long start)
+rman_set_start(struct resource *r, rman_res_t start)
 {
 
 	r->__r_i->r_start = start;
 }
 
-u_long
+rman_res_t
 rman_get_start(struct resource *r)
 {
 
@@ -817,20 +817,20 @@ rman_get_start(struct resource *r)
 }
 
 void
-rman_set_end(struct resource *r, u_long end)
+rman_set_end(struct resource *r, rman_res_t end)
 {
 
 	r->__r_i->r_end = end;
 }
 
-u_long
+rman_res_t
 rman_get_end(struct resource *r)
 {
 
 	return (r->__r_i->r_end);
 }
 
-u_long
+rman_res_t
 rman_get_size(struct resource *r)
 {
 
diff --git a/sys/mips/adm5120/admpci.c b/sys/mips/adm5120/admpci.c
index e8a14a12c436..9b36d37f3f15 100644
--- a/sys/mips/adm5120/admpci.c
+++ b/sys/mips/adm5120/admpci.c
@@ -356,7 +356,7 @@ admpci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
 
 static struct resource *
 admpci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 
 	return (NULL);
diff --git a/sys/mips/adm5120/obio.c b/sys/mips/adm5120/obio.c
index 788e3a8ab9c3..46c09b7ab8ee 100644
--- a/sys/mips/adm5120/obio.c
+++ b/sys/mips/adm5120/obio.c
@@ -103,8 +103,8 @@ static int	obio_activate_resource(device_t, device_t, int, int,
 		    struct resource *);
 static device_t	obio_add_child(device_t, u_int, const char *, int);
 static struct resource *
-		obio_alloc_resource(device_t, device_t, int, int *, u_long,
-		    u_long, u_long, u_int);
+		obio_alloc_resource(device_t, device_t, int, int *, rman_res_t,
+		    rman_res_t, rman_res_t, u_int);
 static int	obio_attach(device_t);
 static int	obio_deactivate_resource(device_t, device_t, int, int,
 		    struct resource *);
@@ -222,7 +222,7 @@ obio_attach(device_t dev)
 
 static struct resource *
 obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct obio_softc		*sc = device_get_softc(bus);
 	struct obio_ivar		*ivar = device_get_ivars(child);
diff --git a/sys/mips/alchemy/obio.c b/sys/mips/alchemy/obio.c
index da05bbbfd20e..3c0fecbdac16 100644
--- a/sys/mips/alchemy/obio.c
+++ b/sys/mips/alchemy/obio.c
@@ -103,8 +103,8 @@ static int	obio_activate_resource(device_t, device_t, int, int,
 		    struct resource *);
 static device_t	obio_add_child(device_t, u_int, const char *, int);
 static struct resource *
-		obio_alloc_resource(device_t, device_t, int, int *, u_long,
-		    u_long, u_long, u_int);
+		obio_alloc_resource(device_t, device_t, int, int *, rman_res_t,
+		    rman_res_t, rman_res_t, u_int);
 static int	obio_attach(device_t);
 static int	obio_deactivate_resource(device_t, device_t, int, int,
 		    struct resource *);
@@ -223,7 +223,7 @@ obio_attach(device_t dev)
 
 static struct resource *
 obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct obio_softc		*sc = device_get_softc(bus);
 	struct obio_ivar		*ivar = device_get_ivars(child);
diff --git a/sys/mips/atheros/apb.c b/sys/mips/atheros/apb.c
index adc375650c96..c072567854c8 100644
--- a/sys/mips/atheros/apb.c
+++ b/sys/mips/atheros/apb.c
@@ -63,8 +63,8 @@ static int	apb_activate_resource(device_t, device_t, int, int,
 		    struct resource *);
 static device_t	apb_add_child(device_t, u_int, const char *, int);
 static struct resource *
-		apb_alloc_resource(device_t, device_t, int, int *, u_long,
-		    u_long, u_long, u_int);
+		apb_alloc_resource(device_t, device_t, int, int *, rman_res_t,
+		    rman_res_t, rman_res_t, u_int);
 static int	apb_attach(device_t);
 static int	apb_deactivate_resource(device_t, device_t, int, int,
 		    struct resource *);
@@ -161,7 +161,7 @@ apb_attach(device_t dev)
 
 static struct resource *
 apb_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct apb_softc		*sc = device_get_softc(bus);
 	struct apb_ivar			*ivar = device_get_ivars(child);
diff --git a/sys/mips/atheros/ar71xx_pci.c b/sys/mips/atheros/ar71xx_pci.c
index f745949d8d43..183f8841fee7 100644
--- a/sys/mips/atheros/ar71xx_pci.c
+++ b/sys/mips/atheros/ar71xx_pci.c
@@ -500,7 +500,7 @@ ar71xx_pci_write_ivar(device_t dev, device_t child, int which,
 
 static struct resource *
 ar71xx_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 
 	struct ar71xx_pci_softc *sc = device_get_softc(bus);
diff --git a/sys/mips/atheros/ar724x_pci.c b/sys/mips/atheros/ar724x_pci.c
index ad8ec09640fd..3b01801d04a9 100644
--- a/sys/mips/atheros/ar724x_pci.c
+++ b/sys/mips/atheros/ar724x_pci.c
@@ -465,7 +465,7 @@ ar724x_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
 
 static struct resource *
 ar724x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct ar71xx_pci_softc *sc = device_get_softc(bus);	
 	struct resource *rv;
diff --git a/sys/mips/atheros/qca955x_pci.c b/sys/mips/atheros/qca955x_pci.c
index 0d78c1eb76b8..626ca377dfc9 100644
--- a/sys/mips/atheros/qca955x_pci.c
+++ b/sys/mips/atheros/qca955x_pci.c
@@ -398,7 +398,7 @@ qca955x_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result
 
 static struct resource *
 qca955x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct ar71xx_pci_softc *sc = device_get_softc(bus);
 	struct resource *rv;
diff --git a/sys/mips/beri/beri_simplebus.c b/sys/mips/beri/beri_simplebus.c
index 54f654a52ac1..31771a5617f2 100644
--- a/sys/mips/beri/beri_simplebus.c
+++ b/sys/mips/beri/beri_simplebus.c
@@ -85,7 +85,7 @@ static int simplebus_teardown_intr(device_t, device_t, struct resource *,
 static int simplebus_activate_resource(device_t, device_t, int, int,
     struct resource *);
 static struct resource *simplebus_alloc_resource(device_t, device_t, int,
-    int *, u_long, u_long, u_long, u_int);
+    int *, rman_res_t, rman_res_t, rman_res_t, u_int);
 static int simplebus_deactivate_resource(device_t, device_t, int, int,
     struct resource *);
 static int simplebus_release_resource(device_t, device_t, int, int,
@@ -250,7 +250,7 @@ simplebus_print_child(device_t dev, device_t child)
 
 static struct resource *
 simplebus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	device_t ic;
 	struct simplebus_devinfo *di;
diff --git a/sys/mips/cavium/ciu.c b/sys/mips/cavium/ciu.c
index 4e069f9b1aab..b4726c58add4 100644
--- a/sys/mips/cavium/ciu.c
+++ b/sys/mips/cavium/ciu.c
@@ -75,7 +75,8 @@ static struct intr_event *ciu_en1_intr_events[CIU_IRQ_EN1_COUNT];
 static int		ciu_probe(device_t);
 static int		ciu_attach(device_t);
 static struct resource	*ciu_alloc_resource(device_t, device_t, int, int *,
-					    u_long, u_long, u_long, u_int);
+					    rman_res_t, rman_res_t, rman_res_t,
+					    u_int);
 static int		ciu_setup_intr(device_t, device_t, struct resource *,
 				       int, driver_filter_t *, driver_intr_t *,
 				       void *, void **);
@@ -171,7 +172,7 @@ ciu_attach(device_t dev)
 
 static struct resource *
 ciu_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		   u_long start, u_long end, u_long count, u_int flags)
+		   rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *res;
 	struct ciu_softc *sc;
diff --git a/sys/mips/cavium/obio.c b/sys/mips/cavium/obio.c
index f3b3bbb8a815..82e5c369ef64 100644
--- a/sys/mips/cavium/obio.c
+++ b/sys/mips/cavium/obio.c
@@ -119,7 +119,7 @@ obio_attach(device_t dev)
 
 static struct resource *
 obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *rv;
 	struct rman *rm;
diff --git a/sys/mips/cavium/octopci.c b/sys/mips/cavium/octopci.c
index f6d73bdc65cc..17a63420f70d 100644
--- a/sys/mips/cavium/octopci.c
+++ b/sys/mips/cavium/octopci.c
@@ -86,7 +86,8 @@ static int		octopci_attach(device_t);
 static int		octopci_read_ivar(device_t, device_t, int,
 					  uintptr_t *);
 static struct resource	*octopci_alloc_resource(device_t, device_t, int, int *,
-						u_long, u_long, u_long, u_int);
+						rman_res_t, rman_res_t,
+						rman_res_t, u_int);
 static int		octopci_activate_resource(device_t, device_t, int, int,
 						  struct resource *);
 static int	octopci_maxslots(device_t);
@@ -231,7 +232,7 @@ octopci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 
 static struct resource *
 octopci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct octopci_softc *sc;
 	struct resource *res;
diff --git a/sys/mips/idt/idtpci.c b/sys/mips/idt/idtpci.c
index d962e6872a36..46c276ae329e 100644
--- a/sys/mips/idt/idtpci.c
+++ b/sys/mips/idt/idtpci.c
@@ -465,7 +465,7 @@ idtpci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
 
 static struct resource *
 idtpci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 
 	struct idtpci_softc *sc = device_get_softc(bus);	
diff --git a/sys/mips/idt/obio.c b/sys/mips/idt/obio.c
index b7b917d69177..c8b4fef677ff 100644
--- a/sys/mips/idt/obio.c
+++ b/sys/mips/idt/obio.c
@@ -59,8 +59,8 @@ static int	obio_activate_resource(device_t, device_t, int, int,
 		    struct resource *);
 static device_t	obio_add_child(device_t, u_int, const char *, int);
 static struct resource *
-		obio_alloc_resource(device_t, device_t, int, int *, u_long,
-		    u_long, u_long, u_int);
+		obio_alloc_resource(device_t, device_t, int, int *, rman_res_t,
+		    rman_res_t, rman_res_t, u_int);
 static int	obio_attach(device_t);
 static int	obio_deactivate_resource(device_t, device_t, int, int,
 		    struct resource *);
@@ -156,7 +156,7 @@ obio_attach(device_t dev)
 
 static struct resource *
 obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct obio_softc		*sc = device_get_softc(bus);
 	struct obio_ivar		*ivar = device_get_ivars(child);
diff --git a/sys/mips/malta/gt.c b/sys/mips/malta/gt.c
index b9cff7d33afb..88746431e1b3 100644
--- a/sys/mips/malta/gt.c
+++ b/sys/mips/malta/gt.c
@@ -76,7 +76,7 @@ gt_attach(device_t dev)
 
 static struct resource *
 gt_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child,
 		    type, rid, start, end, count, flags));
diff --git a/sys/mips/malta/gt_pci.c b/sys/mips/malta/gt_pci.c
index add9c07540f1..5262e66548d2 100644
--- a/sys/mips/malta/gt_pci.c
+++ b/sys/mips/malta/gt_pci.c
@@ -150,7 +150,7 @@ static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int,
     uint32_t, int);
 static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin);
 static struct resource * gt_pci_alloc_resource(device_t, device_t, int, 
-    int *, u_long, u_long, u_long, u_int);
+    int *, rman_res_t, rman_res_t, rman_res_t, u_int);
 
 static void
 gt_pci_mask_irq(void *source)
@@ -631,7 +631,7 @@ gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
 
 static struct resource *
 gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct gt_pci_softc *sc = device_get_softc(bus);	
 	struct resource *rv = NULL;
diff --git a/sys/mips/malta/obio.c b/sys/mips/malta/obio.c
index 21958375fa65..64ac9c7dd854 100644
--- a/sys/mips/malta/obio.c
+++ b/sys/mips/malta/obio.c
@@ -111,7 +111,7 @@ obio_attach(device_t dev)
 
 static struct resource *
 obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *rv;
 	struct rman *rm;
diff --git a/sys/mips/mips/cpu.c b/sys/mips/mips/cpu.c
index 5abd5b66d5a7..60fe134d9ccf 100644
--- a/sys/mips/mips/cpu.c
+++ b/sys/mips/mips/cpu.c
@@ -400,7 +400,8 @@ static devclass_t cpu_devclass;
 static int cpu_probe(device_t);
 static int cpu_attach(device_t);
 static struct resource *cpu_alloc_resource(device_t, device_t, int, int *,
-					   u_long, u_long, u_long, u_int);
+					   rman_res_t, rman_res_t, rman_res_t,
+					   u_int);
 static int cpu_setup_intr(device_t, device_t, struct resource *, int,
 			  driver_filter_t *f, driver_intr_t *, void *, 
 			  void **);
@@ -473,7 +474,7 @@ cpu_attach(device_t dev)
 
 static struct resource *
 cpu_alloc_resource(device_t dev, device_t child, int type, int *rid,
-		   u_long start, u_long end, u_long count, u_int flags)
+		   rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *res;
 
diff --git a/sys/mips/mips/nexus.c b/sys/mips/mips/nexus.c
index 06c031762d8b..d2ee6afbaa52 100644
--- a/sys/mips/mips/nexus.c
+++ b/sys/mips/mips/nexus.c
@@ -81,22 +81,22 @@ static struct rman irq_rman;
 static struct rman mem_rman;
 
 static struct resource *
-		nexus_alloc_resource(device_t, device_t, int, int *, u_long,
-		    u_long, u_long, u_int);
+		nexus_alloc_resource(device_t, device_t, int, int *, rman_res_t,
+		    rman_res_t, rman_res_t, u_int);
 static device_t	nexus_add_child(device_t, u_int, const char *, int);
 static int	nexus_attach(device_t);
 static void	nexus_delete_resource(device_t, device_t, int, int);
 static struct resource_list *
 		nexus_get_reslist(device_t, device_t);
-static int	nexus_get_resource(device_t, device_t, int, int, u_long *,
-		    u_long *);
+static int	nexus_get_resource(device_t, device_t, int, int, rman_res_t *,
+		    rman_res_t *);
 static int	nexus_print_child(device_t, device_t);
 static int	nexus_print_all_resources(device_t dev);
 static int	nexus_probe(device_t);
 static int	nexus_release_resource(device_t, device_t, int, int,
 		    struct resource *);
-static int	nexus_set_resource(device_t, device_t, int, int, u_long,
-		    u_long);
+static int	nexus_set_resource(device_t, device_t, int, int, rman_res_t,
+		    rman_res_t);
 static int	nexus_activate_resource(device_t, device_t, int, int,
 		    struct resource *);
 static int	nexus_deactivate_resource(device_t, device_t, int, int,
@@ -236,7 +236,7 @@ nexus_add_child(device_t bus, u_int order, const char *name, int unit)
  */
 static struct resource *
 nexus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-	u_long start, u_long end, u_long count, u_int flags)
+	rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct nexus_device		*ndev = DEVTONX(child);
 	struct resource			*rv;
@@ -313,7 +313,7 @@ nexus_get_reslist(device_t dev, device_t child)
 
 static int
 nexus_set_resource(device_t dev, device_t child, int type, int rid,
-    u_long start, u_long count)
+    rman_res_t start, rman_res_t count)
 {
 	struct nexus_device		*ndev = DEVTONX(child);
 	struct resource_list		*rl = &ndev->nx_resources;
@@ -332,7 +332,7 @@ nexus_set_resource(device_t dev, device_t child, int type, int rid,
 
 static int
 nexus_get_resource(device_t dev, device_t child, int type, int rid,
-    u_long *startp, u_long *countp)
+    rman_res_t *startp, rman_res_t *countp)
 {
 	struct nexus_device		*ndev = DEVTONX(child);
 	struct resource_list		*rl = &ndev->nx_resources;
diff --git a/sys/mips/nlm/xlp_simplebus.c b/sys/mips/nlm/xlp_simplebus.c
index 5b5eca0d0db2..7d2f697d83a0 100644
--- a/sys/mips/nlm/xlp_simplebus.c
+++ b/sys/mips/nlm/xlp_simplebus.c
@@ -72,7 +72,7 @@ __FBSDID("$FreeBSD$");
  */
 static int		xlp_simplebus_probe(device_t dev);
 static struct resource *xlp_simplebus_alloc_resource(device_t, device_t, int,
-    int *, u_long, u_long, u_long, u_int);
+    int *, rman_res_t, rman_res_t, rman_res_t, u_int);
 static int		xlp_simplebus_activate_resource(device_t, device_t, int,
     int, struct resource *);
 static int		xlp_simplebus_setup_intr(device_t, device_t,
@@ -174,7 +174,7 @@ xlp_simplebus_probe(device_t dev)
 
 static struct resource *
 xlp_simplebus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct rman			*rm;
 	struct resource			*rv;
diff --git a/sys/mips/rmi/iodi.c b/sys/mips/rmi/iodi.c
index 2831834df215..c9c5c459e8e4 100644
--- a/sys/mips/rmi/iodi.c
+++ b/sys/mips/rmi/iodi.c
@@ -67,7 +67,7 @@ extern bus_space_tag_t uart_bus_space_mem;
 
 static struct resource *
 iodi_alloc_resource(device_t, device_t, int, int *,
-    u_long, u_long, u_long, u_int);
+    rman_res_t, rman_res_t, rman_res_t, u_int);
 
 static int
 iodi_activate_resource(device_t, device_t, int, int,
@@ -126,7 +126,7 @@ iodi_setup_intr(device_t dev, device_t child,
 
 static struct resource *
 iodi_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK);
 	const char *name = device_get_name(child);
diff --git a/sys/mips/rmi/xlr_pci.c b/sys/mips/rmi/xlr_pci.c
index b41a5588ecf5..c9d0b35d5e83 100644
--- a/sys/mips/rmi/xlr_pci.c
+++ b/sys/mips/rmi/xlr_pci.c
@@ -516,7 +516,7 @@ mips_platform_pci_teardown_intr(device_t dev, device_t child,
 
 static struct resource *
 xlr_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-	u_long start, u_long end, u_long count, u_int flags)
+	rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct rman *rm;
 	struct resource *rv;
diff --git a/sys/mips/rt305x/obio.c b/sys/mips/rt305x/obio.c
index ff7a32cfff4c..34cec413fd25 100644
--- a/sys/mips/rt305x/obio.c
+++ b/sys/mips/rt305x/obio.c
@@ -98,8 +98,8 @@ static int	obio_activate_resource(device_t, device_t, int, int,
 		    struct resource *);
 static device_t	obio_add_child(device_t, u_int, const char *, int);
 static struct resource *
-		obio_alloc_resource(device_t, device_t, int, int *, u_long,
-		    u_long, u_long, u_int);
+		obio_alloc_resource(device_t, device_t, int, int *, rman_res_t,
+		    rman_res_t, rman_res_t, u_int);
 static int	obio_attach(device_t);
 static int	obio_deactivate_resource(device_t, device_t, int, int,
 		    struct resource *);
@@ -278,7 +278,7 @@ obio_attach(device_t dev)
 
 static struct resource *
 obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct obio_softc		*sc = device_get_softc(bus);
 	struct obio_ivar		*ivar = device_get_ivars(child);
diff --git a/sys/mips/rt305x/rt305x_gpio.c b/sys/mips/rt305x/rt305x_gpio.c
index 1ce02d75f809..e4f645f9b1c6 100644
--- a/sys/mips/rt305x/rt305x_gpio.c
+++ b/sys/mips/rt305x/rt305x_gpio.c
@@ -546,7 +546,7 @@ rt305x_gpio_detach(device_t dev)
 #ifdef notyet
 static struct resource *
 rt305x_gpio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct obio_softc		*sc = device_get_softc(bus);
 	struct resource			*rv;
diff --git a/sys/mips/rt305x/rt305x_pci.c b/sys/mips/rt305x/rt305x_pci.c
index c681dc66c867..68a9d8679aef 100644
--- a/sys/mips/rt305x/rt305x_pci.c
+++ b/sys/mips/rt305x/rt305x_pci.c
@@ -204,7 +204,7 @@ rt305x_pci_write_ivar(device_t dev, device_t child, int which,
 
 static struct resource *
 rt305x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-	u_long start, u_long end, u_long count, u_int flags)
+	rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct rt305x_pci_softc *sc = device_get_softc(bus);
 	struct resource *rv;
diff --git a/sys/mips/sentry5/obio.c b/sys/mips/sentry5/obio.c
index 51eaa9d4e9a3..15abbdf05683 100644
--- a/sys/mips/sentry5/obio.c
+++ b/sys/mips/sentry5/obio.c
@@ -113,7 +113,7 @@ obio_attach(device_t dev)
 
 static struct resource *
 obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *rv;
 	struct rman *rm;
diff --git a/sys/mips/sibyte/sb_zbbus.c b/sys/mips/sibyte/sb_zbbus.c
index b96409b714a4..28584217de03 100644
--- a/sys/mips/sibyte/sb_zbbus.c
+++ b/sys/mips/sibyte/sb_zbbus.c
@@ -280,7 +280,7 @@ zbbus_hinted_child(device_t bus, const char *dname, int dunit)
 
 static struct resource *
 zbbus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		     u_long start, u_long end, u_long count, u_int flags)
+		     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *res;
 	int intrnum, intsrc, isdefault;
diff --git a/sys/mips/sibyte/sb_zbpci.c b/sys/mips/sibyte/sb_zbpci.c
index 7852a41b6a10..df3c4b8ee64b 100644
--- a/sys/mips/sibyte/sb_zbpci.c
+++ b/sys/mips/sibyte/sb_zbpci.c
@@ -165,7 +165,7 @@ zbpci_attach(device_t dev)
 
 static struct resource *
 zbpci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		     u_long start, u_long end, u_long count, u_int flags)
+		     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource *res;
 
diff --git a/sys/pc98/pc98/canbus.c b/sys/pc98/pc98/canbus.c
index daacdbd3e46a..8c3ee4e84885 100644
--- a/sys/pc98/pc98/canbus.c
+++ b/sys/pc98/pc98/canbus.c
@@ -84,7 +84,7 @@ static int	canbus_detach(device_t);
 static int	canbus_print_child(device_t, device_t);
 static device_t	canbus_add_child(device_t, u_int, const char *, int);
 static struct resource *	canbus_alloc_resource(
-    device_t, device_t, int, int *, u_long, u_long, u_long, u_int);
+    device_t, device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int);
 static int	canbus_activate_resource(
     device_t, device_t, int, int, struct resource *);
 static int	canbus_deactivate_resource(
@@ -92,7 +92,7 @@ static int	canbus_deactivate_resource(
 static int	canbus_release_resource(
     device_t, device_t, int, int, struct resource *);
 static int	canbus_set_resource (
-    device_t, device_t, int, int, u_long, u_long);
+    device_t, device_t, int, int, rman_res_t, rman_res_t);
 static void	canbus_delete_resource(device_t, device_t, int, int);
 
 /* canbus local function */
@@ -254,7 +254,7 @@ canbus_add_child(device_t bus, u_int order, const char *name, int unit)
 
 static struct resource *
 canbus_alloc_resource(device_t dev, device_t child, int type,
-    int *rid, u_long start, u_long end, u_long count, u_int flags)
+    int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	return (BUS_ALLOC_RESOURCE(device_get_parent(dev),
 	    child, type, rid, start, end, count, flags));
@@ -286,7 +286,8 @@ canbus_release_resource(
 
 static int
 canbus_set_resource (
-    device_t dev, device_t child, int type, int rid, u_long start, u_long count)
+    device_t dev, device_t child, int type, int rid, rman_res_t start,
+    rman_res_t count)
 {
 	struct  canbus_device *cbdev =
 	    (struct canbus_device *)device_get_ivars(child);
diff --git a/sys/powerpc/mpc85xx/lbc.c b/sys/powerpc/mpc85xx/lbc.c
index 8bb92b289963..f9a1718635a0 100644
--- a/sys/powerpc/mpc85xx/lbc.c
+++ b/sys/powerpc/mpc85xx/lbc.c
@@ -69,7 +69,7 @@ static int lbc_probe(device_t);
 static int lbc_attach(device_t);
 static int lbc_shutdown(device_t);
 static struct resource *lbc_alloc_resource(device_t, device_t, int, int *,
-    u_long, u_long, u_long, u_int);
+    rman_res_t, rman_res_t, rman_res_t, u_int);
 static int lbc_print_child(device_t, device_t);
 static int lbc_release_resource(device_t, device_t, int, int,
     struct resource *);
@@ -663,7 +663,7 @@ lbc_shutdown(device_t dev)
 
 static struct resource *
 lbc_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct lbc_softc *sc;
 	struct lbc_devinfo *di;
diff --git a/sys/powerpc/ofw/ofw_pci.c b/sys/powerpc/ofw/ofw_pci.c
index 2deea2888913..0ca5bc0ff487 100644
--- a/sys/powerpc/ofw/ofw_pci.c
+++ b/sys/powerpc/ofw/ofw_pci.c
@@ -62,8 +62,8 @@ __FBSDID("$FreeBSD$");
 static int		ofw_pci_read_ivar(device_t, device_t, int,
 			    uintptr_t *);
 static struct		resource * ofw_pci_alloc_resource(device_t bus,
-			    device_t child, int type, int *rid, u_long start,
-			    u_long end, u_long count, u_int flags);
+			    device_t child, int type, int *rid, rman_res_t start,
+			    rman_res_t end, rman_res_t count, u_int flags);
 static int		ofw_pci_release_resource(device_t bus, device_t child,
     			    int type, int rid, struct resource *res);
 static int		ofw_pci_activate_resource(device_t bus, device_t child,
@@ -72,8 +72,8 @@ static int		ofw_pci_deactivate_resource(device_t bus,
     			    device_t child, int type, int rid,
     			    struct resource *res);
 static int		ofw_pci_adjust_resource(device_t bus, device_t child,
-			    int type, struct resource *res, u_long start,
-			    u_long end);
+			    int type, struct resource *res, rman_res_t start,
+			    rman_res_t end);
 
 /*
  * pcib interface.
@@ -304,7 +304,7 @@ ofw_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 
 static struct resource *
 ofw_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct			ofw_pci_softc *sc;
 	struct			resource *rv;
@@ -450,7 +450,7 @@ ofw_pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
 
 static int
 ofw_pci_adjust_resource(device_t bus, device_t child, int type,
-    struct resource *res, u_long start, u_long end)
+    struct resource *res, rman_res_t start, rman_res_t end)
 {
 	struct rman *rm = NULL;
 	struct ofw_pci_softc *sc = device_get_softc(bus);
diff --git a/sys/powerpc/powermac/macgpio.c b/sys/powerpc/powermac/macgpio.c
index 4544fefd2ab3..8268038b0d90 100644
--- a/sys/powerpc/powermac/macgpio.c
+++ b/sys/powerpc/powermac/macgpio.c
@@ -71,7 +71,7 @@ static int	macgpio_attach(device_t);
 static int	macgpio_print_child(device_t dev, device_t child);
 static void	macgpio_probe_nomatch(device_t, device_t);
 static struct resource *macgpio_alloc_resource(device_t, device_t, int, int *,
-		    u_long, u_long, u_long, u_int);
+		    rman_res_t, rman_res_t, rman_res_t, u_int);
 static int	macgpio_activate_resource(device_t, device_t, int, int,
 		    struct resource *);
 static int	macgpio_deactivate_resource(device_t, device_t, int, int,
@@ -267,7 +267,8 @@ macgpio_probe_nomatch(device_t dev, device_t child)
 
 static struct resource *
 macgpio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		     u_long start, u_long end, u_long count, u_int flags)
+		     rman_res_t start, rman_res_t end, rman_res_t count,
+		     u_int flags)
 {
 	struct macgpio_devinfo *dinfo;
 
diff --git a/sys/powerpc/powermac/macio.c b/sys/powerpc/powermac/macio.c
index b495cb3e684a..669e907d0772 100644
--- a/sys/powerpc/powermac/macio.c
+++ b/sys/powerpc/powermac/macio.c
@@ -78,7 +78,8 @@ static int  macio_attach(device_t);
 static int  macio_print_child(device_t dev, device_t child);
 static void macio_probe_nomatch(device_t, device_t);
 static struct   resource *macio_alloc_resource(device_t, device_t, int, int *,
-					       u_long, u_long, u_long, u_int);
+					       rman_res_t, rman_res_t, rman_res_t,
+					       u_int);
 static int  macio_activate_resource(device_t, device_t, int, int,
 				    struct resource *);
 static int  macio_deactivate_resource(device_t, device_t, int, int,
@@ -479,7 +480,8 @@ macio_probe_nomatch(device_t dev, device_t child)
 
 static struct resource *
 macio_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		     u_long start, u_long end, u_long count, u_int flags)
+		     rman_res_t start, rman_res_t end, rman_res_t count,
+		     u_int flags)
 {
 	struct		macio_softc *sc;
 	int		needactivate;
diff --git a/sys/powerpc/powermac/uninorth.c b/sys/powerpc/powermac/uninorth.c
index 421e62581d5f..e34c9d8325ad 100644
--- a/sys/powerpc/powermac/uninorth.c
+++ b/sys/powerpc/powermac/uninorth.c
@@ -72,7 +72,8 @@ static int  unin_chip_attach(device_t);
 static int  unin_chip_print_child(device_t dev, device_t child);
 static void unin_chip_probe_nomatch(device_t, device_t);
 static struct resource *unin_chip_alloc_resource(device_t, device_t, int, int *,
-						 u_long, u_long, u_long, u_int);
+						 rman_res_t, rman_res_t,
+						 rman_res_t, u_int);
 static int  unin_chip_activate_resource(device_t, device_t, int, int,
 					struct resource *);
 static int  unin_chip_deactivate_resource(device_t, device_t, int, int,
@@ -455,7 +456,8 @@ unin_chip_probe_nomatch(device_t dev, device_t child)
 
 static struct resource *
 unin_chip_alloc_resource(device_t bus, device_t child, int type, int *rid,
-			 u_long start, u_long end, u_long count, u_int flags)
+			 rman_res_t start, rman_res_t end, rman_res_t count,
+			 u_int flags)
 {
 	struct		unin_chip_softc *sc;
 	int		needactivate;
diff --git a/sys/powerpc/psim/ata_iobus.c b/sys/powerpc/psim/ata_iobus.c
index 69c203624682..bf059b7da185 100644
--- a/sys/powerpc/psim/ata_iobus.c
+++ b/sys/powerpc/psim/ata_iobus.c
@@ -59,7 +59,8 @@ static  int  ata_iobus_attach(device_t dev);
 static  int  ata_iobus_probe(device_t dev);
 static  int  ata_iobus_print_child(device_t dev, device_t child);
 struct resource *ata_iobus_alloc_resource(device_t, device_t, int, int *,
-					  u_long, u_long, u_long, u_int);
+					  rman_res_t, rman_res_t, rman_res_t,
+					  u_int);
 static int ata_iobus_release_resource(device_t, device_t, int, int,
 				      struct resource *);
 
@@ -135,7 +136,8 @@ ata_iobus_print_child(device_t dev, device_t child)
 
 struct resource *
 ata_iobus_alloc_resource(device_t dev, device_t child, int type, int *rid,
-			 u_long start, u_long end, u_long count, u_int flags)
+			 rman_res_t start, rman_res_t end, rman_res_t count,
+			 u_int flags)
 {
 	struct resource *res = NULL;
 	int myrid;
diff --git a/sys/powerpc/psim/iobus.c b/sys/powerpc/psim/iobus.c
index 6a6ac2724374..21f53f1f11d4 100644
--- a/sys/powerpc/psim/iobus.c
+++ b/sys/powerpc/psim/iobus.c
@@ -72,7 +72,8 @@ static void iobus_probe_nomatch(device_t, device_t);
 static int  iobus_read_ivar(device_t, device_t, int, uintptr_t *);
 static int  iobus_write_ivar(device_t, device_t, int, uintptr_t);
 static struct   resource *iobus_alloc_resource(device_t, device_t, int, int *,
-					       u_long, u_long, u_long, u_int);
+					       rman_res_t, rman_res_t, rman_res_t,
+					       u_int);
 static int  iobus_activate_resource(device_t, device_t, int, int,
 				    struct resource *);
 static int  iobus_deactivate_resource(device_t, device_t, int, int,
@@ -305,7 +306,8 @@ iobus_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
 
 static struct resource *
 iobus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		     u_long start, u_long end, u_long count, u_int flags)
+		     rman_res_t start, rman_res_t end, rman_res_t count,
+		     u_int flags)
 {
 	struct iobus_softc *sc;
 	int  needactivate;
diff --git a/sys/sparc64/central/central.c b/sys/sparc64/central/central.c
index 86cb3f49c87e..62fa79d364f1 100644
--- a/sys/sparc64/central/central.c
+++ b/sys/sparc64/central/central.c
@@ -183,8 +183,8 @@ central_attach(device_t dev)
 
 static int
 central_adjust_resource(device_t bus __unused, device_t child __unused,
-    int type __unused, struct resource *r __unused, u_long start __unused,
-    u_long end __unused)
+    int type __unused, struct resource *r __unused, rman_res_t start __unused,
+    rman_res_t end __unused)
 {
 
 	return (ENXIO);
@@ -215,7 +215,7 @@ central_probe_nomatch(device_t dev, device_t child)
 
 static struct resource *
 central_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource_list *rl;
 	struct resource_list_entry *rle;
diff --git a/sys/sparc64/ebus/ebus.c b/sys/sparc64/ebus/ebus.c
index 0967c5d7d8af..961dd07f9b37 100644
--- a/sys/sparc64/ebus/ebus.c
+++ b/sys/sparc64/ebus/ebus.c
@@ -427,7 +427,7 @@ ebus_probe_nomatch(device_t dev, device_t child)
 
 static struct resource *
 ebus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct ebus_softc *sc;
 	struct resource_list *rl;
@@ -544,8 +544,8 @@ ebus_activate_resource(device_t bus, device_t child, int type, int rid,
 
 static int
 ebus_adjust_resource(device_t bus __unused, device_t child __unused,
-    int type __unused, struct resource *res __unused, u_long start __unused,
-    u_long end __unused)
+    int type __unused, struct resource *res __unused, rman_res_t start __unused,
+    rman_res_t end __unused)
 {
 
 	return (ENXIO);
diff --git a/sys/sparc64/fhc/fhc.c b/sys/sparc64/fhc/fhc.c
index 4d6a6bd01e85..3de81ff2b162 100644
--- a/sys/sparc64/fhc/fhc.c
+++ b/sys/sparc64/fhc/fhc.c
@@ -420,7 +420,7 @@ fhc_setup_intr(device_t bus, device_t child, struct resource *r, int flags,
 
 static struct resource *
 fhc_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource_list *rl;
 	struct resource_list_entry *rle;
@@ -479,8 +479,8 @@ fhc_alloc_resource(device_t bus, device_t child, int type, int *rid,
 
 static int
 fhc_adjust_resource(device_t bus __unused, device_t child __unused,
-    int type __unused, struct resource *r __unused, u_long start __unused,
-    u_long end __unused)
+    int type __unused, struct resource *r __unused, rman_res_t start __unused,
+    rman_res_t end __unused)
 {
 
 	return (ENXIO);
diff --git a/sys/sparc64/isa/isa.c b/sys/sparc64/isa/isa.c
index 678344028bfc..ad4bcdb1d1d7 100644
--- a/sys/sparc64/isa/isa.c
+++ b/sys/sparc64/isa/isa.c
@@ -273,7 +273,7 @@ isa_setup_children(device_t dev, phandle_t parent)
 
 struct resource *
 isa_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	/*
 	 * Consider adding a resource definition.
diff --git a/sys/sparc64/pci/apb.c b/sys/sparc64/pci/apb.c
index c0d61728de8f..c2fe50828e46 100644
--- a/sys/sparc64/pci/apb.c
+++ b/sys/sparc64/pci/apb.c
@@ -130,7 +130,7 @@ apb_probe(device_t dev)
 }
 
 static void
-apb_map_print(uint8_t map, u_long scale)
+apb_map_print(uint8_t map, rman_res_t scale)
 {
 	int i, first;
 
@@ -144,7 +144,7 @@ apb_map_print(uint8_t map, u_long scale)
 }
 
 static int
-apb_checkrange(uint8_t map, u_long scale, u_long start, u_long end)
+apb_checkrange(uint8_t map, rman_res_t scale, rman_res_t start, rman_res_t end)
 {
 	int i, ei;
 
@@ -227,7 +227,7 @@ apb_attach(device_t dev)
  */
 static struct resource *
 apb_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct apb_softc *sc;
 
@@ -287,7 +287,7 @@ apb_alloc_resource(device_t dev, device_t child, int type, int *rid,
 
 static int
 apb_adjust_resource(device_t dev, device_t child, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 	struct apb_softc *sc;
 
diff --git a/sys/sparc64/pci/fire.c b/sys/sparc64/pci/fire.c
index be0c64babea4..c2d22853e4c5 100644
--- a/sys/sparc64/pci/fire.c
+++ b/sys/sparc64/pci/fire.c
@@ -1852,7 +1852,7 @@ fire_teardown_intr(device_t dev, device_t child, struct resource *ires,
 
 static struct resource *
 fire_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct fire_softc *sc;
 
diff --git a/sys/sparc64/pci/ofw_pci.c b/sys/sparc64/pci/ofw_pci.c
index a18052f7647c..8babd49bb160 100644
--- a/sys/sparc64/pci/ofw_pci.c
+++ b/sys/sparc64/pci/ofw_pci.c
@@ -287,7 +287,7 @@ ofw_pci_read_ivar(device_t dev, device_t child __unused, int which,
 
 struct resource *
 ofw_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct ofw_pci_softc *sc;
 	struct resource *rv;
@@ -362,7 +362,7 @@ ofw_pci_activate_resource(device_t bus, device_t child, int type, int rid,
 
 int
 ofw_pci_adjust_resource(device_t bus, device_t child, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 	struct ofw_pci_softc *sc;
 	struct rman *rm;
diff --git a/sys/sparc64/pci/psycho.c b/sys/sparc64/pci/psycho.c
index 38f4656abc63..496df96895d4 100644
--- a/sys/sparc64/pci/psycho.c
+++ b/sys/sparc64/pci/psycho.c
@@ -1038,7 +1038,7 @@ psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
 
 static struct resource *
 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct psycho_softc *sc;
 
diff --git a/sys/sparc64/pci/sbbc.c b/sys/sparc64/pci/sbbc.c
index f1e7fab94ced..e5093630085d 100644
--- a/sys/sparc64/pci/sbbc.c
+++ b/sys/sparc64/pci/sbbc.c
@@ -397,7 +397,7 @@ sbbc_pci_attach(device_t dev)
 
 static struct resource *
 sbbc_bus_alloc_resource(device_t dev, device_t child __unused, int type,
-    int *rid, u_long start, u_long end, u_long count, u_int flags)
+    int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct sbbc_softc *sc;
 
@@ -435,8 +435,8 @@ sbbc_bus_deactivate_resource(device_t bus, device_t child, int type, int rid,
 
 static int
 sbbc_bus_adjust_resource(device_t bus __unused, device_t child __unused,
-    int type __unused, struct resource *res __unused, u_long start __unused,
-    u_long end __unused)
+    int type __unused, struct resource *res __unused, rman_res_t start __unused,
+    rman_res_t end __unused)
 {
 
 	return (ENXIO);
diff --git a/sys/sparc64/pci/schizo.c b/sys/sparc64/pci/schizo.c
index ed1cccdaac19..a96155bd94bf 100644
--- a/sys/sparc64/pci/schizo.c
+++ b/sys/sparc64/pci/schizo.c
@@ -1196,7 +1196,7 @@ schizo_setup_intr(device_t dev, device_t child, struct resource *ires,
 
 static struct resource *
 schizo_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct schizo_softc *sc;
 
diff --git a/sys/sparc64/sbus/sbus.c b/sys/sparc64/sbus/sbus.c
index 0b2765579f6e..e4bc3b464e0c 100644
--- a/sys/sparc64/sbus/sbus.c
+++ b/sys/sparc64/sbus/sbus.c
@@ -710,7 +710,7 @@ sbus_setup_intr(device_t dev, device_t child, struct resource *ires, int flags,
 
 static struct resource *
 sbus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct sbus_softc *sc;
 	struct rman *rm;
@@ -821,7 +821,7 @@ sbus_activate_resource(device_t bus, device_t child, int type, int rid,
 
 static int
 sbus_adjust_resource(device_t bus, device_t child, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 	struct sbus_softc *sc;
 	int i;
diff --git a/sys/sparc64/sparc64/nexus.c b/sys/sparc64/sparc64/nexus.c
index 30374e53a85c..708222060742 100644
--- a/sys/sparc64/sparc64/nexus.c
+++ b/sys/sparc64/sparc64/nexus.c
@@ -359,7 +359,7 @@ nexus_describe_intr(device_t bus __unused, device_t child __unused,
 
 static struct resource *
 nexus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct nexus_softc *sc;
 	struct rman *rm;
@@ -445,7 +445,7 @@ nexus_deactivate_resource(device_t bus __unused, device_t child __unused,
 
 static int
 nexus_adjust_resource(device_t bus, device_t child __unused, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 	struct nexus_softc *sc;
 	struct rman *rm;
diff --git a/sys/sparc64/sparc64/upa.c b/sys/sparc64/sparc64/upa.c
index cd615d90528c..f3a73bc2afc3 100644
--- a/sys/sparc64/sparc64/upa.c
+++ b/sys/sparc64/sparc64/upa.c
@@ -194,7 +194,7 @@ upa_attach(device_t dev)
 	int i, imr, j, rid;
 #if 1
 	device_t *children, schizo;
-	u_long scount, sstart, ucount, ustart;
+	rman_res_t scount, sstart, ucount, ustart;
 	int nchildren;
 #endif
 
@@ -403,7 +403,7 @@ upa_probe_nomatch(device_t dev, device_t child)
 
 static struct resource *
 upa_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct resource_list *rl;
 	struct resource_list_entry *rle;
@@ -510,8 +510,8 @@ upa_setup_intr(device_t dev, device_t child, struct resource *ires, int flags,
 
 static int
 upa_adjust_resource(device_t bus __unused, device_t child __unused,
-    int type __unused, struct resource *r __unused, u_long start __unused,
-    u_long end __unused)
+    int type __unused, struct resource *r __unused, rman_res_t start __unused,
+    rman_res_t end __unused)
 {
 
 	return (ENXIO);
diff --git a/sys/sys/_types.h b/sys/sys/_types.h
index 7904a4f77898..3b3c16d3684e 100644
--- a/sys/sys/_types.h
+++ b/sys/sys/_types.h
@@ -112,4 +112,6 @@ typedef union {
 	__int64_t	_mbstateL;	/* for alignment */
 } __mbstate_t;
 
+typedef unsigned long	__rman_res_t;
+
 #endif /* !_SYS__TYPES_H_ */
diff --git a/sys/sys/bus.h b/sys/sys/bus.h
index 42d3a3fea5e8..4348ae7e304b 100644
--- a/sys/sys/bus.h
+++ b/sys/sys/bus.h
@@ -292,9 +292,9 @@ struct resource_list_entry {
 	int	rid;			/**< @brief resource identifier */
 	int	flags;			/**< @brief resource flags */
 	struct	resource *res;		/**< @brief the real resource when allocated */
-	u_long	start;			/**< @brief start of resource range */
-	u_long	end;			/**< @brief end of resource range */
-	u_long	count;			/**< @brief count within range */
+	rman_res_t	start;		/**< @brief start of resource range */
+	rman_res_t	end;		/**< @brief end of resource range */
+	rman_res_t	count;			/**< @brief count within range */
 };
 STAILQ_HEAD(resource_list, resource_list_entry);
 
@@ -307,10 +307,10 @@ void	resource_list_free(struct resource_list *rl);
 struct resource_list_entry *
 	resource_list_add(struct resource_list *rl,
 			  int type, int rid,
-			  u_long start, u_long end, u_long count);
+			  rman_res_t start, rman_res_t end, rman_res_t count);
 int	resource_list_add_next(struct resource_list *rl,
 			  int type,
-			  u_long start, u_long end, u_long count);
+			  rman_res_t start, rman_res_t end, rman_res_t count);
 int	resource_list_busy(struct resource_list *rl,
 			   int type, int rid);
 int	resource_list_reserved(struct resource_list *rl, int type, int rid);
@@ -323,8 +323,8 @@ struct resource *
 	resource_list_alloc(struct resource_list *rl,
 			    device_t bus, device_t child,
 			    int type, int *rid,
-			    u_long start, u_long end,
-			    u_long count, u_int flags);
+			    rman_res_t start, rman_res_t end,
+			    rman_res_t count, u_int flags);
 int	resource_list_release(struct resource_list *rl,
 			      device_t bus, device_t child,
 			      int type, int rid, struct resource *res);
@@ -335,8 +335,8 @@ struct resource *
 	resource_list_reserve(struct resource_list *rl,
 			      device_t bus, device_t child,
 			      int type, int *rid,
-			      u_long start, u_long end,
-			      u_long count, u_int flags);
+			      rman_res_t start, rman_res_t end,
+			      rman_res_t count, u_int flags);
 int	resource_list_unreserve(struct resource_list *rl,
 				device_t bus, device_t child,
 				int type, int rid);
@@ -362,12 +362,12 @@ device_t
 	bus_generic_add_child(device_t dev, u_int order, const char *name,
 			      int unit);
 int	bus_generic_adjust_resource(device_t bus, device_t child, int type,
-				    struct resource *r, u_long start,
-				    u_long end);
+				    struct resource *r, rman_res_t start,
+				    rman_res_t end);
 struct resource *
 	bus_generic_alloc_resource(device_t bus, device_t child, int type,
-				   int *rid, u_long start, u_long end,
-				   u_long count, u_int flags);
+				   int *rid, rman_res_t start, rman_res_t end,
+				   rman_res_t count, u_int flags);
 int	bus_generic_attach(device_t dev);
 int	bus_generic_bind_intr(device_t dev, device_t child,
 			      struct resource *irq, int cpu);
@@ -405,12 +405,12 @@ int	bus_generic_setup_intr(device_t dev, device_t child,
 
 struct resource *
 	bus_generic_rl_alloc_resource (device_t, device_t, int, int *,
-				       u_long, u_long, u_long, u_int);
+				       rman_res_t, rman_res_t, rman_res_t, u_int);
 void	bus_generic_rl_delete_resource (device_t, device_t, int, int);
-int	bus_generic_rl_get_resource (device_t, device_t, int, int, u_long *,
-				     u_long *);
-int	bus_generic_rl_set_resource (device_t, device_t, int, int, u_long,
-				     u_long);
+int	bus_generic_rl_get_resource (device_t, device_t, int, int, rman_res_t *,
+				     rman_res_t *);
+int	bus_generic_rl_set_resource (device_t, device_t, int, int, rman_res_t,
+				     rman_res_t);
 int	bus_generic_rl_release_resource (device_t, device_t, int, int,
 					 struct resource *);
 
@@ -439,10 +439,10 @@ void	bus_release_resources(device_t dev, const struct resource_spec *rs,
 			      struct resource **res);
 
 int	bus_adjust_resource(device_t child, int type, struct resource *r,
-			    u_long start, u_long end);
+			    rman_res_t start, rman_res_t end);
 struct	resource *bus_alloc_resource(device_t dev, int type, int *rid,
-				     u_long start, u_long end, u_long count,
-				     u_int flags);
+				     rman_res_t start, rman_res_t end,
+				     rman_res_t count, u_int flags);
 int	bus_activate_resource(device_t dev, int type, int rid,
 			      struct resource *r);
 int	bus_deactivate_resource(device_t dev, int type, int rid,
@@ -460,11 +460,11 @@ int	bus_bind_intr(device_t dev, struct resource *r, int cpu);
 int	bus_describe_intr(device_t dev, struct resource *irq, void *cookie,
 			  const char *fmt, ...);
 int	bus_set_resource(device_t dev, int type, int rid,
-			 u_long start, u_long count);
+			 rman_res_t start, rman_res_t count);
 int	bus_get_resource(device_t dev, int type, int rid,
-			 u_long *startp, u_long *countp);
-u_long	bus_get_resource_start(device_t dev, int type, int rid);
-u_long	bus_get_resource_count(device_t dev, int type, int rid);
+			 rman_res_t *startp, rman_res_t *countp);
+rman_res_t	bus_get_resource_start(device_t dev, int type, int rid);
+rman_res_t	bus_get_resource_count(device_t dev, int type, int rid);
 void	bus_delete_resource(device_t dev, int type, int rid);
 int	bus_child_present(device_t child);
 int	bus_child_pnpinfo_str(device_t child, char *buf, size_t buflen);
diff --git a/sys/sys/rman.h b/sys/sys/rman.h
index d98dac7f1526..0ccafff456c2 100644
--- a/sys/sys/rman.h
+++ b/sys/sys/rman.h
@@ -61,6 +61,8 @@ enum	rman_type { RMAN_UNINIT = 0, RMAN_GAUGE, RMAN_ARRAY };
  */
 #define RM_TEXTLEN	32
 
+#define	RM_MAX_END	((rman_res_t)~0)
+
 /*
  * Userspace-exported structures.
  */
@@ -70,8 +72,8 @@ struct u_resource {
 	uintptr_t	r_device;		/* device owning this resource */
 	char		r_devname[RM_TEXTLEN];	/* device name XXX obsolete */
 
-	u_long		r_start;		/* offset in resource space */
-	u_long		r_size;			/* size in resource space */
+	rman_res_t	r_start;		/* offset in resource space */
+	rman_res_t	r_size;			/* size in resource space */
 	u_int		r_flags;		/* RF_* flags */
 };
 
@@ -79,8 +81,8 @@ struct u_rman {
 	uintptr_t	rm_handle;		/* rman uniquifier */
 	char		rm_descr[RM_TEXTLEN];	/* rman description */
 
-	u_long		rm_start;		/* base of managed region */
-	u_long		rm_size;		/* size of managed region */
+	rman_res_t	rm_start;		/* base of managed region */
+	bus_size_t	rm_size;		/* size of managed region */
 	enum rman_type	rm_type;		/* region type */
 };
 
@@ -108,47 +110,47 @@ struct rman {
 	struct	resource_head 	rm_list;
 	struct	mtx *rm_mtx;	/* mutex used to protect rm_list */
 	TAILQ_ENTRY(rman)	rm_link; /* link in list of all rmans */
-	u_long	rm_start;	/* index of globally first entry */
-	u_long	rm_end;		/* index of globally last entry */
+	rman_res_t	rm_start;	/* index of globally first entry */
+	rman_res_t	rm_end;	/* index of globally last entry */
 	enum	rman_type rm_type; /* what type of resource this is */
 	const	char *rm_descr;	/* text descripion of this resource */
 };
 TAILQ_HEAD(rman_head, rman);
 
 int	rman_activate_resource(struct resource *r);
-int	rman_adjust_resource(struct resource *r, u_long start, u_long end);
+int	rman_adjust_resource(struct resource *r, rman_res_t start, rman_res_t end);
 int	rman_await_resource(struct resource *r, int pri, int timo);
-int	rman_first_free_region(struct rman *rm, u_long *start, u_long *end);
+int	rman_first_free_region(struct rman *rm, rman_res_t *start, rman_res_t *end);
 bus_space_handle_t rman_get_bushandle(struct resource *);
 bus_space_tag_t rman_get_bustag(struct resource *);
-u_long	rman_get_end(struct resource *);
+rman_res_t	rman_get_end(struct resource *);
 struct device *rman_get_device(struct resource *);
 u_int	rman_get_flags(struct resource *);
 int	rman_get_rid(struct resource *);
-u_long	rman_get_size(struct resource *);
-u_long	rman_get_start(struct resource *);
+rman_res_t	rman_get_size(struct resource *);
+rman_res_t	rman_get_start(struct resource *);
 void   *rman_get_virtual(struct resource *);
 int	rman_deactivate_resource(struct resource *r);
 int	rman_fini(struct rman *rm);
 int	rman_init(struct rman *rm);
 int	rman_init_from_resource(struct rman *rm, struct resource *r);
-int	rman_last_free_region(struct rman *rm, u_long *start, u_long *end);
+int	rman_last_free_region(struct rman *rm, rman_res_t *start, rman_res_t *end);
 uint32_t rman_make_alignment_flags(uint32_t size);
-int	rman_manage_region(struct rman *rm, u_long start, u_long end);
+int	rman_manage_region(struct rman *rm, rman_res_t start, rman_res_t end);
 int	rman_is_region_manager(struct resource *r, struct rman *rm);
 int	rman_release_resource(struct resource *r);
-struct resource *rman_reserve_resource(struct rman *rm, u_long start,
-					u_long end, u_long count,
+struct resource *rman_reserve_resource(struct rman *rm, rman_res_t start,
+					rman_res_t end, rman_res_t count,
 					u_int flags, struct device *dev);
-struct resource *rman_reserve_resource_bound(struct rman *rm, u_long start,
-					u_long end, u_long count, u_long bound,
+struct resource *rman_reserve_resource_bound(struct rman *rm, rman_res_t start,
+					rman_res_t end, rman_res_t count, rman_res_t bound,
 					u_int flags, struct device *dev);
 void	rman_set_bushandle(struct resource *_r, bus_space_handle_t _h);
 void	rman_set_bustag(struct resource *_r, bus_space_tag_t _t);
 void	rman_set_device(struct resource *_r, struct device *_dev);
-void	rman_set_end(struct resource *_r, u_long _end);
+void	rman_set_end(struct resource *_r, rman_res_t _end);
 void	rman_set_rid(struct resource *_r, int _rid);
-void	rman_set_start(struct resource *_r, u_long _start);
+void	rman_set_start(struct resource *_r, rman_res_t _start);
 void	rman_set_virtual(struct resource *_r, void *_v);
 
 extern	struct rman_head rman_head;
diff --git a/sys/sys/types.h b/sys/sys/types.h
index 4dfd8ef19b4d..579b104924af 100644
--- a/sys/sys/types.h
+++ b/sys/sys/types.h
@@ -250,6 +250,8 @@ typedef	__vm_paddr_t	vm_paddr_t;
 typedef	__vm_pindex_t	vm_pindex_t;
 typedef	__vm_size_t	vm_size_t;
 
+typedef __rman_res_t    rman_res_t;
+
 #ifdef _KERNEL
 typedef	int		boolean_t;
 typedef	struct device	*device_t;
diff --git a/sys/x86/include/legacyvar.h b/sys/x86/include/legacyvar.h
index 856b352d8672..7335de2854a0 100644
--- a/sys/x86/include/legacyvar.h
+++ b/sys/x86/include/legacyvar.h
@@ -56,9 +56,10 @@ void	legacy_pcib_write_config(device_t dev, u_int bus, u_int slot,
 int	legacy_pcib_write_ivar(device_t dev, device_t child, int which,
     uintptr_t value);
 struct resource *legacy_pcib_alloc_resource(device_t dev, device_t child,
-    int type, int *rid, u_long start, u_long end, u_long count, u_int flags);
+    int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count,
+    u_int flags);
 int	legacy_pcib_adjust_resource(device_t dev, device_t child, int type,
-    struct resource *r, u_long start, u_long end);
+    struct resource *r, rman_res_t start, rman_res_t end);
 int	legacy_pcib_release_resource(device_t dev, device_t child, int type,
     int rid, struct resource *r);
 int	legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count,
diff --git a/sys/x86/include/pci_cfgreg.h b/sys/x86/include/pci_cfgreg.h
index ea5e3198265f..733b91c4dadf 100644
--- a/sys/x86/include/pci_cfgreg.h
+++ b/sys/x86/include/pci_cfgreg.h
@@ -46,7 +46,7 @@
 #define CONF2_ENABLE_CHK   0x0e
 #define CONF2_ENABLE_RES   0x0e
 
-u_long		hostb_alloc_start(int type, u_long start, u_long end, u_long count);
+rman_res_t	hostb_alloc_start(int type, rman_res_t start, rman_res_t end, rman_res_t count);
 int		pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus);
 int		pci_cfgregopen(void);
 u_int32_t	pci_cfgregread(int bus, int slot, int func, int reg, int bytes);
diff --git a/sys/x86/isa/atrtc.c b/sys/x86/isa/atrtc.c
index d9695942d2d9..c1e796f49a88 100644
--- a/sys/x86/isa/atrtc.c
+++ b/sys/x86/isa/atrtc.c
@@ -241,7 +241,7 @@ static int
 atrtc_attach(device_t dev)
 {
 	struct atrtc_softc *sc;
-	u_long s;
+	rman_res_t s;
 	int i;
 
 	sc = device_get_softc(dev);
diff --git a/sys/x86/isa/clock.c b/sys/x86/isa/clock.c
index 8ed68e0f97d6..8778c0dc627a 100644
--- a/sys/x86/isa/clock.c
+++ b/sys/x86/isa/clock.c
@@ -656,7 +656,7 @@ static int
 attimer_attach(device_t dev)
 {
 	struct attimer_softc *sc;
-	u_long s;
+	rman_res_t s;
 	int i;
 
 	attimer_sc = sc = device_get_softc(dev);
diff --git a/sys/x86/isa/isa.c b/sys/x86/isa/isa.c
index 605af59259a5..3de119f0a68a 100644
--- a/sys/x86/isa/isa.c
+++ b/sys/x86/isa/isa.c
@@ -88,7 +88,7 @@ isa_init(device_t dev)
  */
 struct resource *
 isa_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		   u_long start, u_long end, u_long count, u_int flags)
+		   rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	/*
 	 * Consider adding a resource definition.
diff --git a/sys/x86/pci/pci_bus.c b/sys/x86/pci/pci_bus.c
index 821265dd12e6..5f0df39d59ac 100644
--- a/sys/x86/pci/pci_bus.c
+++ b/sys/x86/pci/pci_bus.c
@@ -578,8 +578,8 @@ static unsigned long host_mem_start = 0x80000000;
 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN, &host_mem_start,
     0, "Limit the host bridge memory to being above this address.");
 
-u_long
-hostb_alloc_start(int type, u_long start, u_long end, u_long count)
+rman_res_t
+hostb_alloc_start(int type, rman_res_t start, rman_res_t end, rman_res_t count)
 {
 
 	if (start + count - 1 != end) {
@@ -593,7 +593,7 @@ hostb_alloc_start(int type, u_long start, u_long end, u_long count)
 
 struct resource *
 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 
 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
@@ -609,7 +609,7 @@ legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
 int
 legacy_pcib_adjust_resource(device_t dev, device_t child, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 
 	if (type == PCI_RES_BUS)
diff --git a/sys/x86/pci/qpi.c b/sys/x86/pci/qpi.c
index 2650986ea5a7..60ad028fd09e 100644
--- a/sys/x86/pci/qpi.c
+++ b/sys/x86/pci/qpi.c
@@ -241,7 +241,7 @@ qpi_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
 #if defined(NEW_PCIB) && defined(PCI_RES_BUS)
 static struct resource *
 qpi_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 
 	if (type == PCI_RES_BUS)
diff --git a/sys/x86/x86/mptable_pci.c b/sys/x86/x86/mptable_pci.c
index 31165ae9d2dd..6533484e18b9 100644
--- a/sys/x86/x86/mptable_pci.c
+++ b/sys/x86/x86/mptable_pci.c
@@ -75,7 +75,7 @@ mptable_hostb_attach(device_t dev)
 
 #ifdef NEW_PCIB
 static int
-mptable_is_isa_range(u_long start, u_long end)
+mptable_is_isa_range(rman_res_t start, rman_res_t end)
 {
 
 	if (end >= 0x10000)
@@ -88,7 +88,7 @@ mptable_is_isa_range(u_long start, u_long end)
 }
 
 static int
-mptable_is_vga_range(u_long start, u_long end)
+mptable_is_vga_range(rman_res_t start, rman_res_t end)
 {
 	if (end >= 0x10000)
 		return (0);
@@ -101,7 +101,7 @@ mptable_is_vga_range(u_long start, u_long end)
 
 static struct resource *
 mptable_hostb_alloc_resource(device_t dev, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
+    rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
 {
 	struct mptable_hostb_softc *sc;
 
@@ -142,7 +142,7 @@ mptable_hostb_alloc_resource(device_t dev, device_t child, int type, int *rid,
 
 static int
 mptable_hostb_adjust_resource(device_t dev, device_t child, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 	struct mptable_hostb_softc *sc;
 
diff --git a/sys/x86/x86/nexus.c b/sys/x86/x86/nexus.c
index fb32c9b849e4..6b61b39236df 100644
--- a/sys/x86/x86/nexus.c
+++ b/sys/x86/x86/nexus.c
@@ -99,9 +99,10 @@ static	int nexus_print_child(device_t, device_t);
 static device_t nexus_add_child(device_t bus, u_int order, const char *name,
 				int unit);
 static	struct resource *nexus_alloc_resource(device_t, device_t, int, int *,
-					      u_long, u_long, u_long, u_int);
+					      rman_res_t, rman_res_t, rman_res_t,
+					      u_int);
 static	int nexus_adjust_resource(device_t, device_t, int, struct resource *,
-				  u_long, u_long);
+				  rman_res_t, rman_res_t);
 #ifdef SMP
 static	int nexus_bind_intr(device_t, device_t, struct resource *, int);
 #endif
@@ -122,8 +123,10 @@ static	int nexus_setup_intr(device_t, device_t, struct resource *, int flags,
 static	int nexus_teardown_intr(device_t, device_t, struct resource *,
 				void *);
 static struct resource_list *nexus_get_reslist(device_t dev, device_t child);
-static	int nexus_set_resource(device_t, device_t, int, int, u_long, u_long);
-static	int nexus_get_resource(device_t, device_t, int, int, u_long *, u_long *);
+static	int nexus_set_resource(device_t, device_t, int, int,
+			       rman_res_t, rman_res_t);
+static	int nexus_get_resource(device_t, device_t, int, int,
+			       rman_res_t *, rman_res_t *);
 static void nexus_delete_resource(device_t, device_t, int, int);
 #ifdef DEV_APIC
 static	int nexus_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs);
@@ -359,7 +362,8 @@ nexus_rman(int type)
  */
 static struct resource *
 nexus_alloc_resource(device_t bus, device_t child, int type, int *rid,
-		     u_long start, u_long end, u_long count, u_int flags)
+		     rman_res_t start, rman_res_t end, rman_res_t count,
+		     u_int flags)
 {
 	struct nexus_device *ndev = DEVTONX(child);
 	struct	resource *rv;
@@ -406,7 +410,7 @@ nexus_alloc_resource(device_t bus, device_t child, int type, int *rid,
 
 static int
 nexus_adjust_resource(device_t bus, device_t child, int type,
-    struct resource *r, u_long start, u_long end)
+    struct resource *r, rman_res_t start, rman_res_t end)
 {
 	struct rman *rm;
 
@@ -574,7 +578,8 @@ nexus_get_reslist(device_t dev, device_t child)
 }
 
 static int
-nexus_set_resource(device_t dev, device_t child, int type, int rid, u_long start, u_long count)
+nexus_set_resource(device_t dev, device_t child, int type, int rid,
+    rman_res_t start, rman_res_t count)
 {
 	struct nexus_device	*ndev = DEVTONX(child);
 	struct resource_list	*rl = &ndev->nx_resources;
@@ -585,7 +590,8 @@ nexus_set_resource(device_t dev, device_t child, int type, int rid, u_long start
 }
 
 static int
-nexus_get_resource(device_t dev, device_t child, int type, int rid, u_long *startp, u_long *countp)
+nexus_get_resource(device_t dev, device_t child, int type, int rid,
+    rman_res_t *startp, rman_res_t *countp)
 {
 	struct nexus_device	*ndev = DEVTONX(child);
 	struct resource_list	*rl = &ndev->nx_resources;

From 0ccc3c81eb84e02cc75d71eed8f734f3f9da961e Mon Sep 17 00:00:00 2001
From: cy <cy@FreeBSD.org>
Date: Wed, 27 Jan 2016 02:25:25 +0000
Subject: [PATCH 075/113] Allow specification of fetch options for ntp
 leap-seconds fetch.

MFC after:	1 week
X-MFC with:	r289421, r293037, r294773
---
 etc/defaults/rc.conf | 2 ++
 etc/rc.d/ntpd        | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/etc/defaults/rc.conf b/etc/defaults/rc.conf
index 380f0d3b32f6..a674acb97532 100644
--- a/etc/defaults/rc.conf
+++ b/etc/defaults/rc.conf
@@ -368,6 +368,8 @@ ntp_db_leapfile="/var/db/ntpd.leap-seconds.list"
 				# Working copy (updated weekly) leapfile
 ntp_leapfile_sources="https://www.ietf.org/timezones/data/leap-seconds.list"
 				# Source from which to fetch leapfile
+ntp_leapfile_fetch_opts="-mq"	# Options to use for ntp leapfile fetch,
+				# e.g. --no-verify-peer
 ntp_leapfile_expiry_days=30	# Check for new leapfile 30 days prior to
 				# expiry.
 ntp_leapfile_fetch_verbose="NO"	# Be verbose during NTP leapfile fetch
diff --git a/etc/rc.d/ntpd b/etc/rc.d/ntpd
index f014110de819..7f28358d7a82 100755
--- a/etc/rc.d/ntpd
+++ b/etc/rc.d/ntpd
@@ -105,7 +105,7 @@ ntpd_fetch_leapfile() {
 		$verbose Within ntp leapfile expiry limit, initiating fetch
 		for url in $ntp_leapfile_sources ; do
 			$verbose fetching $url
-			fetch -mqo $ntp_tmp_leapfile $url && break
+			fetch $ntp_leapfile_fetch_opts -o $ntp_tmp_leapfile $url && break
 		done
 		ntp_ver_no_tmp=$(get_ntp_leapfile_ver $ntp_tmp_leapfile)
 		if [ "$ntp_ver_no_tmp" -gt "$ntp_ver_no_db" ]; then

From c8795644be6731c963c64cd23eecf95e46be5dce Mon Sep 17 00:00:00 2001
From: jhibbits <jhibbits@FreeBSD.org>
Date: Wed, 27 Jan 2016 03:51:24 +0000
Subject: [PATCH 076/113] Fix the build post-r294883.

Pointy-hat to:	jhibbits
X-MFC with:	r294883
---
 sys/sys/rman.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/sys/rman.h b/sys/sys/rman.h
index 0ccafff456c2..9ea7bbabe0fb 100644
--- a/sys/sys/rman.h
+++ b/sys/sys/rman.h
@@ -82,7 +82,7 @@ struct u_rman {
 	char		rm_descr[RM_TEXTLEN];	/* rman description */
 
 	rman_res_t	rm_start;		/* base of managed region */
-	bus_size_t	rm_size;		/* size of managed region */
+	rman_res_t	rm_size;		/* size of managed region */
 	enum rman_type	rm_type;		/* region type */
 };
 

From bfd20a73f3257eeeb2bfe0392c20705dff23849f Mon Sep 17 00:00:00 2001
From: sephe <sephe@FreeBSD.org>
Date: Wed, 27 Jan 2016 03:53:30 +0000
Subject: [PATCH 077/113] hyperv/vmbus: Event handling code refactor.

- Use taskqueue instead of swi for event handling.
- Scan the interrupt flags in filter
- Disable ringbuffer interrupt mask in filter to ensure no unnecessary
  interrupts.

Submitted by:		Jun Su <junsu microsoft com>
Reviewed by:		adrian, sephe, Dexuan <decui microsoft com>
Approved by:		adrian (mentor)
MFC after:		2 weeks
Sponsored by:		Microsoft OSTC
Differential Revision:	https://reviews.freebsd.org/D4920
---
 sys/dev/hyperv/include/hyperv.h             |  2 +
 sys/dev/hyperv/vmbus/hv_channel.c           | 74 ++++++++++++++++++++
 sys/dev/hyperv/vmbus/hv_connection.c        | 77 +++------------------
 sys/dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c | 49 ++++++-------
 sys/dev/hyperv/vmbus/hv_vmbus_priv.h        |  5 +-
 5 files changed, 108 insertions(+), 99 deletions(-)

diff --git a/sys/dev/hyperv/include/hyperv.h b/sys/dev/hyperv/include/hyperv.h
index 1a45b7ba8b3b..852e14ea5690 100644
--- a/sys/dev/hyperv/include/hyperv.h
+++ b/sys/dev/hyperv/include/hyperv.h
@@ -755,6 +755,8 @@ typedef struct hv_vmbus_channel {
 
 	struct mtx			inbound_lock;
 
+	struct taskqueue *		rxq;
+	struct task			channel_task;
 	hv_vmbus_pfn_channel_callback	on_channel_callback;
 	void*				channel_callback_context;
 
diff --git a/sys/dev/hyperv/vmbus/hv_channel.c b/sys/dev/hyperv/vmbus/hv_channel.c
index facddc271cba..762ace4fe423 100644
--- a/sys/dev/hyperv/vmbus/hv_channel.c
+++ b/sys/dev/hyperv/vmbus/hv_channel.c
@@ -51,6 +51,7 @@ static int 	vmbus_channel_create_gpadl_header(
 			uint32_t*			message_count);
 
 static void 	vmbus_channel_set_event(hv_vmbus_channel* channel);
+static void	VmbusProcessChannelEvent(void* channel, int pending);
 
 /**
  *  @brief Trigger an event notification on the specified channel
@@ -114,6 +115,9 @@ hv_vmbus_channel_open(
 	new_channel->on_channel_callback = pfn_on_channel_callback;
 	new_channel->channel_callback_context = context;
 
+	new_channel->rxq = hv_vmbus_g_context.hv_event_queue[new_channel->target_cpu];
+	TASK_INIT(&new_channel->channel_task, 0, VmbusProcessChannelEvent, new_channel);
+
 	/* Allocate the ring buffer */
 	out = contigmalloc((send_ring_buffer_size + recv_ring_buffer_size),
 	    M_DEVBUF, M_ZERO, 0UL, BUS_SPACE_MAXADDR, PAGE_SIZE, 0);
@@ -517,12 +521,18 @@ static void
 hv_vmbus_channel_close_internal(hv_vmbus_channel *channel)
 {
 	int ret = 0;
+	struct taskqueue *rxq = channel->rxq;
 	hv_vmbus_channel_close_channel* msg;
 	hv_vmbus_channel_msg_info* info;
 
 	channel->state = HV_CHANNEL_OPEN_STATE;
 	channel->sc_creation_callback = NULL;
 
+	/*
+	 * set rxq to NULL to avoid more requests be scheduled
+	 */
+	channel->rxq = NULL;
+	taskqueue_drain(rxq, &channel->channel_task);
 	/*
 	 * Grab the lock to prevent race condition when a packet received
 	 * and unloading driver is in the process.
@@ -876,3 +886,67 @@ hv_vmbus_channel_recv_packet_raw(
 
 	return (0);
 }
+
+
+/**
+ * Process a channel event notification
+ */
+static void
+VmbusProcessChannelEvent(void* context, int pending)
+{
+	void* arg;
+	uint32_t bytes_to_read;
+	hv_vmbus_channel* channel = (hv_vmbus_channel*)context;
+	boolean_t is_batched_reading;
+
+	/**
+	 * Find the channel based on this relid and invokes
+	 * the channel callback to process the event
+	 */
+
+	if (channel == NULL) {
+		return;
+	}
+	/**
+	 * To deal with the race condition where we might
+	 * receive a packet while the relevant driver is
+	 * being unloaded, dispatch the callback while
+	 * holding the channel lock. The unloading driver
+	 * will acquire the same channel lock to set the
+	 * callback to NULL. This closes the window.
+	 */
+
+	/*
+	 * Disable the lock due to newly added WITNESS check in r277723.
+	 * Will seek other way to avoid race condition.
+	 * -- whu
+	 */
+	// mtx_lock(&channel->inbound_lock);
+	if (channel->on_channel_callback != NULL) {
+		arg = channel->channel_callback_context;
+		is_batched_reading = channel->batched_reading;
+		/*
+		 * Optimize host to guest signaling by ensuring:
+		 * 1. While reading the channel, we disable interrupts from
+		 *    host.
+		 * 2. Ensure that we process all posted messages from the host
+		 *    before returning from this callback.
+		 * 3. Once we return, enable signaling from the host. Once this
+		 *    state is set we check to see if additional packets are
+		 *    available to read. In this case we repeat the process.
+		 */
+		do {
+			if (is_batched_reading)
+				hv_ring_buffer_read_begin(&channel->inbound);
+
+			channel->on_channel_callback(arg);
+
+			if (is_batched_reading)
+				bytes_to_read =
+				    hv_ring_buffer_read_end(&channel->inbound);
+			else
+				bytes_to_read = 0;
+		} while (is_batched_reading && (bytes_to_read != 0));
+	}
+	// mtx_unlock(&channel->inbound_lock);
+}
diff --git a/sys/dev/hyperv/vmbus/hv_connection.c b/sys/dev/hyperv/vmbus/hv_connection.c
index 97071cc4c526..05b16120f303 100644
--- a/sys/dev/hyperv/vmbus/hv_connection.c
+++ b/sys/dev/hyperv/vmbus/hv_connection.c
@@ -334,79 +334,13 @@ hv_vmbus_disconnect(void) {
 	return (ret);
 }
 
-/**
- * Process a channel event notification
- */
-static void
-VmbusProcessChannelEvent(uint32_t relid) 
-{
-	void* arg;
-	uint32_t bytes_to_read;
-	hv_vmbus_channel* channel;
-	boolean_t is_batched_reading;
-
-	/**
-	 * Find the channel based on this relid and invokes
-	 * the channel callback to process the event
-	 */
-
-	channel = hv_vmbus_g_connection.channels[relid];
-
-	if (channel == NULL) {
-		return;
-	}
-	/**
-	 * To deal with the race condition where we might
-	 * receive a packet while the relevant driver is 
-	 * being unloaded, dispatch the callback while 
-	 * holding the channel lock. The unloading driver
-	 * will acquire the same channel lock to set the
-	 * callback to NULL. This closes the window.
-	 */
-
-	/*
-	 * Disable the lock due to newly added WITNESS check in r277723.
-	 * Will seek other way to avoid race condition.
-	 * -- whu
-	 */
-	// mtx_lock(&channel->inbound_lock);
-	if (channel->on_channel_callback != NULL) {
-		arg = channel->channel_callback_context;
-		is_batched_reading = channel->batched_reading;
-		/*
-		 * Optimize host to guest signaling by ensuring:
-		 * 1. While reading the channel, we disable interrupts from
-		 *    host.
-		 * 2. Ensure that we process all posted messages from the host
-		 *    before returning from this callback.
-		 * 3. Once we return, enable signaling from the host. Once this
-		 *    state is set we check to see if additional packets are
-		 *    available to read. In this case we repeat the process.
-		 */
-		do {
-			if (is_batched_reading)
-				hv_ring_buffer_read_begin(&channel->inbound);
-
-			channel->on_channel_callback(arg);
-
-			if (is_batched_reading)
-				bytes_to_read =
-				    hv_ring_buffer_read_end(&channel->inbound);
-			else
-				bytes_to_read = 0;
-		} while (is_batched_reading && (bytes_to_read != 0));
-	}
-	// mtx_unlock(&channel->inbound_lock);
-}
-
 /**
  * Handler for events
  */
 void
-hv_vmbus_on_events(void *arg) 
+hv_vmbus_on_events(int cpu)
 {
 	int bit;
-	int cpu;
 	int dword;
 	void *page_addr;
 	uint32_t* recv_interrupt_page = NULL;
@@ -415,7 +349,6 @@ hv_vmbus_on_events(void *arg)
 	hv_vmbus_synic_event_flags *event;
 	/* int maxdword = PAGE_SIZE >> 3; */
 
-	cpu = (int)(long)arg;
 	KASSERT(cpu <= mp_maxid, ("VMBUS: hv_vmbus_on_events: "
 	    "cpu out of range!"));
 
@@ -457,8 +390,14 @@ hv_vmbus_on_events(void *arg)
 				 */
 				continue;
 			    } else {
-				VmbusProcessChannelEvent(rel_id);
+				hv_vmbus_channel * channel = hv_vmbus_g_connection.channels[rel_id];
+				/* if channel is closed or closing */
+				if (channel == NULL || channel->rxq == NULL)
+					continue;
 
+				if (channel->batched_reading)
+					hv_ring_buffer_read_begin(&channel->inbound);
+				taskqueue_enqueue_fast(channel->rxq, &channel->channel_task);
 			    }
 			}
 		    }
diff --git a/sys/dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c b/sys/dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c
index 6df466468170..7eac11679290 100644
--- a/sys/dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c
+++ b/sys/dev/hyperv/vmbus/hv_vmbus_drv_freebsd.c
@@ -177,7 +177,7 @@ hv_vmbus_isr(struct trapframe *frame)
 	    (hv_vmbus_protocal_version == HV_VMBUS_VERSION_WIN7)) {
 		/* Since we are a child, we only need to check bit 0 */
 		if (synch_test_and_clear_bit(0, &event->flags32[0])) {
-			swi_sched(hv_vmbus_g_context.event_swintr[cpu], 0);
+			hv_vmbus_on_events(cpu);
 		}
 	} else {
 		/*
@@ -187,7 +187,7 @@ hv_vmbus_isr(struct trapframe *frame)
 		 * Directly schedule the event software interrupt on
 		 * current cpu.
 		 */
-		swi_sched(hv_vmbus_g_context.event_swintr[cpu], 0);
+		hv_vmbus_on_events(cpu);
 	}
 
 	/* Check if there are actual msgs to be process */
@@ -225,7 +225,6 @@ hv_vmbus_isr(struct trapframe *frame)
 	return (FILTER_HANDLED);
 }
 
-uint32_t hv_vmbus_swintr_event_cpu[MAXCPU];
 u_long *hv_vmbus_intr_cpu[MAXCPU];
 
 void
@@ -472,6 +471,7 @@ vmbus_bus_init(void)
 {
 	int i, j, n, ret;
 	char buf[MAXCOMLEN + 1];
+	cpuset_t cpu_mask;
 
 	if (vmbus_inited)
 		return (0);
@@ -508,10 +508,7 @@ vmbus_bus_init(void)
 	setup_args.vector = hv_vmbus_g_context.hv_cb_vector;
 
 	CPU_FOREACH(j) {
-		hv_vmbus_swintr_event_cpu[j] = 0;
-		hv_vmbus_g_context.hv_event_intr_event[j] = NULL;
 		hv_vmbus_g_context.hv_msg_intr_event[j] = NULL;
-		hv_vmbus_g_context.event_swintr[j] = NULL;
 		hv_vmbus_g_context.msg_swintr[j] = NULL;
 
 		snprintf(buf, sizeof(buf), "cpu%d:hyperv", j);
@@ -525,6 +522,20 @@ vmbus_bus_init(void)
 	 * Per cpu setup.
 	 */
 	CPU_FOREACH(j) {
+		/*
+		 * Setup taskqueue to handle events
+		 */
+		hv_vmbus_g_context.hv_event_queue[j] = taskqueue_create_fast("hyperv event", M_WAITOK,
+			taskqueue_thread_enqueue, &hv_vmbus_g_context.hv_event_queue[j]);
+		if (hv_vmbus_g_context.hv_event_queue[j] == NULL) {
+			if (bootverbose)
+				printf("VMBUS: failed to setup taskqueue\n");
+			goto cleanup1;
+		}
+		CPU_SETOF(j, &cpu_mask);
+		taskqueue_start_threads_cpuset(&hv_vmbus_g_context.hv_event_queue[j], 1, PI_NET, &cpu_mask,
+			"hvevent%d", j);
+
 		/*
 		 * Setup software interrupt thread and handler for msg handling.
 		 */
@@ -543,27 +554,13 @@ vmbus_bus_init(void)
 		 */
 		ret = intr_event_bind(hv_vmbus_g_context.hv_msg_intr_event[j],
 		    j);
-	 	if (ret) {
+		if (ret) {
 			if(bootverbose)
 				printf("VMBUS: failed to bind msg swi thread "
 				    "to cpu %d\n", j);
 			goto cleanup1;
 		}
 
-		/*
-		 * Setup software interrupt thread and handler for
-		 * event handling.
-		 */
-		ret = swi_add(&hv_vmbus_g_context.hv_event_intr_event[j],
-		    "hv_event", hv_vmbus_on_events, (void *)(long)j,
-		    SWI_CLOCK, 0, &hv_vmbus_g_context.event_swintr[j]);
-		if (ret) {
-			if(bootverbose)
-				printf("VMBUS: failed to setup event swi for "
-				    "cpu %d\n", j);
-			goto cleanup1;
-		}
-
 		/*
 		 * Prepare the per cpu msg and event pages to be called on each cpu.
 		 */
@@ -607,12 +604,11 @@ vmbus_bus_init(void)
 	 * remove swi and vmbus callback vector;
 	 */
 	CPU_FOREACH(j) {
+		if (hv_vmbus_g_context.hv_event_queue[j] != NULL)
+			taskqueue_free(hv_vmbus_g_context.hv_event_queue[j]);
 		if (hv_vmbus_g_context.msg_swintr[j] != NULL)
 			swi_remove(hv_vmbus_g_context.msg_swintr[j]);
-		if (hv_vmbus_g_context.event_swintr[j] != NULL)
-			swi_remove(hv_vmbus_g_context.event_swintr[j]);
 		hv_vmbus_g_context.hv_msg_intr_event[j] = NULL;	
-		hv_vmbus_g_context.hv_event_intr_event[j] = NULL;	
 	}
 
 	vmbus_vector_free(hv_vmbus_g_context.hv_cb_vector);
@@ -677,12 +673,11 @@ vmbus_bus_exit(void)
 
 	/* remove swi */
 	CPU_FOREACH(i) {
+		if (hv_vmbus_g_context.hv_event_queue[i] != NULL)
+			taskqueue_free(hv_vmbus_g_context.hv_event_queue[i]);
 		if (hv_vmbus_g_context.msg_swintr[i] != NULL)
 			swi_remove(hv_vmbus_g_context.msg_swintr[i]);
-		if (hv_vmbus_g_context.event_swintr[i] != NULL)
-			swi_remove(hv_vmbus_g_context.event_swintr[i]);
 		hv_vmbus_g_context.hv_msg_intr_event[i] = NULL;	
-		hv_vmbus_g_context.hv_event_intr_event[i] = NULL;	
 	}
 
 	vmbus_vector_free(hv_vmbus_g_context.hv_cb_vector);
diff --git a/sys/dev/hyperv/vmbus/hv_vmbus_priv.h b/sys/dev/hyperv/vmbus/hv_vmbus_priv.h
index 13a35c4142f9..538ab1e7222e 100644
--- a/sys/dev/hyperv/vmbus/hv_vmbus_priv.h
+++ b/sys/dev/hyperv/vmbus/hv_vmbus_priv.h
@@ -202,9 +202,8 @@ typedef struct {
 	 * Each cpu has its own software interrupt handler for channel
 	 * event and msg handling.
 	 */
-	struct intr_event		*hv_event_intr_event[MAXCPU];
+	struct taskqueue		*hv_event_queue[MAXCPU];
 	struct intr_event		*hv_msg_intr_event[MAXCPU];
-	void				*event_swintr[MAXCPU];
 	void				*msg_swintr[MAXCPU];
 	/*
 	 * Host use this vector to intrrupt guest for vmbus channel
@@ -717,7 +716,7 @@ int			hv_vmbus_connect(void);
 int			hv_vmbus_disconnect(void);
 int			hv_vmbus_post_message(void *buffer, size_t buf_size);
 int			hv_vmbus_set_event(hv_vmbus_channel *channel);
-void			hv_vmbus_on_events(void *);
+void			hv_vmbus_on_events(int cpu);
 
 /**
  * Event Timer interfaces

From 2d888f0f179f82e4954414909d56d9ec141a06d2 Mon Sep 17 00:00:00 2001
From: glebius <glebius@FreeBSD.org>
Date: Wed, 27 Jan 2016 04:59:28 +0000
Subject: [PATCH 078/113] Fix build on i386. I can't yet understand why does it
 build on amd64.

---
 sys/dev/cxgb/ulp/tom/cxgb_cpl_io.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/dev/cxgb/ulp/tom/cxgb_cpl_io.c b/sys/dev/cxgb/ulp/tom/cxgb_cpl_io.c
index d896020abf39..b41f0c662a08 100644
--- a/sys/dev/cxgb/ulp/tom/cxgb_cpl_io.c
+++ b/sys/dev/cxgb/ulp/tom/cxgb_cpl_io.c
@@ -62,9 +62,9 @@ __FBSDID("$FreeBSD$");
 #include <netinet/in_var.h>
 
 #include <netinet/ip.h>
-#include <netinet/tcp_var.h>
 #define TCPSTATES
 #include <netinet/tcp_fsm.h>
+#include <netinet/tcp_var.h>
 #include <netinet/toecore.h>
 #include <netinet/tcp_seq.h>
 #include <netinet/tcp_timer.h>

From 22b66950884956f1dd04283498f785817e894fd6 Mon Sep 17 00:00:00 2001
From: glebius <glebius@FreeBSD.org>
Date: Wed, 27 Jan 2016 05:15:53 +0000
Subject: [PATCH 079/113] More fixes to the build.

---
 sys/dev/cxgb/ulp/tom/cxgb_listen.c | 2 +-
 sys/dev/cxgbe/tom/t4_connect.c     | 2 +-
 sys/dev/cxgbe/tom/t4_listen.c      | 2 +-
 sys/dev/cxgbe/tom/t4_tom.c         | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/sys/dev/cxgb/ulp/tom/cxgb_listen.c b/sys/dev/cxgb/ulp/tom/cxgb_listen.c
index b7d69df6cd21..183102036be8 100644
--- a/sys/dev/cxgb/ulp/tom/cxgb_listen.c
+++ b/sys/dev/cxgb/ulp/tom/cxgb_listen.c
@@ -44,9 +44,9 @@ __FBSDID("$FreeBSD$");
 #include <netinet/in_pcb.h>
 #include <netinet/in_var.h>
 #include <netinet/tcp_timer.h>
-#include <netinet/tcp_var.h>
 #define TCPSTATES
 #include <netinet/tcp_fsm.h>
+#include <netinet/tcp_var.h>
 #include <netinet/toecore.h>
 
 #include "cxgb_include.h"
diff --git a/sys/dev/cxgbe/tom/t4_connect.c b/sys/dev/cxgbe/tom/t4_connect.c
index d3841aa73133..d6855e223b8d 100644
--- a/sys/dev/cxgbe/tom/t4_connect.c
+++ b/sys/dev/cxgbe/tom/t4_connect.c
@@ -49,9 +49,9 @@ __FBSDID("$FreeBSD$");
 #include <netinet/in.h>
 #include <netinet/in_pcb.h>
 #include <netinet/ip.h>
-#include <netinet/tcp_var.h>
 #define TCPSTATES
 #include <netinet/tcp_fsm.h>
+#include <netinet/tcp_var.h>
 #include <netinet/toecore.h>
 
 #include "common/common.h"
diff --git a/sys/dev/cxgbe/tom/t4_listen.c b/sys/dev/cxgbe/tom/t4_listen.c
index 5af9260371f8..36b53d386ac2 100644
--- a/sys/dev/cxgbe/tom/t4_listen.c
+++ b/sys/dev/cxgbe/tom/t4_listen.c
@@ -56,9 +56,9 @@ __FBSDID("$FreeBSD$");
 #include <netinet6/in6_fib.h>
 #include <netinet6/scope6_var.h>
 #include <netinet/tcp_timer.h>
-#include <netinet/tcp_var.h>
 #define TCPSTATES
 #include <netinet/tcp_fsm.h>
+#include <netinet/tcp_var.h>
 #include <netinet/toecore.h>
 
 #include "common/common.h"
diff --git a/sys/dev/cxgbe/tom/t4_tom.c b/sys/dev/cxgbe/tom/t4_tom.c
index c136834019b8..c9dd159aebc7 100644
--- a/sys/dev/cxgbe/tom/t4_tom.c
+++ b/sys/dev/cxgbe/tom/t4_tom.c
@@ -52,10 +52,10 @@ __FBSDID("$FreeBSD$");
 #include <netinet/in_var.h>
 #include <netinet/ip.h>
 #include <netinet/ip6.h>
-#include <netinet/tcp_var.h>
 #include <netinet6/scope6_var.h>
 #define TCPSTATES
 #include <netinet/tcp_fsm.h>
+#include <netinet/tcp_var.h>
 #include <netinet/toecore.h>
 
 #ifdef TCP_OFFLOAD

From d1f282a35f58e873cec934651e2d9107b50b1d0c Mon Sep 17 00:00:00 2001
From: ngie <ngie@FreeBSD.org>
Date: Wed, 27 Jan 2016 06:14:20 +0000
Subject: [PATCH 080/113] Require /sbin/mount_cd9660 when running the cd9660
 tests

In some cases the test system might not have mount_cd9660(8). Don't
implicitly rely on it while testing cd9660 support; explicitly rely
on it

MFC after: 1 week
Reported by: mjohnston
Sponsored by: EMC / Isilon Storage Division
---
 usr.sbin/makefs/tests/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/usr.sbin/makefs/tests/Makefile b/usr.sbin/makefs/tests/Makefile
index 437327710912..8cd315ab0329 100644
--- a/usr.sbin/makefs/tests/Makefile
+++ b/usr.sbin/makefs/tests/Makefile
@@ -8,6 +8,8 @@ BINDIR=		${TESTSDIR}
 SCRIPTS+=	makefs_tests_common.sh
 SCRIPTSNAME_makefs_tests_common.sh=	makefs_tests_common.sh
 
+TEST_METADATA.makefs_cd9660_tests+=	required_files="/sbin/mount_cd9660"
+
 .for t in ${ATF_TESTS_SH}
 TEST_METADATA.$t+=	required_user="root"
 .endfor

From 1f1c0f4112dbf60fee7e350dd01863d75a57446e Mon Sep 17 00:00:00 2001
From: dteske <dteske@FreeBSD.org>
Date: Wed, 27 Jan 2016 06:16:53 +0000
Subject: [PATCH 081/113] Remove unused function prototype

MFC after:	3 days
X-MFC-to:	stable/10
---
 lib/libdpv/dialog_util.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/lib/libdpv/dialog_util.h b/lib/libdpv/dialog_util.h
index e279c3f0621a..b0c73c52e446 100644
--- a/lib/libdpv/dialog_util.h
+++ b/lib/libdpv/dialog_util.h
@@ -55,7 +55,6 @@ extern int dheight, dwidth;
 
 __BEGIN_DECLS
 uint8_t		 dialog_prompt_nlstate(const char *_prompt);
-void		 dialog_gauge_free(void);
 void		 dialog_maxsize_free(void);
 char		*dialog_prompt_lastline(char *_prompt, uint8_t _nlstate);
 int		 dialog_maxcols(void);

From 9e39febd77269eef9d0d16682859af23e9cc83ac Mon Sep 17 00:00:00 2001
From: dteske <dteske@FreeBSD.org>
Date: Wed, 27 Jan 2016 06:21:35 +0000
Subject: [PATCH 082/113] Fix a crash if `-D' is used without `-t title'

dialog(3)'s dlg_reallocate_gauge(), used both by dialog(3)'s dialog_gauge()
and dialog(1)'s `--gauge', will segmentation fault in strlen(3) if no title
is set for the widget. Reproducible with `dialog --gauge hi 6 20' (adding
`--title ""' is enough to prevent segmentation fault).

MFC after:	3 days
X-MFC-to:	stable/10
---
 lib/libdpv/dialog_util.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/lib/libdpv/dialog_util.c b/lib/libdpv/dialog_util.c
index d047a25e5ae3..267d7a56dfdb 100644
--- a/lib/libdpv/dialog_util.c
+++ b/lib/libdpv/dialog_util.c
@@ -261,6 +261,13 @@ dialog_spawn_gauge(char *init_prompt, pid_t *pid)
 			errx(EXIT_FAILURE, "Out of memory?!");
 		sprintf(dargv[n++], "--title");
 		dargv[n++] = title;
+	} else {
+		if ((dargv[n] = malloc(8)) == NULL)
+			errx(EXIT_FAILURE, "Out of memory?!");
+		sprintf(dargv[n++], "--title");
+		if ((dargv[n] = malloc(8)) == NULL)
+			errx(EXIT_FAILURE, "Out of memory?!");
+		sprintf(dargv[n++], "");
 	}
 	if (backtitle != NULL) {
 		if ((dargv[n] = malloc(12)) == NULL)

From a1b53b920d16bc7b413aea094827f963b1bb84b0 Mon Sep 17 00:00:00 2001
From: ngie <ngie@FreeBSD.org>
Date: Wed, 27 Jan 2016 06:24:19 +0000
Subject: [PATCH 083/113] Adjust vm.max_wired in order to avoid hitting EAGAIN
 artificially

Set vm.max_wired to INT_MAX in :mlock_err, :mlock_mmap, and :mlock_nested to
avoid hitting EAGAIN artificially on the system when running the tests

Require root privileges in order to set the sysctl

Add allow_sysctl_side_effects to require.config as this test is now adjusting
sysctls that can affect the global system state

Unlike the version submitted by cem in OneFS, this version uses a scratch file
to save/restore the previous value of the sysctl. I _really_, _really_ wish
there were better hooks in atf/kyua for per test suite setup/teardown -- using
a file is kludgy, but it's the best I can do to avoid situations where (for
instance), sysctl(3) may fail and drop a core outside the kyua sandbox.

Based on a patch submitted by cem, but modified to take business logic out of
ATF_TP_ADD_TCS(3).

Differential Revision: https://reviews.freebsd.org/D4779
MFC after: 1 month
Sponsored by: EMC / Isilon Storage Division
---
 contrib/netbsd-tests/lib/libc/sys/t_mlock.c | 137 ++++++++++++++++++++
 1 file changed, 137 insertions(+)

diff --git a/contrib/netbsd-tests/lib/libc/sys/t_mlock.c b/contrib/netbsd-tests/lib/libc/sys/t_mlock.c
index 0397b5cdac6a..85d82c7ac2cd 100644
--- a/contrib/netbsd-tests/lib/libc/sys/t_mlock.c
+++ b/contrib/netbsd-tests/lib/libc/sys/t_mlock.c
@@ -47,12 +47,89 @@ __RCSID("$NetBSD: t_mlock.c,v 1.5 2014/02/26 20:49:26 martin Exp $");
 #include <unistd.h>
 
 #ifdef __FreeBSD__
+#include <limits.h>
 #define _KMEMUSER
 #include <machine/vmparam.h>
 #endif
 
 static long page = 0;
 
+#ifdef __FreeBSD__
+#define	VM_MAX_WIRED "vm.max_wired"
+
+static void
+vm_max_wired_sysctl(int *old_value, int *new_value)
+{
+	size_t old_len;
+	size_t new_len = (new_value == NULL ? 0 : sizeof(int));
+
+	if (old_value == NULL)
+		printf("Setting the new value to %d\n", *new_value);
+	else {
+		ATF_REQUIRE_MSG(sysctlbyname(VM_MAX_WIRED, NULL, &old_len,
+		    new_value, new_len) == 0,
+		    "sysctlbyname(%s) failed: %s", VM_MAX_WIRED, strerror(errno));
+	}
+
+	ATF_REQUIRE_MSG(sysctlbyname(VM_MAX_WIRED, old_value, &old_len,
+	    new_value, new_len) == 0,
+	    "sysctlbyname(%s) failed: %s", VM_MAX_WIRED, strerror(errno));
+
+	if (old_value != NULL)
+		printf("Saved the old value (%d)\n", *old_value);
+}
+
+static void
+set_vm_max_wired(int new_value)
+{
+	FILE *fp;
+	int old_value;
+
+	fp = fopen(VM_MAX_WIRED, "w");
+	if (fp == NULL) {
+		atf_tc_skip("could not open %s for writing: %s",
+		    VM_MAX_WIRED, strerror(errno));
+		return;
+	}
+
+	vm_max_wired_sysctl(&old_value, NULL);
+
+	ATF_REQUIRE_MSG(fprintf(fp, "%d", old_value) > 0,
+	    "saving %s failed", VM_MAX_WIRED);
+
+	fclose(fp);
+
+	vm_max_wired_sysctl(NULL, &new_value);
+}
+
+static void
+restore_vm_max_wired(void)
+{
+	FILE *fp;
+	int saved_max_wired;
+
+	fp = fopen(VM_MAX_WIRED, "r");
+	if (fp == NULL) {
+		perror("fopen failed\n");
+		return;
+	}
+
+	if (fscanf(fp, "%d", &saved_max_wired) != 1) {
+		perror("fscanf failed\n");
+		fclose(fp);
+		return;
+	}
+
+	fclose(fp);
+	printf("old value in %s: %d\n", VM_MAX_WIRED, saved_max_wired);
+
+	if (saved_max_wired == 0) /* This will cripple the test host */
+		return;
+
+	vm_max_wired_sysctl(NULL, &saved_max_wired);
+}
+#endif
+
 ATF_TC(mlock_clip);
 ATF_TC_HEAD(mlock_clip, tc)
 {
@@ -78,11 +155,19 @@ ATF_TC_BODY(mlock_clip, tc)
 	free(buf);
 }
 
+#ifdef __FreeBSD__
+ATF_TC_WITH_CLEANUP(mlock_err);
+#else
 ATF_TC(mlock_err);
+#endif
 ATF_TC_HEAD(mlock_err, tc)
 {
 	atf_tc_set_md_var(tc, "descr",
 	    "Test error conditions in mlock(2) and munlock(2)");
+#ifdef __FreeBSD__
+	atf_tc_set_md_var(tc, "require.config", "allow_sysctl_side_effects");
+	atf_tc_set_md_var(tc, "require.user", "root");
+#endif
 }
 
 ATF_TC_BODY(mlock_err, tc)
@@ -99,6 +184,8 @@ ATF_TC_BODY(mlock_err, tc)
 	if ((uintptr_t)VM_MIN_ADDRESS > 0)
 		null_errno = EINVAL;	/* NULL is not inside user VM */
 #endif
+	/* Set max_wired really really high to avoid EAGAIN */
+	set_vm_max_wired(INT_MAX);
 #else
 	if (sysctlbyname("vm.minaddress", &vmin, &len, NULL, 0) != 0)
 		atf_tc_fail("failed to read vm.minaddress");
@@ -139,6 +226,14 @@ ATF_TC_BODY(mlock_err, tc)
 	ATF_REQUIRE_ERRNO(ENOMEM, munlock(invalid_ptr, page) == -1);
 }
 
+#ifdef __FreeBSD__
+ATF_TC_CLEANUP(mlock_err, tc)
+{
+
+	restore_vm_max_wired();
+}
+#endif
+
 ATF_TC(mlock_limits);
 ATF_TC_HEAD(mlock_limits, tc)
 {
@@ -200,10 +295,18 @@ ATF_TC_BODY(mlock_limits, tc)
 	free(buf);
 }
 
+#ifdef __FreeBSD__
+ATF_TC_WITH_CLEANUP(mlock_mmap);
+#else
 ATF_TC(mlock_mmap);
+#endif
 ATF_TC_HEAD(mlock_mmap, tc)
 {
 	atf_tc_set_md_var(tc, "descr", "Test mlock(2)-mmap(2) interaction");
+#ifdef __FreeBSD__
+	atf_tc_set_md_var(tc, "require.config", "allow_sysctl_side_effects");
+	atf_tc_set_md_var(tc, "require.user", "root");
+#endif
 }
 
 ATF_TC_BODY(mlock_mmap, tc)
@@ -215,6 +318,11 @@ ATF_TC_BODY(mlock_mmap, tc)
 #endif
 	void *buf;
 
+#ifdef __FreeBSD__
+	/* Set max_wired really really high to avoid EAGAIN */
+	set_vm_max_wired(INT_MAX);
+#endif
+
 	/*
 	 * Make a wired RW mapping and check that mlock(2)
 	 * does not fail for the (already locked) mapping.
@@ -248,11 +356,27 @@ ATF_TC_BODY(mlock_mmap, tc)
 	ATF_REQUIRE(munmap(buf, page) == 0);
 }
 
+#ifdef __FreeBSD__
+ATF_TC_CLEANUP(mlock_mmap, tc)
+{
+
+	restore_vm_max_wired();
+}
+#endif
+
+#ifdef __FreeBSD__
+ATF_TC_WITH_CLEANUP(mlock_nested);
+#else
 ATF_TC(mlock_nested);
+#endif
 ATF_TC_HEAD(mlock_nested, tc)
 {
 	atf_tc_set_md_var(tc, "descr",
 	    "Test that consecutive mlock(2) calls succeed");
+#ifdef __FreeBSD__
+	atf_tc_set_md_var(tc, "require.config", "allow_sysctl_side_effects");
+	atf_tc_set_md_var(tc, "require.user", "root");
+#endif
 }
 
 ATF_TC_BODY(mlock_nested, tc)
@@ -260,6 +384,11 @@ ATF_TC_BODY(mlock_nested, tc)
 	const size_t maxiter = 100;
 	void *buf;
 
+#ifdef __FreeBSD__
+	/* Set max_wired really really high to avoid EAGAIN */
+	set_vm_max_wired(INT_MAX);
+#endif
+
 	buf = malloc(page);
 	ATF_REQUIRE(buf != NULL);
 
@@ -270,6 +399,14 @@ ATF_TC_BODY(mlock_nested, tc)
 	free(buf);
 }
 
+#ifdef __FreeBSD__
+ATF_TC_CLEANUP(mlock_nested, tc)
+{
+
+	restore_vm_max_wired();
+}
+#endif
+
 ATF_TP_ADD_TCS(tp)
 {
 

From 2dbb39130019d05d6f738a3393c9e7c1c5ce080d Mon Sep 17 00:00:00 2001
From: araujo <araujo@FreeBSD.org>
Date: Wed, 27 Jan 2016 06:28:56 +0000
Subject: [PATCH 084/113] Fix regression introduced on r293801. The UID/GID 93
 is in using by jaber on PORTS, we will use UID/GID 160 for ypldap(8).

Reported by:	antoine
Approved by:	bapt (mentor)
Differential Revision:	https://reviews.freebsd.org/D5062
---
 etc/group         | 1 +
 etc/master.passwd | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/etc/group b/etc/group
index ae013e809115..c20f1d93dd3c 100644
--- a/etc/group
+++ b/etc/group
@@ -29,6 +29,7 @@ dialer:*:68:
 network:*:69:
 audit:*:77:
 www:*:80:
+_ypldap:*:160:
 hast:*:845:
 nogroup:*:65533:
 nobody:*:65534:
diff --git a/etc/master.passwd b/etc/master.passwd
index fc7fef59438b..e6031924ac59 100644
--- a/etc/master.passwd
+++ b/etc/master.passwd
@@ -22,6 +22,6 @@ uucp:*:66:66::0:0:UUCP pseudo-user:/var/spool/uucppublic:/usr/local/libexec/uucp
 pop:*:68:6::0:0:Post Office Owner:/nonexistent:/usr/sbin/nologin
 auditdistd:*:78:77::0:0:Auditdistd unprivileged user:/var/empty:/usr/sbin/nologin
 www:*:80:80::0:0:World Wide Web Owner:/nonexistent:/usr/sbin/nologin
-_ypldap:*:93:93::0:0:YP Ldap unprivileged user:/var/empty:/usr/sbin/nologin
+_ypldap:*:160:160::0:0:YP Ldap unprivileged user:/var/empty:/usr/sbin/nologin
 hast:*:845:845::0:0:HAST unprivileged user:/var/empty:/usr/sbin/nologin
 nobody:*:65534:65534::0:0:Unprivileged user:/nonexistent:/usr/sbin/nologin

From 61503a8b9a08d7b89fb84849b5755265ed602016 Mon Sep 17 00:00:00 2001
From: ngie <ngie@FreeBSD.org>
Date: Wed, 27 Jan 2016 07:06:49 +0000
Subject: [PATCH 085/113] Add debug output via ATF_REQUIRE_MSG when the first
 call to mlock(2) fails

This helps identify the problem with running this test on my VM
hosts (ENOMEM)

MFC after: 3 days
Sponsored by: EMC / Isilon Storage Division
---
 contrib/netbsd-tests/lib/libc/sys/t_mincore.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/contrib/netbsd-tests/lib/libc/sys/t_mincore.c b/contrib/netbsd-tests/lib/libc/sys/t_mincore.c
index 499493f380ad..872856eba469 100644
--- a/contrib/netbsd-tests/lib/libc/sys/t_mincore.c
+++ b/contrib/netbsd-tests/lib/libc/sys/t_mincore.c
@@ -206,7 +206,8 @@ ATF_TC_BODY(mincore_resid, tc)
 		    "might be low on memory");
 
 #ifdef __FreeBSD__
-	ATF_REQUIRE(mlock(addr, npgs * page) == 0);
+	ATF_REQUIRE_MSG(mlock(addr, npgs * page) == 0, "mlock failed: %s",
+	    strerror(errno));
 #endif
 	ATF_REQUIRE(check_residency(addr, npgs) == npgs);
 	ATF_REQUIRE(munmap(addr, npgs * page) == 0);

From c07f0f872d21c891ec351eccf996f445a63a30e7 Mon Sep 17 00:00:00 2001
From: delphij <delphij@FreeBSD.org>
Date: Wed, 27 Jan 2016 07:20:55 +0000
Subject: [PATCH 086/113] Implement AT_SECURE properly.

AT_SECURE auxv entry has been added to the Linux 2.5 kernel to pass a
boolean flag indicating whether secure mode should be enabled. 1 means
that the program has changes its credentials during the execution.
Being exported AT_SECURE used by glibc issetugid() call.

Submitted by:	imp, dchagin
Security:	FreeBSD-SA-16:10.linux
Security:	CVE-2016-1883
---
 sys/amd64/linux/linux_sysvec.c     | 4 +++-
 sys/amd64/linux32/linux32_sysvec.c | 4 +++-
 sys/i386/linux/linux_sysvec.c      | 4 +++-
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/sys/amd64/linux/linux_sysvec.c b/sys/amd64/linux/linux_sysvec.c
index d49ca79256dc..0bdcba09ad71 100644
--- a/sys/amd64/linux/linux_sysvec.c
+++ b/sys/amd64/linux/linux_sysvec.c
@@ -271,6 +271,7 @@ elf_linux_fixup(register_t **stack_base, struct image_params *imgp)
 	Elf_Addr *pos;
 	struct ps_strings *arginfo;
 	struct proc *p;
+	int issetugid;
 
 	p = imgp->proc;
 	arginfo = (struct ps_strings *)p->p_sysent->sv_psstrings;
@@ -281,6 +282,7 @@ elf_linux_fixup(register_t **stack_base, struct image_params *imgp)
 	args = (Elf64_Auxargs *)imgp->auxargs;
 	pos = base + (imgp->args->argc + imgp->args->envc + 2);
 
+	issetugid = p->p_flag & P_SUGID ? 1 : 0;
 	AUXARGS_ENTRY(pos, LINUX_AT_SYSINFO_EHDR,
 	    imgp->proc->p_sysent->sv_shared_page_base);
 	AUXARGS_ENTRY(pos, LINUX_AT_HWCAP, cpu_feature);
@@ -296,7 +298,7 @@ elf_linux_fixup(register_t **stack_base, struct image_params *imgp)
 	AUXARGS_ENTRY(pos, AT_EUID, imgp->proc->p_ucred->cr_svuid);
 	AUXARGS_ENTRY(pos, AT_GID, imgp->proc->p_ucred->cr_rgid);
 	AUXARGS_ENTRY(pos, AT_EGID, imgp->proc->p_ucred->cr_svgid);
-	AUXARGS_ENTRY(pos, LINUX_AT_SECURE, 0);
+	AUXARGS_ENTRY(pos, LINUX_AT_SECURE, issetugid);
 	AUXARGS_ENTRY(pos, LINUX_AT_PLATFORM, PTROUT(linux_platform));
 	AUXARGS_ENTRY(pos, LINUX_AT_RANDOM, imgp->canary);
 	if (imgp->execpathp != 0)
diff --git a/sys/amd64/linux32/linux32_sysvec.c b/sys/amd64/linux32/linux32_sysvec.c
index 7d3615eb7520..f89b8fae3e11 100644
--- a/sys/amd64/linux32/linux32_sysvec.c
+++ b/sys/amd64/linux32/linux32_sysvec.c
@@ -230,6 +230,7 @@ elf_linux_fixup(register_t **stack_base, struct image_params *imgp)
 	Elf32_Addr *base;
 	Elf32_Addr *pos;
 	struct linux32_ps_strings *arginfo;
+	int issetugid;
 
 	arginfo = (struct linux32_ps_strings *)LINUX32_PS_STRINGS;
 
@@ -239,6 +240,7 @@ elf_linux_fixup(register_t **stack_base, struct image_params *imgp)
 	args = (Elf32_Auxargs *)imgp->auxargs;
 	pos = base + (imgp->args->argc + imgp->args->envc + 2);
 
+	issetugid = imgp->proc->p_flag & P_SUGID ? 1 : 0;
 	AUXARGS_ENTRY_32(pos, LINUX_AT_SYSINFO_EHDR,
 	    imgp->proc->p_sysent->sv_shared_page_base);
 	AUXARGS_ENTRY_32(pos, LINUX_AT_SYSINFO, linux32_vsyscall);
@@ -261,7 +263,7 @@ elf_linux_fixup(register_t **stack_base, struct image_params *imgp)
 	AUXARGS_ENTRY_32(pos, AT_FLAGS, args->flags);
 	AUXARGS_ENTRY_32(pos, AT_ENTRY, args->entry);
 	AUXARGS_ENTRY_32(pos, AT_BASE, args->base);
-	AUXARGS_ENTRY_32(pos, LINUX_AT_SECURE, 0);
+	AUXARGS_ENTRY_32(pos, LINUX_AT_SECURE, issetugid);
 	AUXARGS_ENTRY_32(pos, AT_UID, imgp->proc->p_ucred->cr_ruid);
 	AUXARGS_ENTRY_32(pos, AT_EUID, imgp->proc->p_ucred->cr_svuid);
 	AUXARGS_ENTRY_32(pos, AT_GID, imgp->proc->p_ucred->cr_rgid);
diff --git a/sys/i386/linux/linux_sysvec.c b/sys/i386/linux/linux_sysvec.c
index cc5fcaab3942..c4a5ee59276b 100644
--- a/sys/i386/linux/linux_sysvec.c
+++ b/sys/i386/linux/linux_sysvec.c
@@ -238,11 +238,13 @@ elf_linux_fixup(register_t **stack_base, struct image_params *imgp)
 	Elf32_Addr *uplatform;
 	struct ps_strings *arginfo;
 	register_t *pos;
+	int issetugid;
 
 	KASSERT(curthread->td_proc == imgp->proc,
 	    ("unsafe elf_linux_fixup(), should be curproc"));
 
 	p = imgp->proc;
+	issetugid = imgp->proc->p_flag & P_SUGID ? 1 : 0;
 	arginfo = (struct ps_strings *)p->p_sysent->sv_psstrings;
 	uplatform = (Elf32_Addr *)((caddr_t)arginfo - linux_szplatform);
 	args = (Elf32_Auxargs *)imgp->auxargs;
@@ -270,7 +272,7 @@ elf_linux_fixup(register_t **stack_base, struct image_params *imgp)
 	AUXARGS_ENTRY(pos, AT_FLAGS, args->flags);
 	AUXARGS_ENTRY(pos, AT_ENTRY, args->entry);
 	AUXARGS_ENTRY(pos, AT_BASE, args->base);
-	AUXARGS_ENTRY(pos, LINUX_AT_SECURE, 0);
+	AUXARGS_ENTRY(pos, LINUX_AT_SECURE, issetugid);
 	AUXARGS_ENTRY(pos, AT_UID, imgp->proc->p_ucred->cr_ruid);
 	AUXARGS_ENTRY(pos, AT_EUID, imgp->proc->p_ucred->cr_svuid);
 	AUXARGS_ENTRY(pos, AT_GID, imgp->proc->p_ucred->cr_rgid);

From 2af1c82fc1f9ccdd73b6255b84c1a1667f7ce818 Mon Sep 17 00:00:00 2001
From: glebius <glebius@FreeBSD.org>
Date: Wed, 27 Jan 2016 07:34:00 +0000
Subject: [PATCH 087/113] Fix issues with TCP_CONGESTION handling after
 r294540: o Return back the buf[TCP_CA_NAME_MAX] for TCP_CONGESTION,   for
 TCP_CCALGOOPT use dynamically allocated *pbuf. o For SOPT_SET TCP_CONGESTION
 do NULL terminating of string   taking from userland. o For SOPT_SET
 TCP_CONGESTION do the search for the algorithm   keeping the inpcb lock. o
 For SOPT_GET TCP_CONGESTION first strlcpy() the name   holding the inpcb lock
 into temporary buffer, then copyout.

Together with:	lstewart
---
 sys/netinet/tcp_usrreq.c | 31 +++++++++++++++----------------
 1 file changed, 15 insertions(+), 16 deletions(-)

diff --git a/sys/netinet/tcp_usrreq.c b/sys/netinet/tcp_usrreq.c
index 0a87a6219b7b..204db3963193 100644
--- a/sys/netinet/tcp_usrreq.c
+++ b/sys/netinet/tcp_usrreq.c
@@ -1479,7 +1479,8 @@ tcp_default_ctloutput(struct socket *so, struct sockopt *sopt, struct inpcb *inp
 	u_int	ui;
 	struct	tcp_info ti;
 	struct cc_algo *algo;
-	char	*buf;
+	char	*pbuf, buf[TCP_CA_NAME_MAX];
+	size_t	len;
 
 	/*
 	 * For TCP_CCALGOOPT forward the control to CC module, for both
@@ -1488,22 +1489,22 @@ tcp_default_ctloutput(struct socket *so, struct sockopt *sopt, struct inpcb *inp
 	switch (sopt->sopt_name) {
 	case TCP_CCALGOOPT:
 		INP_WUNLOCK(inp);
-		buf = malloc(sopt->sopt_valsize, M_TEMP, M_WAITOK | M_ZERO);
-		error = sooptcopyin(sopt, buf, sopt->sopt_valsize,
+		pbuf = malloc(sopt->sopt_valsize, M_TEMP, M_WAITOK | M_ZERO);
+		error = sooptcopyin(sopt, pbuf, sopt->sopt_valsize,
 		    sopt->sopt_valsize);
 		if (error) {
-			free(buf, M_TEMP);
+			free(pbuf, M_TEMP);
 			return (error);
 		}
 		INP_WLOCK_RECHECK(inp);
 		if (CC_ALGO(tp)->ctl_output != NULL)
-			error = CC_ALGO(tp)->ctl_output(tp->ccv, sopt, buf);
+			error = CC_ALGO(tp)->ctl_output(tp->ccv, sopt, pbuf);
 		else
 			error = ENOENT;
 		INP_WUNLOCK(inp);
 		if (error == 0 && sopt->sopt_dir == SOPT_GET)
-			error = sooptcopyout(sopt, buf, sopt->sopt_valsize);
-		free(buf, M_TEMP);
+			error = sooptcopyout(sopt, pbuf, sopt->sopt_valsize);
+		free(pbuf, M_TEMP);
 		return (error);
 	}
 
@@ -1600,24 +1601,22 @@ tcp_default_ctloutput(struct socket *so, struct sockopt *sopt, struct inpcb *inp
 
 		case TCP_CONGESTION:
 			INP_WUNLOCK(inp);
-			buf = malloc(TCP_CA_NAME_MAX, M_TEMP, M_WAITOK|M_ZERO);
-			error = sooptcopyin(sopt, buf, TCP_CA_NAME_MAX, 1);
-			if (error) {
-				free(buf, M_TEMP);
+			error = sooptcopyin(sopt, buf, TCP_CA_NAME_MAX - 1, 1);
+			if (error)
 				break;
-			}
+			buf[sopt->sopt_valsize] = '\0';
+			INP_WLOCK_RECHECK(inp);
 			CC_LIST_RLOCK();
 			STAILQ_FOREACH(algo, &cc_list, entries)
 				if (strncmp(buf, algo->name,
 				    TCP_CA_NAME_MAX) == 0)
 					break;
 			CC_LIST_RUNLOCK();
-			free(buf, M_TEMP);
 			if (algo == NULL) {
+				INP_WUNLOCK(inp);
 				error = EINVAL;
 				break;
 			}
-			INP_WLOCK_RECHECK(inp);
 			/*
 			 * We hold a write lock over the tcb so it's safe to
 			 * do these things without ordering concerns.
@@ -1786,9 +1785,9 @@ tcp_default_ctloutput(struct socket *so, struct sockopt *sopt, struct inpcb *inp
 			error = sooptcopyout(sopt, &ti, sizeof ti);
 			break;
 		case TCP_CONGESTION:
+			len = strlcpy(buf, CC_ALGO(tp)->name, TCP_CA_NAME_MAX);
 			INP_WUNLOCK(inp);
-			error = sooptcopyout(sopt, CC_ALGO(tp)->name,
-			    TCP_CA_NAME_MAX);
+			error = sooptcopyout(sopt, buf, len + 1);
 			break;
 		case TCP_KEEPIDLE:
 		case TCP_KEEPINTVL:

From d5eb8171ceea1d3e00ff7236209db42f557f025c Mon Sep 17 00:00:00 2001
From: br <br@FreeBSD.org>
Date: Wed, 27 Jan 2016 10:34:07 +0000
Subject: [PATCH 088/113] Add the RISC-V MD parts of libthread_db.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D5064
---
 lib/libthread_db/arch/riscv/libpthread_md.c | 104 ++++++++++++++++++++
 1 file changed, 104 insertions(+)
 create mode 100644 lib/libthread_db/arch/riscv/libpthread_md.c

diff --git a/lib/libthread_db/arch/riscv/libpthread_md.c b/lib/libthread_db/arch/riscv/libpthread_md.c
new file mode 100644
index 000000000000..31b72ce8fa30
--- /dev/null
+++ b/lib/libthread_db/arch/riscv/libpthread_md.c
@@ -0,0 +1,104 @@
+/*-
+ * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Portions of this software were developed by SRI International and the
+ * University of Cambridge Computer Laboratory under DARPA/AFRL contract
+ * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Portions of this software were developed by the University of Cambridge
+ * Computer Laboratory as part of the CTSRD Project, with support from the
+ * UK Higher Education Innovation Fund (HEIF).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/types.h>
+#include <string.h>
+#include <thread_db.h>
+
+#include "libpthread_db.h"
+
+void
+pt_reg_to_ucontext(const struct reg *r, ucontext_t *uc)
+{
+	mcontext_t *mc;
+
+	mc = &uc->uc_mcontext;
+
+	memcpy(mc->mc_gpregs.gp_t, r->t, sizeof(mc->mc_gpregs.gp_t));
+	memcpy(mc->mc_gpregs.gp_s, r->s, sizeof(mc->mc_gpregs.gp_s));
+	memcpy(mc->mc_gpregs.gp_a, r->a, sizeof(mc->mc_gpregs.gp_a));
+	mc->mc_gpregs.gp_ra = r->ra;
+	mc->mc_gpregs.gp_sp = r->sp;
+	mc->mc_gpregs.gp_gp = r->gp;
+	mc->mc_gpregs.gp_tp = r->tp;
+	mc->mc_gpregs.gp_sepc = r->sepc;
+	mc->mc_gpregs.gp_sstatus = r->sstatus;
+}
+
+void
+pt_ucontext_to_reg(const ucontext_t *uc, struct reg *r)
+{
+	const mcontext_t *mc;
+
+	mc = &uc->uc_mcontext;
+
+	memcpy(r->t, mc->mc_gpregs.gp_t, sizeof(mc->mc_gpregs.gp_t));
+	memcpy(r->s, mc->mc_gpregs.gp_s, sizeof(mc->mc_gpregs.gp_s));
+	memcpy(r->a, mc->mc_gpregs.gp_a, sizeof(mc->mc_gpregs.gp_a));
+	r->ra = mc->mc_gpregs.gp_ra;
+	r->sp = mc->mc_gpregs.gp_sp;
+	r->gp = mc->mc_gpregs.gp_gp;
+	r->tp = mc->mc_gpregs.gp_tp;
+	r->sepc = mc->mc_gpregs.gp_sepc;
+	r->sstatus = mc->mc_gpregs.gp_sstatus;
+}
+
+void
+pt_fpreg_to_ucontext(const struct fpreg *r __unused, ucontext_t *uc __unused)
+{
+
+	/* RISCVTODO */
+}
+
+void
+pt_ucontext_to_fpreg(const ucontext_t *uc __unused, struct fpreg *r __unused)
+{
+
+	/* RISCVTODO */
+}
+
+void
+pt_md_init(void)
+{
+}
+
+int
+pt_reg_sstep(struct reg *reg __unused, int step __unused)
+{
+
+	return (0);
+}

From bf4d31468166ff9c7213b935db107710e338159a Mon Sep 17 00:00:00 2001
From: des <des@FreeBSD.org>
Date: Wed, 27 Jan 2016 13:40:44 +0000
Subject: [PATCH 089/113] Switch UseDNS back on

---
 crypto/openssh/FREEBSD-upgrade | 1 +
 crypto/openssh/servconf.c      | 2 +-
 crypto/openssh/sshd_config     | 2 +-
 crypto/openssh/sshd_config.5   | 6 ++++--
 4 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/crypto/openssh/FREEBSD-upgrade b/crypto/openssh/FREEBSD-upgrade
index 811623529674..7acd51fbe663 100644
--- a/crypto/openssh/FREEBSD-upgrade
+++ b/crypto/openssh/FREEBSD-upgrade
@@ -117,6 +117,7 @@
       - PasswordAuthentication defaults to "no".
       - VersionAddendum defaults to "FreeBSD-YYYYMMDD".
       - PrivilegeSeparation defaults to "sandbox".
+      - UseDNS defaults to "yes".
 
 2) Modified client-side defaults
 
diff --git a/crypto/openssh/servconf.c b/crypto/openssh/servconf.c
index ff61471dae2b..6f5c07d7a559 100644
--- a/crypto/openssh/servconf.c
+++ b/crypto/openssh/servconf.c
@@ -320,7 +320,7 @@ fill_default_server_options(ServerOptions *options)
 	if (options->max_sessions == -1)
 		options->max_sessions = DEFAULT_SESSIONS_MAX;
 	if (options->use_dns == -1)
-		options->use_dns = 0;
+		options->use_dns = 1;
 	if (options->client_alive_interval == -1)
 		options->client_alive_interval = 0;
 	if (options->client_alive_count_max == -1)
diff --git a/crypto/openssh/sshd_config b/crypto/openssh/sshd_config
index 694654d35d4d..6ab7900bc544 100644
--- a/crypto/openssh/sshd_config
+++ b/crypto/openssh/sshd_config
@@ -115,7 +115,7 @@
 #Compression delayed
 #ClientAliveInterval 0
 #ClientAliveCountMax 3
-#UseDNS no
+#UseDNS yes
 #PidFile /var/run/sshd.pid
 #MaxStartups 10:30:100
 #PermitTunnel no
diff --git a/crypto/openssh/sshd_config.5 b/crypto/openssh/sshd_config.5
index 4a0f72d1f259..9945fc93cab0 100644
--- a/crypto/openssh/sshd_config.5
+++ b/crypto/openssh/sshd_config.5
@@ -1541,8 +1541,8 @@ the resolved host name for the remote IP address maps back to the
 very same IP address.
 .Pp
 If this option is set to
-.Dq no
-(the default) then only addresses and not host names may be used in
+.Dq no ,
+then only addresses and not host names may be used in
 .Pa ~/.ssh/known_hosts
 .Cm from
 and
@@ -1550,6 +1550,8 @@ and
 .Cm Match
 .Cm Host
 directives.
+The default is
+.Dq yes .
 .It Cm UseLogin
 Specifies whether
 .Xr login 1

From aad03cf95cc55ec999cf45e2fabdaadecbc27624 Mon Sep 17 00:00:00 2001
From: br <br@FreeBSD.org>
Date: Wed, 27 Jan 2016 14:10:50 +0000
Subject: [PATCH 090/113] Add pthread MD part for RISC-V.

Reviewed by:	andrew
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D5063
---
 lib/libthr/arch/riscv/include/pthread_md.h | 92 ++++++++++++++++++++++
 1 file changed, 92 insertions(+)
 create mode 100644 lib/libthr/arch/riscv/include/pthread_md.h

diff --git a/lib/libthr/arch/riscv/include/pthread_md.h b/lib/libthr/arch/riscv/include/pthread_md.h
new file mode 100644
index 000000000000..86eccc15e0eb
--- /dev/null
+++ b/lib/libthr/arch/riscv/include/pthread_md.h
@@ -0,0 +1,92 @@
+/*-
+ * Copyright (c) 2005 David Xu <davidxu@freebsd.org>
+ * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
+ * All rights reserved.
+ *
+ * Portions of this software were developed by SRI International and the
+ * University of Cambridge Computer Laboratory under DARPA/AFRL contract
+ * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Portions of this software were developed by the University of Cambridge
+ * Computer Laboratory as part of the CTSRD Project, with support from the
+ * UK Higher Education Innovation Fund (HEIF).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+/*
+ * Machine-dependent thread prototypes/definitions.
+ */
+#ifndef _PTHREAD_MD_H_
+#define	_PTHREAD_MD_H_
+
+#include <sys/types.h>
+#include <stddef.h>
+
+#define	CPU_SPINWAIT
+#define	DTV_OFFSET		offsetof(struct tcb, tcb_dtv)
+#define	TP_OFFSET		0x10
+
+/*
+ * Variant I tcb. The structure layout is fixed, don't blindly
+ * change it!
+ */
+struct tcb {
+	void			*tcb_dtv;
+	struct pthread		*tcb_thread;
+};
+
+/* Called from the thread to set its private data. */
+static __inline void
+_tcb_set(struct tcb *tcb)
+{
+
+	__asm __volatile("mv tp, %0" :: "r"((uint8_t *)tcb + TP_OFFSET));
+}
+
+/*
+ * Get the current tcb.
+ */
+static __inline struct tcb *
+_tcb_get(void)
+{
+	register uint8_t *_tp;
+
+	__asm __volatile("mv %0, tp" : "=r"(_tp));
+
+	return ((struct tcb *)(_tp - TP_OFFSET));
+}
+
+extern struct pthread *_thr_initial;
+
+static __inline struct pthread *
+_get_curthread(void)
+{
+
+	if (_thr_initial)
+		return (_tcb_get()->tcb_thread);
+	return (NULL);
+}
+
+#endif /* _PTHREAD_MD_H_ */

From 9ad1767fb136f7c8fa5c12f554b25812dbb698c5 Mon Sep 17 00:00:00 2001
From: hselasky <hselasky@FreeBSD.org>
Date: Wed, 27 Jan 2016 14:46:30 +0000
Subject: [PATCH 091/113] Fix generation of dependency rules for the LinuxKPI,
 the MLX5 driver and all of OFED except MLX4[EN/IB].

Sponsored by:	Mellanox Technologies
MFC after:	1 week
---
 sys/conf/files        | 137 +++++++++++++++---------------------------
 sys/conf/kern.post.mk |  27 +++++++--
 2 files changed, 73 insertions(+), 91 deletions(-)

diff --git a/sys/conf/files b/sys/conf/files
index 076b3ce36356..bbf971319e09 100644
--- a/sys/conf/files
+++ b/sys/conf/files
@@ -3821,133 +3821,96 @@ nlm/sm_inter_xdr.c		optional nfslockd | nfsd
 
 # Linux Kernel Programming Interface
 compat/linuxkpi/common/src/linux_kmod.c		optional compat_linuxkpi \
-	no-depend compile-with "${LINUXKPI_C}"
+	compile-with "${LINUXKPI_C}"
 compat/linuxkpi/common/src/linux_compat.c	optional compat_linuxkpi \
-	no-depend compile-with "${LINUXKPI_C}"
+	compile-with "${LINUXKPI_C}"
 compat/linuxkpi/common/src/linux_pci.c		optional compat_linuxkpi pci \
-	no-depend compile-with "${LINUXKPI_C}"
+	compile-with "${LINUXKPI_C}"
 compat/linuxkpi/common/src/linux_idr.c		optional compat_linuxkpi \
-	no-depend compile-with "${LINUXKPI_C}"
+	compile-with "${LINUXKPI_C}"
 compat/linuxkpi/common/src/linux_radix.c	optional compat_linuxkpi \
-	no-depend compile-with "${LINUXKPI_C}"
+	compile-with "${LINUXKPI_C}"
 compat/linuxkpi/common/src/linux_usb.c		optional compat_linuxkpi usb \
-	no-depend compile-with "${LINUXKPI_C}"
+	compile-with "${LINUXKPI_C}"
 
 # OpenFabrics Enterprise Distribution (Infiniband)
 ofed/drivers/infiniband/core/addr.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/agent.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/cache.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 # XXX Mad.c must be ordered before cm.c for sysinit sets to occur in
 # the correct order.
 ofed/drivers/infiniband/core/mad.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/cm.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/ -Wno-unused-function"
 ofed/drivers/infiniband/core/cma.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/device.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/fmr_pool.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/iwcm.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/mad_rmpp.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/multicast.c	optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/packer.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/peer_mem.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/sa_query.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/smi.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/sysfs.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/ucm.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/ucma.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/ud_header.c	optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/umem.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/user_mad.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/uverbs_cmd.c	optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/uverbs_main.c	optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/uverbs_marshall.c	optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 ofed/drivers/infiniband/core/verbs.c		optional ofed		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/core/"
 
 ofed/drivers/infiniband/ulp/ipoib/ipoib_cm.c	optional ipoib		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 #ofed/drivers/infiniband/ulp/ipoib/ipoib_fs.c	optional ipoib		\
-#	no-depend							\
 #	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c	optional ipoib		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c	optional ipoib		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c	optional ipoib	\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 ofed/drivers/infiniband/ulp/ipoib/ipoib_verbs.c	optional ipoib		\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 #ofed/drivers/infiniband/ulp/ipoib/ipoib_vlan.c	optional ipoib		\
-#	no-depend							\
 #	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/"
 
 ofed/drivers/infiniband/ulp/sdp/sdp_bcopy.c	optional sdp inet	\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/"
 ofed/drivers/infiniband/ulp/sdp/sdp_main.c	optional sdp inet 	\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/"
 ofed/drivers/infiniband/ulp/sdp/sdp_rx.c	optional sdp inet 	\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/"
 ofed/drivers/infiniband/ulp/sdp/sdp_cma.c	optional sdp inet 	\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/"
 ofed/drivers/infiniband/ulp/sdp/sdp_tx.c	optional sdp inet 	\
-	no-depend							\
 	compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/"
 
 ofed/drivers/infiniband/hw/mlx4/alias_GUID.c    optional mlx4ib         \
@@ -4077,95 +4040,95 @@ ofed/drivers/net/mlx4/en_tx.c			optional mlxen		\
 	compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
 
 dev/mlx5/mlx5_core/mlx5_alloc.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_cmd.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_cq.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_eq.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_flow_table.c		optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_fw.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_health.c		optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_mad.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_main.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_mcg.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_mr.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_pagealloc.c		optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_pd.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_port.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_qp.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_srq.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_transobj.c		optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_uar.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_vport.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_core/mlx5_wq.c			optional mlx5 pci	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 
 dev/mlx5/mlx5_en/mlx5_en_ethtool.c		optional mlx5en pci inet inet6	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_en/mlx5_en_main.c			optional mlx5en pci inet inet6	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_en/mlx5_en_tx.c			optional mlx5en pci inet inet6	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_en/mlx5_en_flow_table.c		optional mlx5en pci inet inet6	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_en/mlx5_en_rx.c			optional mlx5en pci inet inet6	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 dev/mlx5/mlx5_en/mlx5_en_txrx.c			optional mlx5en pci inet inet6	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 
 ofed/drivers/infiniband/hw/mthca/mthca_allocator.c	optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_av.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_catas.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_cmd.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_cq.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_eq.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_mad.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_main.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_mcg.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_memfree.c	optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_mr.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_pd.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_profile.c	optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_provider.c	optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_qp.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_reset.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_srq.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 ofed/drivers/infiniband/hw/mthca/mthca_uar.c		optional mthca	\
-	no-depend compile-with "${OFED_C}"
+	compile-with "${OFED_C}"
 
 # crypto support
 opencrypto/cast.c		optional crypto | ipsec
diff --git a/sys/conf/kern.post.mk b/sys/conf/kern.post.mk
index 65d162b81a48..56f7c507f1fb 100644
--- a/sys/conf/kern.post.mk
+++ b/sys/conf/kern.post.mk
@@ -186,12 +186,23 @@ genassym.o: $S/$M/$M/genassym.c
 
 ${SYSTEM_OBJS} genassym.o vers.o: opt_global.h
 
+# Normal files first
+CFILES_NORMAL=	${CFILES:N*/cddl/*:N*fs/nfsclient/nfs_clkdtrace*:N*/compat/linuxkpi/common/*:N*/ofed/*:N*/dev/mlx5/*}
+SFILES_NORMAL=	${SFILES:N*/cddl/*}
+
 # We have "special" -I include paths for zfs/dtrace files in 'depend'.
-CFILES_NOCDDL=	${CFILES:N*/cddl/*:N*fs/nfsclient/nfs_clkdtrace*}
-SFILES_NOCDDL=	${SFILES:N*/cddl/*}
 CFILES_CDDL=	${CFILES:M*/cddl/*}
 SFILES_CDDL=	${SFILES:M*/cddl/*}
 
+# We have "special" -I include paths for LinuxKPI.
+CFILES_LINUXKPI=${CFILES:M*/compat/linuxkpi/common/*}
+
+# We have "special" -I include paths for OFED.
+CFILES_OFED=${CFILES:M*/ofed/*}
+
+# We have "special" -I include paths for MLX5.
+CFILES_MLX5=${CFILES:M*/dev/mlx5/*}
+
 kernel-depend: .depend
 # The argument list can be very long, so use make -V and xargs to
 # pass it to mkdep.
@@ -220,12 +231,20 @@ DEPENDFILES_OBJS=	${DEPENDOBJS:O:u:C/^/.depend./}
 .depend: .PRECIOUS ${SRCS}
 .if ${MK_FAST_DEPEND} == "no"
 	rm -f ${.TARGET}.tmp
-	${MAKE} -V CFILES_NOCDDL -V SYSTEM_CFILES -V GEN_CFILES | \
+# C files
+	${MAKE} -V CFILES_NORMAL -V SYSTEM_CFILES -V GEN_CFILES | \
 	    CC="${_MKDEPCC}" xargs mkdep -a -f ${.TARGET}.tmp ${CFLAGS}
 	${MAKE} -V CFILES_CDDL | \
 	    CC="${_MKDEPCC}" xargs mkdep -a -f ${.TARGET}.tmp ${ZFS_CFLAGS} \
 	    ${FBT_CFLAGS} ${DTRACE_CFLAGS}
-	${MAKE} -V SFILES_NOCDDL | \
+	${MAKE} -V CFILES_LINUXKPI | \
+	    CC="${_MKDEPCC}" xargs mkdep -a -f ${.TARGET}.tmp \
+		${CFLAGS} ${LINUXKPI_INCLUDES}
+	${MAKE} -V CFILES_OFED -V CFILES_MLX5 | \
+	    CC="${_MKDEPCC}" xargs mkdep -a -f ${.TARGET}.tmp \
+		${CFLAGS} ${OFEDINCLUDES}
+# Assembly files
+	${MAKE} -V SFILES_NORMAL | \
 	    CC="${_MKDEPCC}" xargs mkdep -a -f ${.TARGET}.tmp ${ASM_CFLAGS}
 	${MAKE} -V SFILES_CDDL | \
 	    CC="${_MKDEPCC}" xargs mkdep -a -f ${.TARGET}.tmp ${ZFS_ASM_CFLAGS}

From 79f412ad44fac73a7ef6a1f14cfdf6864ae1bc09 Mon Sep 17 00:00:00 2001
From: skra <skra@FreeBSD.org>
Date: Wed, 27 Jan 2016 14:47:00 +0000
Subject: [PATCH 092/113] Fix my email.

---
 share/misc/committers-src.dot | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/share/misc/committers-src.dot b/share/misc/committers-src.dot
index 1cfe6d50d161..6c240cf61842 100644
--- a/share/misc/committers-src.dot
+++ b/share/misc/committers-src.dot
@@ -288,7 +288,7 @@ sephe [label="Sepherosa Ziehau\nsephe@FreeBSD.org\n2007/03/28"]
 sepotvin [label="Stephane E. Potvin\nsepotvin@FreeBSD.org\n2007/02/15"]
 simon [label="Simon L. Nielsen\nsimon@FreeBSD.org\n2006/03/07"]
 sjg [label="Simon J. Gerraty\nsjg@FreeBSD.org\n2012/10/23"]
-skra [label="Svatopluk Kraus\nslm@FreeBSD.org\n2015/10/28"]
+skra [label="Svatopluk Kraus\nskra@FreeBSD.org\n2015/10/28"]
 slm [label="Stephen McConnell\nslm@FreeBSD.org\n2014/05/07"]
 smh [label="Steven Hartland\nsmh@FreeBSD.org\n2012/11/12"]
 sobomax [label="Maxim Sobolev\nsobomax@FreeBSD.org\n2001/07/25"]

From d2ce3b96899b55779d81ed942b224085cfc6f678 Mon Sep 17 00:00:00 2001
From: dteske <dteske@FreeBSD.org>
Date: Wed, 27 Jan 2016 15:28:23 +0000
Subject: [PATCH 093/113] Fix fatal warn when compiling under GCC 5.2.0

GCC 5.2.0 generates the following [fatal] warning:
dialog_util.c:270:23: error:
zero-length gnu_printf format string [-Werror=format-zero-length]
   sprintf(dargv[n++], "");

Fix malloc argument while here, removing sprintf.

Reported by:	Ruslan Bukin <ruslan.bukin at cl cam ac uk>
---
 lib/libdpv/dialog_util.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/libdpv/dialog_util.c b/lib/libdpv/dialog_util.c
index 267d7a56dfdb..21baf98606fb 100644
--- a/lib/libdpv/dialog_util.c
+++ b/lib/libdpv/dialog_util.c
@@ -265,9 +265,9 @@ dialog_spawn_gauge(char *init_prompt, pid_t *pid)
 		if ((dargv[n] = malloc(8)) == NULL)
 			errx(EXIT_FAILURE, "Out of memory?!");
 		sprintf(dargv[n++], "--title");
-		if ((dargv[n] = malloc(8)) == NULL)
+		if ((dargv[n] = malloc(1)) == NULL)
 			errx(EXIT_FAILURE, "Out of memory?!");
-		sprintf(dargv[n++], "");
+		*dargv[n++] = '\0';
 	}
 	if (backtitle != NULL) {
 		if ((dargv[n] = malloc(12)) == NULL)

From 57291730689d515a8e74c0f0f020c4271a385eb5 Mon Sep 17 00:00:00 2001
From: asomers <asomers@FreeBSD.org>
Date: Wed, 27 Jan 2016 16:13:10 +0000
Subject: [PATCH 094/113] Fix grep_test:recurse with ZFS and TMPFS tmpdirs

contrib/netbsd-tests/usr.bin/grep/t_grep.sh
	Fix grep_test:recurse when /tmp is either zfs or tmpfs. The test was
	relying on an implicit ordering of directory recursion which happens
	to be true when using UFS. grep's specification requires no such
	ordering. The solution is to ignore the order of grep's results.

Reviewed by:	ngie
MFC after:	32 days
Sponsored by:	Spectra Logic Corp
Differential Revision:	https://reviews.freebsd.org/D4925
---
 contrib/netbsd-tests/usr.bin/grep/t_grep.sh | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/contrib/netbsd-tests/usr.bin/grep/t_grep.sh b/contrib/netbsd-tests/usr.bin/grep/t_grep.sh
index 7e530169141b..95f077802df9 100755
--- a/contrib/netbsd-tests/usr.bin/grep/t_grep.sh
+++ b/contrib/netbsd-tests/usr.bin/grep/t_grep.sh
@@ -70,7 +70,15 @@ recurse_body()
 	echo -e "cod\ndover sole\nhaddock\nhalibut\npilchard" > recurse/d/fish
 	echo -e "cod\nhaddock\nplaice" > recurse/a/f/favourite-fish
 
+	# Begin FreeBSD
+	if true; then
+		atf_check -o file:"$(atf_get_srcdir)/d_recurse.out" -x "grep -r haddock recurse | sort"
+	else
+	# End FreeBSD
 	atf_check -o file:"$(atf_get_srcdir)/d_recurse.out" grep -r haddock recurse
+	# Begin FreeBSD
+	fi
+	# End FreeBSD
 }
 
 atf_test_case recurse_symlink

From 3eabf52b202db2d07e5e22ed3035b455eacf29ae Mon Sep 17 00:00:00 2001
From: asomers <asomers@FreeBSD.org>
Date: Wed, 27 Jan 2016 16:17:15 +0000
Subject: [PATCH 095/113] syslogd: Enable repeated line compression for lines
 of any length.

Enable repeated line compression for lines of any length, instead of only
short lines. AFAICT repeated line compression was limited to short lines as
a RAM optimization, which made sense when karels added it in 1988, but no
longer.  The penalty is a paltry 904B of RAM per file logged.

Reviewed by:	rpaulo
MFC after:	32 days
Sponsored by:	Spectra Logic Corp
Differential Revision:	https://reviews.freebsd.org/D4475
---
 usr.sbin/syslogd/syslogd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/usr.sbin/syslogd/syslogd.c b/usr.sbin/syslogd/syslogd.c
index cd0f1b64ccf4..df01676dd079 100644
--- a/usr.sbin/syslogd/syslogd.c
+++ b/usr.sbin/syslogd/syslogd.c
@@ -69,7 +69,7 @@ __FBSDID("$FreeBSD$");
  */
 
 #define	MAXLINE		1024		/* maximum line length */
-#define	MAXSVLINE	120		/* maximum saved line length */
+#define	MAXSVLINE	MAXLINE		/* maximum saved line length */
 #define	DEFUPRI		(LOG_USER|LOG_NOTICE)
 #define	DEFSPRI		(LOG_KERN|LOG_CRIT)
 #define	TIMERINTVL	30		/* interval for checking flush, mark */

From fcd747ffb0fe692e5ec1668020a51cd34d3897f9 Mon Sep 17 00:00:00 2001
From: imp <imp@FreeBSD.org>
Date: Wed, 27 Jan 2016 16:36:18 +0000
Subject: [PATCH 096/113] Fix mistake when transitioning to the new defines
 with ZFS loader. I hate adding yet another define, but it is the lessor of
 the evil choices available. Kill another evil by removing PATH_BOOT3 and
 replacing it with PATH_LOADER or PATH_LOADER_ZFS as appropriate.

PR: 206659
---
 sys/boot/common/paths.h          | 2 +-
 sys/boot/i386/boot2/boot2.c      | 2 +-
 sys/boot/i386/gptboot/gptboot.c  | 4 ++--
 sys/boot/i386/zfsboot/zfsboot.c  | 4 ++--
 sys/boot/mips/beri/boot2/boot2.c | 2 +-
 sys/boot/pc98/boot2/boot2.c      | 2 +-
 6 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/sys/boot/common/paths.h b/sys/boot/common/paths.h
index 23f5d2160c6f..9ed45e646a3e 100644
--- a/sys/boot/common/paths.h
+++ b/sys/boot/common/paths.h
@@ -31,9 +31,9 @@
 
 #define PATH_DOTCONFIG	"/boot.config"
 #define PATH_CONFIG	"/boot/config"
-#define PATH_BOOT3	"/boot/loader"
 #define PATH_LOADER	"/boot/loader"
 #define PATH_LOADER_EFI	"/boot/loader.efi"
+#define PATH_LOADER_ZFS	"/boot/zfsloader"
 #define PATH_KERNEL	"/boot/kernel/kernel"
 
 #endif /* _PATHS_H_ */
diff --git a/sys/boot/i386/boot2/boot2.c b/sys/boot/i386/boot2/boot2.c
index 68d5de5198fd..3d8c4074a147 100644
--- a/sys/boot/i386/boot2/boot2.c
+++ b/sys/boot/i386/boot2/boot2.c
@@ -235,7 +235,7 @@ main(void)
      */
 
     if (!kname) {
-	kname = PATH_BOOT3;
+	kname = PATH_LOADER;
 	if (autoboot && !keyhit(3*SECOND)) {
 	    load();
 	    kname = PATH_KERNEL;
diff --git a/sys/boot/i386/gptboot/gptboot.c b/sys/boot/i386/gptboot/gptboot.c
index 96495d25ccbf..a1f46ebcc3d0 100644
--- a/sys/boot/i386/gptboot/gptboot.c
+++ b/sys/boot/i386/gptboot/gptboot.c
@@ -178,7 +178,7 @@ main(void)
 
 		if (autoboot && keyhit(3)) {
 			if (*kname == '\0')
-				memcpy(kname, PATH_BOOT3, sizeof(PATH_BOOT3));
+				memcpy(kname, PATH_LOADER, sizeof(PATH_LOADER));
 			break;
 		}
 		autoboot = 0;
@@ -190,7 +190,7 @@ main(void)
 		 */
 		if (*kname != '\0')
 			load();
-		memcpy(kname, PATH_BOOT3, sizeof(PATH_BOOT3));
+		memcpy(kname, PATH_LOADER, sizeof(PATH_LOADER));
 		load();
 		memcpy(kname, PATH_KERNEL, sizeof(PATH_KERNEL));
 		load();
diff --git a/sys/boot/i386/zfsboot/zfsboot.c b/sys/boot/i386/zfsboot/zfsboot.c
index 51c9af15625c..6fbbc6f38174 100644
--- a/sys/boot/i386/zfsboot/zfsboot.c
+++ b/sys/boot/i386/zfsboot/zfsboot.c
@@ -546,12 +546,12 @@ main(void)
     }
 
     /*
-     * Try to exec stage 3 boot loader. If interrupted by a keypress,
+     * Try to exec /boot/loader. If interrupted by a keypress,
      * or in case of failure, try to load a kernel directly instead.
      */
 
     if (autoboot && !*kname) {
-	memcpy(kname, PATH_BOOT3, sizeof(PATH_BOOT3));
+	memcpy(kname, PATH_LOADER_ZFS, sizeof(PATH_LOADER_ZFS));
 	if (!keyhit(3)) {
 	    load();
 	    memcpy(kname, PATH_KERNEL, sizeof(PATH_KERNEL));
diff --git a/sys/boot/mips/beri/boot2/boot2.c b/sys/boot/mips/beri/boot2/boot2.c
index 2a0fd816a625..2f02c8264c41 100644
--- a/sys/boot/mips/beri/boot2/boot2.c
+++ b/sys/boot/mips/beri/boot2/boot2.c
@@ -248,7 +248,7 @@ main(u_int argc, const char *argv[], const char *envv[], uint64_t memsize)
      */
 
     if (!kname) {
-	kname = PATH_BOOT3;
+	kname = PATH_LOADER;
 	if (autoboot && !keyhit(3*SECOND)) {
 	    boot_fromfs();
 	    kname = PATH_KERNEL;
diff --git a/sys/boot/pc98/boot2/boot2.c b/sys/boot/pc98/boot2/boot2.c
index a9bf47594664..b5825168d84e 100644
--- a/sys/boot/pc98/boot2/boot2.c
+++ b/sys/boot/pc98/boot2/boot2.c
@@ -374,7 +374,7 @@ main(void)
      */
 
     if (!kname) {
-	kname = PATH_BOOT3;
+	kname = PATH_LOADER;
 	if (autoboot && !keyhit(3*SECOND)) {
 	    load();
 	    kname = PATH_KERNEL;

From e7702ce3dffefab878927f99d7bc663b9869846c Mon Sep 17 00:00:00 2001
From: allanjude <allanjude@FreeBSD.org>
Date: Wed, 27 Jan 2016 16:45:23 +0000
Subject: [PATCH 097/113] ficl on i386 should cast to unsigned char output to
 support efi i386

make it possible for efi_console to recognize and translate box characters
on i386 build (unsigned versus signed char passed as int issue).

Submitted by:	Toomas Soome <tsoome at me.com>
Reviewed by:	emaste, smh, dteske
MFC after:	3 days
Differential Revision:	https://reviews.freebsd.org/D4993
---
 sys/boot/ficl/i386/sysdep.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sys/boot/ficl/i386/sysdep.c b/sys/boot/ficl/i386/sysdep.c
index 39c853b4ec6f..df0891ddd5d0 100644
--- a/sys/boot/ficl/i386/sysdep.c
+++ b/sys/boot/ficl/i386/sysdep.c
@@ -58,7 +58,7 @@ void  ficlTextOut(FICL_VM *pVM, char *msg, int fNewline)
     IGNORE(pVM);
 
     while(*msg != 0)
-	putchar(*(msg++));
+	putchar((unsigned char)*(msg++));
     if (fNewline)
 	putchar('\n');
 

From 9893ec50e04c048e43ed5fe6017bfdfdea2cbdfe Mon Sep 17 00:00:00 2001
From: andrew <andrew@FreeBSD.org>
Date: Wed, 27 Jan 2016 17:33:31 +0000
Subject: [PATCH 098/113] When finding the physical address of a device allow
 intermediate addresses to be 64-bit on 32-bit architectures. It is not
 uncommon for device trees to use the upper 32-bits to store what effectively
 is an index into the parent ranges property. In this case, when running with
 a 32-bit bus_addr_t and bus_size_t, we would previously truncate the address,
 this may then incorrectly match the wrong range, and return the wrong
 address.

Tested by:	bz (earlier version)
---
 sys/dev/ofw/ofw_subr.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/sys/dev/ofw/ofw_subr.c b/sys/dev/ofw/ofw_subr.c
index e046406557b9..68ba18ee24a7 100644
--- a/sys/dev/ofw/ofw_subr.c
+++ b/sys/dev/ofw/ofw_subr.c
@@ -75,8 +75,8 @@ ofw_reg_to_paddr(phandle_t dev, int regno, bus_addr_t *paddr,
     bus_size_t *psize, pcell_t *ppci_hi)
 {
 	pcell_t cell[32], pci_hi;
-	bus_addr_t addr, raddr, baddr;
-	bus_size_t size, rsize;
+	uint64_t addr, raddr, baddr;
+	uint64_t size, rsize;
 	uint32_t c, nbridge, naddr, nsize;
 	phandle_t bridge, parent;
 	u_int spc, rspc;
@@ -167,6 +167,11 @@ ofw_reg_to_paddr(phandle_t dev, int regno, bus_addr_t *paddr,
 		get_addr_props(bridge, &naddr, &nsize, &pci);
 	}
 
+	KASSERT(addr <= BUS_SPACE_MAXADDR,
+	    ("Bus sddress is too large: %jx", (intmax_t)addr));
+	KASSERT(size <= BUS_SPACE_MAXSIZE,
+	    ("Bus size is too large: %jx", (intmax_t)addr));
+
 	*paddr = addr;
 	*psize = size;
 	if (ppci_hi != NULL)

From 5d125a19675da01292b0e7923072ecc5ab263f14 Mon Sep 17 00:00:00 2001
From: andrew <andrew@FreeBSD.org>
Date: Wed, 27 Jan 2016 17:47:07 +0000
Subject: [PATCH 099/113] Fix the value we print when the size is too large.
 While here fix the types we cast to to be unsigned as the data is unsigned.

Reviewed by:	ian
---
 sys/dev/ofw/ofw_subr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/sys/dev/ofw/ofw_subr.c b/sys/dev/ofw/ofw_subr.c
index 68ba18ee24a7..c9b99bfb38f0 100644
--- a/sys/dev/ofw/ofw_subr.c
+++ b/sys/dev/ofw/ofw_subr.c
@@ -168,9 +168,9 @@ ofw_reg_to_paddr(phandle_t dev, int regno, bus_addr_t *paddr,
 	}
 
 	KASSERT(addr <= BUS_SPACE_MAXADDR,
-	    ("Bus sddress is too large: %jx", (intmax_t)addr));
+	    ("Bus sddress is too large: %jx", (uintmax_t)addr));
 	KASSERT(size <= BUS_SPACE_MAXSIZE,
-	    ("Bus size is too large: %jx", (intmax_t)addr));
+	    ("Bus size is too large: %jx", (uintmax_t)size));
 
 	*paddr = addr;
 	*psize = size;

From 169dd4da8ec4b82f421e68b485d8db9cc7e8130a Mon Sep 17 00:00:00 2001
From: jhb <jhb@FreeBSD.org>
Date: Wed, 27 Jan 2016 17:55:01 +0000
Subject: [PATCH 100/113] Convert ss_sp in stack_t and sigstack to void *.

POSIX requires these members to be of type void * rather than the
char * inherited from 4BSD.  NetBSD and OpenBSD both changed their
fields to void * back in 1998.  No new build failures were reported
via an exp-run.

PR:		206503 (exp-run)
Reviewed by:	kib
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D5092
---
 sys/amd64/amd64/machdep.c          | 2 +-
 sys/amd64/ia32/ia32_signal.c       | 6 +++---
 sys/amd64/linux/linux_sysvec.c     | 2 +-
 sys/amd64/linux32/linux32_sysvec.c | 4 ++--
 sys/arm/arm/machdep.c              | 2 +-
 sys/arm64/arm64/machdep.c          | 2 +-
 sys/arm64/arm64/vm_machdep.c       | 2 +-
 sys/i386/i386/machdep.c            | 6 +++---
 sys/i386/linux/linux_sysvec.c      | 4 ++--
 sys/i386/svr4/svr4_machdep.c       | 2 +-
 sys/mips/mips/freebsd32_machdep.c  | 2 +-
 sys/mips/mips/pm_machdep.c         | 2 +-
 sys/mips/mips/vm_machdep.c         | 2 +-
 sys/powerpc/powerpc/exec_machdep.c | 2 +-
 sys/sparc64/sparc64/machdep.c      | 2 +-
 sys/sys/signal.h                   | 5 ++---
 16 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/sys/amd64/amd64/machdep.c b/sys/amd64/amd64/machdep.c
index 1bf735fd3eaa..c07d09cd1e8d 100644
--- a/sys/amd64/amd64/machdep.c
+++ b/sys/amd64/amd64/machdep.c
@@ -389,7 +389,7 @@ sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size;
+		sp = (char *)td->td_sigstk.ss_sp + td->td_sigstk.ss_size;
 #if defined(COMPAT_43)
 		td->td_sigstk.ss_flags |= SS_ONSTACK;
 #endif
diff --git a/sys/amd64/ia32/ia32_signal.c b/sys/amd64/ia32/ia32_signal.c
index 983101319731..4947f01dacb0 100644
--- a/sys/amd64/ia32/ia32_signal.c
+++ b/sys/amd64/ia32/ia32_signal.c
@@ -354,7 +354,7 @@ ia32_osendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		fp = (struct ia32_sigframe3 *)(td->td_sigstk.ss_sp +
+		fp = (struct ia32_sigframe3 *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(sf));
 		td->td_sigstk.ss_flags |= SS_ONSTACK;
 	} else
@@ -488,7 +488,7 @@ freebsd4_ia32_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		sfp = (struct ia32_sigframe4 *)(td->td_sigstk.ss_sp +
+		sfp = (struct ia32_sigframe4 *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(sf));
 	} else
 		sfp = (struct ia32_sigframe4 *)regs->tf_rsp - 1;
@@ -622,7 +622,7 @@ ia32_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig))
-		sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size;
+		sp = (char *)td->td_sigstk.ss_sp + td->td_sigstk.ss_size;
 	else
 		sp = (char *)regs->tf_rsp;
 	if (xfpusave != NULL) {
diff --git a/sys/amd64/linux/linux_sysvec.c b/sys/amd64/linux/linux_sysvec.c
index 0bdcba09ad71..6089a9097eae 100644
--- a/sys/amd64/linux/linux_sysvec.c
+++ b/sys/amd64/linux/linux_sysvec.c
@@ -630,7 +630,7 @@ linux_rt_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size -
+		sp = (caddr_t)td->td_sigstk.ss_sp + td->td_sigstk.ss_size -
 		    sizeof(struct l_rt_sigframe);
 	} else
 		sp = (caddr_t)regs->tf_rsp - sizeof(struct l_rt_sigframe) - 128;
diff --git a/sys/amd64/linux32/linux32_sysvec.c b/sys/amd64/linux32/linux32_sysvec.c
index f89b8fae3e11..673ea4f5bcd4 100644
--- a/sys/amd64/linux32/linux32_sysvec.c
+++ b/sys/amd64/linux32/linux32_sysvec.c
@@ -315,7 +315,7 @@ linux_rt_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	 */
 	if ((td->td_pflags & TDP_ALTSTACK) && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		fp = (struct l_rt_sigframe *)(td->td_sigstk.ss_sp +
+		fp = (struct l_rt_sigframe *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(struct l_rt_sigframe));
 	} else
 		fp = (struct l_rt_sigframe *)regs->tf_rsp - 1;
@@ -460,7 +460,7 @@ linux_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	 */
 	if ((td->td_pflags & TDP_ALTSTACK) && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		fp = (struct l_sigframe *)(td->td_sigstk.ss_sp +
+		fp = (struct l_sigframe *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(struct l_sigframe));
 	} else
 		fp = (struct l_sigframe *)regs->tf_rsp - 1;
diff --git a/sys/arm/arm/machdep.c b/sys/arm/arm/machdep.c
index d1f8592d67df..d2811a6dc071 100644
--- a/sys/arm/arm/machdep.c
+++ b/sys/arm/arm/machdep.c
@@ -296,7 +296,7 @@ sendsig(catcher, ksi, mask)
 	/* Allocate and validate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !(onstack) &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		fp = (struct sigframe *)(td->td_sigstk.ss_sp +
+		fp = (struct sigframe *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size);
 #if defined(COMPAT_43)
 		td->td_sigstk.ss_flags |= SS_ONSTACK;
diff --git a/sys/arm64/arm64/machdep.c b/sys/arm64/arm64/machdep.c
index 0e61817bc98e..409ecd316b27 100644
--- a/sys/arm64/arm64/machdep.c
+++ b/sys/arm64/arm64/machdep.c
@@ -527,7 +527,7 @@ sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate and validate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !onstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		fp = (struct sigframe *)(td->td_sigstk.ss_sp +
+		fp = (struct sigframe *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size);
 #if defined(COMPAT_43)
 		td->td_sigstk.ss_flags |= SS_ONSTACK;
diff --git a/sys/arm64/arm64/vm_machdep.c b/sys/arm64/arm64/vm_machdep.c
index edcdeca1f742..6794b1b411e2 100644
--- a/sys/arm64/arm64/vm_machdep.c
+++ b/sys/arm64/arm64/vm_machdep.c
@@ -186,7 +186,7 @@ cpu_set_upcall_kse(struct thread *td, void (*entry)(void *), void *arg,
 {
 	struct trapframe *tf = td->td_frame;
 
-	tf->tf_sp = STACKALIGN(stack->ss_sp + stack->ss_size);
+	tf->tf_sp = STACKALIGN((uintptr_t)stack->ss_sp + stack->ss_size);
 	tf->tf_elr = (register_t)entry;
 	tf->tf_x[0] = (register_t)arg;
 }
diff --git a/sys/i386/i386/machdep.c b/sys/i386/i386/machdep.c
index 67f6ee0b3636..15bc75c2d7b7 100644
--- a/sys/i386/i386/machdep.c
+++ b/sys/i386/i386/machdep.c
@@ -368,7 +368,7 @@ osendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		fp = (struct osigframe *)(td->td_sigstk.ss_sp +
+		fp = (struct osigframe *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(struct osigframe));
 #if defined(COMPAT_43)
 		td->td_sigstk.ss_flags |= SS_ONSTACK;
@@ -515,7 +515,7 @@ freebsd4_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		sfp = (struct sigframe4 *)(td->td_sigstk.ss_sp +
+		sfp = (struct sigframe4 *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(struct sigframe4));
 #if defined(COMPAT_43)
 		td->td_sigstk.ss_flags |= SS_ONSTACK;
@@ -675,7 +675,7 @@ sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		sp = td->td_sigstk.ss_sp + td->td_sigstk.ss_size;
+		sp = (char *)td->td_sigstk.ss_sp + td->td_sigstk.ss_size;
 #if defined(COMPAT_43)
 		td->td_sigstk.ss_flags |= SS_ONSTACK;
 #endif
diff --git a/sys/i386/linux/linux_sysvec.c b/sys/i386/linux/linux_sysvec.c
index c4a5ee59276b..211ec13cc070 100644
--- a/sys/i386/linux/linux_sysvec.c
+++ b/sys/i386/linux/linux_sysvec.c
@@ -451,7 +451,7 @@ linux_rt_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	 */
 	if ((td->td_pflags & TDP_ALTSTACK) && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		fp = (struct l_rt_sigframe *)(td->td_sigstk.ss_sp +
+		fp = (struct l_rt_sigframe *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(struct l_rt_sigframe));
 	} else
 		fp = (struct l_rt_sigframe *)regs->tf_esp - 1;
@@ -591,7 +591,7 @@ linux_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	 */
 	if ((td->td_pflags & TDP_ALTSTACK) && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		fp = (struct l_sigframe *)(td->td_sigstk.ss_sp +
+		fp = (struct l_sigframe *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(struct l_sigframe));
 	} else
 		fp = (struct l_sigframe *)regs->tf_esp - 1;
diff --git a/sys/i386/svr4/svr4_machdep.c b/sys/i386/svr4/svr4_machdep.c
index 5747b92686ac..ddc2594326e2 100644
--- a/sys/i386/svr4/svr4_machdep.c
+++ b/sys/i386/svr4/svr4_machdep.c
@@ -441,7 +441,7 @@ svr4_sendsig(catcher, ksi, mask)
 	 */
 	if ((td->td_pflags & TDP_ALTSTACK) && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		fp = (struct svr4_sigframe *)(td->td_sigstk.ss_sp +
+		fp = (struct svr4_sigframe *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(struct svr4_sigframe));
 		td->td_sigstk.ss_flags |= SS_ONSTACK;
 	} else {
diff --git a/sys/mips/mips/freebsd32_machdep.c b/sys/mips/mips/freebsd32_machdep.c
index f4ace04d7e9a..4ed58e219a04 100644
--- a/sys/mips/mips/freebsd32_machdep.c
+++ b/sys/mips/mips/freebsd32_machdep.c
@@ -410,7 +410,7 @@ freebsd32_sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate and validate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		sfp = (struct sigframe32 *)((vm_offset_t)(td->td_sigstk.ss_sp +
+		sfp = (struct sigframe32 *)(((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(struct sigframe32))
 		    & ~(sizeof(__int64_t) - 1));
 	} else
diff --git a/sys/mips/mips/pm_machdep.c b/sys/mips/mips/pm_machdep.c
index 9bccaec5207e..2b02ba9571a4 100644
--- a/sys/mips/mips/pm_machdep.c
+++ b/sys/mips/mips/pm_machdep.c
@@ -126,7 +126,7 @@ sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate and validate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		sfp = (struct sigframe *)((vm_offset_t)(td->td_sigstk.ss_sp +
+		sfp = (struct sigframe *)(((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(struct sigframe))
 		    & ~(sizeof(__int64_t) - 1));
 	} else
diff --git a/sys/mips/mips/vm_machdep.c b/sys/mips/mips/vm_machdep.c
index 42f3f687ba7f..f952eccbe777 100644
--- a/sys/mips/mips/vm_machdep.c
+++ b/sys/mips/mips/vm_machdep.c
@@ -432,7 +432,7 @@ cpu_set_upcall_kse(struct thread *td, void (*entry)(void *), void *arg,
 	 * in ``See MIPS Run'' by D. Sweetman, p. 269
 	 * align stack
 	 */
-	sp = ((register_t)(intptr_t)(stack->ss_sp + stack->ss_size) & ~0x7) -
+	sp = (((intptr_t)stack->ss_sp + stack->ss_size) & ~0x7) -
 	    CALLFRAME_SIZ;
 
 	/*
diff --git a/sys/powerpc/powerpc/exec_machdep.c b/sys/powerpc/powerpc/exec_machdep.c
index e9eff548a3f3..d657244ffe56 100644
--- a/sys/powerpc/powerpc/exec_machdep.c
+++ b/sys/powerpc/powerpc/exec_machdep.c
@@ -219,7 +219,7 @@ sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	 */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		usfp = (void *)(td->td_sigstk.ss_sp +
+		usfp = (void *)((uintptr_t)td->td_sigstk.ss_sp +
 		   td->td_sigstk.ss_size - rndfsize);
 	} else {
 		usfp = (void *)(tf->fixreg[1] - rndfsize);
diff --git a/sys/sparc64/sparc64/machdep.c b/sys/sparc64/sparc64/machdep.c
index d3cd7a248543..294990339969 100644
--- a/sys/sparc64/sparc64/machdep.c
+++ b/sys/sparc64/sparc64/machdep.c
@@ -646,7 +646,7 @@ sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 	/* Allocate and validate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
-		sfp = (struct sigframe *)(td->td_sigstk.ss_sp +
+		sfp = (struct sigframe *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size - sizeof(struct sigframe));
 	} else
 		sfp = (struct sigframe *)sp - 1;
diff --git a/sys/sys/signal.h b/sys/sys/signal.h
index 81e06a85d93c..259c39aed4f9 100644
--- a/sys/sys/signal.h
+++ b/sys/sys/signal.h
@@ -362,7 +362,7 @@ typedef	struct sigaltstack {
 #else
 typedef	struct {
 #endif
-	char	*ss_sp;			/* signal stack base */
+	void	*ss_sp;			/* signal stack base */
 	__size_t ss_size;		/* signal stack length */
 	int	ss_flags;		/* SS_DISABLE and/or SS_ONSTACK */
 } stack_t;
@@ -406,8 +406,7 @@ struct osigcontext {
  * Structure used in sigstack call.
  */
 struct sigstack {
-	/* XXX ss_sp's type should be `void *'. */
-	char	*ss_sp;			/* signal stack pointer */
+	void	*ss_sp;			/* signal stack pointer */
 	int	ss_onstack;		/* current status */
 };
 #endif

From 0769763b2b58f3394d217653110064346deb8c20 Mon Sep 17 00:00:00 2001
From: glebius <glebius@FreeBSD.org>
Date: Wed, 27 Jan 2016 17:59:39 +0000
Subject: [PATCH 101/113] Rename netinet/tcp_cc.h to netinet/cc/cc.h.

Discussed with:	lstewart
---
 share/man/man9/mod_cc.9           | 2 +-
 sys/netinet/cc/cc.c               | 2 +-
 sys/netinet/{tcp_cc.h => cc/cc.h} | 6 +++---
 sys/netinet/cc/cc_cdg.c           | 2 +-
 sys/netinet/cc/cc_chd.c           | 2 +-
 sys/netinet/cc/cc_cubic.c         | 2 +-
 sys/netinet/cc/cc_dctcp.c         | 2 +-
 sys/netinet/cc/cc_hd.c            | 2 +-
 sys/netinet/cc/cc_htcp.c          | 2 +-
 sys/netinet/cc/cc_newreno.c       | 2 +-
 sys/netinet/cc/cc_vegas.c         | 2 +-
 sys/netinet/tcp_input.c           | 2 +-
 sys/netinet/tcp_output.c          | 2 +-
 sys/netinet/tcp_stacks/fastpath.c | 2 +-
 sys/netinet/tcp_subr.c            | 2 +-
 sys/netinet/tcp_timer.c           | 2 +-
 sys/netinet/tcp_usrreq.c          | 2 +-
 17 files changed, 19 insertions(+), 19 deletions(-)
 rename sys/netinet/{tcp_cc.h => cc/cc.h} (98%)

diff --git a/share/man/man9/mod_cc.9 b/share/man/man9/mod_cc.9
index 05205ed84551..7e9ab2488437 100644
--- a/share/man/man9/mod_cc.9
+++ b/share/man/man9/mod_cc.9
@@ -41,7 +41,7 @@
 .Nd Modular Congestion Control
 .Sh SYNOPSIS
 .In netinet/tcp.h
-.In netinet/tcp_cc.h
+.In netinet/cc/cc.h
 .In netinet/cc/cc_module.h
 .Fn DECLARE_CC_MODULE "ccname" "ccalgo"
 .Fn CCV "ccv" "what"
diff --git a/sys/netinet/cc/cc.c b/sys/netinet/cc/cc.c
index 718bfb4009e7..da44f36aff87 100644
--- a/sys/netinet/cc/cc.c
+++ b/sys/netinet/cc/cc.c
@@ -69,7 +69,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/in_pcb.h>
 #include <netinet/tcp.h>
 #include <netinet/tcp_var.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 
 #include <netinet/cc/cc_module.h>
 
diff --git a/sys/netinet/tcp_cc.h b/sys/netinet/cc/cc.h
similarity index 98%
rename from sys/netinet/tcp_cc.h
rename to sys/netinet/cc/cc.h
index d90cd1945582..1da6f62079e4 100644
--- a/sys/netinet/tcp_cc.h
+++ b/sys/netinet/cc/cc.h
@@ -48,8 +48,8 @@
  *   http://caia.swin.edu.au/urp/newtcp/
  */
 
-#ifndef _NETINET_TCP_CC_H_
-#define _NETINET_TCP_CC_H_
+#ifndef _NETINET_CC_CC_H_
+#define _NETINET_CC_CC_H_
 
 #if !defined(_KERNEL)
 #error "no user-servicable parts inside"
@@ -175,4 +175,4 @@ extern struct rwlock cc_list_lock;
 #define	CC_LIST_WUNLOCK()	rw_wunlock(&cc_list_lock)
 #define	CC_LIST_LOCK_ASSERT()	rw_assert(&cc_list_lock, RA_LOCKED)
 
-#endif /* _NETINET_TCP_CC_H_ */
+#endif /* _NETINET_CC_CC_H_ */
diff --git a/sys/netinet/cc/cc_cdg.c b/sys/netinet/cc/cc_cdg.c
index ec4e73c8c304..09336e777560 100644
--- a/sys/netinet/cc/cc_cdg.c
+++ b/sys/netinet/cc/cc_cdg.c
@@ -69,7 +69,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp_seq.h>
 #include <netinet/tcp_timer.h>
 #include <netinet/tcp_var.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #include <netinet/cc/cc_module.h>
 
 #include <netinet/khelp/h_ertt.h>
diff --git a/sys/netinet/cc/cc_chd.c b/sys/netinet/cc/cc_chd.c
index 67cf5f369352..d7b53fec4d6a 100644
--- a/sys/netinet/cc/cc_chd.c
+++ b/sys/netinet/cc/cc_chd.c
@@ -71,7 +71,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp_seq.h>
 #include <netinet/tcp_timer.h>
 #include <netinet/tcp_var.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #include <netinet/cc/cc_module.h>
 
 #include <netinet/khelp/h_ertt.h>
diff --git a/sys/netinet/cc/cc_cubic.c b/sys/netinet/cc/cc_cubic.c
index 5e9404a7d7cd..9fdb99ea74bc 100644
--- a/sys/netinet/cc/cc_cubic.c
+++ b/sys/netinet/cc/cc_cubic.c
@@ -63,7 +63,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp_seq.h>
 #include <netinet/tcp_timer.h>
 #include <netinet/tcp_var.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #include <netinet/cc/cc_cubic.h>
 #include <netinet/cc/cc_module.h>
 
diff --git a/sys/netinet/cc/cc_dctcp.c b/sys/netinet/cc/cc_dctcp.c
index 63e4250f4748..fd36d1ce6694 100644
--- a/sys/netinet/cc/cc_dctcp.c
+++ b/sys/netinet/cc/cc_dctcp.c
@@ -53,7 +53,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp.h>
 #include <netinet/tcp_seq.h>
 #include <netinet/tcp_var.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #include <netinet/cc/cc_module.h>
 
 #define	CAST_PTR_INT(X)	(*((int*)(X)))
diff --git a/sys/netinet/cc/cc_hd.c b/sys/netinet/cc/cc_hd.c
index a9d6f872d34c..591142ce75f2 100644
--- a/sys/netinet/cc/cc_hd.c
+++ b/sys/netinet/cc/cc_hd.c
@@ -72,7 +72,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp_seq.h>
 #include <netinet/tcp_timer.h>
 #include <netinet/tcp_var.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #include <netinet/cc/cc_module.h>
 
 #include <netinet/khelp/h_ertt.h>
diff --git a/sys/netinet/cc/cc_htcp.c b/sys/netinet/cc/cc_htcp.c
index e5d1c9bb2fbc..97012f5e5d06 100644
--- a/sys/netinet/cc/cc_htcp.c
+++ b/sys/netinet/cc/cc_htcp.c
@@ -66,7 +66,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp_seq.h>
 #include <netinet/tcp_timer.h>
 #include <netinet/tcp_var.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #include <netinet/cc/cc_module.h>
 
 /* Fixed point math shifts. */
diff --git a/sys/netinet/cc/cc_newreno.c b/sys/netinet/cc/cc_newreno.c
index e887d0db9a1b..97ec35f44e10 100644
--- a/sys/netinet/cc/cc_newreno.c
+++ b/sys/netinet/cc/cc_newreno.c
@@ -65,7 +65,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp.h>
 #include <netinet/tcp_seq.h>
 #include <netinet/tcp_var.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #include <netinet/cc/cc_module.h>
 
 static void	newreno_ack_received(struct cc_var *ccv, uint16_t type);
diff --git a/sys/netinet/cc/cc_vegas.c b/sys/netinet/cc/cc_vegas.c
index db894ab047b0..b3eea5967078 100644
--- a/sys/netinet/cc/cc_vegas.c
+++ b/sys/netinet/cc/cc_vegas.c
@@ -72,7 +72,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp.h>
 #include <netinet/tcp_timer.h>
 #include <netinet/tcp_var.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #include <netinet/cc/cc_module.h>
 
 #include <netinet/khelp/h_ertt.h>
diff --git a/sys/netinet/tcp_input.c b/sys/netinet/tcp_input.c
index 7b2193e5aad3..102430dfe3c2 100644
--- a/sys/netinet/tcp_input.c
+++ b/sys/netinet/tcp_input.c
@@ -107,7 +107,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp_var.h>
 #include <netinet6/tcp6_var.h>
 #include <netinet/tcpip.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #ifdef TCPPCAP
 #include <netinet/tcp_pcap.h>
 #endif
diff --git a/sys/netinet/tcp_output.c b/sys/netinet/tcp_output.c
index cdfed3663bff..f810ee65f97c 100644
--- a/sys/netinet/tcp_output.c
+++ b/sys/netinet/tcp_output.c
@@ -77,7 +77,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp_timer.h>
 #include <netinet/tcp_var.h>
 #include <netinet/tcpip.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #ifdef TCPPCAP
 #include <netinet/tcp_pcap.h>
 #endif
diff --git a/sys/netinet/tcp_stacks/fastpath.c b/sys/netinet/tcp_stacks/fastpath.c
index c3664df25a94..6af9212b22cd 100644
--- a/sys/netinet/tcp_stacks/fastpath.c
+++ b/sys/netinet/tcp_stacks/fastpath.c
@@ -107,7 +107,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet6/tcp6_var.h>
 #include <netinet/tcpip.h>
 #include <netinet/tcp_syncache.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #ifdef TCPDEBUG
 #include <netinet/tcp_debug.h>
 #endif /* TCPDEBUG */
diff --git a/sys/netinet/tcp_subr.c b/sys/netinet/tcp_subr.c
index 0d16330bee84..e6fdb7df6b6c 100644
--- a/sys/netinet/tcp_subr.c
+++ b/sys/netinet/tcp_subr.c
@@ -95,7 +95,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp_timer.h>
 #include <netinet/tcp_var.h>
 #include <netinet/tcp_syncache.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #ifdef INET6
 #include <netinet6/tcp6_var.h>
 #endif
diff --git a/sys/netinet/tcp_timer.c b/sys/netinet/tcp_timer.c
index 303f9a20270e..046febade670 100644
--- a/sys/netinet/tcp_timer.c
+++ b/sys/netinet/tcp_timer.c
@@ -68,7 +68,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp_fsm.h>
 #include <netinet/tcp_timer.h>
 #include <netinet/tcp_var.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #ifdef INET6
 #include <netinet6/tcp6_var.h>
 #endif
diff --git a/sys/netinet/tcp_usrreq.c b/sys/netinet/tcp_usrreq.c
index 204db3963193..94dd74e498ce 100644
--- a/sys/netinet/tcp_usrreq.c
+++ b/sys/netinet/tcp_usrreq.c
@@ -90,7 +90,7 @@ __FBSDID("$FreeBSD$");
 #include <netinet/tcp_timer.h>
 #include <netinet/tcp_var.h>
 #include <netinet/tcpip.h>
-#include <netinet/tcp_cc.h>
+#include <netinet/cc/cc.h>
 #ifdef TCPPCAP
 #include <netinet/tcp_pcap.h>
 #endif

From 57a7c410cb9612a0ba15636e037b5ee56c1a0efa Mon Sep 17 00:00:00 2001
From: trasz <trasz@FreeBSD.org>
Date: Wed, 27 Jan 2016 18:12:42 +0000
Subject: [PATCH 102/113] Improve reporting of connection problems in
 iscsid(8).

Obtained from:	Mellanox Technologies
MFC after:	1 month
Sponsored by:	The FreeBSD Foundation
---
 usr.sbin/iscsid/pdu.c | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/usr.sbin/iscsid/pdu.c b/usr.sbin/iscsid/pdu.c
index 4672ecd21516..78aa065acef1 100644
--- a/usr.sbin/iscsid/pdu.c
+++ b/usr.sbin/iscsid/pdu.c
@@ -34,7 +34,9 @@ __FBSDID("$FreeBSD$");
 #include <sys/types.h>
 #include <sys/uio.h>
 #include <assert.h>
+#include <errno.h>
 #include <stdlib.h>
+#include <string.h>
 #include <unistd.h>
 
 #include "iscsid.h"
@@ -177,18 +179,23 @@ pdu_padding(const struct pdu *pdu)
 }
 
 static void
-pdu_read(int fd, char *data, size_t len)
+pdu_read(const struct connection *conn, char *data, size_t len)
 {
 	ssize_t ret;
 
 	while (len > 0) {
-		ret = read(fd, data, len);
+		ret = read(conn->conn_socket, data, len);
 		if (ret < 0) {
-			if (timed_out())
+			if (timed_out()) {
+				fail(conn, "Login Phase timeout");
 				log_errx(1, "exiting due to timeout");
+			}
+			fail(conn, strerror(errno));
 			log_err(1, "read");
-		} else if (ret == 0)
+		} else if (ret == 0) {
+			fail(conn, "connection lost");
 			log_errx(1, "read: connection lost");
+		}
 		len -= ret;
 		data += ret;
 	}
@@ -207,7 +214,7 @@ pdu_receive(struct pdu *pdu)
 
 	assert(pdu->pdu_connection->conn_conf.isc_iser == 0);
 
-	pdu_read(pdu->pdu_connection->conn_socket,
+	pdu_read(pdu->pdu_connection,
 	    (char *)pdu->pdu_bhs, sizeof(*pdu->pdu_bhs));
 
 	len = pdu_ahs_length(pdu);
@@ -227,13 +234,13 @@ pdu_receive(struct pdu *pdu)
 		if (pdu->pdu_data == NULL)
 			log_err(1, "malloc");
 
-		pdu_read(pdu->pdu_connection->conn_socket,
+		pdu_read(pdu->pdu_connection,
 		    (char *)pdu->pdu_data, pdu->pdu_data_len);
 
 		padding = pdu_padding(pdu);
 		if (padding != 0) {
 			assert(padding < sizeof(dummy));
-			pdu_read(pdu->pdu_connection->conn_socket,
+			pdu_read(pdu->pdu_connection,
 			    (char *)dummy, padding);
 		}
 	}

From 4019d3df8f10fcc6dc8a7e78356272af60783b5a Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 19:11:11 +0000
Subject: [PATCH 103/113] Drop any previous fd when setting a new one.

Reported by:	mjg
Sponsored by:	EMC / Isilon Storage Division
MFC after:	2 weeks
---
 sys/dev/filemon/filemon.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/sys/dev/filemon/filemon.c b/sys/dev/filemon/filemon.c
index b302de9f6924..4721d0a0c45d 100644
--- a/sys/dev/filemon/filemon.c
+++ b/sys/dev/filemon/filemon.c
@@ -148,6 +148,9 @@ filemon_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flag __unused,
 	switch (cmd) {
 	/* Set the output file descriptor. */
 	case FILEMON_SET_FD:
+		if (filemon->fp != NULL)
+			fdrop(filemon->fp, td);
+
 		error = fget_write(td, *(int *)data,
 #if __FreeBSD_version >= 900041
 		    cap_rights_init(&rights, CAP_PWRITE),

From 0e3463672209718efb883b2e8b3580c7ea014463 Mon Sep 17 00:00:00 2001
From: mjg <mjg@FreeBSD.org>
Date: Wed, 27 Jan 2016 19:55:02 +0000
Subject: [PATCH 104/113] ktrace: tidy up ktrstruct

- minor style fixes
- avoid doing strlen twice [1]

PR:		206648
Submitted by:	C Turt <ecturt gmail.com> (original version) [1]
---
 sys/kern/kern_ktrace.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/sys/kern/kern_ktrace.c b/sys/kern/kern_ktrace.c
index 367610b34a3a..139fd31a9ac0 100644
--- a/sys/kern/kern_ktrace.c
+++ b/sys/kern/kern_ktrace.c
@@ -757,15 +757,16 @@ ktrstruct(name, data, datalen)
 	size_t datalen;
 {
 	struct ktr_request *req;
-	char *buf = NULL;
-	size_t buflen;
+	char *buf;
+	size_t buflen, namelen;
 
-	if (!data)
+	if (data == NULL)
 		datalen = 0;
-	buflen = strlen(name) + 1 + datalen;
+	namelen = strlen(name) + 1;
+	buflen = namelen + datalen;
 	buf = malloc(buflen, M_KTRACE, M_WAITOK);
 	strcpy(buf, name);
-	bcopy(data, buf + strlen(name) + 1, datalen);
+	bcopy(data, buf + namelen, datalen);
 	if ((req = ktr_getrequest(KTR_STRUCT)) == NULL) {
 		free(buf, M_KTRACE);
 		return;

From 259ddf80ecfd4b3c47d6baf7ed8b7f6882dae51d Mon Sep 17 00:00:00 2001
From: kan <kan@FreeBSD.org>
Date: Wed, 27 Jan 2016 20:20:35 +0000
Subject: [PATCH 105/113] Make .debug file for libgcc_s.so.1 more useful.

The files compiled into libgcc_s.so.1 did not have -g on
compiler command line, making generated .debug quite
pointless.
---
 gnu/lib/libgcc/Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gnu/lib/libgcc/Makefile b/gnu/lib/libgcc/Makefile
index cdf62dd3df78..05f796197eb7 100644
--- a/gnu/lib/libgcc/Makefile
+++ b/gnu/lib/libgcc/Makefile
@@ -211,7 +211,7 @@ COMMONHDRS+=	unwind.h
 HIDE =  -fvisibility=hidden -DHIDE_EXPORTS
 CC_T =	${CC} -c ${CFLAGS} ${HIDE} -fPIC
 CC_P =	${CC} -c ${CFLAGS} ${HIDE} -p -fPIC
-CC_S =	${CC} -c ${CFLAGS} ${PICFLAG} -DSHARED
+CC_S =	${CC} -c ${CFLAGS} ${SHARED_CFLAGS} ${PICFLAG} -DSHARED
 
 #-----------------------------------------------------------------------
 #

From 35f6152a71b342af29980776f503f4a20ad239bd Mon Sep 17 00:00:00 2001
From: kan <kan@FreeBSD.org>
Date: Wed, 27 Jan 2016 20:20:37 +0000
Subject: [PATCH 106/113] Do not unlock rtld_phdr_lock over callback
 invocations.

The dl_iterate_phdr consumer code in libgcc does not expect multiple
callbacks running concurrently. This was fixed once already in r178807,
but accidentally got reverted in r294373.
---
 libexec/rtld-elf/rtld.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/libexec/rtld-elf/rtld.c b/libexec/rtld-elf/rtld.c
index 863fe25f619a..912358c0c1d1 100644
--- a/libexec/rtld-elf/rtld.c
+++ b/libexec/rtld-elf/rtld.c
@@ -3533,11 +3533,9 @@ dl_iterate_phdr(__dl_iterate_hdr_callback callback, void *param)
 		TAILQ_INSERT_AFTER(&obj_list, obj, &marker, next);
 		rtld_fill_dl_phdr_info(obj, &phdr_info);
 		lock_release(rtld_bind_lock, &bind_lockstate);
-		lock_release(rtld_phdr_lock, &phdr_lockstate);
 
 		error = callback(&phdr_info, sizeof phdr_info, param);
 
-		wlock_acquire(rtld_phdr_lock, &phdr_lockstate);
 		rlock_acquire(rtld_bind_lock, &bind_lockstate);
 		obj = globallist_next(&marker);
 		TAILQ_REMOVE(&obj_list, &marker, next);
@@ -3551,9 +3549,9 @@ dl_iterate_phdr(__dl_iterate_hdr_callback callback, void *param)
 	if (error == 0) {
 		rtld_fill_dl_phdr_info(&obj_rtld, &phdr_info);
 		lock_release(rtld_bind_lock, &bind_lockstate);
-		lock_release(rtld_phdr_lock, &phdr_lockstate);
 		error = callback(&phdr_info, sizeof(phdr_info), param);
 	}
+	lock_release(rtld_phdr_lock, &phdr_lockstate);
 	return (error);
 }
 

From 1025b8f013128e27850da281f3d9b623514a4e1d Mon Sep 17 00:00:00 2001
From: emaste <emaste@FreeBSD.org>
Date: Wed, 27 Jan 2016 20:23:42 +0000
Subject: [PATCH 107/113] Replace prebuilt uuencoded gallant.fnt with editable
 hex version

---
 share/vt/fonts/gallant.fnt.uu | 192 -----------------------------
 share/vt/fonts/gallant.hex    | 226 ++++++++++++++++++++++++++++++++++
 2 files changed, 226 insertions(+), 192 deletions(-)
 delete mode 100644 share/vt/fonts/gallant.fnt.uu
 create mode 100644 share/vt/fonts/gallant.hex

diff --git a/share/vt/fonts/gallant.fnt.uu b/share/vt/fonts/gallant.fnt.uu
deleted file mode 100644
index 84f30a13b345..000000000000
--- a/share/vt/fonts/gallant.fnt.uu
+++ /dev/null
@@ -1,192 +0,0 @@
-# $FreeBSD$
-begin 644 gallant.fnt
-M5D9.5#`P,#(,%@``````OP````(`````````````````````````````````
-M```````````````````````````````````````````````&``8`!@`&``8`
-M!@`&``8`!@`&``8```````8`!@```````````````````!F`&8`9@!F`&8`9
-M@````````````````````````````````````````````S`#,`,P!F`?\!_P
-M#,`,P!F`&8!_P'_`,P!F`&8````````````````````&`!^`/\!FX&9@9@`^
-M`!^`!\`&8`9@9F!_P#^`!@```````````````````#A@1,!$P$6`.8`#``,`
-M!@`,``P`&<`:(#(@,B!AP```````````````````!P`/@!C`&,`8P`^`'@`^
-M`'<`8V!AX&'`88`_X!Y@```````````````````,`!X`'@`&``8`#``8`!``
-M``````````````````````````````````````#``8`#@`,`!P`&``8`!@`&
-M``8`!P`#``.``8``P```````````````````,``8`!P`#``.``8`!@`&``8`
-M!@`.``P`'``8`#````````````````````````````````\`!@!F8';@&8``
-M`!F`=N!F8`8`#P`````````````````````````````````&``8`!@`&`'_@
-M?^`&``8`!@`&````````````````````````````````````````````````
-M````#``>`!X`!@`&``P`&``0``````````````````````````````!_X'_@
-M```````````````````````````````````````````````````````````,
-M`!X`'@`,`````````````````````&``P`#``8`!@`,``P`&``P`#``8`!@`
-M,``P`&`````````````````````'``^`$8`0P##`,,`PP##`,,`PP##`,(`8
-M@!\`#@````````````````````(`!@`.`!X`-@`&``8`!@`&``8`!@`&``8`
-M!@`_P```````````````````'P`_@&'`0,``P`#``,`!@`,`!@`,`!@`,"!_
-MX'_@```````````````````/@!_`(.!`8`!@`.`'P`_``.``8`!@0&!@0#^`
-M'P````````````````````&``X`#@`6`!8`)@`F`$8`1@"&`/^!_X`&``8`!
-M@```````````````````#\`/P!``$``@`#^`,<``X`!@`&``8$!@8&`PP!^`
-M```````````````````'``P`&``P`#``8`!G@&_`<.!@8&!@8&!P0#^`'P``
-M`````````````````!_@/^!@0`!``,``@`"``8`!``$``P`"``(`!@`$````
-M````````````````#P`1@##`,,`PP!B`#0`&``L`$8`PP##`,,`8@`\`````
-M```````````````/@!'`(.!@8&!@8&!PX#]@'F``8`#``,`!@`<`/```````
-M```````````````````````````,`!X`'@`,```````,`!X`'@`,````````
-M````````````````````````````#``>`!X`#```````#``>`!X`!@`&``P`
-M&``0`````````````````````&`!P`<`'@!X`'@`'@`'``'``&``````````
-M````````````````````````````?\!_P`````!_P'_`````````````````
-M`````````````````````&``.``>``>``>`!X`>`'@`X`&``````````````
-M```````/`!^`.<`@P`#``,`!@`,`!@`,``P```````P`#```````````````
-M``````````````^`/\`P8&!@9R!OH&R@;*!GX&``,``_X`_@````````````
-M```````&``8`"P`+``D`$8`1@!"`/\`@P"!`0&!`8.#P````````````````
-M`````/\`8(!@P&#`8,!A@'^`8,!@8&!@8&!@8&#`_X``````````````````
-M````#\`08"`@(`!@`&``8`!@`&``8``@`#`@&$`/@```````````````````
-M``#_`&'`8,!@8&!@8&!@8&!@8&!@8&!@8$!A@/X`````````````````````
-M`'_`,$`P0#``,``P@#^`,(`P`#``,``P(#`@?^``````````````````````
-M?\`P0#!`,``P`#"`/X`P@#``,``P`#``,`!X```````````````````````/
-MP!!@("`@`&``8`!@`&``8?!@8"!@,&`88`^``````````````````````/#P
-M8&!@8&!@8&!@8'_@8&!@8&!@8&!@8&!@\/``````````````````````'X`&
-M``8`!@`&``8`!@`&``8`!@`&``8`!@`?@``````````````````````?@`8`
-M!@`&``8`!@`&``8`!@`&``8`!@`&``8`!@`&``0`.``P`````````/#@88!C
-M`&8`;`!X`'@`?`!N`&<`8X!AP&#@\'``````````````````````>``P`#``
-M,``P`#``,``P`#``,``P`#`@,"!_X`````````````````````#@<&#@<.!P
-MX'#@66!98%E@36!.8$Y@1&!$8.3P`````````````````````,!P8"!P('@@
-M6"!,($8@1R!#($&@0.!`X$!@X#``````````````````````#P`1P"#`(&!@
-M8&!@8&!@8&!@8&`@0#!`&(`/``````````````````````!_@##`,&`P8#!@
-M,,`W@#``,``P`#``,``P`'@```````````````````````\`$<`@P"!@8&!@
-M8&!@8&!@8&!@,$`X0!^`#@`?`".0`>``````````````_P!A@&#`8,!@P&"`
-M?P!\`&X`9P!C@&'`8.#P<``````````````````````?X#!@8"!@('``/``>
-M``>``<``X$!@0&!@P'^``````````````````````'_@1B`&``8`!@`&``8`
-M!@`&``8`!@`&``8`'X``````````````````````\'!@(&`@8"!@(&`@8"!@
-M(&`@8"!@('!`/\`?@`````````````````````#@X&!`,(`P@#"`&0`9`!D`
-M#``.``X`!``$``0``````````````````````/[P9B!F(&8@=B!W0#-`-T`[
-MP#N`&8`9@!F`&8``````````````````````\'!@(#!`.(`8@`T`!@`&``L`
-M$8`1P"#`0&#@\`````````````````````#P<&`@,$`8@!B`#0`&``8`!@`&
-M``8`!@`&``\``````````````````````#_@(,``P`&``8`#``,`!@`&``P`
-M#``8`!@@/^````````````````````?`!\`&``8`!@`&``8`!@`&``8`!@`&
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From 25f4b65b5a614be2d7ac4328829c58a899bab130 Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 21:12:18 +0000
Subject: [PATCH 108/113] filemon_ioctl: Handle error from
 devfs_get_cdevpriv(9).

MFC after:	2 weeks
Sponsored by:	EMC / Isilon Storage Division
---
 sys/dev/filemon/filemon.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/sys/dev/filemon/filemon.c b/sys/dev/filemon/filemon.c
index 4721d0a0c45d..e16ad08ab836 100644
--- a/sys/dev/filemon/filemon.c
+++ b/sys/dev/filemon/filemon.c
@@ -143,7 +143,8 @@ filemon_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flag __unused,
 	cap_rights_t rights;
 #endif
 
-	devfs_get_cdevpriv((void **) &filemon);
+	if ((error = devfs_get_cdevpriv((void **) &filemon)) != 0)
+		return (error);
 
 	switch (cmd) {
 	/* Set the output file descriptor. */

From 7819d93d8425f7966490bfd633e495dbf057e19c Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 21:14:09 +0000
Subject: [PATCH 109/113] filemon_ioctl: Lock the associated filemon handle
 before writing to it.

Reported by:	mjg
MFC after:	2 weeks
Sponsored by:	EMC / Isilon Storage Division
---
 sys/dev/filemon/filemon.c         | 3 +++
 sys/dev/filemon/filemon_wrapper.c | 7 -------
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/sys/dev/filemon/filemon.c b/sys/dev/filemon/filemon.c
index e16ad08ab836..90cf586e4515 100644
--- a/sys/dev/filemon/filemon.c
+++ b/sys/dev/filemon/filemon.c
@@ -146,6 +146,8 @@ filemon_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flag __unused,
 	if ((error = devfs_get_cdevpriv((void **) &filemon)) != 0)
 		return (error);
 
+	filemon_filemon_lock(filemon);
+
 	switch (cmd) {
 	/* Set the output file descriptor. */
 	case FILEMON_SET_FD:
@@ -177,6 +179,7 @@ filemon_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flag __unused,
 		break;
 	}
 
+	filemon_filemon_unlock(filemon);
 	return (error);
 }
 
diff --git a/sys/dev/filemon/filemon_wrapper.c b/sys/dev/filemon/filemon_wrapper.c
index d107a40892f6..7ba843dcf1ea 100644
--- a/sys/dev/filemon/filemon_wrapper.c
+++ b/sys/dev/filemon/filemon_wrapper.c
@@ -115,21 +115,14 @@ filemon_comment(struct filemon *filemon)
 	int len;
 	struct timeval now;
 
-	/* Load timestamp before locking.  Less accurate but less contention. */
 	getmicrotime(&now);
 
-	/* Lock the found filemon structure. */
-	filemon_filemon_lock(filemon);
-
 	len = snprintf(filemon->msgbufr, sizeof(filemon->msgbufr),
 	    "# filemon version %d\n# Target pid %d\n# Start %ju.%06ju\nV %d\n",
 	    FILEMON_VERSION, curproc->p_pid, (uintmax_t)now.tv_sec,
 	    (uintmax_t)now.tv_usec, FILEMON_VERSION);
 
 	filemon_output(filemon, filemon->msgbufr, len);
-
-	/* Unlock the found filemon structure. */
-	filemon_filemon_unlock(filemon);
 }
 
 static int

From 36b5b4fdf85dc4c5f943d37989db0d537856cdd7 Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 21:17:43 +0000
Subject: [PATCH 110/113] filemon_comment has nothing to do with wrappers so
 move it out of filemon_wrapper.c.

It only prints the header from filemon_ioctl.  Keep the name though to stay
closer to other implementations.

MFC after:	2 weeks
Sponsored by:	EMC / Isilon Storage Division
---
 sys/dev/filemon/filemon.c         | 16 ++++++++++++++++
 sys/dev/filemon/filemon_wrapper.c | 16 ----------------
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/sys/dev/filemon/filemon.c b/sys/dev/filemon/filemon.c
index 90cf586e4515..909e0cfc2c0a 100644
--- a/sys/dev/filemon/filemon.c
+++ b/sys/dev/filemon/filemon.c
@@ -104,6 +104,22 @@ static struct cdev *filemon_dev;
 #include "filemon_lock.c"
 #include "filemon_wrapper.c"
 
+static void
+filemon_comment(struct filemon *filemon)
+{
+	int len;
+	struct timeval now;
+
+	getmicrotime(&now);
+
+	len = snprintf(filemon->msgbufr, sizeof(filemon->msgbufr),
+	    "# filemon version %d\n# Target pid %d\n# Start %ju.%06ju\nV %d\n",
+	    FILEMON_VERSION, curproc->p_pid, (uintmax_t)now.tv_sec,
+	    (uintmax_t)now.tv_usec, FILEMON_VERSION);
+
+	filemon_output(filemon, filemon->msgbufr, len);
+}
+
 static void
 filemon_dtr(void *data)
 {
diff --git a/sys/dev/filemon/filemon_wrapper.c b/sys/dev/filemon/filemon_wrapper.c
index 7ba843dcf1ea..9beb573966bc 100644
--- a/sys/dev/filemon/filemon_wrapper.c
+++ b/sys/dev/filemon/filemon_wrapper.c
@@ -109,22 +109,6 @@ filemon_pid_check(struct proc *p)
 	return (NULL);
 }
 
-static void
-filemon_comment(struct filemon *filemon)
-{
-	int len;
-	struct timeval now;
-
-	getmicrotime(&now);
-
-	len = snprintf(filemon->msgbufr, sizeof(filemon->msgbufr),
-	    "# filemon version %d\n# Target pid %d\n# Start %ju.%06ju\nV %d\n",
-	    FILEMON_VERSION, curproc->p_pid, (uintmax_t)now.tv_sec,
-	    (uintmax_t)now.tv_usec, FILEMON_VERSION);
-
-	filemon_output(filemon, filemon->msgbufr, len);
-}
-
 static int
 filemon_wrapper_chdir(struct thread *td, struct chdir_args *uap)
 {

From 0b10a802f877a41beb1b823c21a6a4b241ed8e28 Mon Sep 17 00:00:00 2001
From: mckusick <mckusick@FreeBSD.org>
Date: Wed, 27 Jan 2016 21:23:01 +0000
Subject: [PATCH 111/113] The bread() function was inconsistent about whether
 it would return a buffer pointer in the event of an error (for some errors it
 would return a buffer pointer and for other errors it would not return a
 buffer pointer). The cluster_read() function was similarly inconsistent.

Clients of these functions were inconsistent in handling errors.
Some would assume that no buffer was returned after an error and
would thus lose buffers under certain error conditions. Others would
assume that brelse() should always be called after an error and
would thus panic the system under certain error conditions.

To correct both of these problems with minimal code churn, bread()
and cluster_write() now always free the buffer when returning an
error thus ensuring that buffers will never be lost. The brelse()
routine checks for being passed a NULL buffer pointer and silently
returns to avoid panics. Thus both approaches to handling error
returns from bread() and cluster_read() will work correctly.

Future code should be written assuming that bread() and cluster_read()
will never return a buffer with an error, so should not attempt to
brelse() the buffer when an error is returned.

Reviewed by: kib
---
 sys/kern/vfs_bio.c      | 12 ++++++++++++
 sys/kern/vfs_cluster.c  | 18 ++++++++++++++----
 sys/ufs/ffs/ffs_inode.c |  4 +---
 3 files changed, 27 insertions(+), 7 deletions(-)

diff --git a/sys/kern/vfs_bio.c b/sys/kern/vfs_bio.c
index 6b8f79f96232..eb392cb1b834 100644
--- a/sys/kern/vfs_bio.c
+++ b/sys/kern/vfs_bio.c
@@ -1809,6 +1809,8 @@ breada(struct vnode * vp, daddr_t * rablkno, int * rabsize,
  * must clear BIO_ERROR and B_INVAL prior to initiating I/O.  If B_CACHE
  * is set, the buffer is valid and we do not have to do anything, see
  * getblk(). Also starts asynchronous I/O on read-ahead blocks.
+ *
+ * Always return a NULL buffer pointer (in bpp) when returning an error.
  */
 int
 breadn_flags(struct vnode *vp, daddr_t blkno, int size, daddr_t *rablkno,
@@ -1844,6 +1846,10 @@ breadn_flags(struct vnode *vp, daddr_t blkno, int size, daddr_t *rablkno,
 
 	if (readwait) {
 		rv = bufwait(bp);
+		if (rv != 0) {
+			brelse(bp);
+			*bpp = NULL;
+		}
 	}
 	return (rv);
 }
@@ -2238,6 +2244,12 @@ brelse(struct buf *bp)
 {
 	int qindex;
 
+	/*
+	 * Many function erroneously call brelse with a NULL bp under rare
+	 * error conditions. Simply return when called with a NULL bp.
+	 */
+	if (bp == NULL)
+		return;
 	CTR3(KTR_BUF, "brelse(%p) vp %p flags %X",
 	    bp, bp->b_vp, bp->b_flags);
 	KASSERT(!(bp->b_flags & (B_CLUSTER|B_PAGING)),
diff --git a/sys/kern/vfs_cluster.c b/sys/kern/vfs_cluster.c
index 476b28a01533..9871a505631d 100644
--- a/sys/kern/vfs_cluster.c
+++ b/sys/kern/vfs_cluster.c
@@ -119,6 +119,8 @@ cluster_read(struct vnode *vp, u_quad_t filesize, daddr_t lblkno, long size,
 	 * get the requested block
 	 */
 	*bpp = reqbp = bp = getblk(vp, lblkno, size, 0, 0, gbflags);
+	if (bp == NULL)
+		return (EBUSY);
 	origblkno = lblkno;
 
 	/*
@@ -295,10 +297,18 @@ cluster_read(struct vnode *vp, u_quad_t filesize, daddr_t lblkno, long size,
 		curthread->td_ru.ru_inblock++;
 	}
 
-	if (reqbp)
-		return (bufwait(reqbp));
-	else
-		return (error);
+	if (reqbp) {
+		/*
+		 * Like bread, always brelse() the buffer when
+		 * returning an error.
+		 */
+		error = bufwait(reqbp);
+		if (error != 0) {
+			brelse(reqbp);
+			*bpp = NULL;
+		}
+	}
+	return (error);
 }
 
 /*
diff --git a/sys/ufs/ffs/ffs_inode.c b/sys/ufs/ffs/ffs_inode.c
index 1647080371e9..b41e04b05ad6 100644
--- a/sys/ufs/ffs/ffs_inode.c
+++ b/sys/ufs/ffs/ffs_inode.c
@@ -113,10 +113,8 @@ ffs_update(vp, waitfor)
 	     fsbtodb(fs, ino_to_fsba(fs, ip->i_number)),
 	     (int) fs->fs_bsize, 0, 0, 0, NOCRED, flags, &bp);
 	if (error != 0) {
-		if (error != EBUSY) {
-			brelse(bp);
+		if (error != EBUSY)
 			return (error);
-		}
 		KASSERT((IS_SNAPSHOT(ip)), ("EBUSY from non-snapshot"));
 		/*
 		 * Wait for our inode block to become available.

From 32cb8b928ab479168c225f3499c467fc1c2c443f Mon Sep 17 00:00:00 2001
From: mckusick <mckusick@FreeBSD.org>
Date: Wed, 27 Jan 2016 21:27:05 +0000
Subject: [PATCH 112/113] This fixes a bug in UFS2 exported NFS volumes. An NFS
 client can crash a server that has exported UFS2 by presenting a filehandle
 with an inode number that references an uninitialized inode in a cylinder
 group. The problem is that UFS2 only initializes blocks of inodes as they are
 first allocated and ffs_fhtovp() does not validate that the inode is in a
 range of inodes that have been initialized. Attempting to read an
 uninitialized inode gets random data from the disk. When the kernel tries to
 interpret it as an inode, panics often arise.

Reported by: Christos Zoulas (from NetBSD)
Reviewed by: kib
---
 sys/ufs/ffs/ffs_vfsops.c | 31 ++++++++++++++++++++++++++++---
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/sys/ufs/ffs/ffs_vfsops.c b/sys/ufs/ffs/ffs_vfsops.c
index 82c22fded92c..a82ef61bc5b9 100644
--- a/sys/ufs/ffs/ffs_vfsops.c
+++ b/sys/ufs/ffs/ffs_vfsops.c
@@ -1797,6 +1797,7 @@ ffs_vgetf(mp, ino, flags, vpp, ffs_flags)
  *
  * Have to be really careful about stale file handles:
  * - check that the inode number is valid
+ * - for UFS2 check that the inode number is initialized
  * - call ffs_vget() to get the locked inode
  * - check for an unallocated inode (i_mode == 0)
  * - check that the given client host has export rights and return
@@ -1810,13 +1811,37 @@ ffs_fhtovp(mp, fhp, flags, vpp)
 	struct vnode **vpp;
 {
 	struct ufid *ufhp;
+	struct ufsmount *ump;
 	struct fs *fs;
+	struct cg *cgp;
+	struct buf *bp;
+	ino_t ino;
+	u_int cg;
+	int error;
 
 	ufhp = (struct ufid *)fhp;
-	fs = VFSTOUFS(mp)->um_fs;
-	if (ufhp->ufid_ino < ROOTINO ||
-	    ufhp->ufid_ino >= fs->fs_ncg * fs->fs_ipg)
+	ino = ufhp->ufid_ino;
+	ump = VFSTOUFS(mp);
+	fs = ump->um_fs;
+	if (ino < ROOTINO || ino >= fs->fs_ncg * fs->fs_ipg)
 		return (ESTALE);
+	/*
+	 * Need to check if inode is initialized because UFS2 does lazy
+	 * initialization and nfs_fhtovp can offer arbitrary inode numbers.
+	 */
+	if (fs->fs_magic != FS_UFS2_MAGIC)
+		return (ufs_fhtovp(mp, ufhp, flags, vpp));
+	cg = ino_to_cg(fs, ino);
+	error = bread(ump->um_devvp, fsbtodb(fs, cgtod(fs, cg)),
+		(int)fs->fs_cgsize, NOCRED, &bp);
+	if (error)
+		return (error);
+	cgp = (struct cg *)bp->b_data;
+	if (!cg_chkmagic(cgp) || ino >= cg * fs->fs_ipg + cgp->cg_initediblk) {
+		brelse(bp);
+		return (ESTALE);
+	}
+	brelse(bp);
 	return (ufs_fhtovp(mp, ufhp, flags, vpp));
 }
 

From 10573611b43e8082c286b3e78d3b4d021883b6e8 Mon Sep 17 00:00:00 2001
From: bdrewery <bdrewery@FreeBSD.org>
Date: Wed, 27 Jan 2016 21:37:43 +0000
Subject: [PATCH 113/113] filemon_dtr: Lock the associated filemon handle
 before writing to it.

Reported by:	mjg
MFC after:	2 weeks
Sponsored by:	EMC / Isilon Storage Division
---
 sys/dev/filemon/filemon.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/sys/dev/filemon/filemon.c b/sys/dev/filemon/filemon.c
index 909e0cfc2c0a..0ec83465dbed 100644
--- a/sys/dev/filemon/filemon.c
+++ b/sys/dev/filemon/filemon.c
@@ -126,14 +126,16 @@ filemon_dtr(void *data)
 	struct filemon *filemon = data;
 
 	if (filemon != NULL) {
-		struct file *fp = filemon->fp;
+		struct file *fp;
 
-		/* Get exclusive write access. */
+		/* Follow same locking order as filemon_pid_check. */
 		filemon_lock_write();
+		filemon_filemon_lock(filemon);
 
 		/* Remove from the in-use list. */
 		TAILQ_REMOVE(&filemons_inuse, filemon, link);
 
+		fp = filemon->fp;
 		filemon->fp = NULL;
 		filemon->pid = -1;
 
@@ -141,6 +143,7 @@ filemon_dtr(void *data)
 		TAILQ_INSERT_TAIL(&filemons_free, filemon, link);
 
 		/* Give up write access. */
+		filemon_filemon_unlock(filemon);
 		filemon_unlock_write();
 
 		if (fp != NULL)