Add SID, THS, and CPU operating points.
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@ -27,6 +27,21 @@
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*/
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/ {
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cpus {
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cpu@0 {
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clocks = <&cpu>;
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clock-latency = <2000000>;
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operating-points = <
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/* kHz uV */
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1200000 1300000
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1008000 1200000
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816000 1100000
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648000 1040000
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408000 1040000
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>;
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};
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};
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clocks {
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pll_hsic: clk@01c20044 {
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#clock-cells = <0>;
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@ -49,6 +64,14 @@
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"usb_hsic_pll", "usb_hsic_12m",
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"usb_otg_ohci", "usb_ohci0";
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};
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ths_clk: clk@01c20074 {
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#clock-cells = <0>;
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compatible = "allwinner,sun50i-a64-ths-clk";
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reg = <0x01c20074 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "ths";
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};
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};
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soc {
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@ -79,6 +102,21 @@
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#size-cells = <0>;
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};
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sid: eeprom@01c14000 {
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compatible = "allwinner,sun8i-a83t-sid";
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reg = <0x01c14000 0x400>;
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};
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rtp: rtp@01c25000 {
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compatible = "allwinner,sun50i-a64-ts";
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reg = <0x01c25000 0x400>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 72>, <&ths_clk>;
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clock-names = "ahb", "ths";
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resets = <&ahb_rst 136>;
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#thermal-sensor-cells = <0>;
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};
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usbphy: phy@01c19400 {
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compatible = "allwinner,sun50i-a64-usb-phy";
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reg = <0x01c19400 0x24 0x01c1a800 0x4 0x01c1b800 0x4>;
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