UART Clock Selection Register holds a divider value for a supplied clock,
not a final baud rate. The value for this register has to be calculated. Sponsored by: DARPA, AFRL
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@ -80,22 +80,6 @@ enum UART_DM_BITS_PER_CHAR {
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/* UART Clock Selection Register, write only */
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#define UART_DM_CSR 0x08
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#define UART_DM_CSR_115200 0xff
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#define UART_DM_CSR_57600 0xee
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#define UART_DM_CSR_38400 0xdd
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#define UART_DM_CSR_28800 0xcc
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#define UART_DM_CSR_19200 0xbb
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#define UART_DM_CSR_14400 0xaa
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#define UART_DM_CSR_9600 0x99
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#define UART_DM_CSR_7200 0x88
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#define UART_DM_CSR_4800 0x77
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#define UART_DM_CSR_3600 0x66
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#define UART_DM_CSR_2400 0x55
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#define UART_DM_CSR_1200 0x44
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#define UART_DM_CSR_600 0x33
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#define UART_DM_CSR_300 0x22
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#define UART_DM_CSR_150 0x11
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#define UART_DM_CSR_75 0x00
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/* UART DM TX FIFO Registers - 4, write only */
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#define UART_DM_TF(x) (0x70 + (4 * (x)))
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