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UART Clock Selection Register holds a divider value for a supplied clock,

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not a final baud rate. The value for this register has to be calculated.

Sponsored by:	DARPA, AFRL
This commit is contained in:
br 2018-01-18 18:19:31 +00:00
parent 317d4fe843
commit afe48fcda0
1 changed files with 0 additions and 16 deletions
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16
sys/dev/uart/uart_dev_msm.h
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@ -80,22 +80,6 @@ enum UART_DM_BITS_PER_CHAR {
/* UART Clock Selection Register, write only */
#define UART_DM_CSR 0x08
#define UART_DM_CSR_115200 0xff
#define UART_DM_CSR_57600 0xee
#define UART_DM_CSR_38400 0xdd
#define UART_DM_CSR_28800 0xcc
#define UART_DM_CSR_19200 0xbb
#define UART_DM_CSR_14400 0xaa
#define UART_DM_CSR_9600 0x99
#define UART_DM_CSR_7200 0x88
#define UART_DM_CSR_4800 0x77
#define UART_DM_CSR_3600 0x66
#define UART_DM_CSR_2400 0x55
#define UART_DM_CSR_1200 0x44
#define UART_DM_CSR_600 0x33
#define UART_DM_CSR_300 0x22
#define UART_DM_CSR_150 0x11
#define UART_DM_CSR_75 0x00
/* UART DM TX FIFO Registers - 4, write only */
#define UART_DM_TF(x) (0x70 + (4 * (x)))