Final fix for alignment issues with the page table first patched with

r333273 and partially reverted with r333594.

Older CPUs implement addition of offsets into the page table by a
bitwise OR rather than actual addition, which only works if the table is
aligned at a multiple of its own size (they also require it to be aligned
at a multiple of 256KB). Newer ones do not have that requirement, but it
hardly matters to enforce it anyway.

The original code was failing on newer systems with huge amounts of RAM
(> 512 GB), in which the page table was 4 GB in size. Because the
bootstrap memory allocator took its alignment parameter as an int, this
turned into a 0, removing any alignment constraint at all and making
the MMU fail. The first round of this patch (r333273) fixed this case by
aligning it at 256 KB, which broke older CPUs. Fix this instead by widening
the alignment parameter.

sys/powerpc/aim/mmu_oea64.c

@@ -2446,7 +2446,7 @@ moea64_remove_all(mmu_t mmu, vm_page_t m)
  * calculated.
  */
 vm_offset_t
-moea64_bootstrap_alloc(vm_size_t size, u_int align)
+moea64_bootstrap_alloc(vm_size_t size, vm_size_t align)
 {
 	vm_offset_t	s, e;
 	int		i, j;

sys/powerpc/aim/mmu_oea64.h

@@ -39,7 +39,7 @@ extern mmu_def_t oea64_mmu;
  */
 
 /* Allocate physical memory for use in moea64_bootstrap. */
-vm_offset_t	moea64_bootstrap_alloc(vm_size_t, u_int);
+vm_offset_t	moea64_bootstrap_alloc(vm_size_t size, vm_size_t align);
 /* Set an LPTE structure to match the contents of a PVO */
 void	moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte);
 

sys/powerpc/aim/moea64_native.c

@@ -453,10 +453,11 @@ moea64_bootstrap_native(mmu_t mmup, vm_offset_t kernelstart,
 	}
 	/*
 	 * PTEG table must be aligned on a 256k boundary, but can be placed
-	 * anywhere with that alignment. Some of our hash calculations,
-	 * however, assume that the PTEG table is aligned to its own size
-	 * (low-order bits are zero in an OR). As such, make alignment
-	 * bigger than strictly necessary for the time being.
+	 * anywhere with that alignment on POWER ISA 3+ systems. On earlier
+	 * systems, offset addition is done by the CPU with bitwise OR rather
+	 * than addition, so the table must also be aligned on a boundary of
+	 * its own size. Pick the larger of the two, which works on all
+	 * systems.
 	 */
 	moea64_pteg_table = (struct lpte *)moea64_bootstrap_alloc(size, 
 	    MAX(256*1024, size));