diff --git a/sys/boot/sparc64/loader/main.c b/sys/boot/sparc64/loader/main.c index 7a85dc2c5772..b02b4bbab973 100644 --- a/sys/boot/sparc64/loader/main.c +++ b/sys/boot/sparc64/loader/main.c @@ -9,6 +9,7 @@ #include __FBSDID("$FreeBSD$"); + /* * FreeBSD/sparc64 kernel loader - machine dependent part * @@ -28,7 +29,6 @@ __FBSDID("$FreeBSD$"); #include #include -#include #include #include #include @@ -438,7 +438,7 @@ mmu_mapin_sun4u(vm_offset_t va, vm_size_t len) while (len) { if (dtlb_va_to_pa_sun4u(va) == (vm_offset_t)-1 || itlb_va_to_pa_sun4u(va) == (vm_offset_t)-1) { - /* Allocate a physical page, claim the virtual area */ + /* Allocate a physical page, claim the virtual area. */ if (pa == (vm_offset_t)-1) { pa = alloc_phys(PAGE_SIZE_4M, PAGE_SIZE_4M); if (pa == (vm_offset_t)-1) @@ -448,7 +448,9 @@ mmu_mapin_sun4u(vm_offset_t va, vm_size_t len) panic("%s: can't claim virtual page " "(wanted %#lx, got %#lx)", __func__, va, mva); - /* The mappings may have changed, be paranoid. */ + /* + * The mappings may have changed, be paranoid. + */ continue; } /* @@ -553,6 +555,7 @@ tlb_init_sun4u(void) } if (cpu != bootcpu) panic("%s: no node for bootcpu?!?!", __func__); + if (OF_getprop(child, "#dtlb-entries", &dtlb_slot_max, sizeof(dtlb_slot_max)) == -1 || OF_getprop(child, "#itlb-entries", &itlb_slot_max, @@ -580,7 +583,7 @@ main(int (*openfirm)(void *)) struct devsw **dp; /* - * Tell the Open Firmware functions where they find the ofw gate. + * Tell the Open Firmware functions where they find the OFW gate. */ OF_init(openfirm); diff --git a/sys/conf/options.sparc64 b/sys/conf/options.sparc64 index 69efd033fee0..f239bbd57a6c 100644 --- a/sys/conf/options.sparc64 +++ b/sys/conf/options.sparc64 @@ -1,22 +1,28 @@ # $FreeBSD$ -SUN4U opt_global.h - GFB_DEBUG opt_gfb.h GFB_NO_FONT_LOADING opt_gfb.h GFB_NO_MODE_CHANGE opt_gfb.h -PSYCHO_DEBUG opt_psycho.h -DEBUGGER_ON_POWERFAIL opt_psycho.h -OFW_PCI_DEBUG opt_ofw_pci.h -OFWCONS_POLL_HZ opt_ofw.h -# Debug IOMMU inserts/removes using diagnostic accesses. Very loud. -IOMMU_DIAG opt_iommu.h -PMAP_STATS opt_pmap.h +SUN4U opt_global.h ATKBD_DFLT_KEYMAP opt_atkbd.h + +# Debug IOMMU inserts/removes using diagnostic accesses. This is very loud. +IOMMU_DIAG opt_iommu.h + +OFWCONS_POLL_HZ opt_ofw.h + +OFW_PCI_DEBUG opt_ofw_pci.h + +PMAP_STATS opt_pmap.h + PSM_DEBUG opt_psm.h PSM_HOOKRESUME opt_psm.h PSM_RESETAFTERSUSPEND opt_psm.h + +DEBUGGER_ON_POWERFAIL opt_psycho.h +PSYCHO_DEBUG opt_psycho.h + SUNKBD_DFLT_KEYMAP opt_sunkbd.h SUNKBD_EMULATE_ATKBD opt_sunkbd.h diff --git a/sys/sparc64/pci/ofw_pci.h b/sys/sparc64/pci/ofw_pci.h index 352b8b883efa..252f474a90f8 100644 --- a/sys/sparc64/pci/ofw_pci.h +++ b/sys/sparc64/pci/ofw_pci.h @@ -32,7 +32,7 @@ */ #ifndef _SPARC64_PCI_OFW_PCI_H_ -#define _SPARC64_PCI_OFW_PCI_H_ +#define _SPARC64_PCI_OFW_PCI_H_ #include @@ -40,7 +40,7 @@ typedef uint32_t ofw_pci_intr_t; /* PCI range child spaces. XXX: are these MI? */ #define OFW_PCI_CS_CONFIG 0x00 -#define OFW_PCI_CS_IO 0x01 +#define OFW_PCI_CS_IO 0x01 #define OFW_PCI_CS_MEM32 0x02 #define OFW_PCI_CS_MEM64 0x03 @@ -62,4 +62,7 @@ struct ofw_pci_ranges { (((uint64_t)(r)->size_hi << 32) | (uint64_t)(r)->size_lo) #define OFW_PCI_RANGE_CS(r) (((r)->cspace >> 24) & 0x03) +/* default values */ +#define OFW_PCI_LATENCY 64 + #endif /* ! _SPARC64_PCI_OFW_PCI_H_ */ diff --git a/sys/sparc64/pci/ofw_pcibus.c b/sys/sparc64/pci/ofw_pcibus.c index 3732ac3ba26a..b26400679e8c 100644 --- a/sys/sparc64/pci/ofw_pcibus.c +++ b/sys/sparc64/pci/ofw_pcibus.c @@ -60,10 +60,10 @@ __FBSDID("$FreeBSD$"); #include "pcib_if.h" #include "pci_if.h" -/* Helper functions. */ +/* Helper functions */ static void ofw_pcibus_setup_device(device_t, u_int, u_int, u_int); -/* Methods. */ +/* Methods */ static device_probe_t ofw_pcibus_probe; static device_attach_t ofw_pcibus_attach; static pci_assign_interrupt_t ofw_pcibus_assign_interrupt; @@ -123,12 +123,12 @@ ofw_pcibus_setup_device(device_t bridge, u_int busno, u_int slot, u_int func) uint32_t reg; /* - * Initialize the latency timer register for busmaster devices to work - * properly. This is another task which the firmware does not always - * perform. The Min_Gnt register can be used to compute it's recommended - * value: it contains the desired latency in units of 1/4 us. To - * calculate the correct latency timer value, the clock frequency of - * the bus (defaulting to 33Mhz) should be used and no wait states + * Initialize the latency timer register for busmaster devices to + * work properly. This is another task which the firmware doesn't + * always perform. The Min_Gnt register can be used to compute its + * recommended value: it contains the desired latency in units of + * 1/4 us. To calculate the correct latency timer value, the clock + * frequency of the bus (defaulting to 33MHz) and no wait states * should be assumed. */ if (OF_getprop(ofw_bus_get_node(bridge), "clock-frequency", ®, @@ -151,17 +151,18 @@ ofw_pcibus_setup_device(device_t bridge, u_int busno, u_int slot, u_int func) /* * Compute a value to write into the cache line size register. * The role of the streaming cache is unclear in write invalidate - * transfers, so it is made sure that it's line size is always reached. - * Generally, the cache line size is fixed at 64 bytes by Fireplane/ - * Safari, JBus and UPA. + * transfers, so it is made sure that it's line size is always + * reached. Generally, the cache line size is fixed at 64 bytes + * by Fireplane/Safari, JBus and UPA. */ PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_CACHELNSZ, STRBUF_LINESZ / sizeof(uint32_t), 1); #endif /* - * The preset in the intline register is usually wrong. Reset it to 255, - * so that the PCI code will reroute the interrupt if needed. + * The preset in the intline register is usually wrong. Reset + * it to 255, so that the PCI code will reroute the interrupt if + * needed. */ PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_INTLINE, PCI_INVALID_IRQ, 1); @@ -183,7 +184,6 @@ ofw_pcibus_attach(device_t dev) if (bootverbose) device_printf(dev, "domain=%d, physical bus=%d\n", domain, busno); - node = ofw_bus_get_node(dev); #ifndef SUN4V @@ -237,7 +237,8 @@ ofw_pcibus_assign_interrupt(device_t dev, device_t child) } else if (intr >= 255) { /* * A fully specified interrupt (including IGN), as present on - * SPARCengine Ultra AX and e450. Extract the INO and return it. + * SPARCengine Ultra AX and E450. Extract the INO and return + * it. */ return (INTINO(intr)); #endif @@ -245,11 +246,12 @@ ofw_pcibus_assign_interrupt(device_t dev, device_t child) /* * If we got intr from a property, it may or may not be an intpin. * For on-board devices, it frequently is not, and is completely out - * of the valid intpin range. For PCI slots, it hopefully is, otherwise - * we will have trouble interfacing with non-OFW buses such as cardbus. + * of the valid intpin range. For PCI slots, it hopefully is, + * otherwise we will have trouble interfacing with non-OFW buses + * such as cardbus. * Since we cannot tell which it is without violating layering, we - * will always use the route_interrupt method, and treat exceptions on - * the level they become apparent. + * will always use the route_interrupt method, and treat exceptions + * on the level they become apparent. */ return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr)); } diff --git a/sys/sparc64/pci/psycho.c b/sys/sparc64/pci/psycho.c index 034e794a356d..88d7bc88c17e 100644 --- a/sys/sparc64/pci/psycho.c +++ b/sys/sparc64/pci/psycho.c @@ -281,7 +281,6 @@ psycho_probe(device_t dev) device_set_desc(dev, "U2P UPA-PCI bridge"); return (0); } - return (ENXIO); } @@ -331,6 +330,7 @@ psycho_attach(device_t dev) default: panic("%s: bogus PCI control register location", __func__); + /* NOTREACHED */ } } else { rid = 0; @@ -651,7 +651,7 @@ psycho_attach(device_t dev) * firmware. */ PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC, - PCIR_LATTIMER, 64, 1); + PCIR_LATTIMER, OFW_PCI_LATENCY, 1); for (n = PCIR_VENDOR; n < PCIR_STATUS; n += sizeof(uint16_t)) le16enc(&sc->sc_pci_hpbcfg[n], bus_space_read_2( @@ -966,6 +966,7 @@ psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, break; default: panic("%s: bad width", __func__); + /* NOTREACHED */ } if (i) { @@ -1001,6 +1002,7 @@ psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, break; default: panic("%s: bad width", __func__); + /* NOTREACHED */ } } @@ -1278,6 +1280,7 @@ psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, break; default: return (NULL); + /* NOTREACHED */ } rv = rman_reserve_resource(rm, start, end, count, flags, child); @@ -1294,7 +1297,6 @@ psycho_alloc_resource(device_t bus, device_t child, int type, int *rid, return (NULL); } } - return (rv); } diff --git a/sys/sparc64/sparc64/exception.S b/sys/sparc64/sparc64/exception.S index 777e1455d151..877fac021ef5 100644 --- a/sys/sparc64/sparc64/exception.S +++ b/sys/sparc64/sparc64/exception.S @@ -235,7 +235,7 @@ END(tl1_kstack_fault) /* * Magic to resume from a spill or fill trap. If we get an alignment or an - * mmu fault during a spill or a fill, this macro will detect the fault and + * MMU fault during a spill or a fill, this macro will detect the fault and * resume at a set instruction offset in the trap handler. * * To check if the previous trap was a spill/fill we convert the trapped pc @@ -287,7 +287,7 @@ END(tl1_kstack_fault) inc 16, ASP_REG /* - * For certain faults we need to clear the SFSR mmu register before returning. + * For certain faults we need to clear the SFSR MMU register before returning. */ #define RSF_CLR_SFSR \ wr %g0, ASI_DMMU, %asi ; \ @@ -1078,7 +1078,7 @@ ENTRY(tl0_dmmu_prot_trap) membar #Sync /* - * Save the mmu registers and call common trap code. + * Save the MMU registers and call common trap code. */ tl0_split clr %o1 @@ -2370,10 +2370,10 @@ END(tl0_intr) ENTRY(tl0_ret) /* * Check for pending asts atomically with returning. We must raise - * the pil before checking, and if no asts are found the pil must + * the PIL before checking, and if no asts are found the PIL must * remain raised until the retry is executed, or we risk missing asts - * caused by interrupts occuring after the test. If the pil is lowered, - * as it is when we call ast, the check must be re-executed. + * caused by interrupts occuring after the test. If the PIL is + * lowered, as it is when we call ast, the check must be re-executed. */ wrpr %g0, PIL_TICK, %pil ldx [PCPU(CURTHREAD)], %l0 @@ -2384,7 +2384,7 @@ ENTRY(tl0_ret) nop /* - * We have an ast. Re-enable interrupts and handle it, then restart + * We have an AST. Re-enable interrupts and handle it, then restart * the return sequence. */ wrpr %g0, 0, %pil diff --git a/sys/sparc64/sparc64/locore.S b/sys/sparc64/sparc64/locore.S index 9a05f4666830..ace549e64273 100644 --- a/sys/sparc64/sparc64/locore.S +++ b/sys/sparc64/sparc64/locore.S @@ -45,7 +45,7 @@ __FBSDID("$FreeBSD$"); ENTRY(btext) ENTRY(_start) /* - * Initialize misc state to known values. Interrupts disabled, normal + * Initialize misc. state to known values: interrupts disabled, normal * globals, windows flushed (cr = 0, cs = nwindows - 1), no clean * windows, pil 0, and floating point disabled. */ diff --git a/sys/sparc64/sparc64/mp_machdep.c b/sys/sparc64/sparc64/mp_machdep.c index fb3002d3116d..d3572f265886 100644 --- a/sys/sparc64/sparc64/mp_machdep.c +++ b/sys/sparc64/sparc64/mp_machdep.c @@ -394,7 +394,7 @@ cpu_mp_bootstrap(struct pcpu *pc) while (csa->csa_count != 0) ; - /* ok, now enter the scheduler */ + /* Ok, now enter the scheduler. */ sched_throw(NULL); }