o) Free mbufs in error cases.

o) Clear/acknowledge receive interrupt at end of thread.  This gives the
   management interfaces performance on the order of 100Mbps rather than
   the previous level of 10Mbps on my MR-730.

sys/mips/cavium/if_octm.c

@@ -511,9 +511,15 @@ octm_rx_intr(void *arg)
 			continue;
 		}
 
+		m_freem(m);
+
 		if (len == 0)
 			break;
 
 		sc->sc_ifp->if_ierrors++;
 	}
+
+	/* Acknowledge interrupts.  */
+	cvmx_write_csr(CVMX_MIXX_ISR(sc->sc_port), mixx_isr.u64);
+	cvmx_read_csr(CVMX_MIXX_ISR(sc->sc_port));
 }