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Add the CNTHCTL_EL2 register bits missed in r286674

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This commit is contained in:
Andrew Turner 2015-08-12 17:09:57 +00:00
parent f03aa10f47
commit b1bacc1cbd
1 changed files with 7 additions and 0 deletions
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7
sys/arm64/include/armreg.h
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@ -41,6 +41,13 @@
#define WRITE_SPECIALREG(reg, val) \
__asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val))
/* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */
#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */
#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/
/* CPACR_EL1 */
#define CPACR_FPEN_MASK (0x3 << 20)
#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */