sys/arm/arm/mpcore_timer.c

@@ -67,6 +67,8 @@ __FBSDID("$FreeBSD$");
 #include <machine/bus.h>
 #include <machine/fdt.h>
 
+#include <arm/arm/mpcore_timervar.h>
+
 /* Private (per-CPU) timer register map */
 #define PRV_TIMER_LOAD                 0x0000
 #define PRV_TIMER_COUNT                0x0004
@@ -100,7 +102,7 @@ struct arm_tmr_softc {
 	bus_space_tag_t		gbl_bst;
 	bus_space_handle_t	prv_bsh;
 	bus_space_handle_t	gbl_bsh;
-	uint32_t		clkfreq;
+	uint64_t		clkfreq;
 	struct eventtimer	et;
 };
 
@@ -114,7 +116,7 @@ static struct resource_spec arm_tmr_spec[] = {
 
 static struct arm_tmr_softc *arm_tmr_sc = NULL;
 
-uint32_t platform_arm_tmr_freq = 0;
+static uint64_t platform_arm_tmr_freq = 0;
 
 #define	tmr_prv_read_4(reg)		\
     bus_space_read_4(arm_tmr_sc->prv_bst, arm_tmr_sc->prv_bsh, reg)
@@ -209,6 +211,7 @@ static int
 arm_tmr_stop(struct eventtimer *et)
 {
 	tmr_prv_write_4(PRV_TIMER_CTRL, 0);
+	tmr_prv_write_4(PRV_TIMER_INTR, PRV_TIMER_INTR_EVENT);
 	return (0);
 }
 
@@ -278,24 +281,29 @@ arm_tmr_attach(device_t dev)
 	phandle_t node;
 	pcell_t clock;
 	void *ihl;
+	boolean_t fixed_freq;
 
 	if (arm_tmr_sc)
 		return (ENXIO);
 
-	if (platform_arm_tmr_freq != 0)
-		sc->clkfreq = platform_arm_tmr_freq;
-	else {
-		/* Get the base clock frequency */
-		node = ofw_bus_get_node(dev);
-		if ((OF_getprop(node, "clock-frequency", &clock,
-		    sizeof(clock))) <= 0) {
-			device_printf(dev, "missing clock-frequency attribute in FDT\n");
-			return (ENXIO);
+	if (platform_arm_tmr_freq == ARM_TMR_FREQUENCY_VARIES) {
+		fixed_freq = false;
+	} else {
+		fixed_freq = true;
+		if (platform_arm_tmr_freq != 0) {
+			sc->clkfreq = platform_arm_tmr_freq;
+		} else {
+			/* Get the base clock frequency */
+			node = ofw_bus_get_node(dev);
+			if ((OF_getencprop(node, "clock-frequency", &clock,
+			    sizeof(clock))) <= 0) {
+				device_printf(dev, "missing clock-frequency "
+				    "attribute in FDT\n");
+				return (ENXIO);
+			}
 		}
-		sc->clkfreq = fdt32_to_cpu(clock);
 	}
 
-
 	if (bus_alloc_resources(dev, arm_tmr_spec, sc->tmr_res)) {
 		device_printf(dev, "could not allocate resources\n");
 		return (ENXIO);
@@ -315,14 +323,6 @@ arm_tmr_attach(device_t dev)
 	tmr_prv_write_4(PRV_TIMER_CTRL, 0x00000000);
 	tmr_gbl_write_4(GBL_TIMER_CTRL, 0x00000000);
 
-	/* Setup and enable the global timer to use as the timecounter */
-	tmr_gbl_write_4(GBL_TIMER_CTRL, (0x00 << GBL_TIMER_CTR_PRESCALER_SHIFT) | 
-					GBL_TIMER_CTRL_TIMER_ENABLE);
-
-	arm_tmr_timecount.tc_frequency = sc->clkfreq;
-	tc_init(&arm_tmr_timecount);
-
-	/* Setup and enable the timer */
 	if (bus_setup_intr(dev, sc->tmr_res[3], INTR_TYPE_CLK, arm_tmr_intr,
 			NULL, sc, &ihl) != 0) {
 		bus_release_resources(dev, arm_tmr_spec, sc->tmr_res);
@@ -330,13 +330,35 @@ arm_tmr_attach(device_t dev)
 		return (ENXIO);
 	}
 
+	/*
+	 * If the clock is fixed-frequency, setup and enable the global timer to
+	 * use as the timecounter.  If it's variable frequency it won't work as
+	 * a timecounter.  We also can't use it for DELAY(), so hopefully the
+	 * platform provides its own implementation.  If it doesn't, ours will
+	 * get used, but since the frequency isn't set, it will only use the
+	 * bogus loop counter.
+	 */
+	if (fixed_freq)  {
+		tmr_gbl_write_4(GBL_TIMER_CTRL, GBL_TIMER_CTRL_TIMER_ENABLE);
+		arm_tmr_timecount.tc_frequency = sc->clkfreq;
+		tc_init(&arm_tmr_timecount);
+	}
+
+	/*
+	 * Setup and register the eventtimer.  Most event timers set their min
+	 * and max period values to some value calculated from the clock
+	 * frequency.  We might not know yet what our runtime clock frequency
+	 * will be, so we just use some safe values.  A max of 2 seconds ensures
+	 * that even if our base clock frequency is 2GHz (meaning a 4GHz CPU),
+	 * we won't overflow our 32-bit timer count register.  A min of 20
+	 * nanoseconds is pretty much completely arbitrary.
+	 */
 	sc->et.et_name = "MPCore";
 	sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | ET_FLAGS_PERCPU;
 	sc->et.et_quality = 1000;
-
 	sc->et.et_frequency = sc->clkfreq;
-	sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency;
-	sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
+	sc->et.et_min_period = 20 * SBT_1NS;
+	sc->et.et_max_period =  2 * SBT_1S;
 	sc->et.et_start = arm_tmr_start;
 	sc->et.et_stop = arm_tmr_stop;
 	sc->et.et_priv = sc;
@@ -361,6 +383,31 @@ static devclass_t arm_tmr_devclass;
 
 DRIVER_MODULE(mp_tmr, simplebus, arm_tmr_driver, arm_tmr_devclass, 0, 0);
 
+/*
+ * Handle a change in clock frequency.  The mpcore timer runs at half the CPU
+ * frequency.  When the CPU frequency changes due to power-saving or thermal
+ * managment, the platform-specific code that causes the frequency change calls
+ * this routine to inform the clock driver, and we in turn inform the event
+ * timer system, which actually updates the value in et->frequency for us and
+ * reschedules the current event(s) in a way that's atomic with respect to
+ * start/stop/intr code that may be running on various CPUs at the time of the
+ * call.
+ *
+ * This routine can also be called by a platform's early init code.  If the
+ * value passed is ARM_TMR_FREQUENCY_VARIES, that will cause the attach() code
+ * to register as an eventtimer, but not a timecounter.  If the value passed in
+ * is any other non-zero value it is used as the fixed frequency for the timer.
+ */
+void
+arm_tmr_change_frequency(uint64_t newfreq)
+{
+
+	if (arm_tmr_sc == NULL)
+		platform_arm_tmr_freq = newfreq;
+	else
+		et_change_frequency(&arm_tmr_sc->et, newfreq);
+}
+
 /**
  *	DELAY - Delay for at least usec microseconds.
  *	@usec: number of microseconds to delay by
@@ -380,7 +427,7 @@ arm_tmr_DELAY(int usec)
 	uint32_t first, last;
 
 	/* Check the timers are setup, if not just use a for loop for the meantime */
-	if (arm_tmr_sc == NULL) {
+	if (arm_tmr_sc == NULL || arm_tmr_timecount.tc_frequency == 0) {
 		for (; usec > 0; usec--)
 			for (counts = 200; counts > 0; counts--)
 				cpufunc_nullop();	/* Prevent gcc from optimizing

sys/arm/arm/mpcore_timervar.h

@@ -0,0 +1,47 @@
+/*-
+ * Copyright (c) 2014 Ian Lepore <ian@freebsd.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_ARM_MPCORE_TIMERVAR_H_
+#define	_ARM_MPCORE_TIMERVAR_H_
+
+/*
+ * This value, passed to arm_tmr_change_frequency() any time before the mpcore
+ * timer device attaches, informs the driver that the mpcore clock frequency can
+ * change on the fly, and thus can't be used as a timecounter.  The hardware can
+ * still be used as an eventtimer, as long as each frequency change is
+ * communicated to it with calls to arm_tmr_change_frequency().
+ */
+#define	ARM_TMR_FREQUENCY_VARIES	-1ULL
+
+/*
+ * Inform the mpcore timer driver of a new clock frequency.  This can be called
+ * both before and after the mpcore timer driver attaches.
+ */
+void	arm_tmr_change_frequency(uint64_t newfreq);
+
+#endif

sys/arm/ti/omap4/omap4_prcm_clks.c

@@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$");
 #include <machine/resource.h>
 #include <machine/intr.h>
 
+#include <arm/arm/mpcore_timervar.h>
 #include <arm/ti/tivar.h>
 #include <arm/ti/ti_prcm.h>
 #include <arm/ti/omap4/omap4_reg.h>
@@ -1404,7 +1405,7 @@ omap4_prcm_attach(device_t dev)
 	omap4_prcm_sc = sc;
 	ti_cpu_reset = omap4_prcm_reset;
 	omap4_clk_get_arm_fclk_freq(NULL, &freq);
-	platform_arm_tmr_freq = freq / 2;
+	arm_tmr_change_frequency(freq / 2);
 
 	return (0);
 }