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Pull in r175962 from upstream llvm trunk:

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X86: Disable cmov-memory patterns on subtargets without cmov.

  Fixes PR15115.

For the i386 arch, this should enable cmov instructions only on
-march=pentiumpro and higher.  Since our default CPU is i486, cmov
instructions will now be disabled by default.

MFC after:	1 week
This commit is contained in:
Dimitry Andric 2013-02-23 22:48:12 +00:00
parent e5b6b345cf
commit b2a67e7b16
1 changed files with 8 additions and 6 deletions
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14
contrib/llvm/lib/Target/X86/X86InstrCompiler.td
View File

@ -1076,12 +1076,14 @@ def : Pat<(X86cmp GR64:$src1, 0),
// inverted.
multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
Instruction Inst64> {
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
(Inst16 GR16:$src2, addr:$src1)>;
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
(Inst32 GR32:$src2, addr:$src1)>;
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
(Inst64 GR64:$src2, addr:$src1)>;
let Predicates = [HasCMov] in {
def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
(Inst16 GR16:$src2, addr:$src1)>;
def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
(Inst32 GR32:$src2, addr:$src1)>;
def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
(Inst64 GR64:$src2, addr:$src1)>;
}
}
defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;