From b2edbc662ebd9c1333069a1982df629a97b41158 Mon Sep 17 00:00:00 2001 From: Neel Natu Date: Thu, 21 Jan 2010 02:21:31 +0000 Subject: [PATCH] Get rid of redundant setting of interrupt enable bit when restoring the status register from the PCB. Remove a couple of misleading comments while I am here. The comments are misleading because they imply that interrupts will be enabled after the status register is restored from the PCB. This is not the case because the processor is at the exception level (SR_EXL is set). Approved by: imp (mentor) --- sys/mips/mips/exception.S | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/sys/mips/mips/exception.S b/sys/mips/mips/exception.S index 7fdbd00f0ce7..182ff850d987 100644 --- a/sys/mips/mips/exception.S +++ b/sys/mips/mips/exception.S @@ -581,16 +581,10 @@ NNON_LEAF(MipsUserGenException, STAND_FRAME_SIZE, ra) #ifdef TARGET_OCTEON and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) #endif - or k0, k0, (MIPS_SR_INT_IE) .set noat RESTORE_U_PCB_REG(AT, AST, k1) -/* - * The restoration of the user SR must be done only after - * k1 is no longer needed. Otherwise, k1 will get clobbered after - * interrupts are enabled. - */ - mtc0 k0, COP_0_STATUS_REG # still exeption level + mtc0 k0, COP_0_STATUS_REG # still exception level ITLBNOPFIX sync eret @@ -814,15 +808,9 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE, ra) #ifdef TARGET_OCTEON and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) #endif - or k0, k0, (MIPS_SR_INT_IE|SR_EXL) .set noat RESTORE_U_PCB_REG(AT, AST, k1) -/* - * The restoration of the user SR must be done only after - * k1 is no longer needed. Otherwise, k1 will get clobbered after - * interrupts are enabled. - */ mtc0 k0, COP_0_STATUS_REG # SR with EXL set. ITLBNOPFIX sync