Add genet driver for Raspberry Pi 4B Ethernet
Add driver for Broadcom "GENET" version 5, as found in BCM-2711 on Raspberry Pi 4B. The driver is derived in part from the bcmgenet.c driver in NetBSD, along with bcmgenetreg.h. Reviewed by: manu Obtained from: in part from NetBSD Relnotes: yes, note addition Differential Revision: https://reviews.freebsd.org/D24436
This commit is contained in:
karels
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932b6bd887
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sys/arm64/broadcom/genet/if_genet.c
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sys/arm64/broadcom/genet/if_genet.c
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sys/arm64/broadcom/genet/if_genetreg.h
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sys/arm64/broadcom/genet/if_genetreg.h
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/* $NetBSD: bcmgenetreg.h,v 1.2 2020/02/22 13:41:41 jmcneill Exp $ */
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/* derived from NetBSD's bcmgenetreg.h */
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/*-
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* Copyright (c) 2020 Michael J Karels
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* Copyright (c) 2020 Jared McNeill <jmcneill@invisible.ca>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Broadcom GENETv5
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*/
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#ifndef _BCMGENETREG_H
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#define _BCMGENETREG_H
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#define GENET_SYS_REV_CTRL 0x000
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#define SYS_REV_MAJOR __BITS(27,24)
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#define SYS_REV_MINOR __BITS(19,16)
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#define REV_MAJOR 0xf000000
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#define REV_MAJOR_SHIFT 24
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#define REV_MAJOR_V5 6
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#define REV_MINOR 0xf0000
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#define REV_MINOR_SHIFT 16
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#define REV_PHY 0xffff
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#define GENET_SYS_PORT_CTRL 0x004
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#define GENET_SYS_PORT_MODE_EXT_GPHY 3
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#define GENET_SYS_RBUF_FLUSH_CTRL 0x008
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#define GENET_SYS_RBUF_FLUSH_RESET __BIT(1)
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#define GENET_SYS_TBUF_FLUSH_CTRL 0x00c
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#define GENET_EXT_RGMII_OOB_CTRL 0x08c
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#define GENET_EXT_RGMII_OOB_ID_MODE_DISABLE __BIT(16)
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#define GENET_EXT_RGMII_OOB_RGMII_MODE_EN __BIT(6)
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#define GENET_EXT_RGMII_OOB_OOB_DISABLE __BIT(5)
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#define GENET_EXT_RGMII_OOB_RGMII_LINK __BIT(4)
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#define GENET_INTRL2_CPU_STAT 0x200
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#define GENET_INTRL2_CPU_CLEAR 0x208
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#define GENET_INTRL2_CPU_STAT_MASK 0x20c
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#define GENET_INTRL2_CPU_SET_MASK 0x210
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#define GENET_INTRL2_CPU_CLEAR_MASK 0x214
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#define GENET_IRQ_MDIO_ERROR __BIT(24)
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#define GENET_IRQ_MDIO_DONE __BIT(23)
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#define GENET_IRQ_TXDMA_DONE __BIT(16)
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#define GENET_IRQ_RXDMA_DONE __BIT(13)
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#define GENET_RBUF_CTRL 0x300
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#define GENET_RBUF_BAD_DIS __BIT(2)
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#define GENET_RBUF_ALIGN_2B __BIT(1)
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#define GENET_RBUF_64B_EN __BIT(0)
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#define GENET_RBUF_CHECK_CTRL 0x314
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#define GENET_RBUF_CHECK_CTRL_EN __BIT(0)
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#define GENET_RBUF_CHECK_SKIP_FCS __BIT(4)
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#define GENET_RBUF_TBUF_SIZE_CTRL 0x3b4
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#define GENET_TBUF_CTRL 0x600
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#define GENET_UMAC_CMD 0x808
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#define GENET_UMAC_CMD_LCL_LOOP_EN __BIT(15)
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#define GENET_UMAC_CMD_SW_RESET __BIT(13)
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#define GENET_UMAC_CMD_PROMISC __BIT(4)
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#ifdef __BITS
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#define GENET_UMAC_CMD_SPEED __BITS(3,2)
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#define GENET_UMAC_CMD_SPEED_10 0
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#define GENET_UMAC_CMD_SPEED_100 1
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#define GENET_UMAC_CMD_SPEED_1000 2
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#else
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#define GENET_UMAC_CMD_SPEED (3 << 2)
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#define GENET_UMAC_CMD_SPEED_10 (0 << 2)
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#define GENET_UMAC_CMD_SPEED_100 (1 << 2)
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#define GENET_UMAC_CMD_SPEED_1000 (2 << 2)
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#define GENET_UMAC_CMD_CRC_FWD __BIT(6)
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#endif
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#define GENET_UMAC_CMD_RXEN __BIT(1)
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#define GENET_UMAC_CMD_TXEN __BIT(0)
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#define GENET_UMAC_MAC0 0x80c
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#define GENET_UMAC_MAC1 0x810
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#define GENET_UMAC_MAX_FRAME_LEN 0x814
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#define GENET_UMAC_TX_FLUSH 0xb34
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#define GENET_UMAC_MIB_CTRL 0xd80
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#define GENET_UMAC_MIB_RESET_TX __BIT(2)
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#define GENET_UMAC_MIB_RESET_RUNT __BIT(1)
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#define GENET_UMAC_MIB_RESET_RX __BIT(0)
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#define GENET_MDIO_CMD 0xe14
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#define GENET_MDIO_START_BUSY __BIT(29)
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#define GENET_MDIO_READ_FAILED __BIT(28)
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#define GENET_MDIO_READ __BIT(27)
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#define GENET_MDIO_WRITE __BIT(26)
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#define GENET_MDIO_PMD __BITS(25,21)
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#define GENET_MDIO_REG __BITS(20,16)
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#define GENET_MDIO_ADDR_SHIFT 21
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#define GENET_MDIO_REG_SHIFT 16
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#define GENET_MDIO_VAL_MASK 0xffff
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#define GENET_UMAC_MDF_CTRL 0xe50
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#define GENET_UMAC_MDF_ADDR0(n) (0xe54 + (n) * 0x8)
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#define GENET_UMAC_MDF_ADDR1(n) (0xe58 + (n) * 0x8)
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#define GENET_MAX_MDF_FILTER 17
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#define GENET_DMA_DESC_COUNT 256
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#define GENET_DMA_DESC_SIZE 12
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#define GENET_DMA_DEFAULT_QUEUE 16
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#define GENET_DMA_RING_SIZE 0x40
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#define GENET_DMA_RINGS_SIZE (GENET_DMA_RING_SIZE * (GENET_DMA_DEFAULT_QUEUE + 1))
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#define GENET_RX_BASE 0x2000
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#define GENET_TX_BASE 0x4000
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#define GENET_RX_DMA_RINGBASE(qid) (GENET_RX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid))
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#define GENET_RX_DMA_WRITE_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x00)
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#define GENET_RX_DMA_WRITE_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x04)
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#define GENET_RX_DMA_PROD_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x08)
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#define GENET_RX_DMA_CONS_INDEX(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x0c)
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#define GENET_RX_DMA_PROD_CONS_MASK 0xffff
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#define GENET_RX_DMA_RING_BUF_SIZE(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x10)
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#define GENET_RX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16)
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#define GENET_RX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0)
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#define GENET_RX_DMA_RING_BUF_SIZE_DESC_SHIFT 16
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#define GENET_RX_DMA_RING_BUF_SIZE_BUF_LEN_MASK 0xffff
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#define GENET_RX_DMA_START_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x14)
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#define GENET_RX_DMA_START_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x18)
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#define GENET_RX_DMA_END_ADDR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x1c)
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#define GENET_RX_DMA_END_ADDR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x20)
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#define GENET_RX_DMA_XON_XOFF_THRES(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x28)
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#define GENET_RX_DMA_XON_XOFF_THRES_LO __BITS(31,16)
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#define GENET_RX_DMA_XON_XOFF_THRES_HI __BITS(15,0)
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#define GENET_RX_DMA_XON_XOFF_THRES_LO_SHIFT 16
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#define GENET_RX_DMA_READ_PTR_LO(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x2c)
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#define GENET_RX_DMA_READ_PTR_HI(qid) (GENET_RX_DMA_RINGBASE(qid) + 0x30)
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#define GENET_TX_DMA_RINGBASE(qid) (GENET_TX_BASE + 0xc00 + GENET_DMA_RING_SIZE * (qid))
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#define GENET_TX_DMA_READ_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x00)
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#define GENET_TX_DMA_READ_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x04)
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#define GENET_TX_DMA_CONS_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x08)
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#define GENET_TX_DMA_PROD_INDEX(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x0c)
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#define GENET_TX_DMA_PROD_CONS_MASK 0xffff
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#define GENET_TX_DMA_RING_BUF_SIZE(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x10)
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#define GENET_TX_DMA_RING_BUF_SIZE_DESC_COUNT __BITS(31,16)
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#define GENET_TX_DMA_RING_BUF_SIZE_BUF_LENGTH __BITS(15,0)
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#define GENET_TX_DMA_RING_BUF_SIZE_DESC_SHIFT 16
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#define GENET_TX_DMA_RING_BUF_SIZE_BUF_LEN_MASK 0xffff
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#define GENET_TX_DMA_START_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x14)
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#define GENET_TX_DMA_START_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x18)
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#define GENET_TX_DMA_END_ADDR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x1c)
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#define GENET_TX_DMA_END_ADDR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x20)
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#define GENET_TX_DMA_MBUF_DONE_THRES(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x24)
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#define GENET_TX_DMA_FLOW_PERIOD(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x28)
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#define GENET_TX_DMA_WRITE_PTR_LO(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x2c)
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#define GENET_TX_DMA_WRITE_PTR_HI(qid) (GENET_TX_DMA_RINGBASE(qid) + 0x30)
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#define GENET_RX_DESC_STATUS(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00)
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#define GENET_RX_DESC_STATUS_BUFLEN __BITS(27,16)
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#define GENET_RX_DESC_STATUS_BUFLEN_MASK 0xfff0000
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#define GENET_RX_DESC_STATUS_BUFLEN_SHIFT 16
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#define GENET_RX_DESC_STATUS_OWN __BIT(15) /* ??? */
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#define GENET_RX_DESC_STATUS_CKSUM_OK __BIT(15)
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#define GENET_RX_DESC_STATUS_EOP __BIT(14)
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#define GENET_RX_DESC_STATUS_SOP __BIT(13)
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#define GENET_RX_DESC_STATUS_RX_ERROR __BIT(2)
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#define GENET_RX_DESC_ADDRESS_LO(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04)
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#define GENET_RX_DESC_ADDRESS_HI(idx) (GENET_RX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08)
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#define GENET_TX_DESC_STATUS(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x00)
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#define GENET_TX_DESC_STATUS_BUFLEN __BITS(27,16)
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#define GENET_TX_DESC_STATUS_OWN __BIT(15)
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#define GENET_TX_DESC_STATUS_EOP __BIT(14)
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#define GENET_TX_DESC_STATUS_SOP __BIT(13)
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#define GENET_TX_DESC_STATUS_QTAG __BITS(12,7)
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#define GENET_TX_DESC_STATUS_CRC __BIT(6)
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#define GENET_TX_DESC_STATUS_CKSUM __BIT(4)
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#define GENET_TX_DESC_STATUS_BUFLEN_SHIFT 16
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#define GENET_TX_DESC_STATUS_BUFLEN_MASK 0x7ff0000
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#define GENET_TX_DESC_STATUS_QTAG_MASK 0x1f80
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#define GENET_TX_DESC_ADDRESS_LO(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x04)
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#define GENET_TX_DESC_ADDRESS_HI(idx) (GENET_TX_BASE + GENET_DMA_DESC_SIZE * (idx) + 0x08)
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/* Status block prepended to tx/rx packets (optional) */
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struct statusblock {
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u_int32_t status_buflen;
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u_int32_t extstatus;
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u_int32_t rxcsum;
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u_int32_t spare1[9];
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u_int32_t txcsuminfo;
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u_int32_t spare2[3];
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};
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/* bits in txcsuminfo */
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#define TXCSUM_LEN_VALID __BIT(31)
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#define TXCSUM_OFF_SHIFT 16
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#define TXCSUM_UDP __BIT(15)
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#define GENET_RX_DMA_RING_CFG (GENET_RX_BASE + 0x1040 + 0x00)
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#define GENET_RX_DMA_CTRL (GENET_RX_BASE + 0x1040 + 0x04)
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#define GENET_RX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1)
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#define GENET_RX_DMA_CTRL_EN __BIT(0)
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#define GENET_RX_SCB_BURST_SIZE (GENET_RX_BASE + 0x1040 + 0x0c)
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#define GENET_TX_DMA_RING_CFG (GENET_TX_BASE + 0x1040 + 0x00)
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#define GENET_TX_DMA_CTRL (GENET_TX_BASE + 0x1040 + 0x04)
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#define GENET_TX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1)
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#define GENET_TX_DMA_CTRL_EN __BIT(0)
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#define GENET_TX_SCB_BURST_SIZE (GENET_TX_BASE + 0x1040 + 0x0c)
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#endif /* !_BCMGENETREG_H */
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@ -170,6 +170,7 @@ device vnic # Cavium ThunderX NIC
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device al_eth # Annapurna Alpine Ethernet NIC
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device dwc_rk # Rockchip Designware
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device dwc_socfpga # Altera SOCFPGA Ethernet MAC
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device genet # Broadcom on RPi4
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# Etherswitch devices
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device etherswitch # Enable etherswitch support
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@ -74,8 +74,10 @@
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#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFFUL
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#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFFUL
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#define BUS_SPACE_MAXADDR_40BIT 0xFFFFFFFFFFUL
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#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFFUL
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#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFFUL
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#define BUS_SPACE_MAXSIZE_40BIT 0xFFFFFFFFFFUL
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#define BUS_SPACE_MAXADDR 0xFFFFFFFFFFFFFFFFUL
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#define BUS_SPACE_MAXSIZE 0xFFFFFFFFFFFFFFFFUL
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@ -178,6 +178,7 @@ arm64/arm64/vm_machdep.c standard
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arm64/broadcom/brcmmdio/mdio_mux_iproc.c optional fdt
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arm64/broadcom/brcmmdio/mdio_nexus_iproc.c optional fdt
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arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c optional fdt pci
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arm64/broadcom/genet/if_genet.c optional SOC_BRCM_BCM2838 fdt genet
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arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt
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arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci
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arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt
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