Add initial BCM57765 family support. The BCM57765 family seems to
have similar hardware features of BCM5718 family except the number of receive return ring is 4. The BCM57765 family is known to support IEEE 802.3az EEE(Energy Efficient Ethernet) but this change does not include EEE support code. I hope EEE is implemented in near future. This change will support BCM57761, BCM57765, BCM57781, BCM57785, BCM57791 and BCM57795. All hardware offloading features are supported and suspend/resume also should work. Many thanks to Broadcom for continuing support of FreeBSD. Tested by: Paul Thornton (prt <> prt dot org) HW donated by: Broadcom
This commit is contained in:
Pyun YongHyeon
parent
cc3cbd9b4d
commit
b4a256ac67
@ -214,9 +214,15 @@ static const struct bge_type {
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5906 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM5906M },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM57760 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM57761 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM57765 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM57780 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM57781 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM57785 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM57788 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM57790 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM57791 },
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{ BCOM_VENDORID, BCOM_DEVICEID_BCM57795 },
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{ SK_VENDORID, SK_DEVICEID_ALTIMA },
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@ -307,6 +313,8 @@ static const struct bge_revision {
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{ BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
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{ BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
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{ BGE_CHIPID_BCM5906_A2, "BCM5906 A2" },
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{ BGE_CHIPID_BCM57765_A0, "BCM57765 A0" },
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{ BGE_CHIPID_BCM57765_B0, "BCM57765 B0" },
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{ BGE_CHIPID_BCM57780_A0, "BCM57780 A0" },
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{ BGE_CHIPID_BCM57780_A1, "BCM57780 A1" },
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@ -335,6 +343,7 @@ static const struct bge_revision const bge_majorrevs[] = {
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/* 5754 and 5787 share the same ASIC ID */
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{ BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
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{ BGE_ASICREV_BCM5906, "unknown BCM5906" },
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{ BGE_ASICREV_BCM57765, "unknown BCM57765" },
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{ BGE_ASICREV_BCM57780, "unknown BCM57780" },
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{ BGE_ASICREV_BCM5717, "unknown BCM5717" },
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@ -1467,8 +1476,11 @@ bge_chipinit(struct bge_softc *sc)
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if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
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sc->bge_asicrev == BGE_ASICREV_BCM5704)
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dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
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if (BGE_IS_5717_PLUS(sc))
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if (BGE_IS_5717_PLUS(sc)) {
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dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
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if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
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dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
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}
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pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
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/*
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@ -1552,7 +1564,8 @@ bge_blockinit(struct bge_softc *sc)
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}
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/* Configure mbuf pool watermarks */
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if (sc->bge_asicrev == BGE_ASICREV_BCM5717) {
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if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
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sc->bge_asicrev == BGE_ASICREV_BCM57765) {
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
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if (sc->bge_ifp->if_mtu > ETHERMTU) {
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CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
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@ -1819,7 +1832,8 @@ bge_blockinit(struct bge_softc *sc)
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limit = 16;
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} else if (!BGE_IS_5705_PLUS(sc))
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limit = BGE_RX_RINGS_MAX;
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else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
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else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
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sc->bge_asicrev == BGE_ASICREV_BCM57765)
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limit = 4;
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else
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limit = 1;
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@ -2180,6 +2194,15 @@ bge_probe(device_t dev)
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id = pci_read_config(dev,
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BGE_PCI_GEN2_PRODID_ASICREV, 4);
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break;
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case BCOM_DEVICEID_BCM57761:
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case BCOM_DEVICEID_BCM57765:
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case BCOM_DEVICEID_BCM57781:
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case BCOM_DEVICEID_BCM57785:
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case BCOM_DEVICEID_BCM57791:
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case BCOM_DEVICEID_BCM57795:
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id = pci_read_config(dev,
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BGE_PCI_GEN15_PRODID_ASICREV, 4);
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break;
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default:
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id = pci_read_config(dev,
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BGE_PCI_PRODID_ASICREV, 4);
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@ -2694,6 +2717,15 @@ bge_attach(device_t dev)
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sc->bge_chipid = pci_read_config(dev,
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BGE_PCI_GEN2_PRODID_ASICREV, 4);
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break;
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case BCOM_DEVICEID_BCM57761:
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case BCOM_DEVICEID_BCM57765:
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case BCOM_DEVICEID_BCM57781:
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case BCOM_DEVICEID_BCM57785:
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case BCOM_DEVICEID_BCM57791:
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case BCOM_DEVICEID_BCM57795:
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sc->bge_chipid = pci_read_config(dev,
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BGE_PCI_GEN15_PRODID_ASICREV, 4);
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break;
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default:
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sc->bge_chipid = pci_read_config(dev,
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BGE_PCI_PRODID_ASICREV, 4);
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@ -2750,9 +2782,11 @@ bge_attach(device_t dev)
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/* Save chipset family. */
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switch (sc->bge_asicrev) {
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case BGE_ASICREV_BCM5717:
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sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
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case BGE_ASICREV_BCM57765:
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sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
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BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
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BGE_FLAG_SHORT_DMA_BUG | BGE_FLAG_JUMBO_FRAME;
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BGE_FLAG_JUMBO_FRAME;
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break;
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case BGE_ASICREV_BCM5755:
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case BGE_ASICREV_BCM5761:
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@ -2801,6 +2835,7 @@ bge_attach(device_t dev)
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sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
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sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
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sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
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sc->bge_asicrev != BGE_ASICREV_BCM57765 &&
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sc->bge_asicrev != BGE_ASICREV_BCM57780) {
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if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
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sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
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@ -3466,6 +3501,9 @@ bge_reset(struct bge_softc *sc)
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device_printf(dev,
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"firmware handshake timed out, found 0x%08x\n",
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val);
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/* BCM57765 A0 needs additional time before accessing. */
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if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
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DELAY(10 * 1000); /* XXX */
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}
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/*
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@ -3506,7 +3544,7 @@ bge_reset(struct bge_softc *sc)
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/* XXX: Broadcom Linux driver. */
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if (sc->bge_flags & BGE_FLAG_PCIE &&
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sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
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!BGE_IS_5717_PLUS(sc) &&
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sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
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sc->bge_asicrev != BGE_ASICREV_BCM5785) {
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/* Enable Data FIFO protection. */
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@ -4739,7 +4777,10 @@ bge_init_locked(struct bge_softc *sc)
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* this number of frames, it will drop subsequent incoming
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* frames until the MBUF High Watermark is reached.
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*/
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CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
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if (sc->bge_asicrev == BGE_ASICREV_BCM57765)
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CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
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else
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CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
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/* Clear MAC statistics. */
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if (BGE_IS_5705_PLUS(sc))
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@ -223,6 +223,7 @@
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#define BGE_PCI_ISR_MBX_LO 0xB4
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#define BGE_PCI_PRODID_ASICREV 0xBC
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#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4
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#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC
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/* PCI Misc. Host control register */
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#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
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@ -318,6 +319,8 @@
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#define BGE_CHIPID_BCM57780_A1 0x57780001
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#define BGE_CHIPID_BCM5717_A0 0x05717000
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#define BGE_CHIPID_BCM5717_B0 0x05717100
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#define BGE_CHIPID_BCM57765_A0 0x57785000
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#define BGE_CHIPID_BCM57765_B0 0x57785100
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/* shorthand one */
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#define BGE_ASICREV(x) ((x) >> 12)
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@ -342,6 +345,7 @@
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#define BGE_ASICREV_BCM5761 0x5761
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#define BGE_ASICREV_BCM5784 0x5784
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#define BGE_ASICREV_BCM5785 0x5785
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#define BGE_ASICREV_BCM57765 0x57785
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#define BGE_ASICREV_BCM57780 0x57780
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/* chip revisions */
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@ -381,6 +385,8 @@
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#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24)
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#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28)
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#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380
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#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
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#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
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#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
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@ -2298,9 +2304,15 @@ struct bge_status_block {
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#define BCOM_DEVICEID_BCM5906 0x1712
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#define BCOM_DEVICEID_BCM5906M 0x1713
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#define BCOM_DEVICEID_BCM57760 0x1690
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#define BCOM_DEVICEID_BCM57761 0x16B0
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#define BCOM_DEVICEID_BCM57765 0x16B4
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#define BCOM_DEVICEID_BCM57780 0x1692
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#define BCOM_DEVICEID_BCM57781 0x16B1
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#define BCOM_DEVICEID_BCM57785 0x16B5
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#define BCOM_DEVICEID_BCM57788 0x1691
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#define BCOM_DEVICEID_BCM57790 0x1694
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#define BCOM_DEVICEID_BCM57791 0x16B2
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#define BCOM_DEVICEID_BCM57795 0x16B6
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/*
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* Alteon AceNIC PCI vendor/device ID.
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