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Use relaxed (write-only) memory barriers when writing some of queue index

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registers (for now on ISP2400+).  We never read those registers back and
AFAIK their semantics does not require any immediate reaction on write.
This commit is contained in:
mav 2013-11-10 23:48:16 +00:00
parent 963d7e1a2a
commit b5ebe2e35e
2 changed files with 42 additions and 0 deletions
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33
sys/dev/isp/isp_freebsd.h
View File

@ -459,6 +459,39 @@ default: \
break; \
}
#define MEMORYBARRIERW(isp, type, offset, size, chan) \
switch (type) { \
case SYNC_SFORDEV: \
{ \
struct isp_fc *fc = ISP_FC_PC(isp, chan); \
bus_dmamap_sync(fc->tdmat, fc->tdmap, \
BUS_DMASYNC_PREWRITE); \
break; \
} \
case SYNC_REQUEST: \
bus_dmamap_sync(isp->isp_osinfo.cdmat, \
isp->isp_osinfo.cdmap, BUS_DMASYNC_PREWRITE); \
break; \
case SYNC_SFORCPU: \
{ \
struct isp_fc *fc = ISP_FC_PC(isp, chan); \
bus_dmamap_sync(fc->tdmat, fc->tdmap, \
BUS_DMASYNC_POSTWRITE); \
break; \
} \
case SYNC_RESULT: \
bus_dmamap_sync(isp->isp_osinfo.cdmat, \
isp->isp_osinfo.cdmap, BUS_DMASYNC_POSTWRITE); \
break; \
case SYNC_REG: \
bus_space_barrier(isp->isp_osinfo.bus_tag, \
isp->isp_osinfo.bus_handle, offset, size, \
BUS_SPACE_BARRIER_WRITE); \
break; \
default: \
break; \
}
#define MBOX_ACQUIRE isp_mbox_acquire
#define MBOX_WAIT_COMPLETE isp_mbox_wait_complete
#define MBOX_NOTIFY_COMPLETE isp_mbox_notify_done

9
sys/dev/isp/isp_pci.c
View File

@ -1432,6 +1432,15 @@ isp_pci_wr_reg_2400(ispsoftc_t *isp, int regoff, uint32_t val)
case BIU2400_GPIOE:
case BIU2400_HSEMA:
BXW4(isp, IspVirt2Off(isp, regoff), val);
#ifdef MEMORYBARRIERW
if (regoff == BIU2400_REQINP ||
regoff == BIU2400_RSPOUTP ||
regoff == BIU2400_PRI_REQINP ||
regoff == BIU2400_ATIO_RSPOUTP)
MEMORYBARRIERW(isp, SYNC_REG,
IspVirt2Off(isp, regoff), 4, -1)
else
#endif
MEMORYBARRIER(isp, SYNC_REG, IspVirt2Off(isp, regoff), 4, -1);
break;
default: