Merge in rev 1.2 which provides some FreeBSD a.out support.
This commit is contained in:
obrien
parent
c38b722874
commit
b64c124edf
@ -1,5 +1,6 @@
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/* tc-i386.h -- Header file for tc-i386.c
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Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.
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Copyright (C) 1989, 92, 93, 94, 95, 96, 97, 98, 99, 2000
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Free Software Foundation.
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This file is part of GAS, the GNU Assembler.
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@ -18,6 +19,8 @@
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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/* $FreeBSD$ */
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#ifndef TC_I386
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#define TC_I386 1
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@ -37,11 +40,6 @@ struct fix;
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type. The idea is that if the original type is already some kind of PIC
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relocation, we leave it alone, otherwise we give it the desired type */
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#define TC_RELOC(X,Y) (((X) != BFD_RELOC_386_PLT32 && \
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(X) != BFD_RELOC_386_GOTOFF && \
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(X) != BFD_RELOC_386_GOT32 && \
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(X) != BFD_RELOC_386_GOTPC) ? Y : X)
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#define tc_fix_adjustable(X) tc_i386_fix_adjustable(X)
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extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
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@ -61,45 +59,51 @@ extern int tc_i386_fix_adjustable PARAMS ((struct fix *));
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checked here. I am not sure if some of the others are ever used with
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pcrel, but it is easier to be safe than sorry. */
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#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
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((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \
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&& (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \
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&& (FIX)->fx_r_type != BFD_RELOC_386_GOTPC)
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#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
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((FIX)->fx_r_type != BFD_RELOC_386_PLT32 \
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&& (FIX)->fx_r_type != BFD_RELOC_386_GOT32 \
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&& (FIX)->fx_r_type != BFD_RELOC_386_GOTPC \
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&& ((FIX)->fx_addsy == NULL \
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|| (! S_IS_EXTERNAL ((FIX)->fx_addsy) \
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&& ! S_IS_WEAK ((FIX)->fx_addsy) \
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&& S_IS_DEFINED ((FIX)->fx_addsy) \
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&& ! S_IS_COMMON ((FIX)->fx_addsy))))
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#define TARGET_ARCH bfd_arch_i386
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#ifdef OBJ_AOUT
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#ifdef TE_FreeBSD
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#define TARGET_FORMAT "a.out-i386-freebsd"
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#define AOUT_TARGET_FORMAT "a.out-i386-freebsd"
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#endif
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#ifdef TE_NetBSD
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#define TARGET_FORMAT "a.out-i386-netbsd"
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#define AOUT_TARGET_FORMAT "a.out-i386-netbsd"
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#endif
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#ifdef TE_386BSD
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#define TARGET_FORMAT "a.out-i386-bsd"
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#define AOUT_TARGET_FORMAT "a.out-i386-bsd"
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#endif
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#ifdef TE_LINUX
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#define TARGET_FORMAT "a.out-i386-linux"
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#define AOUT_TARGET_FORMAT "a.out-i386-linux"
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#endif
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#ifdef TE_Mach
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#define TARGET_FORMAT "a.out-mach3"
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#define AOUT_TARGET_FORMAT "a.out-mach3"
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#endif
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#ifdef TE_DYNIX
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#define TARGET_FORMAT "a.out-i386-dynix"
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#define AOUT_TARGET_FORMAT "a.out-i386-dynix"
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#endif
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#ifndef TARGET_FORMAT
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#define TARGET_FORMAT "a.out-i386"
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#ifndef AOUT_TARGET_FORMAT
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#define AOUT_TARGET_FORMAT "a.out-i386"
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#endif
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#endif /* OBJ_AOUT */
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#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
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|| (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
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|| (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
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extern const char *i386_target_format PARAMS ((void));
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#define TARGET_FORMAT i386_target_format ()
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#else
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#ifdef OBJ_ELF
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#define TARGET_FORMAT "elf32-i386"
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#endif
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#ifdef OBJ_MAYBE_ELF
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#ifdef OBJ_MAYBE_COFF
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extern const char *i386_target_format PARAMS ((void));
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#define TARGET_FORMAT i386_target_format ()
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#ifdef OBJ_AOUT
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#define TARGET_FORMAT AOUT_TARGET_FORMAT
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#endif
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#endif
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@ -111,12 +115,26 @@ extern const char *i386_target_format PARAMS ((void));
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#define BFD_ARCH bfd_arch_i386
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#define COFF_FLAGS F_AR32WR
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#define TC_COUNT_RELOC(x) ((x)->fx_addsy || (x)->fx_r_type==7)
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#define TC_FORCE_RELOCATION(x) ((x)->fx_r_type==7)
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#define TC_COFF_FIX2RTYPE(fixP) tc_coff_fix2rtype(fixP)
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extern short tc_coff_fix2rtype PARAMS ((struct fix *));
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#define TC_COFF_SIZEMACHDEP(frag) tc_coff_sizemachdep(frag)
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extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
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#ifdef TE_GO32
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/* DJGPP now expects some sections to be 2**4 aligned. */
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#define SUB_SEGMENT_ALIGN(SEG) \
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((strcmp (obj_segment_name (SEG), ".text") == 0 \
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|| strcmp (obj_segment_name (SEG), ".data") == 0 \
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|| strcmp (obj_segment_name (SEG), ".bss") == 0 \
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|| strncmp (obj_segment_name (SEG), ".gnu.linkonce.t", 15) == 0 \
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|| strncmp (obj_segment_name (SEG), ".gnu.linkonce.d", 15) == 0 \
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|| strncmp (obj_segment_name (SEG), ".gnu.linkonce.r", 15) == 0) \
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? 4 \
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: 2)
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#else
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#define SUB_SEGMENT_ALIGN(SEG) 2
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#endif
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#define TC_RVA_RELOC 7
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/* Need this for PIC relocations */
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#define NEED_FX_R_TYPE
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@ -134,6 +152,9 @@ extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
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#endif /* ! BFD_ASSEMBLER */
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#define TC_FORCE_RELOCATION(fixp) tc_i386_force_relocation(fixp)
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extern int tc_i386_force_relocation PARAMS ((struct fix *));
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#ifdef BFD_ASSEMBLER
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#define NO_RELOC BFD_RELOC_NONE
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#else
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@ -144,12 +165,14 @@ extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
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#ifndef BFD_ASSEMBLER
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#ifndef OBJ_AOUT
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#ifndef TE_PE
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#ifndef TE_GO32
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/* Local labels starts with .L */
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#define LOCAL_LABEL(name) (name[0] == '.' \
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&& (name[1] == 'L' || name[1] == 'X' || name[1] == '.'))
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#endif
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#endif
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#endif
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#endif
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#define LOCAL_LABELS_FB 1
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@ -157,16 +180,27 @@ extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
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#define tc_crawl_symbol_chain(a) {;} /* not used */
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#define tc_headers_hook(a) {;} /* not used */
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extern const char extra_symbol_chars[];
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#define tc_symbol_chars extra_symbol_chars
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#define MAX_OPERANDS 3 /* max operands per insn */
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#define MAX_PREFIXES 5 /* max prefixes per opcode */
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#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn */
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#define MAX_MEMORY_OPERANDS 2 /* max memory ref per insn (lcall uses 2) */
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#define MAX_IMMEDIATE_OPERANDS 2/* max immediates per insn (lcall, ljmp) */
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#define MAX_MEMORY_OPERANDS 2 /* max memory refs per insn (string ops) */
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/* Prefixes will be emitted in the order defined below.
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WAIT_PREFIX must be the first prefix since FWAIT is really is an
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instruction, and so must come before any prefixes. */
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#define WAIT_PREFIX 0
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#define LOCKREP_PREFIX 1
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#define ADDR_PREFIX 2
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#define DATA_PREFIX 3
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#define SEG_PREFIX 4
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#define MAX_PREFIXES 5 /* max prefixes per opcode */
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/* we define the syntax here (modulo base,index,scale syntax) */
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#define REGISTER_PREFIX '%'
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#define IMMEDIATE_PREFIX '$'
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#define ABSOLUTE_PREFIX '*'
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#define PREFIX_SEPERATOR '/'
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#define TWO_BYTE_OPCODE_ESCAPE 0x0f
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#define NOP_OPCODE (char) 0x90
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@ -181,11 +215,17 @@ extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
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#define NO_INDEX_REGISTER ESP_REG_NUM
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/* index_base_byte.base for no base register addressing */
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#define NO_BASE_REGISTER EBP_REG_NUM
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#define NO_BASE_REGISTER_16 6
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/* these are the att as opcode suffixes, making movl --> mov, for example */
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#define DWORD_OPCODE_SUFFIX 'l'
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#define WORD_OPCODE_SUFFIX 'w'
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#define BYTE_OPCODE_SUFFIX 'b'
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/* these are the instruction mnemonic suffixes. */
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#define WORD_MNEM_SUFFIX 'w'
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#define BYTE_MNEM_SUFFIX 'b'
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#define SHORT_MNEM_SUFFIX 's'
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#define LONG_MNEM_SUFFIX 'l'
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/* Intel Syntax */
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#define LONG_DOUBLE_MNEM_SUFFIX 'x'
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/* Intel Syntax */
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#define DWORD_MNEM_SUFFIX 'd'
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/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */
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#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */
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@ -193,67 +233,88 @@ extern int tc_coff_sizemachdep PARAMS ((fragS *frag));
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#define END_OF_INSN '\0'
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/* Intel Syntax */
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/* Values 0-4 map onto scale factor */
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#define BYTE_PTR 0
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#define WORD_PTR 1
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#define DWORD_PTR 2
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#define QWORD_PTR 3
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#define XWORD_PTR 4
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#define SHORT 5
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#define OFFSET_FLAT 6
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#define FLAT 7
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#define NONE_FOUND 8
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/*
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When an operand is read in it is classified by its type. This type includes
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all the possible ways an operand can be used. Thus, '%eax' is both 'register
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# 0' and 'The Accumulator'. In our language this is expressed by OR'ing
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'Reg32' (any 32 bit register) and 'Acc' (the accumulator).
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Operands are classified so that we can match given operand types with
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the opcode table in i386-opcode.h.
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the opcode table in opcode/i386.h.
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*/
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#define Unknown 0x0
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/* register */
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#define Reg8 0x1 /* 8 bit reg */
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#define Reg16 0x2 /* 16 bit reg */
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#define Reg32 0x4 /* 32 bit reg */
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#define Reg (Reg8|Reg16|Reg32) /* gen'l register */
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#define WordReg (Reg16|Reg32) /* for push/pop operands */
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#define Reg8 0x1 /* 8 bit reg */
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#define Reg16 0x2 /* 16 bit reg */
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#define Reg32 0x4 /* 32 bit reg */
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/* immediate */
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#define Imm8 0x8 /* 8 bit immediate */
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#define Imm8S 0x10 /* 8 bit immediate sign extended */
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#define Imm16 0x20 /* 16 bit immediate */
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#define Imm32 0x40 /* 32 bit immediate */
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#define Imm1 0x80 /* 1 bit immediate */
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#define ImmUnknown Imm32 /* for unknown expressions */
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#define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
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#define Imm8 0x8 /* 8 bit immediate */
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#define Imm8S 0x10 /* 8 bit immediate sign extended */
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#define Imm16 0x20 /* 16 bit immediate */
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#define Imm32 0x40 /* 32 bit immediate */
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#define Imm1 0x80 /* 1 bit immediate */
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/* memory */
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#define Disp8 0x200 /* 8 bit displacement (for jumps) */
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#define Disp16 0x400 /* 16 bit displacement */
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#define Disp32 0x800 /* 32 bit displacement */
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#define Disp (Disp8|Disp16|Disp32) /* General displacement */
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#define DispUnknown Disp32 /* for unknown size displacements */
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#define Mem8 0x1000
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#define Mem16 0x2000
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#define Mem32 0x4000
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#define BaseIndex 0x8000
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#define Mem (Disp|Mem8|Mem16|Mem32|BaseIndex) /* General memory */
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#define WordMem (Mem16|Mem32|Disp|BaseIndex)
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#define ByteMem (Mem8|Disp|BaseIndex)
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#define BaseIndex 0x100
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/* Disp8,16,32 are used in different ways, depending on the
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instruction. For jumps, they specify the size of the PC relative
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displacement, for baseindex type instructions, they specify the
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size of the offset relative to the base register, and for memory
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offset instructions such as `mov 1234,%al' they specify the size of
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the offset relative to the segment base. */
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#define Disp8 0x200 /* 8 bit displacement */
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#define Disp16 0x400 /* 16 bit displacement */
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#define Disp32 0x800 /* 32 bit displacement */
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/* specials */
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#define InOutPortReg 0x10000 /* register to hold in/out port addr = dx */
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#define ShiftCount 0x20000 /* register to hold shift cound = cl */
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#define Control 0x40000 /* Control register */
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#define Debug 0x80000 /* Debug register */
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#define Test 0x100000 /* Test register */
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#define FloatReg 0x200000 /* Float register */
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#define FloatAcc 0x400000 /* Float stack top %st(0) */
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#define SReg2 0x800000 /* 2 bit segment register */
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#define SReg3 0x1000000 /* 3 bit segment register */
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#define Acc 0x2000000 /* Accumulator %al or %ax or %eax */
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#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
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#define JumpAbsolute 0x4000000
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#define Abs8 0x08000000
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#define Abs16 0x10000000
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#define Abs32 0x20000000
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#define Abs (Abs8|Abs16|Abs32)
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#define RegMMX 0x40000000 /* MMX register */
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#define InOutPortReg 0x1000 /* register to hold in/out port addr = dx */
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#define ShiftCount 0x2000 /* register to hold shift cound = cl */
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#define Control 0x4000 /* Control register */
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#define Debug 0x8000 /* Debug register */
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#define Test 0x10000 /* Test register */
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#define FloatReg 0x20000 /* Float register */
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#define FloatAcc 0x40000 /* Float stack top %st(0) */
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#define SReg2 0x80000 /* 2 bit segment register */
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#define SReg3 0x100000 /* 3 bit segment register */
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#define Acc 0x200000 /* Accumulator %al or %ax or %eax */
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#define JumpAbsolute 0x400000
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#define RegMMX 0x800000 /* MMX register */
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#define RegXMM 0x1000000 /* XMM registers in PIII */
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#define EsSeg 0x2000000 /* String insn operand with fixed es segment */
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/* InvMem is for instructions with a modrm byte that only allow a
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general register encoding in the i.tm.mode and i.tm.regmem fields,
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eg. control reg moves. They really ought to support a memory form,
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but don't, so we add an InvMem flag to the register operand to
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indicate that it should be encoded in the i.tm.regmem field. */
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#define InvMem 0x4000000
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#define Byte (Reg8|Imm8|Imm8S)
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#define Word (Reg16|Imm16)
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#define DWord (Reg32|Imm32)
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#define Reg (Reg8|Reg16|Reg32) /* gen'l register */
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#define WordReg (Reg16|Reg32)
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#define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
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#define Imm (Imm8|Imm8S|Imm16|Imm32) /* gen'l immediate */
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#define Disp (Disp8|Disp16|Disp32) /* General displacement */
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#define AnyMem (Disp|BaseIndex|InvMem) /* General memory */
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/* The following aliases are defined because the opcode table
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carefully specifies the allowed memory types for each instruction.
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At the moment we can only tell a memory reference size by the
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instruction suffix, so there's not much point in defining Mem8,
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Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
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the suffix directly to check memory operands. */
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#define LLongMem AnyMem /* 64 bits (or more) */
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#define LongMem AnyMem /* 32 bit memory ref */
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#define ShortMem AnyMem /* 16 bit memory ref */
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#define WordMem AnyMem /* 16 or 32 bit memory ref */
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#define ByteMem AnyMem /* 8 bit memory ref */
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#define SMALLEST_DISP_TYPE(num) \
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fits_in_signed_byte(num) ? (Disp8|Disp32|Abs8|Abs32) : (Disp32|Abs32)
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(fits_in_signed_byte(num) ? (Disp8|Disp32) : Disp32)
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typedef struct
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{
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@ -263,13 +324,16 @@ typedef struct
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/* how many operands */
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unsigned int operands;
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/* base_opcode is the fundamental opcode byte with a optional prefix(es). */
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/* base_opcode is the fundamental opcode byte without optional
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prefix(es). */
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unsigned int base_opcode;
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/* extension_opcode is the 3 bit extension for group <n> insns.
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This field is also used to store the 8-bit opcode suffix for the
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AMD 3DNow! instructions.
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If this template has no extension opcode (the usual case) use None */
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unsigned char extension_opcode;
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#define None 0xff /* If no extension_opcode is possible. */
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unsigned int extension_opcode;
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#define None 0xffff /* If no extension_opcode is possible. */
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/* the bits in opcode_modifier are used to generate the final opcode from
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the base_opcode. These bits also are used to detect alternate forms of
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@ -277,41 +341,37 @@ typedef struct
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unsigned int opcode_modifier;
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/* opcode_modifier bits: */
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#define W 0x1 /* set if operands are words or dwords */
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#define D 0x2 /* D = 0 if Reg --> Regmem; D = 1 if Regmem --> Reg */
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/* direction flag for floating insns: MUST BE 0x400 */
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#define FloatD 0x400
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/* shorthand */
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#define DW (D|W)
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#define ShortForm 0x10 /* register is in low 3 bits of opcode */
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#define ShortFormW 0x20 /* ShortForm and W bit is 0x8 */
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#define Seg2ShortForm 0x40 /* encoding of load segment reg insns */
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#define Seg3ShortForm 0x80 /* fs/gs segment register insns. */
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#define Jump 0x100 /* special case for jump insns. */
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#define W 0x1 /* set if operands can be words or dwords
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encoded the canonical way */
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#define D 0x2 /* D = 0 if Reg --> Regmem;
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D = 1 if Regmem --> Reg: MUST BE 0x2 */
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#define Modrm 0x4
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#define FloatR 0x8 /* src/dest swap for floats: MUST BE 0x8 */
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#define ShortForm 0x10 /* register is in low 3 bits of opcode */
|
||||
#define FloatMF 0x20 /* FP insn memory format bit, sized by 0x4 */
|
||||
#define Jump 0x40 /* special case for jump insns. */
|
||||
#define JumpDword 0x80 /* call and jump */
|
||||
#define JumpByte 0x100 /* loop and jecxz */
|
||||
#define JumpInterSegment 0x200 /* special case for intersegment leaps/calls */
|
||||
/* 0x400 CANNOT BE USED since it's already used by FloatD above */
|
||||
#define DONT_USE 0x400
|
||||
#define NoModrm 0x800
|
||||
#define Modrm 0x1000
|
||||
#define imulKludge 0x2000
|
||||
#define JumpByte 0x4000
|
||||
#define JumpDword 0x8000
|
||||
#define ReverseRegRegmem 0x10000
|
||||
#define Data16 0x20000 /* needs data prefix if in 32-bit mode */
|
||||
#define Data32 0x40000 /* needs data prefix if in 16-bit mode */
|
||||
#define iclrKludge 0x80000 /* used to convert clr to xor */
|
||||
#define FWait 0x100000 /* instruction needs FWAIT */
|
||||
|
||||
/* (opcode_modifier & COMES_IN_ALL_SIZES) is true if the
|
||||
instuction comes in byte, word, and dword sizes and is encoded into
|
||||
machine code in the canonical way. */
|
||||
#define COMES_IN_ALL_SIZES (W)
|
||||
|
||||
/* (opcode_modifier & COMES_IN_BOTH_DIRECTIONS) indicates that the
|
||||
source and destination operands can be reversed by setting either
|
||||
the D (for integer insns) or the FloatD (for floating insns) bit
|
||||
in base_opcode. */
|
||||
#define COMES_IN_BOTH_DIRECTIONS (D|FloatD)
|
||||
#define FloatD 0x400 /* direction for float insns: MUST BE 0x400 */
|
||||
#define Seg2ShortForm 0x800 /* encoding of load segment reg insns */
|
||||
#define Seg3ShortForm 0x1000 /* fs/gs segment register insns. */
|
||||
#define Size16 0x2000 /* needs size prefix if in 32-bit mode */
|
||||
#define Size32 0x4000 /* needs size prefix if in 16-bit mode */
|
||||
#define IgnoreSize 0x8000 /* instruction ignores operand size prefix */
|
||||
#define DefaultSize 0x10000 /* default insn size depends on mode */
|
||||
#define No_bSuf 0x20000 /* b suffix on instruction illegal */
|
||||
#define No_wSuf 0x40000 /* w suffix on instruction illegal */
|
||||
#define No_lSuf 0x80000 /* l suffix on instruction illegal */
|
||||
#define No_sSuf 0x100000 /* s suffix on instruction illegal */
|
||||
#define No_dSuf 0x200000 /* d suffix on instruction illegal */
|
||||
#define No_xSuf 0x400000 /* x suffix on instruction illegal */
|
||||
#define FWait 0x800000 /* instruction needs FWAIT */
|
||||
#define IsString 0x1000000 /* quick test for string instructions */
|
||||
#define regKludge 0x2000000 /* fake an extra reg operand for clr, imul */
|
||||
#define IsPrefix 0x4000000 /* opcode is a prefix */
|
||||
#define ImmExt 0x8000000 /* instruction has extension in 8 bit imm */
|
||||
#define Ugh 0x80000000 /* deprecated fp insn, gets a warning */
|
||||
|
||||
/* operand_types[i] describes the type of operand i. This is made
|
||||
by OR'ing together all of the possible type masks. (e.g.
|
||||
@ -330,8 +390,8 @@ template;
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
template *start;
|
||||
template *end;
|
||||
const template *start;
|
||||
const template *end;
|
||||
} templates;
|
||||
|
||||
/* these are for register name --> number & type hash lookup */
|
||||
@ -341,7 +401,6 @@ typedef struct
|
||||
unsigned int reg_type;
|
||||
unsigned int reg_num;
|
||||
}
|
||||
|
||||
reg_entry;
|
||||
|
||||
typedef struct
|
||||
@ -349,37 +408,25 @@ typedef struct
|
||||
char *seg_name;
|
||||
unsigned int seg_prefix;
|
||||
}
|
||||
|
||||
seg_entry;
|
||||
|
||||
/* these are for prefix name --> prefix code hash lookup */
|
||||
typedef struct
|
||||
{
|
||||
char *prefix_name;
|
||||
unsigned char prefix_code;
|
||||
}
|
||||
|
||||
prefix_entry;
|
||||
|
||||
/* 386 operand encoding bytes: see 386 book for details of this. */
|
||||
typedef struct
|
||||
{
|
||||
unsigned regmem:3; /* codes register or memory operand */
|
||||
unsigned reg:3; /* codes register operand (or extended opcode) */
|
||||
unsigned mode:2; /* how to interpret regmem & reg */
|
||||
unsigned int regmem; /* codes register or memory operand */
|
||||
unsigned int reg; /* codes register operand (or extended opcode) */
|
||||
unsigned int mode; /* how to interpret regmem & reg */
|
||||
}
|
||||
|
||||
modrm_byte;
|
||||
|
||||
/* 386 opcode byte to code indirect addressing. */
|
||||
typedef struct
|
||||
{
|
||||
unsigned base:3;
|
||||
unsigned index:3;
|
||||
unsigned scale:2;
|
||||
unsigned base;
|
||||
unsigned index;
|
||||
unsigned scale;
|
||||
}
|
||||
|
||||
base_index_byte;
|
||||
sib_byte;
|
||||
|
||||
/* The name of the global offset table generated by the compiler. Allow
|
||||
this to be overridden if need be. */
|
||||
@ -399,21 +446,10 @@ void i386_validate_fix PARAMS ((struct fix *));
|
||||
extern const struct relax_type md_relax_table[];
|
||||
#define TC_GENERIC_RELAX_TABLE md_relax_table
|
||||
|
||||
|
||||
extern int flag_16bit_code;
|
||||
|
||||
#ifdef BFD_ASSEMBLER
|
||||
#define md_maybe_text() \
|
||||
((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
|
||||
#else
|
||||
#define md_maybe_text() \
|
||||
(now_seg != data_section && now_seg != bss_section)
|
||||
#endif
|
||||
|
||||
#define md_do_align(n, fill, len, max, around) \
|
||||
if ((n) && !need_pass_2 \
|
||||
&& (!(fill) || ((char)*(fill) == (char)0x90 && (len) == 1)) \
|
||||
&& md_maybe_text ()) \
|
||||
&& subseg_text_p (now_seg)) \
|
||||
{ \
|
||||
char *p; \
|
||||
p = frag_var (rs_align_code, 15, 1, (relax_substateT) max, \
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user