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Some devices (e.g. Intel AHCI and NICs) support quad-word access to

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register pairs where two 32-bit registers make up a larger logical
size.  Support those access by splitting the quad-word into two
double-words.

Reviewed by:	grehan
This commit is contained in:
Tycho Nightingale 2014-06-06 16:18:37 +00:00
parent 9225c8085b
commit b6ae8b050b
1 changed files with 21 additions and 4 deletions
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25
usr.sbin/bhyve/pci_emul.c
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@ -375,10 +375,27 @@ pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
offset = addr - pdi->pi_bar[bidx].addr;
if (dir == MEM_F_WRITE)
(*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, size, *val);
else
*val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, offset, size);
if (dir == MEM_F_WRITE) {
if (pdi->pi_bar[bidx].type == PCIBAR_MEM32 && size == 8) {
(*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
4, *val & 0xffffffff);
(*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4,
4, *val >> 32);
} else {
(*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset,
size, *val);
}
} else {
if (pdi->pi_bar[bidx].type == PCIBAR_MEM32 && size == 8) {
*val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
offset, 4);
*val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
offset + 4, 4) << 32;
} else {
*val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx,
offset, size);
}
}
return (0);
}