- Updated support for 5716.
- Added some additional code for debug builds. - Fixed a problem printing physical memory on 64bit system during debugging. - Modified some of the context memory and mailbox register names to more clearly distinguish their use. - Added memory barriers for Intel CPUs when accessing host memory data structures which are written by hardware. MFC after: Two weeks.
This commit is contained in:
David Christensen
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@ -557,6 +557,15 @@
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#endif /* BCE_DEBUG */
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#if defined(__i386__) || defined(__amd64__)
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#define mb() __asm volatile("mfence" ::: "memory")
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#define wmb() __asm volatile("sfence" ::: "memory")
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#define rmb() __asm volatile("lfence" ::: "memory")
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#else
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#define mb()
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#define rmb()
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#define wmb()
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#endif
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/****************************************************************************/
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/* Device identification definitions. */
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@ -568,7 +577,7 @@
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#define BRCM_DEVICEID_BCM5708S 0x16AC
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#define BRCM_DEVICEID_BCM5709 0x1639
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#define BRCM_DEVICEID_BCM5709S 0x163A
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#define BRCM_DEVICEID_BCM5716 0x1654
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#define BRCM_DEVICEID_BCM5716 0x163B
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#define HP_VENDORID 0x103C
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@ -1396,75 +1405,104 @@ struct l2_fhdr {
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/*
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* l2_context definition
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* l2_tx_context definition (5706 and 5708)
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*/
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#define BCE_L2CTX_TYPE 0x00000000
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#define BCE_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
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#define BCE_L2CTX_TYPE_TYPE (0xf<<28)
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#define BCE_L2CTX_TYPE_TYPE_EMPTY (0<<28)
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#define BCE_L2CTX_TYPE_TYPE_L2 (1<<28)
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#define BCE_L2CTX_TX_TYPE 0x00000000
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#define BCE_L2CTX_TX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
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#define BCE_L2CTX_TX_TYPE_TYPE (0xf<<28)
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#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY (0<<28)
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#define BCE_L2CTX_TX_TYPE_TYPE_L2 (1<<28)
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#define BCE_L2CTX_TYPE_XI 0x00000080
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#define BCE_L2CTX_TX_HOST_BIDX 0x00000088
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#define BCE_L2CTX_EST_NBD 0x00000088
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#define BCE_L2CTX_CMD_TYPE 0x00000088
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#define BCE_L2CTX_CMD_TYPE_TYPE (0xf<<24)
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#define BCE_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
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#define BCE_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
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#define BCE_L2CTX_TX_HOST_BIDX 0x00000088
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#define BCE_L2CTX_TX_EST_NBD 0x00000088
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#define BCE_L2CTX_TX_CMD_TYPE 0x00000088
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#define BCE_L2CTX_TX_CMD_TYPE_TYPE (0xf<<24)
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#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 (0<<24)
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#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP (1<<24)
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#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090
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#define BCE_L2CTX_TSCH_BSEQ 0x00000094
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#define BCE_L2CTX_TBDR_BSEQ 0x00000098
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#define BCE_L2CTX_TBDR_BOFF 0x0000009c
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#define BCE_L2CTX_TBDR_BIDX 0x0000009c
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#define BCE_L2CTX_TBDR_BHADDR_HI 0x000000a0
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#define BCE_L2CTX_TBDR_BHADDR_LO 0x000000a4
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#define BCE_L2CTX_TXP_BOFF 0x000000a8
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#define BCE_L2CTX_TXP_BIDX 0x000000a8
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#define BCE_L2CTX_TXP_BSEQ 0x000000ac
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#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090
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#define BCE_L2CTX_TX_TSCH_BSEQ 0x00000094
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#define BCE_L2CTX_TX_TBDR_BSEQ 0x00000098
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#define BCE_L2CTX_TX_TBDR_BOFF 0x0000009c
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#define BCE_L2CTX_TX_TBDR_BIDX 0x0000009c
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#define BCE_L2CTX_TX_TBDR_BHADDR_HI 0x000000a0
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#define BCE_L2CTX_TX_TBDR_BHADDR_LO 0x000000a4
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#define BCE_L2CTX_TX_TXP_BOFF 0x000000a8
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#define BCE_L2CTX_TX_TXP_BIDX 0x000000a8
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#define BCE_L2CTX_TX_TXP_BSEQ 0x000000ac
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#define BCE_L2CTX_CMD_TYPE_XI 0x00000240
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#define BCE_L2CTX_TBDR_BHADDR_HI_XI 0x00000258
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#define BCE_L2CTX_TBDR_BHADDR_LO_XI 0x0000025c
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/*
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* l2_tx_context definition (5709 and 5716)
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*/
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#define BCE_L2CTX_TX_TYPE_XI 0x00000080
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#define BCE_L2CTX_TX_TYPE_SIZE_L2_XI ((0xc0/0x20)<<16)
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#define BCE_L2CTX_TX_TYPE_TYPE_XI (0xf<<28)
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#define BCE_L2CTX_TX_TYPE_TYPE_EMPTY_XI (0<<28)
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#define BCE_L2CTX_TX_TYPE_TYPE_L2_XI (1<<28)
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#define BCE_L2CTX_TX_CMD_TYPE_XI 0x00000240
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#define BCE_L2CTX_TX_CMD_TYPE_TYPE_XI (0xf<<24)
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#define BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI (0<<24)
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#define BCE_L2CTX_TX_CMD_TYPE_TYPE_TCP_XI (1<<24)
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#define BCE_L2CTX_TX_HOST_BIDX_XI 0x00000240
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#define BCE_L2CTX_TX_HOST_BSEQ_XI 0x00000248
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#define BCE_L2CTX_TX_TBDR_BHADDR_HI_XI 0x00000258
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#define BCE_L2CTX_TX_TBDR_BHADDR_LO_XI 0x0000025c
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/*
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* l2_bd_chain_context definition
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* l2_rx_context definition (5706, 5708, 5709, and 5716)
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*/
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#define BCE_L2CTX_BD_PRE_READ 0x00000000
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#define BCE_L2CTX_CTX_SIZE 0x00000000
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#define BCE_L2CTX_CTX_TYPE 0x00000000
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#define BCE_L2CTX_LO_WATER_MARK_DEFAULT 32
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#define BCE_L2CTX_LO_WATER_MARK_SCALE 4
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#define BCE_L2CTX_LO_WATER_MARK_DIS 0
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#define BCE_L2CTX_HI_WATER_MARK_SHIFT 4
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#define BCE_L2CTX_HI_WATER_MARK_SCALE 16
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#define BCE_L2CTX_WATER_MARKS_MSK 0x000000ff
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#define BCE_L2CTX_RX_WATER_MARK 0x00000000
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#define BCE_L2CTX_RX_LO_WATER_MARK_SHIFT 0
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#define BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT 32
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#define BCE_L2CTX_RX_LO_WATER_MARK_SCALE 4
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#define BCE_L2CTX_RX_LO_WATER_MARK_DIS 0
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#define BCE_L2CTX_RX_HI_WATER_MARK_SHIFT 4
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#define BCE_L2CTX_RX_HI_WATER_MARK_SCALE 16
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#define BCE_L2CTX_RX_WATER_MARKS_MSK 0x000000ff
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#define BCE_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
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#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
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#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
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#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
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#define BCE_L2CTX_RX_BD_PRE_READ 0x00000000
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#define BCE_L2CTX_RX_BD_PRE_READ_SHIFT 8
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#define BCE_L2CTX_HOST_BDIDX 0x00000004
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#define BCE_L2CTX_HOST_BSEQ 0x00000008
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#define BCE_L2CTX_NX_BSEQ 0x0000000c
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#define BCE_L2CTX_NX_BDHADDR_HI 0x00000010
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#define BCE_L2CTX_NX_BDHADDR_LO 0x00000014
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#define BCE_L2CTX_NX_BDIDX 0x00000018
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#define BCE_L2CTX_RX_CTX_SIZE 0x00000000
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#define BCE_L2CTX_RX_CTX_SIZE_SHIFT 16
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#define BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 ((0x20/20)<<BCE_L2CTX_RX_CTX_SIZE_SHIFT)
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/* Page Buffer Descriptor Index */
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#define BCE_L2CTX_HOST_PG_BDIDX 0x00000044
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/* SKB and Page Buffer Size */
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#define BCE_L2CTX_PG_BUF_SIZE 0x00000048
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/* Page Chain BD Context */
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#define BCE_L2CTX_RBDC_KEY 0x0000004c
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#define BCE_L2CTX_RBDC_JUMBO_KEY 0x3ffe
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/* Page Chain Next BD Host Address */
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#define BCE_L2CTX_NX_PG_BDHADDR_HI 0x00000050
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#define BCE_L2CTX_NX_PG_BDHADDR_LO 0x00000054
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#define BCE_L2CTX_NX_PG_BDIDX 0x00000058
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#define BCE_L2CTX_RX_CTX_TYPE 0x00000000
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#define BCE_L2CTX_RX_CTX_TYPE_SHIFT 24
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#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
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#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
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#define BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
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#define BCE_L2CTX_RX_HOST_BDIDX 0x00000004
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#define BCE_L2CTX_RX_HOST_BSEQ 0x00000008
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#define BCE_L2CTX_RX_NX_BSEQ 0x0000000c
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#define BCE_L2CTX_RX_NX_BDHADDR_HI 0x00000010
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#define BCE_L2CTX_RX_NX_BDHADDR_LO 0x00000014
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#define BCE_L2CTX_RX_NX_BDIDX 0x00000018
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#define BCE_L2CTX_RX_HOST_PG_BDIDX 0x00000044
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#define BCE_L2CTX_RX_PG_BUF_SIZE 0x00000048
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#define BCE_L2CTX_RX_RBDC_KEY 0x0000004c
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#define BCE_L2CTX_RX_RBDC_JUMBO_KEY 0x3ffe
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#define BCE_L2CTX_RX_NX_PG_BDHADDR_HI 0x00000050
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#define BCE_L2CTX_RX_NX_PG_BDHADDR_LO 0x00000054
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#define BCE_L2CTX_RX_NX_PG_BDIDX 0x00000058
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/*
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* l2_mq definitions (5706, 5708, 5709, and 5716)
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*/
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#define BCE_L2MQ_RX_HOST_BDIDX 0x00000004
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#define BCE_L2MQ_RX_HOST_BSEQ 0x00000008
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#define BCE_L2MQ_RX_HOST_PG_BDIDX 0x00000044
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#define BCE_L2MQ_TX_HOST_BIDX 0x00000088
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#define BCE_L2MQ_TX_HOST_BSEQ 0x00000090
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/*
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* pci_config_l definition
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@ -6477,10 +6515,6 @@ struct bce_softc
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/* Receive mode settings (i.e promiscuous, multicast, etc.). */
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u32 rx_mode;
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#ifdef DEVICE_POLLING
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int bce_rxcycles; /* Counter for receive polling cycles */
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#endif
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/* Bus tag for the bce controller. */
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bus_dma_tag_t parent_tag;
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