[rt305x] add register space definitions for later generation chips.
This adds definitions for the MT5350 and MT7620 SoCs. Submitted by: Stanislav Galabov <galabov@gmail.com>
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@ -1,4 +1,5 @@
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/*-
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* Copyright (c) 2015 Stanislav Galabov.
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* Copyright (c) 2010 Aleksandr Rybalko.
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* All rights reserved.
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*
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@ -29,12 +30,7 @@
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#ifndef _RT305XREG_H_
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#define _RT305XREG_H_
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/* XXX: must move to config */
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#define RT305X 1
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#define RT305XF 1
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#define RT3052F 1
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#define __U_BOOT__ 1
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/* XXX: must move to config */
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#include "opt_rt305x.h"
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#ifdef RT3052F
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#define PLATFORM_COUNTER_FREQ (384 * 1000 * 1000)
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@ -42,12 +38,19 @@
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#ifdef RT3050F
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#define PLATFORM_COUNTER_FREQ (320 * 1000 * 1000)
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#endif
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#ifdef MT7620
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#define PLATFORM_COUNTER_FREQ (580 * 1000 * 1000)
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#endif
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#ifdef RT5350
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#define PLATFORM_COUNTER_FREQ (360 * 1000 * 1000)
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#endif
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#ifndef PLATFORM_COUNTER_FREQ
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#error "Nor RT3052F nor RT3050F defined"
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#error "No platform selected"
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#endif
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#define SYSTEM_CLOCK (PLATFORM_COUNTER_FREQ/3)
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#ifndef MT7620
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#define SYSTEM_CLOCK (PLATFORM_COUNTER_FREQ/3)
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#define SDRAM_BASE 0x00000000
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#define SDRAM_END 0x03FFFFFF
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@ -60,16 +63,26 @@
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#define INTCTL_END 0x100002FF
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#define MEMCTRL_BASE 0x10000300
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#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */
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#ifndef RT5350
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#define PCM_BASE 0x10000400
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#define PCM_END 0x100004FF
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#else
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#define PCM_BASE 0x10002000
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#define PCM_END 0x100027FF
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#endif
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#define UART_BASE 0x10000500
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#define UART_END 0x100005FF
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#define PIO_BASE 0x10000600
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#define PIO_END 0x100006FF
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#ifndef RT5350
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#define GDMA_BASE 0x10000700
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#define GDMA_END 0x100007FF /* Generic DMA */
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#define NANDFC_BASE 0x10000800
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#define NANDFC_END 0x100008FF /* NAND Flash Controller */
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#else
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#define GDMA_BASE 0x10002800
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#define GDMA_END 0x10002FFF
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#endif
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#define I2C_BASE 0x10000900
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#define I2C_END 0x100009FF
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#define I2S_BASE 0x10000A00
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@ -87,23 +100,110 @@
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#define ROM_END 0x10119FFF
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#define WLAN_BASE 0x10180000
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#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */
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#ifndef RT5350
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#define USB_OTG_BASE 0x101C0000
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#define USB_OTG_END 0x101FFFFF
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#else
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#define USB_OTG_BASE 0x101C0000
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#define USB_OTG_END 0x101C0FFF
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#define USB_OHCI_BASE 0x101C1000
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#define USB_OHCI_END 0x101C1FFF
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#endif
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#define EMEM_BASE 0x1B000000
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#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */
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#ifdef RT5350
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#define BOOT_ROM_BASE 0x1C000000
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#define BOOT_ROM_END 0x1C003FFF
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#endif
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#ifndef RT5350
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#define FLASH_BASE 0x1F000000
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#define FLASH_END 0x1FFFFFFF /* Flash window */
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#endif
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#define OBIO_MEM_BASE SYSCTL_BASE
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#define OBIO_MEM_START OBIO_MEM_BASE
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#ifndef RT5350
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#define OBIO_MEM_END FLASH_END
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#else
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#define OBIO_MEM_END BOOT_ROM_END
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#endif
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#else /* MT7620 */
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#define SYSTEM_CLOCK (40 * 1000 * 1000)
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#define SDRAM_BASE 0x00000000
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#define SDRAM_END 0x0FFFFFFF
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#define SYSCTL_BASE 0x10000000
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#define SYSCTL_END 0x100000FF
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#define TIMER_BASE 0x10000100
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#define TIMER_END 0x100001FF
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#define INTCTL_BASE 0x10000200
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#define INTCTL_END 0x100002FF
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#define MEMCTRL_BASE 0x10000300
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#define MEMCTRL_END 0x100003FF /* SDRAM & Flash/SRAM */
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#define PCM_BASE 0x10002000
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#define PCM_END 0x100027FF
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#define UART_BASE 0x10000500
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#define UART_END 0x100005FF
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#define PIO_BASE 0x10000600
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#define PIO_END 0x100006FF
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#define GDMA_BASE 0x10002800
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#define GDMA_END 0x10002FFF /* Generic DMA */
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#define NANDFC_BASE 0x10000800
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#define NANDFC_END 0x100008FF /* NAND Flash Controller */
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#define I2C_BASE 0x10000900
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#define I2C_END 0x100009FF
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#define I2S_BASE 0x10000A00
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#define I2S_END 0x10000AFF
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#define SPI_BASE 0x10000B00
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#define SPI_END 0x10000BFF
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#define UARTLITE_BASE 0x10000C00
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#define UARTLITE_END 0x10000CFF
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#define FRENG_BASE 0x10100000
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#define FRENG_END 0x1010FFFF /* Frame Engine */
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#define ETHSW_BASE 0x10110000
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#define ETHSW_END 0x10117FFF /* Ethernet Switch */
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#define ROM_BASE 0x10118000
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#define ROM_END 0x1011FFFF
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#define WLAN_BASE 0x10180000
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#define WLAN_END 0x101BFFFF /* 802.11n MAC/BBP */
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#define USB_OTG_BASE 0x101C0000
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#define USB_OTG_END 0x101C0FFF
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#define USB_OHCI_BASE 0x101C1000
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#define USB_OHCI_END 0x101C1FFF
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#define PCIE_BASE 0x10140000
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#define PCIE_END 0x1017FFFF
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#define SDHC_BASE 0x10130000
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#define SDHC_END 0x10133FFF
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#define PCIE_IO_BASE 0x10160000
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#define PCIE_IO_END 0x1016FFFF
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#define PCIE_MEM_BASE 0x20000000
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#define PCIE_MEM_END 0x2FFFFFFF
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// TODO: fix below mappings?
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#define EMEM_BASE 0x1B000000
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#define EMEM_END 0x1BFFFFFF /* External SRAM/Flash */
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#define FLASH_BASE 0x1F000000
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#define FLASH_END 0x1FFFFFFF /* Flash window */
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#define OBIO_MEM_BASE SYSCTL_BASE
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#define OBIO_MEM_START OBIO_MEM_BASE
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#define OBIO_MEM_END FLASH_END
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#endif
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/* System Control */
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#define SYSCTL_CHIPID0_3 0x00 /* 'R''T''3''0' */
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#define SYSCTL_CHIPID4_7 0x04 /* '5''2'' '' ' */
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#define SYSCTL_CHIPID0_3 0x00
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#define SYSCTL_CHIPID4_7 0x04
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#ifdef RT5350
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#define SYSCTL_REVID 0x0C
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#endif
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#define SYSCTL_SYSCFG 0x10
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#if !defined(RT5350) && !defined(MT7620)
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#define SYSCTL_SYSCFG_INIC_EE_SDRAM (1<<29)
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#define SYSCTL_SYSCFG_INIC_8MB_SDRAM (1<<28)
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#define SYSCTL_SYSCFG_GE0_MODE_MASK 0x03000000
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@ -129,6 +229,18 @@
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#define SYSCTL_SYSCFG_SRAM_CS_MODE_WDOG_RST 1
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#define SYSCTL_SYSCFG_SRAM_CS_MODE_BT_COEX 2
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#define SYSCTL_SYSCFG_SDRAM_CLK_DRV (1<<0) /* 8mA/12mA */
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#endif
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#ifdef RT5350
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#define SYSCTL1_SYSCFG_PULL_EN (1<<26)
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#define SYSCTL1_SYSCFG_SDR_PAD_DRV_MASK 0x0700000
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#define SYSCTL1_SYSCFG_SDR_PAD_DRV_SHIFT 20
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#define SYSCTL1_SYSCFG_SDR_PAD_DRV_0 0
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#define SYSCTL1_SYSCFG_SDR_PAD_DRV_1 1
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#define SYSCTL1_SYSCFG_SDR_PAD_DRV_2 2
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#endif
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#define SYSCTL_SYSCFG1 0x14
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#define SYSCTL_SYSCFG1_USB0_HOST_MODE (1 << 10)
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#define SYSCTL_TESTSTAT 0x18
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#define SYSCTL_TESTSTAT2 0x1C
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@ -142,7 +254,10 @@
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#define SYSCTL_CLKCFG0_SDRAM_CLK_SKEW_3NS_DELAY 3
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#define SYSCTL_CLKCFG1 0x30
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#if !defined(RT5350)
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#define SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2 (1<<30)
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#define SYSCTL_CLKCFG1_UPHY0_CLK_EN (1<<25)
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#define SYSCTL_CLKCFG1_UPHY1_CLK_EN (1<<22)
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#define SYSCTL_CLKCFG1_OTG_CLK_EN (1<<18)
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#define SYSCTL_CLKCFG1_I2S_CLK_EN (1<<15)
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#define SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT (1<<14)
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@ -152,10 +267,21 @@
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#define SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT (1<<6)
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#define SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK 0x0000003f
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#define SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT 0
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#endif
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#ifdef RT5350
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#define SYSCTL_CLKCFG1_SYSTICK_EN (1<<29)
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#define SYSCTL_CLKCFG1_PDMA_CSR_CLK_GATE_BYP (1<<23)
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#define SYSCTL_CLKCFG1_UPHY0_CLK_EN (1<<18)
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#endif
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#define SYSCTL_RSTCTRL 0x34
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#define SYSCTL_RSTCTRL_ETHSW (1<<23)
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#if !defined(MT7620) && !defined(RT5350)
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#define SYSCTL_RSTCTRL_OTG (1<<22)
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#else
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#define SYSCTL_RSTCTRL_UPHY0 (1<<25)
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#define SYSCTL_RSTCTRL_UPHY1 (1<<22)
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#endif
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#define SYSCTL_RSTCTRL_FRENG (1<<21)
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#define SYSCTL_RSTCTRL_WLAN (1<<20)
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#define SYSCTL_RSTCTRL_UARTL (1<<19)
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@ -196,6 +322,9 @@
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#define SYSCTL_MEMO0 0x68
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#define SYSCTL_MEMO1 0x6C
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#define SYSCTL_PPLL_CFG1 0x9C
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#define SYSCTL_PPLL_DRV 0xA0
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/* Timer */
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#define TIMER_TMRSTAT 0x00
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#define TIMER_TMRSTAT_TMR1RST (1<<5)
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@ -249,7 +378,10 @@
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#define IC_OTG 18
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#define IC_ETHSW 17
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#define IC_R2P 15
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#define IC_SDHC 14
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#define IC_UARTLITE 12
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#define IC_SPI 11
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#define IC_I2S 10
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#define IC_PERFC 9
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#define IC_NAND 8
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@ -362,7 +494,39 @@
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*/
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#define GDMACT0_SWMODE (1<<0)
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/* SPI controller interface */
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#define RT305X_SPISTAT 0x00
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/* SPIBUSY is alias for SPIBUSY, because SPISTAT have only BUSY bit*/
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#define RT305X_SPIBUSY RT305X_SPISTAT
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#define RT305X_SPICFG 0x10
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#define MSBFIRST (1<<8)
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#define SPICLKPOL (1<<6)
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#define CAPT_ON_CLK_FALL (1<<5)
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#define TX_ON_CLK_FALL (1<<4)
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#define HIZSPI (1<<3) /* Set SPI pins to Tri-state */
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#define SPI_CLK_SHIFT 0 /* SPI clock divide control */
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#define SPI_CLK_MASK 0x00000007
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#define SPI_CLK_DIV2 0
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#define SPI_CLK_DIV4 1
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#define SPI_CLK_DIV8 2
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#define SPI_CLK_DIV16 3
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#define SPI_CLK_DIV32 4
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#define SPI_CLK_DIV64 5
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#define SPI_CLK_DIV128 6
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#define SPI_CLK_DISABLED 7
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#define RT305X_SPICTL 0x14
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#define HIZSMOSI (1<<3)
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#define START_WRITE (1<<2)
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#define START_READ (1<<1)
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#define CS_HIGH (1<<0)
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#define RT305X_SPIDATA 0x20
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#define SPIDATA_MASK 0x000000ff
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#define RT305X_SPI_WRITE 1
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#define RT305X_SPI_READ 0
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#endif /* _RT305XREG_H_ */
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