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Rename ARM_INTRNG and MIPS_INTRNG to INTRNG. This will help with machine

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independent code that needs to know about INTRNG such as PCI drivers.

Obtained from:	ABT Systems Ltd
Sponsored by:	The FreeBSD Foundation
This commit is contained in:
andrew 2016-04-15 16:05:41 +00:00
parent 3115fdeded
commit b72ace02b4
59 changed files with 166 additions and 166 deletions
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4
sys/arm/allwinner/a10_common.c
View File

@ -42,7 +42,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_aintc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
@ -69,4 +69,4 @@ fdt_pic_decode_t fdt_pic_table[] = {
NULL
};
#endif /* ARM_INTRNG */
#endif /* INTRNG */

2
sys/arm/altera/socfpga/socfpga_common.c
View File

@ -74,7 +74,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)

4
sys/arm/amlogic/aml8726/aml8726_machdep.c
View File

@ -184,7 +184,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
#ifndef DEV_GIC
static int
fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
@ -213,4 +213,4 @@ fdt_pic_decode_t fdt_pic_table[] = {
#endif
NULL
};
#endif /* ARM_INTRNG */
#endif /* INTRNG */

2
sys/arm/annapurna/alpine/common.c
View File

@ -136,7 +136,7 @@ cpu_reset(void)
while (1) {}
}
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
alpine_pic_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt,
int *trig, int *pol)

42
sys/arm/arm/gic.c
View File

@ -50,7 +50,7 @@ __FBSDID("$FreeBSD$");
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/smp.h>
#ifdef ARM_INTRNG
#ifdef INTRNG
#include <sys/sched.h>
#endif
#include <machine/bus.h>
@ -62,7 +62,7 @@ __FBSDID("$FreeBSD$");
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#ifdef ARM_INTRNG
#ifdef INTRNG
#include "pic_if.h"
#endif
@ -116,7 +116,7 @@ __FBSDID("$FreeBSD$");
#define GIC_DEFAULT_ICFGR_INIT 0x00000000
#endif
#ifdef ARM_INTRNG
#ifdef INTRNG
struct gic_irqsrc {
struct intr_irqsrc gi_isrc;
uint32_t gi_irq;
@ -136,7 +136,7 @@ u_int sgi_first_unused = GIC_FIRST_SGI;
#endif
#endif
#ifdef ARM_INTRNG
#ifdef INTRNG
struct arm_gic_range {
uint64_t bus;
uint64_t host;
@ -151,7 +151,7 @@ struct arm_gic_devinfo {
struct arm_gic_softc {
device_t gic_dev;
#ifdef ARM_INTRNG
#ifdef INTRNG
void * gic_intrhand;
struct gic_irqsrc * gic_irqs;
#endif
@ -167,7 +167,7 @@ struct arm_gic_softc {
uint32_t last_irq[MAXCPU];
#endif
#ifdef ARM_INTRNG
#ifdef INTRNG
/* FDT child data */
pcell_t addr_cells;
pcell_t size_cells;
@ -176,14 +176,14 @@ struct arm_gic_softc {
#endif
};
#ifdef ARM_INTRNG
#ifdef INTRNG
#define GIC_INTR_ISRC(sc, irq) (&sc->gic_irqs[irq].gi_isrc)
#endif
static struct resource_spec arm_gic_spec[] = {
{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */
{ SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */
#ifdef ARM_INTRNG
#ifdef INTRNG
{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, /* Parent interrupt */
#endif
{ -1, 0 }
@ -204,7 +204,7 @@ static struct arm_gic_softc *gic_sc = NULL;
#define gic_d_write_4(_sc, _reg, _val) \
bus_space_write_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val))
#ifndef ARM_INTRNG
#ifndef INTRNG
static int gic_config_irq(int irq, enum intr_trigger trig,
enum intr_polarity pol);
static void gic_post_filter(void *);
@ -235,7 +235,7 @@ arm_gic_probe(device_t dev)
return (BUS_PROBE_DEFAULT);
}
#ifdef ARM_INTRNG
#ifdef INTRNG
static inline void
gic_irq_unmask(struct arm_gic_softc *sc, u_int irq)
{
@ -275,7 +275,7 @@ gic_cpu_mask(struct arm_gic_softc *sc)
}
#ifdef SMP
#ifdef ARM_INTRNG
#ifdef INTRNG
static void
arm_gic_init_secondary(device_t dev)
{
@ -347,10 +347,10 @@ arm_gic_init_secondary(device_t dev)
gic_d_write_4(sc, GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
gic_d_write_4(sc, GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F)));
}
#endif /* ARM_INTRNG */
#endif /* INTRNG */
#endif /* SMP */
#ifndef ARM_INTRNG
#ifndef INTRNG
int
gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
int *trig, int *pol)
@ -411,7 +411,7 @@ gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt,
}
#endif
#ifdef ARM_INTRNG
#ifdef INTRNG
static inline intptr_t
gic_xref(device_t dev)
{
@ -570,7 +570,7 @@ arm_gic_attach(device_t dev)
struct arm_gic_softc *sc;
int i;
uint32_t icciidr, mask, nirqs;
#ifdef ARM_INTRNG
#ifdef INTRNG
phandle_t pxref;
intptr_t xref = gic_xref(dev);
#endif
@ -606,7 +606,7 @@ arm_gic_attach(device_t dev)
nirqs = gic_d_read_4(sc, GICD_TYPER);
nirqs = 32 * ((nirqs & 0x1f) + 1);
#ifdef ARM_INTRNG
#ifdef INTRNG
if (arm_gic_register_isrcs(sc, nirqs)) {
device_printf(dev, "could not register irqs\n");
goto cleanup;
@ -662,7 +662,7 @@ arm_gic_attach(device_t dev)
/* Enable interrupt distribution */
gic_d_write_4(sc, GICD_CTLR, 0x01);
#ifndef ARM_INTRNG
#ifndef INTRNG
return (0);
#else
/*
@ -723,7 +723,7 @@ arm_gic_attach(device_t dev)
#endif
}
#ifdef ARM_INTRNG
#ifdef INTRNG
static struct resource *
arm_gic_alloc_resource(device_t bus, device_t child, int type, int *rid,
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
@ -1429,14 +1429,14 @@ pic_ipi_clear(int ipi)
arm_gic_ipi_clear(gic_sc->gic_dev, ipi);
}
#endif
#endif /* ARM_INTRNG */
#endif /* INTRNG */
static device_method_t arm_gic_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, arm_gic_probe),
DEVMETHOD(device_attach, arm_gic_attach),
#ifdef ARM_INTRNG
#ifdef INTRNG
/* Bus interface */
DEVMETHOD(bus_add_child, bus_generic_add_child),
DEVMETHOD(bus_alloc_resource, arm_gic_alloc_resource),
@ -1483,7 +1483,7 @@ EARLY_DRIVER_MODULE(gic, simplebus, arm_gic_driver, arm_gic_devclass, 0, 0,
EARLY_DRIVER_MODULE(gic, ofwbus, arm_gic_driver, arm_gic_devclass, 0, 0,
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
#ifdef ARM_INTRNG
#ifdef INTRNG
/*
* GICv2m support -- the GICv2 MSI/MSI-X controller.
*/

4
sys/arm/arm/machdep_intr.c
View File

@ -49,7 +49,7 @@ __FBSDID("$FreeBSD$");
#include <machine/cpu.h>
#include <machine/smp.h>
#ifdef ARM_INTRNG
#ifdef INTRNG
#include "pic_if.h"
#ifdef SMP
@ -131,7 +131,7 @@ arm_irq_memory_barrier(uintptr_t irq)
cpu_l2cache_drain_writebuf();
}
#ifdef ARM_INTRNG
#ifdef INTRNG
#ifdef SMP
static inline struct intr_ipi *
intr_ipi_lookup(u_int ipi)

18
sys/arm/arm/mp_machdep.c
View File

@ -74,7 +74,7 @@ volatile int mp_naps;
/* Set to 1 once we're ready to let the APs out of the pen. */
volatile int aps_ready = 0;
#ifndef ARM_INTRNG
#ifndef INTRNG
static int ipi_handler(void *arg);
#endif
void set_stackptrs(int cpu);
@ -152,7 +152,7 @@ init_secondary(int cpu)
{
struct pcpu *pc;
uint32_t loop_counter;
#ifndef ARM_INTRNG
#ifndef INTRNG
int start = 0, end = 0;
#endif
uint32_t actlr_mask, actlr_set;
@ -207,7 +207,7 @@ init_secondary(int cpu)
mtx_unlock_spin(&ap_boot_mtx);
#ifndef ARM_INTRNG
#ifndef INTRNG
/* Enable ipi */
#ifdef IPI_IRQ_START
start = IPI_IRQ_START;
@ -243,7 +243,7 @@ init_secondary(int cpu)
/* NOTREACHED */
}
#ifdef ARM_INTRNG
#ifdef INTRNG
static void
ipi_rendezvous(void *dummy __unused)
{
@ -421,14 +421,14 @@ static void
release_aps(void *dummy __unused)
{
uint32_t loop_counter;
#ifndef ARM_INTRNG
#ifndef INTRNG
int start = 0, end = 0;
#endif
if (mp_ncpus == 1)
return;
#ifdef ARM_INTRNG
#ifdef INTRNG
intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
@ -501,7 +501,7 @@ ipi_all_but_self(u_int ipi)
other_cpus = all_cpus;
CPU_CLR(PCPU_GET(cpuid), &other_cpus);
CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
#ifdef ARM_INTRNG
#ifdef INTRNG
intr_ipi_send(other_cpus, ipi);
#else
pic_ipi_send(other_cpus, ipi);
@ -517,7 +517,7 @@ ipi_cpu(int cpu, u_int ipi)
CPU_SET(cpu, &cpus);
CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
#ifdef ARM_INTRNG
#ifdef INTRNG
intr_ipi_send(cpus, ipi);
#else
pic_ipi_send(cpus, ipi);
@ -529,7 +529,7 @@ ipi_selected(cpuset_t cpus, u_int ipi)
{
CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
#ifdef ARM_INTRNG
#ifdef INTRNG
intr_ipi_send(cpus, ipi);
#else
pic_ipi_send(cpus, ipi);

16
sys/arm/arm/nexus.c
View File

@ -86,14 +86,14 @@ static struct resource *nexus_alloc_resource(device_t, device_t, int, int *,
static int nexus_activate_resource(device_t, device_t, int, int,
struct resource *);
static bus_space_tag_t nexus_get_bus_tag(device_t, device_t);
#ifdef ARM_INTRNG
#ifdef INTRNG
#ifdef SMP
static int nexus_bind_intr(device_t, device_t, struct resource *, int);
#endif
#endif
static int nexus_config_intr(device_t dev, int irq, enum intr_trigger trig,
enum intr_polarity pol);
#ifdef ARM_INTRNG
#ifdef INTRNG
static int nexus_describe_intr(device_t dev, device_t child,
struct resource *irq, void *cookie, const char *descr);
#endif
@ -126,7 +126,7 @@ static device_method_t nexus_methods[] = {
DEVMETHOD(bus_setup_intr, nexus_setup_intr),
DEVMETHOD(bus_teardown_intr, nexus_teardown_intr),
DEVMETHOD(bus_get_bus_tag, nexus_get_bus_tag),
#ifdef ARM_INTRNG
#ifdef INTRNG
DEVMETHOD(bus_describe_intr, nexus_describe_intr),
#ifdef SMP
DEVMETHOD(bus_bind_intr, nexus_bind_intr),
@ -280,7 +280,7 @@ nexus_config_intr(device_t dev, int irq, enum intr_trigger trig,
{
int ret = ENODEV;
#ifdef ARM_INTRNG
#ifdef INTRNG
device_printf(dev, "bus_config_intr is obsolete and not supported!\n");
ret = EOPNOTSUPP;
#else
@ -294,14 +294,14 @@ static int
nexus_setup_intr(device_t dev, device_t child, struct resource *res, int flags,
driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep)
{
#ifndef ARM_INTRNG
#ifndef INTRNG
int irq;
#endif
if ((rman_get_flags(res) & RF_SHAREABLE) == 0)
flags |= INTR_EXCL;
#ifdef ARM_INTRNG
#ifdef INTRNG
return(intr_setup_irq(child, res, filt, intr, arg, flags, cookiep));
#else
for (irq = rman_get_start(res); irq <= rman_get_end(res); irq++) {
@ -317,14 +317,14 @@ static int
nexus_teardown_intr(device_t dev, device_t child, struct resource *r, void *ih)
{
#ifdef ARM_INTRNG
#ifdef INTRNG
return (intr_teardown_irq(child, r, ih));
#else
return (arm_remove_irqhandler(rman_get_start(r), ih));
#endif
}
#ifdef ARM_INTRNG
#ifdef INTRNG
static int
nexus_describe_intr(device_t dev, device_t child, struct resource *irq,
void *cookie, const char *descr)

2
sys/arm/at91/at91_common.c
View File

@ -53,7 +53,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_aic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)

4
sys/arm/broadcom/bcm2835/bcm2835_common.c
View File

@ -50,7 +50,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)
@ -78,4 +78,4 @@ fdt_pic_decode_t fdt_pic_table[] = {
&fdt_intc_decode_ic,
NULL
};
#endif /* ARM_INTRNG */
#endif /* INTRNG */

20
sys/arm/broadcom/bcm2835/bcm2835_gpio.c
View File

@ -53,7 +53,7 @@ __FBSDID("$FreeBSD$");
#include "gpio_if.h"
#ifdef ARM_INTRNG
#ifdef INTRNG
#include "pic_if.h"
#endif
@ -84,7 +84,7 @@ struct bcm_gpio_sysctl {
uint32_t pin;
};
#ifdef ARM_INTRNG
#ifdef INTRNG
struct bcm_gpio_irqsrc {
struct intr_irqsrc bgi_isrc;
uint32_t bgi_irq;
@ -105,11 +105,11 @@ struct bcm_gpio_softc {
int sc_ro_npins;
int sc_ro_pins[BCM_GPIO_PINS];
struct gpio_pin sc_gpio_pins[BCM_GPIO_PINS];
#ifndef ARM_INTRNG
#ifndef INTRNG
struct intr_event * sc_events[BCM_GPIO_PINS];
#endif
struct bcm_gpio_sysctl sc_sysctl[BCM_GPIO_PINS];
#ifdef ARM_INTRNG
#ifdef INTRNG
struct bcm_gpio_irqsrc sc_isrcs[BCM_GPIO_PINS];
#else
enum intr_trigger sc_irq_trigger[BCM_GPIO_PINS];
@ -153,7 +153,7 @@ enum bcm_gpio_pud {
static struct bcm_gpio_softc *bcm_gpio_sc = NULL;
#ifdef ARM_INTRNG
#ifdef INTRNG
static int bcm_gpio_intr_bank0(void *arg);
static int bcm_gpio_intr_bank1(void *arg);
static int bcm_gpio_pic_attach(struct bcm_gpio_softc *sc);
@ -691,7 +691,7 @@ bcm_gpio_get_reserved_pins(struct bcm_gpio_softc *sc)
return (0);
}
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
bcm_gpio_intr(void *arg)
{
@ -741,7 +741,7 @@ bcm_gpio_probe(device_t dev)
return (BUS_PROBE_DEFAULT);
}
#ifdef ARM_INTRNG
#ifdef INTRNG
static int
bcm_gpio_intr_attach(device_t dev)
{
@ -862,7 +862,7 @@ bcm_gpio_attach(device_t dev)
sc->sc_gpio_pins[i].gp_pin = j;
sc->sc_gpio_pins[i].gp_caps = BCM_GPIO_DEFAULT_CAPS;
sc->sc_gpio_pins[i].gp_flags = bcm_gpio_func_flag(func);
#ifndef ARM_INTRNG
#ifndef INTRNG
/* The default is active-low interrupts. */
sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL;
sc->sc_irq_polarity[i] = INTR_POLARITY_LOW;
@ -892,7 +892,7 @@ bcm_gpio_detach(device_t dev)
return (EBUSY);
}
#ifdef ARM_INTRNG
#ifdef INTRNG
static inline void
bcm_gpio_isrc_eoi(struct bcm_gpio_softc *sc, struct bcm_gpio_irqsrc *bgi)
{
@ -1372,7 +1372,7 @@ static device_method_t bcm_gpio_methods[] = {
DEVMETHOD(gpio_pin_set, bcm_gpio_pin_set),
DEVMETHOD(gpio_pin_toggle, bcm_gpio_pin_toggle),
#ifdef ARM_INTRNG
#ifdef INTRNG
/* Interrupt controller interface */
DEVMETHOD(pic_disable_intr, bcm_gpio_pic_disable_intr),
DEVMETHOD(pic_enable_intr, bcm_gpio_pic_enable_intr),

20
sys/arm/broadcom/bcm2835/bcm2835_intr.c
View File

@ -52,7 +52,7 @@ __FBSDID("$FreeBSD$");
#include <arm/broadcom/bcm2835/bcm2836.h>
#endif
#ifdef ARM_INTRNG
#ifdef INTRNG
#include "pic_if.h"
#endif
@ -105,7 +105,7 @@ __FBSDID("$FreeBSD$");
#define BANK1_END (BANK1_START + 32 - 1)
#define BANK2_START (BANK1_START + 32)
#define BANK2_END (BANK2_START + 32 - 1)
#ifndef ARM_INTRNG
#ifndef INTRNG
#define BANK3_START (BANK2_START + 32)
#define BANK3_END (BANK3_START + 32 - 1)
#endif
@ -113,7 +113,7 @@ __FBSDID("$FreeBSD$");
#define IS_IRQ_BASIC(n) (((n) >= 0) && ((n) < BANK1_START))
#define IS_IRQ_BANK1(n) (((n) >= BANK1_START) && ((n) <= BANK1_END))
#define IS_IRQ_BANK2(n) (((n) >= BANK2_START) && ((n) <= BANK2_END))
#ifndef ARM_INTRNG
#ifndef INTRNG
#define ID_IRQ_BCM2836(n) (((n) >= BANK3_START) && ((n) <= BANK3_END))
#endif
#define IRQ_BANK1(n) ((n) - BANK1_START)
@ -125,7 +125,7 @@ __FBSDID("$FreeBSD$");
#define dprintf(fmt, args...)
#endif
#ifdef ARM_INTRNG
#ifdef INTRNG
#define BCM_INTC_NIRQS 72 /* 8 + 32 + 32 */
struct bcm_intc_irqsrc {
@ -142,7 +142,7 @@ struct bcm_intc_softc {
struct resource * intc_res;
bus_space_tag_t intc_bst;
bus_space_handle_t intc_bsh;
#ifdef ARM_INTRNG
#ifdef INTRNG
struct resource * intc_irq_res;
void * intc_irq_hdl;
struct bcm_intc_irqsrc intc_isrcs[BCM_INTC_NIRQS];
@ -156,7 +156,7 @@ static struct bcm_intc_softc *bcm_intc_sc = NULL;
#define intc_write_4(_sc, reg, val) \
bus_space_write_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg), (val))
#ifdef ARM_INTRNG
#ifdef INTRNG
static inline void
bcm_intc_isrc_mask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii)
{
@ -360,7 +360,7 @@ bcm_intc_attach(device_t dev)
{
struct bcm_intc_softc *sc = device_get_softc(dev);
int rid = 0;
#ifdef ARM_INTRNG
#ifdef INTRNG
intptr_t xref;
#endif
sc->sc_dev = dev;
@ -374,7 +374,7 @@ bcm_intc_attach(device_t dev)
return (ENXIO);
}
#ifdef ARM_INTRNG
#ifdef INTRNG
xref = OF_xref_from_node(ofw_bus_get_node(dev));
if (bcm_intc_pic_register(sc, xref) != 0) {
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->intc_res);
@ -412,7 +412,7 @@ static device_method_t bcm_intc_methods[] = {
DEVMETHOD(device_probe, bcm_intc_probe),
DEVMETHOD(device_attach, bcm_intc_attach),
#ifdef ARM_INTRNG
#ifdef INTRNG
DEVMETHOD(pic_disable_intr, bcm_intc_disable_intr),
DEVMETHOD(pic_enable_intr, bcm_intc_enable_intr),
DEVMETHOD(pic_map_intr, bcm_intc_map_intr),
@ -434,7 +434,7 @@ static devclass_t bcm_intc_devclass;
DRIVER_MODULE(intc, simplebus, bcm_intc_driver, bcm_intc_devclass, 0, 0);
#ifndef ARM_INTRNG
#ifndef INTRNG
int
arm_get_next_irq(int last_irq)
{

4
sys/arm/broadcom/bcm2835/bcm2836.c
View File

@ -53,7 +53,7 @@ __FBSDID("$FreeBSD$");
#include <dev/ofw/ofw_bus_subr.h>
#include <dev/ofw/ofw_bus.h>
#ifdef ARM_INTRNG
#ifdef INTRNG
#include "pic_if.h"
#else
#include <arm/broadcom/bcm2835/bcm2836.h>
@ -72,7 +72,7 @@ __FBSDID("$FreeBSD$");
#define MAILBOX0_IRQEN (1 << 0)
#endif
#ifdef ARM_INTRNG
#ifdef INTRNG
#define BCM_LINTC_CONTROL_REG 0x00
#define BCM_LINTC_PRESCALER_REG 0x08
#define BCM_LINTC_GPU_ROUTING_REG 0x0c

2
sys/arm/broadcom/bcm2835/bcm2836.h
View File

@ -30,7 +30,7 @@
#ifndef _BCM2815_BCM2836_H
#define _BCM2815_BCM2836_H
#ifndef ARM_INTRNG
#ifndef INTRNG
#define BCM2836_GPU_IRQ 8
int bcm2836_get_next_irq(int);

2
sys/arm/broadcom/bcm2835/bcm2836_mp.c
View File

@ -139,7 +139,7 @@ platform_mp_start_ap(void)
}
}
#ifndef ARM_INTRNG
#ifndef INTRNG
void
pic_ipi_send(cpuset_t cpus, u_int ipi)
{

2
sys/arm/conf/A20
View File

@ -23,7 +23,7 @@ ident A20
include "std.armv6"
include "../allwinner/a20/std.a20"
options ARM_INTRNG
options INTRNG
options SOC_ALLWINNER_A20

2
sys/arm/conf/ALPINE
View File

@ -37,7 +37,7 @@ options DDB #Enable the kernel debugger
# Interrupt controller
device gic
options ARM_INTRNG
options INTRNG
# Pseudo devices
device loop

2
sys/arm/conf/ARMADA38X
View File

@ -62,7 +62,7 @@ device pci
# Interrupt controllers
device gic
options ARM_INTRNG
options INTRNG
# Timers
device mpcore_timer

2
sys/arm/conf/BEAGLEBONE
View File

@ -28,7 +28,7 @@ include "../ti/am335x/std.am335x"
makeoptions MODULES_EXTRA="dtb/am335x am335x_dmtpps"
options ARM_INTRNG
options INTRNG
options HZ=100
options SCHED_4BSD # 4BSD scheduler

2
sys/arm/conf/EXYNOS5.common
View File

@ -87,7 +87,7 @@ device dwmmc
# Interrupt controller
device gic
options ARM_INTRNG
options INTRNG
# ARM Generic Timer
device generic_timer

2
sys/arm/conf/IMX6
View File

@ -22,7 +22,7 @@ ident IMX6
include "std.armv6"
include "../freescale/imx/std.imx6"
options ARM_INTRNG
options INTRNG
options SOC_IMX6

2
sys/arm/conf/ODROIDC1
View File

@ -26,7 +26,7 @@ options SMP # Enable multiple cores
# Interrupt controller
device gic
options ARM_INTRNG
options INTRNG
options FDT_DTB_STATIC
makeoptions FDT_DTS_FILE=odroidc1.dts

2
sys/arm/conf/PANDABOARD
View File

@ -60,7 +60,7 @@ options DDB # Enable the kernel debugger
device fdt_pinctrl
# Interrupt controller
device gic
options ARM_INTRNG
options INTRNG
# ARM MPCore timer
device mpcore_timer

2
sys/arm/conf/RK3188
View File

@ -47,7 +47,7 @@ options ROOTDEVNAME=\"ufs:/dev/mmcsd0\"
# Interrupt controller
device gic
options ARM_INTRNG
options INTRNG
# ARM MPCore timer
device mpcore_timer

2
sys/arm/conf/RPI-B
View File

@ -24,7 +24,7 @@ include "std.armv6"
include "../broadcom/bcm2835/std.rpi"
include "../broadcom/bcm2835/std.bcm2835"
options ARM_INTRNG
options INTRNG
options HZ=100
options SCHED_4BSD # 4BSD scheduler

2
sys/arm/conf/RPI2
View File

@ -24,7 +24,7 @@ include "std.armv6"
include "../broadcom/bcm2835/std.rpi"
include "../broadcom/bcm2835/std.bcm2836"
options ARM_INTRNG
options INTRNG
options HZ=100
options SCHED_ULE # ULE scheduler

2
sys/arm/conf/SOCKIT.common
View File

@ -53,7 +53,7 @@ options INVARIANT_SUPPORT # Extra sanity checks of internal structures, require
# Interrupt controller
device gic
options ARM_INTRNG
options INTRNG
# ARM MPCore timer
device mpcore_timer

2
sys/arm/conf/VIRT
View File

@ -47,7 +47,7 @@ options INVARIANT_SUPPORT # Extra sanity checks of internal structures, require
# Interrupt controller
device gic
options ARM_INTRNG
options INTRNG
# ARM Generic Timer
device generic_timer

2
sys/arm/conf/VSATV102
View File

@ -26,7 +26,7 @@ options SMP # Enable multiple cores
# Interrupt controller
device gic
options ARM_INTRNG
options INTRNG
options FDT_DTB_STATIC
makeoptions FDT_DTS_FILE=vsatv102-m6.dts

2
sys/arm/conf/VYBRID
View File

@ -62,7 +62,7 @@ options NO_SWAPPING
# Interrupt controller
device gic
options ARM_INTRNG
options INTRNG
# ARM MPCore timer
device mpcore_timer

2
sys/arm/conf/ZEDBOARD
View File

@ -52,7 +52,7 @@ options ROOTDEVNAME=\"ufs:mmcsd0s2a\"
# Interrupt controller
device gic
options ARM_INTRNG
options INTRNG
# Cache controller
device pl310 # PL310 L2 cache controller

2
sys/arm/freescale/imx/imx6_machdep.c
View File

@ -58,7 +58,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
static uint32_t gpio1_node;
#ifndef ARM_INTRNG
#ifndef INTRNG
/*
* Work around the linux workaround for imx6 erratum 006687, in which some
* ethernet interrupts don't go to the GPC and thus won't wake the system from

4
sys/arm/freescale/imx/imx_common.c
View File

@ -54,7 +54,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)
@ -71,4 +71,4 @@ fdt_pic_decode_t fdt_pic_table[] = {
&fdt_intc_decode_ic,
NULL
};
#endif /* ARM_INTRNG */
#endif /* INTRNG */

14
sys/arm/freescale/imx/imx_gpio.c
View File

@ -60,7 +60,7 @@ __FBSDID("$FreeBSD$");
#include "gpio_if.h"
#ifdef ARM_INTRNG
#ifdef INTRNG
#include "pic_if.h"
#endif
@ -91,7 +91,7 @@ __FBSDID("$FreeBSD$");
#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
#define NGPIO 32
#ifdef ARM_INTRNG
#ifdef INTRNG
struct gpio_irqsrc {
struct intr_irqsrc gi_isrc;
u_int gi_irq;
@ -110,7 +110,7 @@ struct imx51_gpio_softc {
bus_space_handle_t sc_ioh;
int gpio_npins;
struct gpio_pin gpio_pins[NGPIO];
#ifdef ARM_INTRNG
#ifdef INTRNG
struct gpio_irqsrc gpio_pic_irqsrc[NGPIO];
#endif
};
@ -155,7 +155,7 @@ static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int);
static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *);
static int imx51_gpio_pin_toggle(device_t, uint32_t pin);
#ifdef ARM_INTRNG
#ifdef INTRNG
static int
gpio_pic_map_fdt(device_t dev, u_int ncells, pcell_t *cells, u_int *irqp,
enum intr_polarity *polp, enum intr_trigger *trigp)
@ -653,7 +653,7 @@ imx51_gpio_attach(device_t dev)
*/
WRITE4(sc, IMX_GPIO_IMR_REG, 0);
for (irq = 0; irq < 2; irq++) {
#ifdef ARM_INTRNG
#ifdef INTRNG
if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK,
gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) {
device_printf(dev,
@ -675,7 +675,7 @@ imx51_gpio_attach(device_t dev)
"imx_gpio%d.%d", unit, i);
}
#ifdef ARM_INTRNG
#ifdef INTRNG
gpio_pic_register_isrcs(sc);
intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev)));
#endif
@ -713,7 +713,7 @@ static device_method_t imx51_gpio_methods[] = {
DEVMETHOD(device_attach, imx51_gpio_attach),
DEVMETHOD(device_detach, imx51_gpio_detach),
#ifdef ARM_INTRNG
#ifdef INTRNG
/* Interrupt controller interface */
DEVMETHOD(pic_disable_intr, gpio_pic_disable_intr),
DEVMETHOD(pic_enable_intr, gpio_pic_enable_intr),

2
sys/arm/freescale/vybrid/vf_common.c
View File

@ -66,7 +66,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)

6
sys/arm/include/intr.h
View File

@ -43,7 +43,7 @@
#include <dev/ofw/openfirm.h>
#endif
#ifdef ARM_INTRNG
#ifdef INTRNG
#ifndef NIRQ
#define NIRQ 1024 /* XXX - It should be an option. */
@ -63,7 +63,7 @@ void intr_ipi_setup(u_int, const char *, intr_ipi_handler_t *, void *,
int intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *, void *);
#endif
#else /* ARM_INTRNG */
#else /* INTRNG */
/* XXX move to std.* files? */
#ifdef CPU_XSCALE_81342
@ -111,7 +111,7 @@ int gic_decode_fdt(phandle_t, pcell_t *, int *, int *, int *);
int intr_fdt_map_irq(phandle_t, pcell_t *, int);
#endif
#endif /* ARM_INTRNG */
#endif /* INTRNG */
void arm_irq_memory_barrier(uintptr_t);

4
sys/arm/include/smp.h
View File

@ -6,7 +6,7 @@
#include <sys/_cpuset.h>
#include <machine/pcb.h>
#ifdef ARM_INTRNG
#ifdef INTRNG
enum {
IPI_AST,
IPI_PREEMPT,
@ -37,7 +37,7 @@ void ipi_cpu(int cpu, u_int ipi);
void ipi_selected(cpuset_t cpus, u_int ipi);
/* PIC interface */
#ifndef ARM_INTRNG
#ifndef INTRNG
void pic_ipi_send(cpuset_t cpus, u_int ipi);
void pic_ipi_clear(int ipi);
int pic_ipi_read(int arg);

2
sys/arm/lpc/lpc_intc.c
View File

@ -231,7 +231,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)

20
sys/arm/mv/mpic.c
View File

@ -60,7 +60,7 @@ __FBSDID("$FreeBSD$");
#include <dev/ofw/ofw_bus_subr.h>
#include <dev/fdt/fdt_common.h>
#ifdef ARM_INTRNG
#ifdef INTRNG
#include "pic_if.h"
#endif
@ -98,7 +98,7 @@ __FBSDID("$FreeBSD$");
#define MPIC_PPI 32
#ifdef ARM_INTRNG
#ifdef INTRNG
struct mv_mpic_irqsrc {
struct intr_irqsrc mmi_isrc;
u_int mmi_irq;
@ -115,7 +115,7 @@ struct mv_mpic_softc {
bus_space_tag_t drbl_bst;
bus_space_handle_t drbl_bsh;
struct mtx mtx;
#ifdef ARM_INTRNG
#ifdef INTRNG
struct mv_mpic_irqsrc * mpic_isrcs;
#endif
int nirqs;
@ -151,7 +151,7 @@ static void mpic_mask_irq_err(uintptr_t nb);
static void mpic_unmask_irq_err(uintptr_t nb);
static int mpic_intr(void *arg);
static void mpic_unmask_msi(void);
#ifndef ARM_INTRNG
#ifndef INTRNG
static void arm_mask_irq_err(uintptr_t);
static void arm_unmask_irq_err(uintptr_t);
#endif
@ -185,7 +185,7 @@ mv_mpic_probe(device_t dev)
return (0);
}
#ifdef ARM_INTRNG
#ifdef INTRNG
static int
mv_mpic_register_isrcs(struct mv_mpic_softc *sc)
{
@ -241,7 +241,7 @@ mv_mpic_attach(device_t dev)
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
#ifdef ARM_INTRNG
#ifdef INTRNG
if (sc->mpic_res[3] == NULL)
device_printf(dev, "No interrupt to use.\n");
else
@ -268,7 +268,7 @@ mv_mpic_attach(device_t dev)
val = MPIC_READ(mv_mpic_sc, MPIC_CTRL);
sc->nirqs = MPIC_CTRL_NIRQS(val);
#ifdef ARM_INTRNG
#ifdef INTRNG
if (mv_mpic_register_isrcs(sc) != 0) {
device_printf(dev, "could not register PIC ISRCs\n");
bus_release_resources(dev, mv_mpic_spec, sc->mpic_res);
@ -286,7 +286,7 @@ mv_mpic_attach(device_t dev)
return (0);
}
#ifdef ARM_INTRNG
#ifdef INTRNG
static int
mpic_intr(void *arg)
{
@ -370,7 +370,7 @@ static device_method_t mv_mpic_methods[] = {
DEVMETHOD(device_probe, mv_mpic_probe),
DEVMETHOD(device_attach, mv_mpic_attach),
#ifdef ARM_INTRNG
#ifdef INTRNG
DEVMETHOD(pic_disable_intr, mpic_disable_intr),
DEVMETHOD(pic_enable_intr, mpic_enable_intr),
DEVMETHOD(pic_map_intr, mpic_map_intr),
@ -391,7 +391,7 @@ static devclass_t mv_mpic_devclass;
EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0,
BUS_PASS_INTERRUPT);
#ifndef ARM_INTRNG
#ifndef INTRNG
int
arm_get_next_irq(int last)
{

2
sys/arm/mv/mv_common.c
View File

@ -2282,7 +2282,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)

2
sys/arm/nvidia/tegra124/std.tegra124
View File

@ -6,7 +6,7 @@ makeoptions CONF_CFLAGS="-march=armv7a"
options KERNVIRTADDR = 0xc0200000
makeoptions KERNVIRTADDR = 0xc0200000
options ARM_INTRNG
options INTRNG
options IPI_IRQ_START=0
options IPI_IRQ_END=15

2
sys/arm/qemu/virt_common.c
View File

@ -41,7 +41,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
fdt_pic_decode_t fdt_pic_table[] = {
&gic_decode_fdt,
NULL

2
sys/arm/rockchip/rk30xx_common.c
View File

@ -42,7 +42,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_aintc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)

2
sys/arm/samsung/exynos/exynos5_common.c
View File

@ -53,7 +53,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)

14
sys/arm/ti/aintc.c
View File

@ -48,7 +48,7 @@ __FBSDID("$FreeBSD$");
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#ifdef ARM_INTRNG
#ifdef INTRNG
#include "pic_if.h"
#endif
@ -68,7 +68,7 @@ __FBSDID("$FreeBSD$");
#define INTC_NIRQS 128
#ifdef ARM_INTRNG
#ifdef INTRNG
struct ti_aintc_irqsrc {
struct intr_irqsrc tai_isrc;
u_int tai_irq;
@ -81,7 +81,7 @@ struct ti_aintc_softc {
bus_space_tag_t aintc_bst;
bus_space_handle_t aintc_bsh;
uint8_t ver;
#ifdef ARM_INTRNG
#ifdef INTRNG
struct ti_aintc_irqsrc aintc_isrcs[INTC_NIRQS];
#endif
};
@ -105,7 +105,7 @@ static struct ofw_compat_data compat_data[] = {
{NULL, 0},
};
#ifdef ARM_INTRNG
#ifdef INTRNG
static inline void
ti_aintc_irq_eoi(struct ti_aintc_softc *sc)
{
@ -295,7 +295,7 @@ ti_aintc_attach(device_t dev)
/*Set Priority Threshold */
aintc_write_4(sc, INTC_THRESHOLD, 0xFF);
#ifndef ARM_INTRNG
#ifndef INTRNG
arm_post_filter = aintc_post_filter;
#else
if (ti_aintc_pic_attach(sc) != 0) {
@ -310,7 +310,7 @@ static device_method_t ti_aintc_methods[] = {
DEVMETHOD(device_probe, ti_aintc_probe),
DEVMETHOD(device_attach, ti_aintc_attach),
#ifdef ARM_INTRNG
#ifdef INTRNG
DEVMETHOD(pic_disable_intr, ti_aintc_disable_intr),
DEVMETHOD(pic_enable_intr, ti_aintc_enable_intr),
DEVMETHOD(pic_map_intr, ti_aintc_map_intr),
@ -334,7 +334,7 @@ EARLY_DRIVER_MODULE(aintc, simplebus, ti_aintc_driver, ti_aintc_devclass,
0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
SIMPLEBUS_PNP_INFO(compat_data);
#ifndef ARM_INTRNG
#ifndef INTRNG
int
arm_get_next_irq(int last_irq)
{

4
sys/arm/ti/ti_common.c
View File

@ -53,7 +53,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
#ifdef SOC_TI_AM335X
static int
fdt_aintc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
@ -81,4 +81,4 @@ fdt_pic_decode_t fdt_pic_table[] = {
#endif
NULL
};
#endif /* !ARM_INTRNG */
#endif /* !INTRNG */

16
sys/arm/ti/ti_gpio.c
View File

@ -66,7 +66,7 @@ __FBSDID("$FreeBSD$");
#include "gpio_if.h"
#include "ti_gpio_if.h"
#ifdef ARM_INTRNG
#ifdef INTRNG
#include "pic_if.h"
#endif
@ -121,7 +121,7 @@ __FBSDID("$FreeBSD$");
static int ti_gpio_intr(void *arg);
static int ti_gpio_detach(device_t);
#ifdef ARM_INTRNG
#ifdef INTRNG
static int ti_gpio_pic_attach(struct ti_gpio_softc *sc);
static int ti_gpio_pic_detach(struct ti_gpio_softc *sc);
#endif
@ -546,7 +546,7 @@ ti_gpio_pin_toggle(device_t dev, uint32_t pin)
return (0);
}
#ifndef ARM_INTRNG
#ifndef INTRNG
/**
* ti_gpio_intr - ISR for all GPIO modules
* @arg: the soft context pointer
@ -655,7 +655,7 @@ static int
ti_gpio_attach(device_t dev)
{
struct ti_gpio_softc *sc;
#ifndef ARM_INTRNG
#ifndef INTRNG
unsigned int i;
#endif
int err;
@ -696,7 +696,7 @@ ti_gpio_attach(device_t dev)
return (ENXIO);
}
#ifdef ARM_INTRNG
#ifdef INTRNG
if (ti_gpio_pic_attach(sc) != 0) {
device_printf(dev, "WARNING: unable to attach PIC\n");
ti_gpio_detach(dev);
@ -771,7 +771,7 @@ ti_gpio_detach(device_t dev)
if (sc->sc_mem_res != NULL)
ti_gpio_intr_clr(sc, 0xffffffff);
gpiobus_detach_bus(dev);
#ifdef ARM_INTRNG
#ifdef INTRNG
if (sc->sc_isrcs != NULL)
ti_gpio_pic_detach(sc);
#else
@ -798,7 +798,7 @@ ti_gpio_detach(device_t dev)
return (0);
}
#ifdef ARM_INTRNG
#ifdef INTRNG
static inline void
ti_gpio_rwreg_set(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask)
{
@ -1300,7 +1300,7 @@ static device_method_t ti_gpio_methods[] = {
DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
#ifdef ARM_INTRNG
#ifdef INTRNG
/* Interrupt controller interface */
DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr),
DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr),

6
sys/arm/ti/ti_gpio.h
View File

@ -39,7 +39,7 @@
*/
#define MAX_GPIO_INTRS 8
#ifndef ARM_INTRNG
#ifndef INTRNG
struct ti_gpio_mask_arg {
void *softc;
int pin;
@ -61,7 +61,7 @@ struct ti_gpio_irqsrc {
struct ti_gpio_softc {
device_t sc_dev;
device_t sc_busdev;
#ifndef ARM_INTRNG
#ifndef INTRNG
/* Interrupt trigger type and level. */
enum intr_trigger *sc_irq_trigger;
enum intr_polarity *sc_irq_polarity;
@ -74,7 +74,7 @@ struct ti_gpio_softc {
struct resource *sc_mem_res;
int sc_irq_rid;
struct resource *sc_irq_res;
#ifndef ARM_INTRNG
#ifndef INTRNG
/* Interrupt events. */
struct intr_event **sc_events;
struct ti_gpio_mask_arg *sc_mask_args;

2
sys/arm/versatile/versatile_common.c
View File

@ -50,7 +50,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_intc_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)

2
sys/arm/xilinx/zy7_machdep.c
View File

@ -98,7 +98,7 @@ struct fdt_fixup_entry fdt_fixup_table[] = {
{ NULL, NULL }
};
#ifndef ARM_INTRNG
#ifndef INTRNG
static int
fdt_gic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
int *pol)

6
sys/conf/files.arm
View File

@ -45,8 +45,8 @@ arm/arm/hdmi_if.m optional hdmi
arm/arm/identcpu.c standard
arm/arm/in_cksum.c optional inet | inet6
arm/arm/in_cksum_arm.S optional inet | inet6
arm/arm/intr.c optional !arm_intrng
kern/subr_intr.c optional arm_intrng
arm/arm/intr.c optional !intrng
kern/subr_intr.c optional intrng
arm/arm/locore.S standard no-obj
arm/arm/machdep.c standard
arm/arm/machdep_intr.c standard
@ -115,7 +115,7 @@ font.h optional sc \
compile-with "uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x16.fnt && file2c 'u_char dflt_font_16[16*256] = {' '};' < ${SC_DFLT_FONT}-8x16 > font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x14.fnt && file2c 'u_char dflt_font_14[14*256] = {' '};' < ${SC_DFLT_FONT}-8x14 >> font.h && uudecode < /usr/share/syscons/fonts/${SC_DFLT_FONT}-8x8.fnt && file2c 'u_char dflt_font_8[8*256] = {' '};' < ${SC_DFLT_FONT}-8x8 >> font.h" \
no-obj no-implicit-rule before-depend \
clean "font.h ${SC_DFLT_FONT}-8x14 ${SC_DFLT_FONT}-8x16 ${SC_DFLT_FONT}-8x8"
kern/pic_if.m optional arm_intrng
kern/pic_if.m optional intrng
kern/subr_busdma_bufalloc.c standard
kern/subr_sfbuf.c standard
libkern/arm/aeabi_unwind.c standard

2
sys/conf/options.arm
View File

@ -1,7 +1,6 @@
#$FreeBSD$
ARMV6 opt_global.h
ARM_CACHE_LOCK_ENABLE opt_global.h
ARM_INTRNG opt_global.h
ARM_KERN_DIRECTMAP opt_vm.h
ARM_L2_PIPT opt_global.h
ARM_MANY_BOARD opt_global.h
@ -24,6 +23,7 @@ DEV_PMU opt_global.h
EFI opt_platform.h
FLASHADDR opt_global.h
GIC_DEFAULT_ICFGR_INIT opt_global.h
INTRNG opt_global.h
IPI_IRQ_START opt_smp.h
IPI_IRQ_END opt_smp.h
FREEBSD_BOOT_LOADER opt_global.h

2
sys/conf/options.mips
View File

@ -144,5 +144,5 @@ PV_STATS opt_pmap.h
#
# Options to use INTRNG code
#
MIPS_INTRNG opt_global.h
INTRNG opt_global.h
MIPS_NIRQ opt_global.h

2
sys/dev/fdt/fdt_common.h
View File

@ -45,7 +45,7 @@ struct fdt_sense_level {
enum intr_polarity pol;
};
#if defined(__arm__) && !defined(ARM_INTRNG)
#if defined(__arm__) && !defined(INTRNG)
typedef int (*fdt_pic_decode_t)(phandle_t, pcell_t *, int *, int *, int *);
extern fdt_pic_decode_t fdt_pic_table[];
#endif

4
sys/mips/include/intr.h
View File

@ -39,7 +39,7 @@
#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_
#ifdef MIPS_INTRNG
#ifdef INTRNG
#ifdef FDT
#include <dev/ofw/openfirm.h>
@ -66,6 +66,6 @@ void cpu_establish_softintr(const char *, driver_filter_t *, void (*)(void*),
/* MIPS interrupt C entry point */
void cpu_intr(struct trapframe *);
#endif /* MIPS_INTRNG */
#endif /* INTRNG */
#endif /* _MACHINE_INTR_H */

2
sys/mips/include/smp.h
View File

@ -21,7 +21,7 @@
#include <machine/pcb.h>
#ifdef MIPS_INTRNG
#ifdef INTRNG
# define MIPS_IPI_COUNT 1
# define INTR_IPI_COUNT MIPS_IPI_COUNT
#endif

8
sys/mips/mips/exception.S
View File

@ -646,7 +646,7 @@ NESTED_NOPROFILE(MipsKernIntr, KERN_EXC_FRAME_SIZE, ra)
* Call the interrupt handler. a0 points at the saved frame.
*/
PTR_LA gp, _C_LABEL(_gp)
#ifdef MIPS_INTRNG
#ifdef INTRNG
PTR_LA k0, _C_LABEL(intr_irq_handler)
#else
PTR_LA k0, _C_LABEL(cpu_intr)
@ -762,7 +762,7 @@ NESTED_NOPROFILE(MipsUserIntr, CALLFRAME_SIZ, ra)
/*
* Call the interrupt handler.
*/
#ifdef MIPS_INTRNG
#ifdef INTRNG
PTR_LA k0, _C_LABEL(intr_irq_handler)
#else
PTR_LA k0, _C_LABEL(cpu_intr)
@ -1198,7 +1198,7 @@ FPReturn:
PTR_ADDU sp, sp, CALLFRAME_SIZ
END(MipsFPTrap)
#ifndef MIPS_INTRNG
#ifndef INTRNG
/*
* Interrupt counters for vmstat.
*/
@ -1225,7 +1225,7 @@ sintrcnt:
#else
.int INTRCNT_COUNT * (_MIPS_SZLONG / 8) * 2
#endif
#endif /* MIPS_INTRNG */
#endif /* INTRNG */
/*

14
sys/mips/mips/nexus.c
View File

@ -57,7 +57,7 @@ __FBSDID("$FreeBSD$");
#include <machine/resource.h>
#include <machine/vmparam.h>
#ifdef MIPS_INTRNG
#ifdef INTRNG
#include <machine/intr.h>
#else
#include <machine/intr_machdep.h>
@ -115,7 +115,7 @@ static int nexus_setup_intr(device_t dev, device_t child,
driver_intr_t *intr, void *arg, void **cookiep);
static int nexus_teardown_intr(device_t, device_t, struct resource *,
void *);
#ifdef MIPS_INTRNG
#ifdef INTRNG
#ifdef SMP
static int nexus_bind_intr(device_t, device_t, struct resource *, int);
#endif
@ -148,7 +148,7 @@ static device_method_t nexus_methods[] = {
DEVMETHOD(bus_activate_resource,nexus_activate_resource),
DEVMETHOD(bus_deactivate_resource, nexus_deactivate_resource),
DEVMETHOD(bus_hinted_child, nexus_hinted_child),
#ifdef MIPS_INTRNG
#ifdef INTRNG
DEVMETHOD(bus_config_intr, nexus_config_intr),
DEVMETHOD(bus_describe_intr, nexus_describe_intr),
#ifdef SMP
@ -458,7 +458,7 @@ nexus_setup_intr(device_t dev, device_t child, struct resource *res, int flags,
driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep)
{
#ifdef MIPS_INTRNG
#ifdef INTRNG
return (intr_setup_irq(child, res, filt, intr, arg, flags, cookiep));
#else
int irq;
@ -483,7 +483,7 @@ static int
nexus_teardown_intr(device_t dev, device_t child, struct resource *r, void *ih)
{
#ifdef MIPS_INTRNG
#ifdef INTRNG
return (intr_teardown_irq(child, r, ih));
#else
printf("Unimplemented %s at %s:%d\n", __func__, __FILE__, __LINE__);
@ -491,7 +491,7 @@ nexus_teardown_intr(device_t dev, device_t child, struct resource *r, void *ih)
#endif
}
#ifdef MIPS_INTRNG
#ifdef INTRNG
static int
nexus_config_intr(device_t dev, int irq, enum intr_trigger trig,
enum intr_polarity pol)
@ -527,7 +527,7 @@ nexus_ofw_map_intr(device_t dev, device_t child, phandle_t iparent, int icells,
return (intr_fdt_map_irq(iparent, intr, icells));
}
#endif
#endif /* MIPS_INTRNG */
#endif /* INTRNG */
static void
nexus_hinted_child(device_t bus, const char *dname, int dunit)

6
sys/mips/mips/tick.c
View File

@ -51,7 +51,7 @@ __FBSDID("$FreeBSD$");
#include <machine/locore.h>
#include <machine/md_var.h>
#ifdef MIPS_INTRNG
#ifdef INTRNG
#include <machine/intr.h>
#endif
@ -328,7 +328,7 @@ static int
clock_attach(device_t dev)
{
struct clock_softc *sc;
#ifndef MIPS_INTRNG
#ifndef INTRNG
int error;
#endif
@ -336,7 +336,7 @@ clock_attach(device_t dev)
panic("can't attach more clocks");
softc = sc = device_get_softc(dev);
#ifdef MIPS_INTRNG
#ifdef INTRNG
cpu_establish_hardintr("clock", clock_intr, NULL, sc, 5, INTR_TYPE_CLK,
NULL);
#else