Execute an initial ptesync if and only if the PTE is actually being
invalidated, as opposed to a ref/changed bit update.
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@ -153,13 +153,10 @@ TLBIE(uint64_t vpn) {
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vpn &= ~(0xffffULL << 48);
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#ifdef __powerpc64__
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sched_pin();
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__asm __volatile("ptesync");
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mtx_lock(&tlbie_mutex);
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__asm __volatile("tlbie %0" :: "r"(vpn) : "memory");
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mtx_unlock(&tlbie_mutex);
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__asm __volatile("eieio; tlbsync; ptesync");
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sched_unpin();
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#else
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vpn_hi = (uint32_t)(vpn >> 32);
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vpn_lo = (uint32_t)vpn;
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@ -171,7 +168,6 @@ TLBIE(uint64_t vpn) {
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mr %1, %0; \
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insrdi %1,%5,1,0; \
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mtmsrd %1; isync; \
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ptesync; \
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\
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sld %1,%2,%4; \
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or %1,%1,%3; \
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@ -265,7 +261,9 @@ moea64_pte_clear_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt,
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* As shown in Section 7.6.3.2.3
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*/
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pt->pte_lo &= ~ptebit;
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sched_pin();
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TLBIE(vpn);
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sched_unpin();
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}
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static void
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@ -295,21 +293,16 @@ moea64_pte_unset_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt,
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{
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struct lpte *pt = (struct lpte *)pt_cookie;
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pvo_pt->pte_hi &= ~LPTE_VALID;
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/* Finish all pending operations */
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isync();
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/*
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* Force the reg & chg bits back into the PTEs.
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*/
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SYNC();
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/*
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* Invalidate the pte.
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*/
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isync();
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sched_pin();
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pvo_pt->pte_hi &= ~LPTE_VALID;
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pt->pte_hi &= ~LPTE_VALID;
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PTESYNC();
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TLBIE(vpn);
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sched_unpin();
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/*
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* Save the reg & chg bits.
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