Introduce Mediatek/Ralink PCIe support
This revision introduces PCIe support for the relevant Mediatek/Ralink SoCs. Currently the PCIe support is not converted to INTRNG, this may be a task for the future. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D5886
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sgalabov
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sys/mips/mediatek/mtk_pcie.c
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sys/mips/mediatek/mtk_pcie.c
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sys/mips/mediatek/mtk_pcie.h
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sys/mips/mediatek/mtk_pcie.h
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/*-
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* Copyright (c) 2016 Stanislav Galabov.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __MTK_PCIE_H__
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#define __MTK_PCIE_H__
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#define PCI_MIN_IO_ALLOC 4
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#define PCI_MIN_MEM_ALLOC 16
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#define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
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#define MTK_PCI_NIRQS 3
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#define MTK_PCI_BASESLOT 0
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struct mtk_pci_softc {
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device_t sc_dev;
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struct resource * pci_res[MTK_PCI_NIRQS + 1];
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void * pci_intrhand[MTK_PCI_NIRQS];
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int sc_busno;
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int sc_cur_secbus;
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struct rman sc_mem_rman;
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struct rman sc_io_rman;
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struct rman sc_irq_rman;
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uint32_t sc_num_irq;
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uint32_t sc_irq_start;
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uint32_t sc_irq_end;
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bus_addr_t sc_mem_base;
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bus_addr_t sc_mem_size;
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uint32_t sc_mem_map[(256*1024*1024) /
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(PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
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bus_addr_t sc_io_base;
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bus_addr_t sc_io_size;
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uint32_t sc_io_map[(16*1024*1024) /
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(PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
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struct intr_event *sc_eventstab[MTK_PCI_NIRQS];
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uint32_t pcie_link_status;
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uint32_t num_slots;
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uint32_t socid;
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uint32_t addr_mask;
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};
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#define MTK_PCI_PCICFG 0x0000
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#define MTK_PCI_RESET (1<<1)
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#define MTK_PCI_PCIINT 0x0008
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#define MTK_PCI_PCIENA 0x000C
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#define MTK_PCI_CFGADDR 0x0020
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#define MTK_PCI_CFGDATA 0x0024
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#define MTK_PCI_MEMBASE 0x0028
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#define MTK_PCI_IOBASE 0x002C
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#define MTK_PCI_ARBCTL 0x0080
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#define MTK_PCI_PHY0_CFG 0x0090
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#define MTK_PCI_PCIE0_BAR0SETUP 0x2010
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#define MTK_PCI_PCIE0_BAR1SETUP 0x2014
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#define MTK_PCI_PCIE0_IMBASEBAR0 0x2018
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#define MTK_PCI_PCIE0_ID 0x2030
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#define MTK_PCI_PCIE0_CLASS 0x2034
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#define MTK_PCI_PCIE0_SUBID 0x2038
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#define MTK_PCI_PCIE0_STATUS 0x2050
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#define MTK_PCI_PCIE0_DLECR 0x2060
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#define MTK_PCI_PCIE0_ECRC 0x2064
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#define MTK_PCIE_BAR0SETUP(_s) (MTK_PCI_PCIE0_BAR0SETUP + (_s)*0x1000)
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#define MTK_PCIE_BAR1SETUP(_s) (MTK_PCI_PCIE0_BAR1SETUP + (_s)*0x1000)
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#define MTK_PCIE_IMBASEBAR0(_s) (MTK_PCI_PCIE0_IMBASEBAR0 + (_s)*0x1000)
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#define MTK_PCIE_ID(_s) (MTK_PCI_PCIE0_ID + (_s)*0x1000)
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#define MTK_PCIE_CLASS(_s) (MTK_PCI_PCIE0_CLASS + (_s)*0x1000)
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#define MTK_PCIE_SUBID(_s) (MTK_PCI_PCIE0_SUBID + (_s)*0x1000)
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#define MTK_PCIE_STATUS(_s) (MTK_PCI_PCIE0_STATUS + (_s)*0x1000)
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#define MTK_PCIE0_IRQ 20
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#define MTK_PCIE1_IRQ 21
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#define MTK_PCIE2_IRQ 22
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#define MTK_PCI_INTR_PIN 2
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/* Chip specific defines */
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#define MT7620_MAX_RETRIES 10
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#define MT7620_PCIE_PHY_CFG 0x90
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#define PHY_BUSY (1<<31)
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#define PHY_MODE_WRITE (1<<23)
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#define PHY_ADDR_OFFSET 8
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#define MT7620_PPLL_CFG0 0x98
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#define PPLL_SW_SET (1<<31)
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#define MT7620_PPLL_CFG1 0x9c
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#define PPLL_PD (1<<26)
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#define PPLL_LOCKED (1<<23)
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#define MT7620_PPLL_DRV 0xa0
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#define PDRV_SW_SET (1<<31)
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#define LC_CKDRVPD (1<<19)
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#define LC_CKDRVOHZ (1<<18)
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#define LC_CKDRVHZ (1<<17)
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#define MT7620_PERST_GPIO_MODE (3<<16)
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#define MT7620_PERST (0<<16)
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#define MT7620_GPIO (2<<16)
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#define MT7620_PKG_BGA (1<<16)
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#define MT7628_PERST_GPIO_MODE (1<<16)
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#define MT7628_PERST (0<<16)
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#define MT7621_PERST_GPIO_MODE (3<<10)
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#define MT7621_PERST_GPIO (1<<10)
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#define MT7621_UARTL3_GPIO_MODE (3<<3)
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#define MT7621_UARTL3_GPIO (1<<3)
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#define MT7621_PCIE0_RST (1<<19)
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#define MT7621_PCIE1_RST (1<<8)
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#define MT7621_PCIE2_RST (1<<7)
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#define MT7621_PCIE_RST (MT7621_PCIE0_RST | MT7621_PCIE1_RST | \
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MT7621_PCIE2_RST)
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#define RT3883_PCI_RST (1<<24)
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#define RT3883_PCI_CLK (1<<19)
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#define RT3883_PCI_HOST_MODE (1<<7)
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#define RT3883_PCIE_RC_MODE (1<<8)
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/* End of chip specific defines */
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#define MT_WRITE32(sc, off, val) \
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bus_write_4((sc)->pci_res[0], (off), (val))
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#define MT_WRITE16(sc, off, val) \
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bus_write_2((sc)->pci_res[0], (off), (val))
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#define MT_WRITE8(sc, off, val) \
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bus_write_1((sc)->pci_res[0], (off), (val))
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#define MT_READ32(sc, off) \
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bus_read_4((sc)->pci_res[0], (off))
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#define MT_READ16(sc, off) \
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bus_read_2((sc)->pci_res[0], (off))
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#define MT_READ8(sc, off) \
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bus_read_1((sc)->pci_res[0], (off))
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#define MT_CLR_SET32(sc, off, clr, set) \
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MT_WRITE32((sc), (off), ((MT_READ32((sc), (off)) & ~(clr)) | (off)))
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#endif /* __MTK_PCIE_H__ */
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