Add support for HiFive Unleashed -- the board with a multi-core RISC-V SoC
from SiFive, Inc. The first core on this SoC (hart 0) is a 64-bit microcontroller. o Pick a hart to run boot process using hart lottery. This allows to exclude hart 0 from running the boot process. (BBL releases hart 0 after the main harts, so it never wins the lottery). o Renumber CPUs early on boot. Exclude non-MMU cores. Store the original hart ID in struct pcpu. This allows to find out the correct destination for IPIs and remote sfence calls. Thanks to SiFive, Inc for the board provided. Reviewed by: markj Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D20225
This commit is contained in:
Ruslan Bukin
parent
da153f8e60
commit
b803d0b790
@ -47,7 +47,8 @@
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#define PCPU_MD_FIELDS \
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struct pmap *pc_curpmap; /* Currently active pmap */ \
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uint32_t pc_pending_ipis; /* IPIs pending to this CPU */ \
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char __pad[61]
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uint32_t pc_hart; /* Hart ID */ \
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char __pad[57]
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#ifdef _KERNEL
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@ -207,7 +207,7 @@ ipi_send(struct pcpu *pc, int ipi)
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CTR3(KTR_SMP, "%s: cpu=%d, ipi=%x", __func__, pc->pc_cpuid, ipi);
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atomic_set_32(&pc->pc_pending_ipis, ipi);
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mask = (1 << (pc->pc_cpuid));
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mask = (1 << pc->pc_hart);
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sbi_send_ipi(&mask);
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@ -252,7 +252,7 @@ ipi_selected(cpuset_t cpus, u_int ipi)
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CTR3(KTR_SMP, "%s: pc: %p, ipi: %x\n", __func__, pc,
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ipi);
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atomic_set_32(&pc->pc_pending_ipis, ipi);
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mask |= (1 << (pc->pc_cpuid));
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mask |= (1 << pc->pc_hart);
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}
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}
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sbi_send_ipi(&mask);
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@ -59,11 +59,17 @@ _start:
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sub t1, t1, t0
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li t2, KERNBASE
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sub s9, t2, t1 /* s9 = physmem base */
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mv s10, a0 /* s10 = hart id */
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mv s11, a1 /* s11 = dtbp */
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/* Direct secondary cores to mpentry */
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bnez s10, mpentry
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/*
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* a0 = hart id
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* a1 = dtbp
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*/
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/* Pick a hart to run the boot process. */
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la t0, hart_lottery
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li t1, 1
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amoadd.w t0, t1, 0(t0)
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bnez t0, mpentry
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/*
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* Page tables
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@ -123,7 +129,7 @@ _start:
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/* Create an L2 page superpage for DTB */
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la s1, pagetable_l2_devmap
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mv s2, s11
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mv s2, a1
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srli s2, s2, PAGE_SHIFT
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li t0, (PTE_KERN)
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@ -171,12 +177,18 @@ va:
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addi sp, sp, -PCB_SIZE
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/* Clear BSS */
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la a0, _C_LABEL(__bss_start)
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la s0, _C_LABEL(__bss_start)
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la s1, _C_LABEL(_end)
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1:
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sd zero, 0(a0)
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addi a0, a0, 8
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bltu a0, s1, 1b
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sd zero, 0(s0)
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addi s0, s0, 8
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bltu s0, s1, 1b
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#ifdef SMP
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/* Store boot hart id. */
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la t0, boot_hart
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sw a0, 0(t0)
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#endif
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/* Fill riscv_bootparams */
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addi sp, sp, -40
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@ -190,7 +202,7 @@ va:
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li t0, (VM_MAX_KERNEL_ADDRESS - 2 * L2_SIZE)
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sd t0, 24(sp) /* dtbp_virt */
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sd s11, 32(sp) /* dtbp_phys */
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sd a1, 32(sp) /* dtbp_phys */
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mv a0, sp
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call _C_LABEL(initriscv) /* Off we go */
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@ -233,9 +245,11 @@ pagetable_l2:
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pagetable_l2_devmap:
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.space PAGE_SIZE
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.align 3
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.align 3
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virt_map:
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.quad virt_map
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.quad virt_map
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hart_lottery:
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.space 4
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/* Not in use, but required for linking. */
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.align 3
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@ -278,7 +292,8 @@ ENTRY(mpentry)
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/* Setup stack pointer */
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la t0, secondary_stacks
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li t1, (PAGE_SIZE * KSTACK_PAGES)
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mulw t1, t1, s10
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mulw t2, t1, a0
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add t0, t0, t2
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add t0, t0, t1
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sub t0, t0, s9
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li t1, KERNBASE
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@ -117,6 +117,9 @@ int64_t dcache_line_size; /* The minimum D cache line size */
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int64_t icache_line_size; /* The minimum I cache line size */
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int64_t idcache_line_size; /* The minimum cache line size */
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uint32_t boot_hart; /* The hart we booted on. */
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cpuset_t all_harts;
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extern int *end;
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extern int *initstack_end;
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@ -815,6 +818,7 @@ initriscv(struct riscv_bootparams *rvbp)
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/* Set the pcpu data, this is needed by pmap_bootstrap */
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pcpup = &__pcpu[0];
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pcpu_init(pcpup, 0, sizeof(struct pcpu));
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pcpup->pc_hart = boot_hart;
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/* Set the pcpu pointer */
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__asm __volatile("mv gp, %0" :: "r"(pcpup));
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@ -91,6 +91,9 @@ static int ipi_handler(void *);
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struct mtx ap_boot_mtx;
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struct pcb stoppcbs[MAXCPU];
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extern uint32_t boot_hart;
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extern cpuset_t all_harts;
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#ifdef INVARIANTS
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static uint32_t cpu_reg[MAXCPU][2];
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#endif
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@ -99,7 +102,7 @@ static device_t cpu_list[MAXCPU];
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void mpentry(unsigned long cpuid);
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void init_secondary(uint64_t);
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uint8_t secondary_stacks[MAXCPU - 1][PAGE_SIZE * KSTACK_PAGES] __aligned(16);
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uint8_t secondary_stacks[MAXCPU][PAGE_SIZE * KSTACK_PAGES] __aligned(16);
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/* Set to 1 once we're ready to let the APs out of the pen. */
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volatile int aps_ready = 0;
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@ -182,7 +185,7 @@ riscv64_cpu_attach(device_t dev)
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static void
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release_aps(void *dummy __unused)
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{
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u_long mask;
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cpuset_t mask;
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int cpu, i;
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if (mp_ncpus == 1)
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@ -194,15 +197,13 @@ release_aps(void *dummy __unused)
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atomic_store_rel_int(&aps_ready, 1);
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/* Wake up the other CPUs */
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mask = 0;
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for (i = 1; i < mp_ncpus; i++)
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mask |= (1 << i);
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sbi_send_ipi(&mask);
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mask = all_harts;
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CPU_CLR(boot_hart, &mask);
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printf("Release APs\n");
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sbi_send_ipi(mask.__bits);
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for (i = 0; i < 2000; i++) {
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if (smp_started) {
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for (cpu = 0; cpu <= mp_maxid; cpu++) {
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@ -219,12 +220,19 @@ release_aps(void *dummy __unused)
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SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
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void
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init_secondary(uint64_t cpu)
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init_secondary(uint64_t hart)
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{
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struct pcpu *pcpup;
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u_int cpuid;
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/* Renumber this cpu */
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cpuid = hart;
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if (cpuid < boot_hart)
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cpuid += mp_maxid + 1;
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cpuid -= boot_hart;
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/* Setup the pcpu pointer */
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pcpup = &__pcpu[cpu];
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pcpup = &__pcpu[cpuid];
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__asm __volatile("mv gp, %0" :: "r"(pcpup));
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/* Workaround: make sure wfi doesn't halt the hart */
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@ -366,11 +374,12 @@ cpu_mp_probe(void)
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static boolean_t
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cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
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{
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uint64_t target_cpu;
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struct pcpu *pcpup;
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uint64_t hart;
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u_int cpuid;
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/* Check we are able to start this cpu */
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if (id > mp_maxid)
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/* Check if this hart supports MMU. */
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if (OF_getproplen(node, "mmu-type") < 0)
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return (0);
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KASSERT(id < MAXCPU, ("Too many CPUs"));
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@ -382,28 +391,43 @@ cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
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cpu_reg[id][1] = reg[1];
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#endif
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target_cpu = reg[0];
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hart = reg[0];
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if (addr_size == 2) {
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target_cpu <<= 32;
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target_cpu |= reg[1];
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hart <<= 32;
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hart |= reg[1];
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}
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pcpup = &__pcpu[id];
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KASSERT(hart < MAXCPU, ("Too many harts."));
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/* We are already running on cpu 0 */
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if (id == 0) {
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/* We are already running on this cpu */
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if (hart == boot_hart)
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return (1);
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}
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pcpu_init(pcpup, id, sizeof(struct pcpu));
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/*
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* Rotate the CPU IDs to put the boot CPU as CPU 0.
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* We keep the other CPUs ordered.
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*/
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cpuid = hart;
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if (cpuid < boot_hart)
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cpuid += mp_maxid + 1;
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cpuid -= boot_hart;
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dpcpu[id - 1] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
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dpcpu_init(dpcpu[id - 1], id);
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/* Check if we are able to start this cpu */
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if (cpuid > mp_maxid)
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return (0);
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printf("Starting CPU %u (%lx)\n", id, target_cpu);
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__riscv_boot_ap[id] = 1;
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pcpup = &__pcpu[cpuid];
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pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
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pcpup->pc_hart = hart;
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CPU_SET(id, &all_cpus);
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dpcpu[cpuid - 1] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
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dpcpu_init(dpcpu[cpuid - 1], cpuid);
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printf("Starting CPU %u (hart %lx)\n", cpuid, hart);
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__riscv_boot_ap[hart] = 1;
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CPU_SET(cpuid, &all_cpus);
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CPU_SET(hart, &all_harts);
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return (1);
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}
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@ -417,6 +441,7 @@ cpu_mp_start(void)
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mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
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CPU_SET(0, &all_cpus);
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CPU_SET(boot_hart, &all_harts);
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switch(cpu_enum_method) {
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#ifdef FDT
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@ -435,13 +460,24 @@ cpu_mp_announce(void)
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{
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}
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static boolean_t
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cpu_check_mmu(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
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{
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/* Check if this hart supports MMU. */
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if (OF_getproplen(node, "mmu-type") < 0)
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return (0);
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return (1);
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}
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void
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cpu_mp_setmaxid(void)
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{
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#ifdef FDT
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int cores;
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cores = ofw_cpu_early_foreach(NULL, false);
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cores = ofw_cpu_early_foreach(cpu_check_mmu, true);
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if (cores > 0) {
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cores = MIN(cores, MAXCPU);
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if (bootverbose)
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@ -273,6 +273,8 @@ static struct rwlock pv_list_locks[NPV_LIST_LOCKS];
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static struct md_page *pv_table;
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static struct md_page pv_dummy;
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extern cpuset_t all_harts;
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/*
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* Internal flags for pmap_enter()'s helper functions.
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*/
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@ -737,7 +739,7 @@ pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
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sched_pin();
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mask = pmap->pm_active;
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CPU_CLR(PCPU_GET(cpuid), &mask);
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CPU_CLR(PCPU_GET(hart), &mask);
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fence();
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if (!CPU_EMPTY(&mask) && smp_started)
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sbi_remote_sfence_vma(mask.__bits, va, 1);
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@ -752,7 +754,7 @@ pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
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sched_pin();
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mask = pmap->pm_active;
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CPU_CLR(PCPU_GET(cpuid), &mask);
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CPU_CLR(PCPU_GET(hart), &mask);
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fence();
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if (!CPU_EMPTY(&mask) && smp_started)
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sbi_remote_sfence_vma(mask.__bits, sva, eva - sva + 1);
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@ -772,7 +774,7 @@ pmap_invalidate_all(pmap_t pmap)
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sched_pin();
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mask = pmap->pm_active;
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CPU_CLR(PCPU_GET(cpuid), &mask);
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CPU_CLR(PCPU_GET(hart), &mask);
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/*
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* XXX: The SBI doc doesn't detail how to specify x0 as the
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@ -4255,7 +4257,7 @@ void
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pmap_activate_sw(struct thread *td)
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{
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pmap_t oldpmap, pmap;
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u_int cpu;
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u_int hart;
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oldpmap = PCPU_GET(curpmap);
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pmap = vmspace_pmap(td->td_proc->p_vmspace);
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@ -4263,13 +4265,13 @@ pmap_activate_sw(struct thread *td)
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return;
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load_satp(pmap->pm_satp);
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cpu = PCPU_GET(cpuid);
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hart = PCPU_GET(hart);
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#ifdef SMP
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CPU_SET_ATOMIC(cpu, &pmap->pm_active);
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CPU_CLR_ATOMIC(cpu, &oldpmap->pm_active);
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CPU_SET_ATOMIC(hart, &pmap->pm_active);
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CPU_CLR_ATOMIC(hart, &oldpmap->pm_active);
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#else
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CPU_SET(cpu, &pmap->pm_active);
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CPU_CLR(cpu, &oldpmap->pm_active);
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CPU_SET(hart, &pmap->pm_active);
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CPU_CLR(hart, &oldpmap->pm_active);
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#endif
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PCPU_SET(curpmap, pmap);
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@ -4288,13 +4290,13 @@ pmap_activate(struct thread *td)
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void
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pmap_activate_boot(pmap_t pmap)
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{
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u_int cpu;
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u_int hart;
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cpu = PCPU_GET(cpuid);
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hart = PCPU_GET(hart);
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#ifdef SMP
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CPU_SET_ATOMIC(cpu, &pmap->pm_active);
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CPU_SET_ATOMIC(hart, &pmap->pm_active);
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#else
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CPU_SET(cpu, &pmap->pm_active);
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CPU_SET(hart, &pmap->pm_active);
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#endif
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PCPU_SET(curpmap, pmap);
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}
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@ -4313,8 +4315,8 @@ pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t sz)
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* FENCE.I."
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*/
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sched_pin();
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mask = all_cpus;
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CPU_CLR(PCPU_GET(cpuid), &mask);
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mask = all_harts;
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CPU_CLR(PCPU_GET(hart), &mask);
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fence();
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if (!CPU_EMPTY(&mask) && smp_started)
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sbi_remote_fence_i(mask.__bits);
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