Bring these back to HEAD.
(I thought ncvs@ had rm'ed these MIPS files a long time ago... SVN had better work out - else 7 more files off the vendor branch.)
This commit is contained in:
obrien
parent
8bca5d6f6b
commit
b89ade4fa4
2701
contrib/binutils/bfd/coff-mips.c
Normal file
2701
contrib/binutils/bfd/coff-mips.c
Normal file
File diff suppressed because it is too large
Load Diff
127
contrib/binutils/bfd/cpu-mips.c
Normal file
127
contrib/binutils/bfd/cpu-mips.c
Normal file
@ -0,0 +1,127 @@
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/* bfd back-end for mips support
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Copyright 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001,
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2002, 2003 Free Software Foundation, Inc.
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Written by Steve Chamberlain of Cygnus Support.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
|
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "bfd.h"
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#include "sysdep.h"
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#include "libbfd.h"
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static const bfd_arch_info_type *mips_compatible
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(const bfd_arch_info_type *, const bfd_arch_info_type *);
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/* The default routine tests bits_per_word, which is wrong on mips as
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mips word size doesn't correlate with reloc size. */
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static const bfd_arch_info_type *
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mips_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
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{
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if (a->arch != b->arch)
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return NULL;
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/* Machine compatibility is checked in
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_bfd_mips_elf_merge_private_bfd_data. */
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return a;
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}
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#define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \
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{ \
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BITS_WORD, /* bits in a word */ \
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BITS_ADDR, /* bits in an address */ \
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8, /* 8 bits in a byte */ \
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bfd_arch_mips, \
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NUMBER, \
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"mips", \
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PRINT, \
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3, \
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DEFAULT, \
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mips_compatible, \
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bfd_default_scan, \
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NEXT, \
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}
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enum
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{
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I_mips3000,
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I_mips3900,
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I_mips4000,
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I_mips4010,
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I_mips4100,
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I_mips4111,
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I_mips4120,
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I_mips4300,
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I_mips4400,
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I_mips4600,
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I_mips4650,
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I_mips5000,
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I_mips5400,
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I_mips5500,
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I_mips6000,
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I_mips7000,
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I_mips8000,
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I_mips10000,
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I_mips12000,
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I_mips16,
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I_mips5,
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I_mipsisa32,
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I_mipsisa32r2,
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I_mipsisa64,
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I_mipsisa64r2,
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I_sb1,
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};
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#define NN(index) (&arch_info_struct[(index) + 1])
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static const bfd_arch_info_type arch_info_struct[] =
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{
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N (32, 32, bfd_mach_mips3000, "mips:3000", FALSE, NN(I_mips3000)),
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N (32, 32, bfd_mach_mips3900, "mips:3900", FALSE, NN(I_mips3900)),
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N (64, 64, bfd_mach_mips4000, "mips:4000", FALSE, NN(I_mips4000)),
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N (64, 64, bfd_mach_mips4010, "mips:4010", FALSE, NN(I_mips4010)),
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N (64, 64, bfd_mach_mips4100, "mips:4100", FALSE, NN(I_mips4100)),
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N (64, 64, bfd_mach_mips4111, "mips:4111", FALSE, NN(I_mips4111)),
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N (64, 64, bfd_mach_mips4120, "mips:4120", FALSE, NN(I_mips4120)),
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N (64, 64, bfd_mach_mips4300, "mips:4300", FALSE, NN(I_mips4300)),
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N (64, 64, bfd_mach_mips4400, "mips:4400", FALSE, NN(I_mips4400)),
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N (64, 64, bfd_mach_mips4600, "mips:4600", FALSE, NN(I_mips4600)),
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N (64, 64, bfd_mach_mips4650, "mips:4650", FALSE, NN(I_mips4650)),
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N (64, 64, bfd_mach_mips5000, "mips:5000", FALSE, NN(I_mips5000)),
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N (64, 64, bfd_mach_mips5400, "mips:5400", FALSE, NN(I_mips5400)),
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N (64, 64, bfd_mach_mips5500, "mips:5500", FALSE, NN(I_mips5500)),
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N (32, 32, bfd_mach_mips6000, "mips:6000", FALSE, NN(I_mips6000)),
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N (64, 64, bfd_mach_mips7000, "mips:7000", FALSE, NN(I_mips7000)),
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N (64, 64, bfd_mach_mips8000, "mips:8000", FALSE, NN(I_mips8000)),
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N (64, 64, bfd_mach_mips10000,"mips:10000", FALSE, NN(I_mips10000)),
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N (64, 64, bfd_mach_mips12000,"mips:12000", FALSE, NN(I_mips12000)),
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N (64, 64, bfd_mach_mips16, "mips:16", FALSE, NN(I_mips16)),
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N (64, 64, bfd_mach_mips5, "mips:mips5", FALSE, NN(I_mips5)),
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N (32, 32, bfd_mach_mipsisa32, "mips:isa32", FALSE, NN(I_mipsisa32)),
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N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
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N (64, 64, bfd_mach_mipsisa64, "mips:isa64", FALSE, NN(I_mipsisa64)),
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N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
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N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, 0),
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};
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/* The default architecture is mips:3000, but with a machine number of
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zero. This lets the linker distinguish between a default setting
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of mips, and an explicit setting of mips:3000. */
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const bfd_arch_info_type bfd_mips_arch =
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N (32, 32, 0, "mips", TRUE, &arch_info_struct[0]);
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1618
contrib/binutils/bfd/elf32-mips.c
Normal file
1618
contrib/binutils/bfd/elf32-mips.c
Normal file
File diff suppressed because it is too large
Load Diff
2815
contrib/binutils/bfd/elf64-mips.c
Normal file
2815
contrib/binutils/bfd/elf64-mips.c
Normal file
File diff suppressed because it is too large
Load Diff
486
contrib/binutils/bfd/mipsbsd.c
Normal file
486
contrib/binutils/bfd/mipsbsd.c
Normal file
@ -0,0 +1,486 @@
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/* BFD backend for MIPS BSD (a.out) binaries.
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Copyright 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003
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Free Software Foundation, Inc.
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Written by Ralph Campbell.
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
|
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it under the terms of the GNU General Public License as published by
|
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the Free Software Foundation; either version 2 of the License, or
|
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(at your option) any later version.
|
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|
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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GNU General Public License for more details.
|
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|
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You should have received a copy of the GNU General Public License
|
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along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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/* #define ENTRY_CAN_BE_ZERO */
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#define N_HEADER_IN_TEXT(x) 1
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#define N_SHARED_LIB(x) 0
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#define N_TXTADDR(x) \
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(N_MAGIC(x) != ZMAGIC ? (x).a_entry : /* object file or NMAGIC */\
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TEXT_START_ADDR + EXEC_BYTES_SIZE /* no padding */\
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)
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#define N_DATADDR(x) (N_TXTADDR(x)+N_TXTSIZE(x))
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#define TEXT_START_ADDR 4096
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#define TARGET_PAGE_SIZE 4096
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#define SEGMENT_SIZE TARGET_PAGE_SIZE
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#define DEFAULT_ARCH bfd_arch_mips
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#define MACHTYPE_OK(mtype) ((mtype) == M_UNKNOWN \
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|| (mtype) == M_MIPS1 || (mtype) == M_MIPS2)
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#define MY_symbol_leading_char '\0'
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/* Do not "beautify" the CONCAT* macro args. Traditional C will not
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remove whitespace added here, and thus will fail to concatenate
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the tokens. */
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#define MY(OP) CONCAT2 (mipsbsd_,OP)
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#include "bfd.h"
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#include "sysdep.h"
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#include "libbfd.h"
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#include "libaout.h"
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#define SET_ARCH_MACH(ABFD, EXEC) \
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MY(set_arch_mach) (ABFD, N_MACHTYPE (EXEC)); \
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MY(choose_reloc_size) (ABFD);
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static void MY(set_arch_mach) PARAMS ((bfd *abfd, unsigned long machtype));
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static void MY(choose_reloc_size) PARAMS ((bfd *abfd));
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#define MY_write_object_contents MY(write_object_contents)
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static bfd_boolean MY(write_object_contents) PARAMS ((bfd *abfd));
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/* We can't use MY(x) here because it leads to a recursive call to CONCAT2
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when expanded inside JUMP_TABLE. */
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#define MY_bfd_reloc_type_lookup mipsbsd_reloc_howto_type_lookup
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#define MY_canonicalize_reloc mipsbsd_canonicalize_reloc
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#define MY_bfd_link_hash_table_create _bfd_generic_link_hash_table_create
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#define MY_bfd_link_add_symbols _bfd_generic_link_add_symbols
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#define MY_final_link_callback unused
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#define MY_bfd_final_link _bfd_generic_final_link
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#define MY_backend_data &MY(backend_data)
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#define MY_BFD_TARGET
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#include "aout-target.h"
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static bfd_reloc_status_type mips_fix_jmp_addr
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PARAMS ((bfd *, arelent *, struct bfd_symbol *, PTR, asection *,
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bfd *, char **));
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static reloc_howto_type *MY(reloc_howto_type_lookup)
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PARAMS ((bfd *, bfd_reloc_code_real_type));
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long MY(canonicalize_reloc) PARAMS ((bfd *, sec_ptr, arelent **, asymbol **));
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static void
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MY(set_arch_mach) (abfd, machtype)
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bfd *abfd;
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unsigned long machtype;
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{
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enum bfd_architecture arch;
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unsigned int machine;
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/* Determine the architecture and machine type of the object file. */
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switch (machtype)
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{
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case M_MIPS1:
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arch = bfd_arch_mips;
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machine = bfd_mach_mips3000;
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break;
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case M_MIPS2:
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arch = bfd_arch_mips;
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machine = bfd_mach_mips4000;
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break;
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default:
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arch = bfd_arch_obscure;
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machine = 0;
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break;
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}
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bfd_set_arch_mach (abfd, arch, machine);
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}
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/* Determine the size of a relocation entry, based on the architecture */
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static void
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MY (choose_reloc_size) (abfd)
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bfd *abfd;
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||||
{
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||||
switch (bfd_get_arch (abfd))
|
||||
{
|
||||
case bfd_arch_sparc:
|
||||
case bfd_arch_a29k:
|
||||
case bfd_arch_mips:
|
||||
obj_reloc_entry_size (abfd) = RELOC_EXT_SIZE;
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break;
|
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default:
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obj_reloc_entry_size (abfd) = RELOC_STD_SIZE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Write an object file in BSD a.out format.
|
||||
Section contents have already been written. We write the
|
||||
file header, symbols, and relocation. */
|
||||
|
||||
static bfd_boolean
|
||||
MY (write_object_contents) (abfd)
|
||||
bfd *abfd;
|
||||
{
|
||||
struct external_exec exec_bytes;
|
||||
struct internal_exec *execp = exec_hdr (abfd);
|
||||
|
||||
/* Magic number, maestro, please! */
|
||||
switch (bfd_get_arch (abfd))
|
||||
{
|
||||
case bfd_arch_m68k:
|
||||
switch (bfd_get_mach (abfd))
|
||||
{
|
||||
case bfd_mach_m68010:
|
||||
N_SET_MACHTYPE (*execp, M_68010);
|
||||
break;
|
||||
default:
|
||||
case bfd_mach_m68020:
|
||||
N_SET_MACHTYPE (*execp, M_68020);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case bfd_arch_sparc:
|
||||
N_SET_MACHTYPE (*execp, M_SPARC);
|
||||
break;
|
||||
case bfd_arch_i386:
|
||||
N_SET_MACHTYPE (*execp, M_386);
|
||||
break;
|
||||
case bfd_arch_a29k:
|
||||
N_SET_MACHTYPE (*execp, M_29K);
|
||||
break;
|
||||
case bfd_arch_mips:
|
||||
switch (bfd_get_mach (abfd))
|
||||
{
|
||||
case bfd_mach_mips4000:
|
||||
case bfd_mach_mips6000:
|
||||
N_SET_MACHTYPE (*execp, M_MIPS2);
|
||||
break;
|
||||
default:
|
||||
N_SET_MACHTYPE (*execp, M_MIPS1);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
N_SET_MACHTYPE (*execp, M_UNKNOWN);
|
||||
}
|
||||
|
||||
MY (choose_reloc_size) (abfd);
|
||||
|
||||
WRITE_HEADERS (abfd, execp);
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* MIPS relocation types. */
|
||||
#define MIPS_RELOC_32 0
|
||||
#define MIPS_RELOC_JMP 1
|
||||
#define MIPS_RELOC_WDISP16 2
|
||||
#define MIPS_RELOC_HI16 3
|
||||
#define MIPS_RELOC_HI16_S 4
|
||||
#define MIPS_RELOC_LO16 5
|
||||
|
||||
/* This is only called when performing a BFD_RELOC_MIPS_JMP relocation.
|
||||
The jump destination address is formed from the upper 4 bits of the
|
||||
"current" program counter concatenated with the jump instruction's
|
||||
26 bit field and two trailing zeros.
|
||||
If the destination address is not in the same segment as the "current"
|
||||
program counter, then we need to signal an error. */
|
||||
|
||||
static bfd_reloc_status_type
|
||||
mips_fix_jmp_addr (abfd, reloc_entry, symbol, data, input_section, output_bfd,
|
||||
error_message)
|
||||
bfd *abfd ATTRIBUTE_UNUSED;
|
||||
arelent *reloc_entry;
|
||||
struct bfd_symbol *symbol;
|
||||
PTR data ATTRIBUTE_UNUSED;
|
||||
asection *input_section;
|
||||
bfd *output_bfd;
|
||||
char **error_message ATTRIBUTE_UNUSED;
|
||||
{
|
||||
bfd_vma relocation, pc;
|
||||
|
||||
/* If this is a partial relocation, just continue. */
|
||||
if (output_bfd != (bfd *)NULL)
|
||||
return bfd_reloc_continue;
|
||||
|
||||
/* If this is an undefined symbol, return error */
|
||||
if (bfd_is_und_section (symbol->section)
|
||||
&& (symbol->flags & BSF_WEAK) == 0)
|
||||
return bfd_reloc_undefined;
|
||||
|
||||
/* Work out which section the relocation is targeted at and the
|
||||
initial relocation command value. */
|
||||
if (bfd_is_com_section (symbol->section))
|
||||
relocation = 0;
|
||||
else
|
||||
relocation = symbol->value;
|
||||
|
||||
relocation += symbol->section->output_section->vma;
|
||||
relocation += symbol->section->output_offset;
|
||||
relocation += reloc_entry->addend;
|
||||
|
||||
pc = input_section->output_section->vma + input_section->output_offset +
|
||||
reloc_entry->address + 4;
|
||||
|
||||
if ((relocation & 0xF0000000) != (pc & 0xF0000000))
|
||||
return bfd_reloc_overflow;
|
||||
|
||||
return bfd_reloc_continue;
|
||||
}
|
||||
|
||||
/* This is only called when performing a BFD_RELOC_HI16_S relocation.
|
||||
We need to see if bit 15 is set in the result. If it is, we add
|
||||
0x10000 and continue normally. This will compensate for the sign extension
|
||||
when the low bits are added at run time. */
|
||||
|
||||
static bfd_reloc_status_type
|
||||
mips_fix_hi16_s PARAMS ((bfd *, arelent *, asymbol *, PTR,
|
||||
asection *, bfd *, char **));
|
||||
|
||||
static bfd_reloc_status_type
|
||||
mips_fix_hi16_s (abfd, reloc_entry, symbol, data, input_section,
|
||||
output_bfd, error_message)
|
||||
bfd *abfd ATTRIBUTE_UNUSED;
|
||||
arelent *reloc_entry;
|
||||
asymbol *symbol;
|
||||
PTR data ATTRIBUTE_UNUSED;
|
||||
asection *input_section ATTRIBUTE_UNUSED;
|
||||
bfd *output_bfd;
|
||||
char **error_message ATTRIBUTE_UNUSED;
|
||||
{
|
||||
bfd_vma relocation;
|
||||
|
||||
/* If this is a partial relocation, just continue. */
|
||||
if (output_bfd != (bfd *)NULL)
|
||||
return bfd_reloc_continue;
|
||||
|
||||
/* If this is an undefined symbol, return error. */
|
||||
if (bfd_is_und_section (symbol->section)
|
||||
&& (symbol->flags & BSF_WEAK) == 0)
|
||||
return bfd_reloc_undefined;
|
||||
|
||||
/* Work out which section the relocation is targeted at and the
|
||||
initial relocation command value. */
|
||||
if (bfd_is_com_section (symbol->section))
|
||||
relocation = 0;
|
||||
else
|
||||
relocation = symbol->value;
|
||||
|
||||
relocation += symbol->section->output_section->vma;
|
||||
relocation += symbol->section->output_offset;
|
||||
relocation += reloc_entry->addend;
|
||||
|
||||
if (relocation & 0x8000)
|
||||
reloc_entry->addend += 0x10000;
|
||||
|
||||
return bfd_reloc_continue;
|
||||
}
|
||||
|
||||
static reloc_howto_type mips_howto_table_ext[] = {
|
||||
{MIPS_RELOC_32, 0, 2, 32, FALSE, 0, complain_overflow_bitfield, 0,
|
||||
"32", FALSE, 0, 0xffffffff, FALSE},
|
||||
{MIPS_RELOC_JMP, 2, 2, 26, FALSE, 0, complain_overflow_dont,
|
||||
mips_fix_jmp_addr,
|
||||
"MIPS_JMP", FALSE, 0, 0x03ffffff, FALSE},
|
||||
{MIPS_RELOC_WDISP16, 2, 2, 16, TRUE, 0, complain_overflow_signed, 0,
|
||||
"WDISP16", FALSE, 0, 0x0000ffff, FALSE},
|
||||
{MIPS_RELOC_HI16, 16, 2, 16, FALSE, 0, complain_overflow_bitfield, 0,
|
||||
"HI16", FALSE, 0, 0x0000ffff, FALSE},
|
||||
{MIPS_RELOC_HI16_S, 16, 2, 16, FALSE, 0, complain_overflow_bitfield,
|
||||
mips_fix_hi16_s,
|
||||
"HI16_S", FALSE, 0, 0x0000ffff, FALSE},
|
||||
{MIPS_RELOC_LO16, 0, 2, 16, FALSE, 0, complain_overflow_dont, 0,
|
||||
"LO16", FALSE, 0, 0x0000ffff, FALSE},
|
||||
};
|
||||
|
||||
static reloc_howto_type *
|
||||
MY(reloc_howto_type_lookup) (abfd, code)
|
||||
bfd *abfd;
|
||||
bfd_reloc_code_real_type code;
|
||||
{
|
||||
|
||||
if (bfd_get_arch (abfd) != bfd_arch_mips)
|
||||
return 0;
|
||||
|
||||
switch (code)
|
||||
{
|
||||
case BFD_RELOC_CTOR:
|
||||
case BFD_RELOC_32:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_32]);
|
||||
case BFD_RELOC_MIPS_JMP:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_JMP]);
|
||||
case BFD_RELOC_16_PCREL_S2:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_WDISP16]);
|
||||
case BFD_RELOC_HI16:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_HI16]);
|
||||
case BFD_RELOC_HI16_S:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_HI16_S]);
|
||||
case BFD_RELOC_LO16:
|
||||
return (&mips_howto_table_ext[MIPS_RELOC_LO16]);
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* This is just like the standard aoutx.h version but we need to do our
|
||||
own mapping of external reloc type values to howto entries. */
|
||||
long
|
||||
MY(canonicalize_reloc) (abfd, section, relptr, symbols)
|
||||
bfd *abfd;
|
||||
sec_ptr section;
|
||||
arelent **relptr;
|
||||
asymbol **symbols;
|
||||
{
|
||||
arelent *tblptr = section->relocation;
|
||||
unsigned int count, c;
|
||||
extern reloc_howto_type NAME(aout,ext_howto_table)[];
|
||||
|
||||
/* If we have already read in the relocation table, return the values. */
|
||||
if (section->flags & SEC_CONSTRUCTOR)
|
||||
{
|
||||
arelent_chain *chain = section->constructor_chain;
|
||||
|
||||
for (count = 0; count < section->reloc_count; count++)
|
||||
{
|
||||
*relptr++ = &chain->relent;
|
||||
chain = chain->next;
|
||||
}
|
||||
*relptr = 0;
|
||||
return section->reloc_count;
|
||||
}
|
||||
|
||||
if (tblptr && section->reloc_count)
|
||||
{
|
||||
for (count = 0; count++ < section->reloc_count;)
|
||||
*relptr++ = tblptr++;
|
||||
*relptr = 0;
|
||||
return section->reloc_count;
|
||||
}
|
||||
|
||||
if (!NAME(aout,slurp_reloc_table) (abfd, section, symbols))
|
||||
return -1;
|
||||
tblptr = section->relocation;
|
||||
|
||||
/* fix up howto entries. */
|
||||
for (count = 0; count++ < section->reloc_count;)
|
||||
{
|
||||
c = tblptr->howto - NAME(aout,ext_howto_table);
|
||||
tblptr->howto = &mips_howto_table_ext[c];
|
||||
|
||||
*relptr++ = tblptr++;
|
||||
}
|
||||
*relptr = 0;
|
||||
return section->reloc_count;
|
||||
}
|
||||
|
||||
static const struct aout_backend_data MY(backend_data) = {
|
||||
0, /* zmagic contiguous */
|
||||
1, /* text incl header */
|
||||
0, /* entry is text address */
|
||||
0, /* exec_hdr_flags */
|
||||
TARGET_PAGE_SIZE, /* text vma */
|
||||
MY_set_sizes,
|
||||
0, /* text size includes exec header */
|
||||
0, /* add_dynamic_symbols */
|
||||
0, /* add_one_symbol */
|
||||
0, /* link_dynamic_object */
|
||||
0, /* write_dynamic_symbol */
|
||||
0, /* check_dynamic_reloc */
|
||||
0 /* finish_dynamic_link */
|
||||
};
|
||||
|
||||
extern const bfd_target aout_mips_big_vec;
|
||||
|
||||
const bfd_target aout_mips_little_vec =
|
||||
{
|
||||
"a.out-mips-little", /* name */
|
||||
bfd_target_aout_flavour,
|
||||
BFD_ENDIAN_LITTLE, /* target byte order (little) */
|
||||
BFD_ENDIAN_LITTLE, /* target headers byte order (little) */
|
||||
(HAS_RELOC | EXEC_P | /* object flags */
|
||||
HAS_LINENO | HAS_DEBUG |
|
||||
HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
|
||||
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_CODE | SEC_DATA),
|
||||
MY_symbol_leading_char,
|
||||
' ', /* ar_pad_char */
|
||||
15, /* ar_max_namelen */
|
||||
bfd_getl64, bfd_getl_signed_64, bfd_putl64,
|
||||
bfd_getl32, bfd_getl_signed_32, bfd_putl32,
|
||||
bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
|
||||
bfd_getl64, bfd_getl_signed_64, bfd_putl64,
|
||||
bfd_getl32, bfd_getl_signed_32, bfd_putl32,
|
||||
bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
|
||||
{_bfd_dummy_target, MY_object_p, /* bfd_check_format */
|
||||
bfd_generic_archive_p, MY_core_file_p},
|
||||
{bfd_false, MY_mkobject, /* bfd_set_format */
|
||||
_bfd_generic_mkarchive, bfd_false},
|
||||
{bfd_false, MY_write_object_contents, /* bfd_write_contents */
|
||||
_bfd_write_archive_contents, bfd_false},
|
||||
|
||||
BFD_JUMP_TABLE_GENERIC (MY),
|
||||
BFD_JUMP_TABLE_COPY (MY),
|
||||
BFD_JUMP_TABLE_CORE (MY),
|
||||
BFD_JUMP_TABLE_ARCHIVE (MY),
|
||||
BFD_JUMP_TABLE_SYMBOLS (MY),
|
||||
BFD_JUMP_TABLE_RELOCS (MY),
|
||||
BFD_JUMP_TABLE_WRITE (MY),
|
||||
BFD_JUMP_TABLE_LINK (MY),
|
||||
BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
|
||||
|
||||
& aout_mips_big_vec,
|
||||
|
||||
(PTR) MY_backend_data
|
||||
};
|
||||
|
||||
const bfd_target aout_mips_big_vec =
|
||||
{
|
||||
"a.out-mips-big", /* name */
|
||||
bfd_target_aout_flavour,
|
||||
BFD_ENDIAN_BIG, /* target byte order (big) */
|
||||
BFD_ENDIAN_BIG, /* target headers byte order (big) */
|
||||
(HAS_RELOC | EXEC_P | /* object flags */
|
||||
HAS_LINENO | HAS_DEBUG |
|
||||
HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
|
||||
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_CODE | SEC_DATA),
|
||||
MY_symbol_leading_char,
|
||||
' ', /* ar_pad_char */
|
||||
15, /* ar_max_namelen */
|
||||
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
|
||||
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
|
||||
bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
|
||||
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
|
||||
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
|
||||
bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
|
||||
{_bfd_dummy_target, MY_object_p, /* bfd_check_format */
|
||||
bfd_generic_archive_p, MY_core_file_p},
|
||||
{bfd_false, MY_mkobject, /* bfd_set_format */
|
||||
_bfd_generic_mkarchive, bfd_false},
|
||||
{bfd_false, MY_write_object_contents, /* bfd_write_contents */
|
||||
_bfd_write_archive_contents, bfd_false},
|
||||
|
||||
BFD_JUMP_TABLE_GENERIC (MY),
|
||||
BFD_JUMP_TABLE_COPY (MY),
|
||||
BFD_JUMP_TABLE_CORE (MY),
|
||||
BFD_JUMP_TABLE_ARCHIVE (MY),
|
||||
BFD_JUMP_TABLE_SYMBOLS (MY),
|
||||
BFD_JUMP_TABLE_RELOCS (MY),
|
||||
BFD_JUMP_TABLE_WRITE (MY),
|
||||
BFD_JUMP_TABLE_LINK (MY),
|
||||
BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
|
||||
|
||||
& aout_mips_little_vec,
|
||||
|
||||
(PTR) MY_backend_data
|
||||
};
|
||||
1000
contrib/binutils/bfd/pe-mips.c
Normal file
1000
contrib/binutils/bfd/pe-mips.c
Normal file
File diff suppressed because it is too large
Load Diff
914
contrib/binutils/include/opcode/mips.h
Normal file
914
contrib/binutils/include/opcode/mips.h
Normal file
@ -0,0 +1,914 @@
|
||||
/* mips.h. Mips opcode list for GDB, the GNU debugger.
|
||||
Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by Ralph Campbell and OSF
|
||||
Commented and modified by Ian Lance Taylor, Cygnus Support
|
||||
|
||||
This file is part of GDB, GAS, and the GNU binutils.
|
||||
|
||||
GDB, GAS, and the GNU binutils are free software; you can redistribute
|
||||
them and/or modify them under the terms of the GNU General Public
|
||||
License as published by the Free Software Foundation; either version
|
||||
1, or (at your option) any later version.
|
||||
|
||||
GDB, GAS, and the GNU binutils are distributed in the hope that they
|
||||
will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
|
||||
the GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this file; see the file COPYING. If not, write to the Free
|
||||
Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
|
||||
|
||||
#ifndef _MIPS_H_
|
||||
#define _MIPS_H_
|
||||
|
||||
/* These are bit masks and shift counts to use to access the various
|
||||
fields of an instruction. To retrieve the X field of an
|
||||
instruction, use the expression
|
||||
(i >> OP_SH_X) & OP_MASK_X
|
||||
To set the same field (to j), use
|
||||
i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
|
||||
|
||||
Make sure you use fields that are appropriate for the instruction,
|
||||
of course.
|
||||
|
||||
The 'i' format uses OP, RS, RT and IMMEDIATE.
|
||||
|
||||
The 'j' format uses OP and TARGET.
|
||||
|
||||
The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
|
||||
|
||||
The 'b' format uses OP, RS, RT and DELTA.
|
||||
|
||||
The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
|
||||
|
||||
The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
|
||||
|
||||
A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
|
||||
breakpoint instruction are not defined; Kane says the breakpoint
|
||||
code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
|
||||
only use ten bits). An optional two-operand form of break/sdbbp
|
||||
allows the lower ten bits to be set too, and MIPS32 and later
|
||||
architectures allow 20 bits to be set with a signal operand
|
||||
(using CODE20).
|
||||
|
||||
The syscall instruction uses CODE20.
|
||||
|
||||
The general coprocessor instructions use COPZ. */
|
||||
|
||||
#define OP_MASK_OP 0x3f
|
||||
#define OP_SH_OP 26
|
||||
#define OP_MASK_RS 0x1f
|
||||
#define OP_SH_RS 21
|
||||
#define OP_MASK_FR 0x1f
|
||||
#define OP_SH_FR 21
|
||||
#define OP_MASK_FMT 0x1f
|
||||
#define OP_SH_FMT 21
|
||||
#define OP_MASK_BCC 0x7
|
||||
#define OP_SH_BCC 18
|
||||
#define OP_MASK_CODE 0x3ff
|
||||
#define OP_SH_CODE 16
|
||||
#define OP_MASK_CODE2 0x3ff
|
||||
#define OP_SH_CODE2 6
|
||||
#define OP_MASK_RT 0x1f
|
||||
#define OP_SH_RT 16
|
||||
#define OP_MASK_FT 0x1f
|
||||
#define OP_SH_FT 16
|
||||
#define OP_MASK_CACHE 0x1f
|
||||
#define OP_SH_CACHE 16
|
||||
#define OP_MASK_RD 0x1f
|
||||
#define OP_SH_RD 11
|
||||
#define OP_MASK_FS 0x1f
|
||||
#define OP_SH_FS 11
|
||||
#define OP_MASK_PREFX 0x1f
|
||||
#define OP_SH_PREFX 11
|
||||
#define OP_MASK_CCC 0x7
|
||||
#define OP_SH_CCC 8
|
||||
#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
|
||||
#define OP_SH_CODE20 6
|
||||
#define OP_MASK_SHAMT 0x1f
|
||||
#define OP_SH_SHAMT 6
|
||||
#define OP_MASK_FD 0x1f
|
||||
#define OP_SH_FD 6
|
||||
#define OP_MASK_TARGET 0x3ffffff
|
||||
#define OP_SH_TARGET 0
|
||||
#define OP_MASK_COPZ 0x1ffffff
|
||||
#define OP_SH_COPZ 0
|
||||
#define OP_MASK_IMMEDIATE 0xffff
|
||||
#define OP_SH_IMMEDIATE 0
|
||||
#define OP_MASK_DELTA 0xffff
|
||||
#define OP_SH_DELTA 0
|
||||
#define OP_MASK_FUNCT 0x3f
|
||||
#define OP_SH_FUNCT 0
|
||||
#define OP_MASK_SPEC 0x3f
|
||||
#define OP_SH_SPEC 0
|
||||
#define OP_SH_LOCC 8 /* FP condition code. */
|
||||
#define OP_SH_HICC 18 /* FP condition code. */
|
||||
#define OP_MASK_CC 0x7
|
||||
#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
|
||||
#define OP_MASK_COP1NORM 0x1 /* a single bit. */
|
||||
#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
|
||||
#define OP_MASK_COP1SPEC 0xf
|
||||
#define OP_MASK_COP1SCLR 0x4
|
||||
#define OP_MASK_COP1CMP 0x3
|
||||
#define OP_SH_COP1CMP 4
|
||||
#define OP_SH_FORMAT 21 /* FP short format field. */
|
||||
#define OP_MASK_FORMAT 0x7
|
||||
#define OP_SH_TRUE 16
|
||||
#define OP_MASK_TRUE 0x1
|
||||
#define OP_SH_GE 17
|
||||
#define OP_MASK_GE 0x01
|
||||
#define OP_SH_UNSIGNED 16
|
||||
#define OP_MASK_UNSIGNED 0x1
|
||||
#define OP_SH_HINT 16
|
||||
#define OP_MASK_HINT 0x1f
|
||||
#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
|
||||
#define OP_MASK_MMI 0x3f
|
||||
#define OP_SH_MMISUB 6
|
||||
#define OP_MASK_MMISUB 0x1f
|
||||
#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
|
||||
#define OP_SH_PERFREG 1
|
||||
#define OP_SH_SEL 0 /* Coprocessor select field. */
|
||||
#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
|
||||
#define OP_SH_CODE19 6 /* 19 bit wait code. */
|
||||
#define OP_MASK_CODE19 0x7ffff
|
||||
#define OP_SH_ALN 21
|
||||
#define OP_MASK_ALN 0x7
|
||||
#define OP_SH_VSEL 21
|
||||
#define OP_MASK_VSEL 0x1f
|
||||
#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
|
||||
but 0x8-0xf don't select bytes. */
|
||||
#define OP_SH_VECBYTE 22
|
||||
#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
|
||||
#define OP_SH_VECALIGN 21
|
||||
#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
|
||||
#define OP_SH_INSMSB 11
|
||||
#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
|
||||
#define OP_SH_EXTMSBD 11
|
||||
|
||||
#define OP_OP_COP0 0x10
|
||||
#define OP_OP_COP1 0x11
|
||||
#define OP_OP_COP2 0x12
|
||||
#define OP_OP_COP3 0x13
|
||||
#define OP_OP_LWC1 0x31
|
||||
#define OP_OP_LWC2 0x32
|
||||
#define OP_OP_LWC3 0x33 /* a.k.a. pref */
|
||||
#define OP_OP_LDC1 0x35
|
||||
#define OP_OP_LDC2 0x36
|
||||
#define OP_OP_LDC3 0x37 /* a.k.a. ld */
|
||||
#define OP_OP_SWC1 0x39
|
||||
#define OP_OP_SWC2 0x3a
|
||||
#define OP_OP_SWC3 0x3b
|
||||
#define OP_OP_SDC1 0x3d
|
||||
#define OP_OP_SDC2 0x3e
|
||||
#define OP_OP_SDC3 0x3f /* a.k.a. sd */
|
||||
|
||||
/* Values in the 'VSEL' field. */
|
||||
#define MDMX_FMTSEL_IMM_QH 0x1d
|
||||
#define MDMX_FMTSEL_IMM_OB 0x1e
|
||||
#define MDMX_FMTSEL_VEC_QH 0x15
|
||||
#define MDMX_FMTSEL_VEC_OB 0x16
|
||||
|
||||
/* This structure holds information for a particular instruction. */
|
||||
|
||||
struct mips_opcode
|
||||
{
|
||||
/* The name of the instruction. */
|
||||
const char *name;
|
||||
/* A string describing the arguments for this instruction. */
|
||||
const char *args;
|
||||
/* The basic opcode for the instruction. When assembling, this
|
||||
opcode is modified by the arguments to produce the actual opcode
|
||||
that is used. If pinfo is INSN_MACRO, then this is 0. */
|
||||
unsigned long match;
|
||||
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
|
||||
relevant portions of the opcode when disassembling. If the
|
||||
actual opcode anded with the match field equals the opcode field,
|
||||
then we have found the correct instruction. If pinfo is
|
||||
INSN_MACRO, then this field is the macro identifier. */
|
||||
unsigned long mask;
|
||||
/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
|
||||
of bits describing the instruction, notably any relevant hazard
|
||||
information. */
|
||||
unsigned long pinfo;
|
||||
/* A collection of bits describing the instruction sets of which this
|
||||
instruction or macro is a member. */
|
||||
unsigned long membership;
|
||||
};
|
||||
|
||||
/* These are the characters which may appear in the args field of an
|
||||
instruction. They appear in the order in which the fields appear
|
||||
when the instruction is used. Commas and parentheses in the args
|
||||
string are ignored when assembling, and written into the output
|
||||
when disassembling.
|
||||
|
||||
Each of these characters corresponds to a mask field defined above.
|
||||
|
||||
"<" 5 bit shift amount (OP_*_SHAMT)
|
||||
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
|
||||
"a" 26 bit target address (OP_*_TARGET)
|
||||
"b" 5 bit base register (OP_*_RS)
|
||||
"c" 10 bit breakpoint code (OP_*_CODE)
|
||||
"d" 5 bit destination register specifier (OP_*_RD)
|
||||
"h" 5 bit prefx hint (OP_*_PREFX)
|
||||
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
|
||||
"j" 16 bit signed immediate (OP_*_DELTA)
|
||||
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
|
||||
Also used for immediate operands in vr5400 vector insns.
|
||||
"o" 16 bit signed offset (OP_*_DELTA)
|
||||
"p" 16 bit PC relative branch target address (OP_*_DELTA)
|
||||
"q" 10 bit extra breakpoint code (OP_*_CODE2)
|
||||
"r" 5 bit same register used as both source and target (OP_*_RS)
|
||||
"s" 5 bit source register specifier (OP_*_RS)
|
||||
"t" 5 bit target register (OP_*_RT)
|
||||
"u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
|
||||
"v" 5 bit same register used as both source and destination (OP_*_RS)
|
||||
"w" 5 bit same register used as both target and destination (OP_*_RT)
|
||||
"U" 5 bit same destination register in both OP_*_RD and OP_*_RT
|
||||
(used by clo and clz)
|
||||
"C" 25 bit coprocessor function code (OP_*_COPZ)
|
||||
"B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
|
||||
"J" 19 bit wait function code (OP_*_CODE19)
|
||||
"x" accept and ignore register name
|
||||
"z" must be zero register
|
||||
"K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
|
||||
"+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
|
||||
Enforces: 0 <= pos < 32.
|
||||
"+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
|
||||
Requires that "+A" or "+E" occur first to set position.
|
||||
Enforces: 0 < (pos+size) <= 32.
|
||||
"+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
|
||||
Requires that "+A" or "+E" occur first to set position.
|
||||
Enforces: 0 < (pos+size) <= 32.
|
||||
(Also used by "dext" w/ different limits, but limits for
|
||||
that are checked by the M_DEXT macro.)
|
||||
"+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
|
||||
Enforces: 32 <= pos < 64.
|
||||
"+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
|
||||
Requires that "+A" or "+E" occur first to set position.
|
||||
Enforces: 32 < (pos+size) <= 64.
|
||||
"+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
|
||||
Requires that "+A" or "+E" occur first to set position.
|
||||
Enforces: 32 < (pos+size) <= 64.
|
||||
"+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
|
||||
Requires that "+A" or "+E" occur first to set position.
|
||||
Enforces: 32 < (pos+size) <= 64.
|
||||
|
||||
Floating point instructions:
|
||||
"D" 5 bit destination register (OP_*_FD)
|
||||
"M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
|
||||
"N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
|
||||
"S" 5 bit fs source 1 register (OP_*_FS)
|
||||
"T" 5 bit ft source 2 register (OP_*_FT)
|
||||
"R" 5 bit fr source 3 register (OP_*_FR)
|
||||
"V" 5 bit same register used as floating source and destination (OP_*_FS)
|
||||
"W" 5 bit same register used as floating target and destination (OP_*_FT)
|
||||
|
||||
Coprocessor instructions:
|
||||
"E" 5 bit target register (OP_*_RT)
|
||||
"G" 5 bit destination register (OP_*_RD)
|
||||
"H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
|
||||
"P" 5 bit performance-monitor register (OP_*_PERFREG)
|
||||
"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
|
||||
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
|
||||
see also "k" above
|
||||
"+D" Combined destination register ("G") and sel ("H") for CP0 ops,
|
||||
for pretty-printing in disassembly only.
|
||||
|
||||
Macro instructions:
|
||||
"A" General 32 bit expression
|
||||
"I" 32 bit immediate (value placed in imm_expr).
|
||||
"+I" 32 bit immediate (value placed in imm2_expr).
|
||||
"F" 64 bit floating point constant in .rdata
|
||||
"L" 64 bit floating point constant in .lit8
|
||||
"f" 32 bit floating point constant
|
||||
"l" 32 bit floating point constant in .lit4
|
||||
|
||||
MDMX instruction operands (note that while these use the FP register
|
||||
fields, they accept both $fN and $vN names for the registers):
|
||||
"O" MDMX alignment offset (OP_*_ALN)
|
||||
"Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
|
||||
"X" MDMX destination register (OP_*_FD)
|
||||
"Y" MDMX source register (OP_*_FS)
|
||||
"Z" MDMX source register (OP_*_FT)
|
||||
|
||||
Other:
|
||||
"()" parens surrounding optional value
|
||||
"," separates operands
|
||||
"[]" brackets around index for vector-op scalar operand specifier (vr5400)
|
||||
"+" Start of extension sequence.
|
||||
|
||||
Characters used so far, for quick reference when adding more:
|
||||
"%[]<>(),+"
|
||||
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
|
||||
"abcdefhijklopqrstuvwxz"
|
||||
|
||||
Extension character sequences used so far ("+" followed by the
|
||||
following), for quick reference when adding more:
|
||||
"ABCDEFGHI"
|
||||
*/
|
||||
|
||||
/* These are the bits which may be set in the pinfo field of an
|
||||
instructions, if it is not equal to INSN_MACRO. */
|
||||
|
||||
/* Modifies the general purpose register in OP_*_RD. */
|
||||
#define INSN_WRITE_GPR_D 0x00000001
|
||||
/* Modifies the general purpose register in OP_*_RT. */
|
||||
#define INSN_WRITE_GPR_T 0x00000002
|
||||
/* Modifies general purpose register 31. */
|
||||
#define INSN_WRITE_GPR_31 0x00000004
|
||||
/* Modifies the floating point register in OP_*_FD. */
|
||||
#define INSN_WRITE_FPR_D 0x00000008
|
||||
/* Modifies the floating point register in OP_*_FS. */
|
||||
#define INSN_WRITE_FPR_S 0x00000010
|
||||
/* Modifies the floating point register in OP_*_FT. */
|
||||
#define INSN_WRITE_FPR_T 0x00000020
|
||||
/* Reads the general purpose register in OP_*_RS. */
|
||||
#define INSN_READ_GPR_S 0x00000040
|
||||
/* Reads the general purpose register in OP_*_RT. */
|
||||
#define INSN_READ_GPR_T 0x00000080
|
||||
/* Reads the floating point register in OP_*_FS. */
|
||||
#define INSN_READ_FPR_S 0x00000100
|
||||
/* Reads the floating point register in OP_*_FT. */
|
||||
#define INSN_READ_FPR_T 0x00000200
|
||||
/* Reads the floating point register in OP_*_FR. */
|
||||
#define INSN_READ_FPR_R 0x00000400
|
||||
/* Modifies coprocessor condition code. */
|
||||
#define INSN_WRITE_COND_CODE 0x00000800
|
||||
/* Reads coprocessor condition code. */
|
||||
#define INSN_READ_COND_CODE 0x00001000
|
||||
/* TLB operation. */
|
||||
#define INSN_TLB 0x00002000
|
||||
/* Reads coprocessor register other than floating point register. */
|
||||
#define INSN_COP 0x00004000
|
||||
/* Instruction loads value from memory, requiring delay. */
|
||||
#define INSN_LOAD_MEMORY_DELAY 0x00008000
|
||||
/* Instruction loads value from coprocessor, requiring delay. */
|
||||
#define INSN_LOAD_COPROC_DELAY 0x00010000
|
||||
/* Instruction has unconditional branch delay slot. */
|
||||
#define INSN_UNCOND_BRANCH_DELAY 0x00020000
|
||||
/* Instruction has conditional branch delay slot. */
|
||||
#define INSN_COND_BRANCH_DELAY 0x00040000
|
||||
/* Conditional branch likely: if branch not taken, insn nullified. */
|
||||
#define INSN_COND_BRANCH_LIKELY 0x00080000
|
||||
/* Moves to coprocessor register, requiring delay. */
|
||||
#define INSN_COPROC_MOVE_DELAY 0x00100000
|
||||
/* Loads coprocessor register from memory, requiring delay. */
|
||||
#define INSN_COPROC_MEMORY_DELAY 0x00200000
|
||||
/* Reads the HI register. */
|
||||
#define INSN_READ_HI 0x00400000
|
||||
/* Reads the LO register. */
|
||||
#define INSN_READ_LO 0x00800000
|
||||
/* Modifies the HI register. */
|
||||
#define INSN_WRITE_HI 0x01000000
|
||||
/* Modifies the LO register. */
|
||||
#define INSN_WRITE_LO 0x02000000
|
||||
/* Takes a trap (easier to keep out of delay slot). */
|
||||
#define INSN_TRAP 0x04000000
|
||||
/* Instruction stores value into memory. */
|
||||
#define INSN_STORE_MEMORY 0x08000000
|
||||
/* Instruction uses single precision floating point. */
|
||||
#define FP_S 0x10000000
|
||||
/* Instruction uses double precision floating point. */
|
||||
#define FP_D 0x20000000
|
||||
/* Instruction is part of the tx39's integer multiply family. */
|
||||
#define INSN_MULT 0x40000000
|
||||
/* Instruction synchronize shared memory. */
|
||||
#define INSN_SYNC 0x80000000
|
||||
/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */
|
||||
#define INSN_READ_MDMX_ACC 0
|
||||
/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */
|
||||
#define INSN_WRITE_MDMX_ACC 0
|
||||
|
||||
/* Instruction is actually a macro. It should be ignored by the
|
||||
disassembler, and requires special treatment by the assembler. */
|
||||
#define INSN_MACRO 0xffffffff
|
||||
|
||||
/* Masks used to mark instructions to indicate which MIPS ISA level
|
||||
they were introduced in. ISAs, as defined below, are logical
|
||||
ORs of these bits, indicating that they support the instructions
|
||||
defined at the given level. */
|
||||
|
||||
#define INSN_ISA_MASK 0x00000fff
|
||||
#define INSN_ISA1 0x00000001
|
||||
#define INSN_ISA2 0x00000002
|
||||
#define INSN_ISA3 0x00000004
|
||||
#define INSN_ISA4 0x00000008
|
||||
#define INSN_ISA5 0x00000010
|
||||
#define INSN_ISA32 0x00000020
|
||||
#define INSN_ISA64 0x00000040
|
||||
#define INSN_ISA32R2 0x00000080
|
||||
#define INSN_ISA64R2 0x00000100
|
||||
|
||||
/* Masks used for MIPS-defined ASEs. */
|
||||
#define INSN_ASE_MASK 0x0000f000
|
||||
|
||||
/* MIPS 16 ASE */
|
||||
#define INSN_MIPS16 0x00002000
|
||||
/* MIPS-3D ASE */
|
||||
#define INSN_MIPS3D 0x00004000
|
||||
/* MDMX ASE */
|
||||
#define INSN_MDMX 0x00008000
|
||||
|
||||
/* Chip specific instructions. These are bitmasks. */
|
||||
|
||||
/* MIPS R4650 instruction. */
|
||||
#define INSN_4650 0x00010000
|
||||
/* LSI R4010 instruction. */
|
||||
#define INSN_4010 0x00020000
|
||||
/* NEC VR4100 instruction. */
|
||||
#define INSN_4100 0x00040000
|
||||
/* Toshiba R3900 instruction. */
|
||||
#define INSN_3900 0x00080000
|
||||
/* MIPS R10000 instruction. */
|
||||
#define INSN_10000 0x00100000
|
||||
/* Broadcom SB-1 instruction. */
|
||||
#define INSN_SB1 0x00200000
|
||||
/* NEC VR4111/VR4181 instruction. */
|
||||
#define INSN_4111 0x00400000
|
||||
/* NEC VR4120 instruction. */
|
||||
#define INSN_4120 0x00800000
|
||||
/* NEC VR5400 instruction. */
|
||||
#define INSN_5400 0x01000000
|
||||
/* NEC VR5500 instruction. */
|
||||
#define INSN_5500 0x02000000
|
||||
|
||||
/* MIPS ISA defines, use instead of hardcoding ISA level. */
|
||||
|
||||
#define ISA_UNKNOWN 0 /* Gas internal use. */
|
||||
#define ISA_MIPS1 (INSN_ISA1)
|
||||
#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
|
||||
#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
|
||||
#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
|
||||
#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
|
||||
|
||||
#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
|
||||
#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
|
||||
|
||||
#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
|
||||
#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
|
||||
|
||||
|
||||
/* CPU defines, use instead of hardcoding processor number. Keep this
|
||||
in sync with bfd/archures.c in order for machine selection to work. */
|
||||
#define CPU_UNKNOWN 0 /* Gas internal use. */
|
||||
#define CPU_R3000 3000
|
||||
#define CPU_R3900 3900
|
||||
#define CPU_R4000 4000
|
||||
#define CPU_R4010 4010
|
||||
#define CPU_VR4100 4100
|
||||
#define CPU_R4111 4111
|
||||
#define CPU_VR4120 4120
|
||||
#define CPU_R4300 4300
|
||||
#define CPU_R4400 4400
|
||||
#define CPU_R4600 4600
|
||||
#define CPU_R4650 4650
|
||||
#define CPU_R5000 5000
|
||||
#define CPU_VR5400 5400
|
||||
#define CPU_VR5500 5500
|
||||
#define CPU_R6000 6000
|
||||
#define CPU_RM7000 7000
|
||||
#define CPU_R8000 8000
|
||||
#define CPU_R10000 10000
|
||||
#define CPU_R12000 12000
|
||||
#define CPU_MIPS16 16
|
||||
#define CPU_MIPS32 32
|
||||
#define CPU_MIPS32R2 33
|
||||
#define CPU_MIPS5 5
|
||||
#define CPU_MIPS64 64
|
||||
#define CPU_MIPS64R2 65
|
||||
#define CPU_SB1 12310201 /* octal 'SB', 01. */
|
||||
|
||||
/* Test for membership in an ISA including chip specific ISAs. INSN
|
||||
is pointer to an element of the opcode table; ISA is the specified
|
||||
ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
|
||||
test, or zero if no CPU specific ISA test is desired. */
|
||||
|
||||
#define OPCODE_IS_MEMBER(insn, isa, cpu) \
|
||||
(((insn)->membership & isa) != 0 \
|
||||
|| (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
|
||||
|| (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
|
||||
|| (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
|
||||
|| (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
|
||||
|| (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
|
||||
|| ((cpu == CPU_R10000 || cpu == CPU_R12000) \
|
||||
&& ((insn)->membership & INSN_10000) != 0) \
|
||||
|| (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
|
||||
|| (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
|
||||
|| (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
|
||||
|| (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
|
||||
|| (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
|
||||
|| 0) /* Please keep this term for easier source merging. */
|
||||
|
||||
/* This is a list of macro expanded instructions.
|
||||
|
||||
_I appended means immediate
|
||||
_A appended means address
|
||||
_AB appended means address with base register
|
||||
_D appended means 64 bit floating point constant
|
||||
_S appended means 32 bit floating point constant. */
|
||||
|
||||
enum
|
||||
{
|
||||
M_ABS,
|
||||
M_ADD_I,
|
||||
M_ADDU_I,
|
||||
M_AND_I,
|
||||
M_BEQ,
|
||||
M_BEQ_I,
|
||||
M_BEQL_I,
|
||||
M_BGE,
|
||||
M_BGEL,
|
||||
M_BGE_I,
|
||||
M_BGEL_I,
|
||||
M_BGEU,
|
||||
M_BGEUL,
|
||||
M_BGEU_I,
|
||||
M_BGEUL_I,
|
||||
M_BGT,
|
||||
M_BGTL,
|
||||
M_BGT_I,
|
||||
M_BGTL_I,
|
||||
M_BGTU,
|
||||
M_BGTUL,
|
||||
M_BGTU_I,
|
||||
M_BGTUL_I,
|
||||
M_BLE,
|
||||
M_BLEL,
|
||||
M_BLE_I,
|
||||
M_BLEL_I,
|
||||
M_BLEU,
|
||||
M_BLEUL,
|
||||
M_BLEU_I,
|
||||
M_BLEUL_I,
|
||||
M_BLT,
|
||||
M_BLTL,
|
||||
M_BLT_I,
|
||||
M_BLTL_I,
|
||||
M_BLTU,
|
||||
M_BLTUL,
|
||||
M_BLTU_I,
|
||||
M_BLTUL_I,
|
||||
M_BNE,
|
||||
M_BNE_I,
|
||||
M_BNEL_I,
|
||||
M_DABS,
|
||||
M_DADD_I,
|
||||
M_DADDU_I,
|
||||
M_DDIV_3,
|
||||
M_DDIV_3I,
|
||||
M_DDIVU_3,
|
||||
M_DDIVU_3I,
|
||||
M_DEXT,
|
||||
M_DINS,
|
||||
M_DIV_3,
|
||||
M_DIV_3I,
|
||||
M_DIVU_3,
|
||||
M_DIVU_3I,
|
||||
M_DLA_AB,
|
||||
M_DLCA_AB,
|
||||
M_DLI,
|
||||
M_DMUL,
|
||||
M_DMUL_I,
|
||||
M_DMULO,
|
||||
M_DMULO_I,
|
||||
M_DMULOU,
|
||||
M_DMULOU_I,
|
||||
M_DREM_3,
|
||||
M_DREM_3I,
|
||||
M_DREMU_3,
|
||||
M_DREMU_3I,
|
||||
M_DSUB_I,
|
||||
M_DSUBU_I,
|
||||
M_DSUBU_I_2,
|
||||
M_J_A,
|
||||
M_JAL_1,
|
||||
M_JAL_2,
|
||||
M_JAL_A,
|
||||
M_L_DOB,
|
||||
M_L_DAB,
|
||||
M_LA_AB,
|
||||
M_LB_A,
|
||||
M_LB_AB,
|
||||
M_LBU_A,
|
||||
M_LBU_AB,
|
||||
M_LCA_AB,
|
||||
M_LD_A,
|
||||
M_LD_OB,
|
||||
M_LD_AB,
|
||||
M_LDC1_AB,
|
||||
M_LDC2_AB,
|
||||
M_LDC3_AB,
|
||||
M_LDL_AB,
|
||||
M_LDR_AB,
|
||||
M_LH_A,
|
||||
M_LH_AB,
|
||||
M_LHU_A,
|
||||
M_LHU_AB,
|
||||
M_LI,
|
||||
M_LI_D,
|
||||
M_LI_DD,
|
||||
M_LI_S,
|
||||
M_LI_SS,
|
||||
M_LL_AB,
|
||||
M_LLD_AB,
|
||||
M_LS_A,
|
||||
M_LW_A,
|
||||
M_LW_AB,
|
||||
M_LWC0_A,
|
||||
M_LWC0_AB,
|
||||
M_LWC1_A,
|
||||
M_LWC1_AB,
|
||||
M_LWC2_A,
|
||||
M_LWC2_AB,
|
||||
M_LWC3_A,
|
||||
M_LWC3_AB,
|
||||
M_LWL_A,
|
||||
M_LWL_AB,
|
||||
M_LWR_A,
|
||||
M_LWR_AB,
|
||||
M_LWU_AB,
|
||||
M_MOVE,
|
||||
M_MUL,
|
||||
M_MUL_I,
|
||||
M_MULO,
|
||||
M_MULO_I,
|
||||
M_MULOU,
|
||||
M_MULOU_I,
|
||||
M_NOR_I,
|
||||
M_OR_I,
|
||||
M_REM_3,
|
||||
M_REM_3I,
|
||||
M_REMU_3,
|
||||
M_REMU_3I,
|
||||
M_DROL,
|
||||
M_ROL,
|
||||
M_DROL_I,
|
||||
M_ROL_I,
|
||||
M_DROR,
|
||||
M_ROR,
|
||||
M_DROR_I,
|
||||
M_ROR_I,
|
||||
M_S_DA,
|
||||
M_S_DOB,
|
||||
M_S_DAB,
|
||||
M_S_S,
|
||||
M_SC_AB,
|
||||
M_SCD_AB,
|
||||
M_SD_A,
|
||||
M_SD_OB,
|
||||
M_SD_AB,
|
||||
M_SDC1_AB,
|
||||
M_SDC2_AB,
|
||||
M_SDC3_AB,
|
||||
M_SDL_AB,
|
||||
M_SDR_AB,
|
||||
M_SEQ,
|
||||
M_SEQ_I,
|
||||
M_SGE,
|
||||
M_SGE_I,
|
||||
M_SGEU,
|
||||
M_SGEU_I,
|
||||
M_SGT,
|
||||
M_SGT_I,
|
||||
M_SGTU,
|
||||
M_SGTU_I,
|
||||
M_SLE,
|
||||
M_SLE_I,
|
||||
M_SLEU,
|
||||
M_SLEU_I,
|
||||
M_SLT_I,
|
||||
M_SLTU_I,
|
||||
M_SNE,
|
||||
M_SNE_I,
|
||||
M_SB_A,
|
||||
M_SB_AB,
|
||||
M_SH_A,
|
||||
M_SH_AB,
|
||||
M_SW_A,
|
||||
M_SW_AB,
|
||||
M_SWC0_A,
|
||||
M_SWC0_AB,
|
||||
M_SWC1_A,
|
||||
M_SWC1_AB,
|
||||
M_SWC2_A,
|
||||
M_SWC2_AB,
|
||||
M_SWC3_A,
|
||||
M_SWC3_AB,
|
||||
M_SWL_A,
|
||||
M_SWL_AB,
|
||||
M_SWR_A,
|
||||
M_SWR_AB,
|
||||
M_SUB_I,
|
||||
M_SUBU_I,
|
||||
M_SUBU_I_2,
|
||||
M_TEQ_I,
|
||||
M_TGE_I,
|
||||
M_TGEU_I,
|
||||
M_TLT_I,
|
||||
M_TLTU_I,
|
||||
M_TNE_I,
|
||||
M_TRUNCWD,
|
||||
M_TRUNCWS,
|
||||
M_ULD,
|
||||
M_ULD_A,
|
||||
M_ULH,
|
||||
M_ULH_A,
|
||||
M_ULHU,
|
||||
M_ULHU_A,
|
||||
M_ULW,
|
||||
M_ULW_A,
|
||||
M_USH,
|
||||
M_USH_A,
|
||||
M_USW,
|
||||
M_USW_A,
|
||||
M_USD,
|
||||
M_USD_A,
|
||||
M_XOR_I,
|
||||
M_COP0,
|
||||
M_COP1,
|
||||
M_COP2,
|
||||
M_COP3,
|
||||
M_NUM_MACROS
|
||||
};
|
||||
|
||||
|
||||
/* The order of overloaded instructions matters. Label arguments and
|
||||
register arguments look the same. Instructions that can have either
|
||||
for arguments must apear in the correct order in this table for the
|
||||
assembler to pick the right one. In other words, entries with
|
||||
immediate operands must apear after the same instruction with
|
||||
registers.
|
||||
|
||||
Many instructions are short hand for other instructions (i.e., The
|
||||
jal <register> instruction is short for jalr <register>). */
|
||||
|
||||
extern const struct mips_opcode mips_builtin_opcodes[];
|
||||
extern const int bfd_mips_num_builtin_opcodes;
|
||||
extern struct mips_opcode *mips_opcodes;
|
||||
extern int bfd_mips_num_opcodes;
|
||||
#define NUMOPCODES bfd_mips_num_opcodes
|
||||
|
||||
|
||||
/* The rest of this file adds definitions for the mips16 TinyRISC
|
||||
processor. */
|
||||
|
||||
/* These are the bitmasks and shift counts used for the different
|
||||
fields in the instruction formats. Other than OP, no masks are
|
||||
provided for the fixed portions of an instruction, since they are
|
||||
not needed.
|
||||
|
||||
The I format uses IMM11.
|
||||
|
||||
The RI format uses RX and IMM8.
|
||||
|
||||
The RR format uses RX, and RY.
|
||||
|
||||
The RRI format uses RX, RY, and IMM5.
|
||||
|
||||
The RRR format uses RX, RY, and RZ.
|
||||
|
||||
The RRI_A format uses RX, RY, and IMM4.
|
||||
|
||||
The SHIFT format uses RX, RY, and SHAMT.
|
||||
|
||||
The I8 format uses IMM8.
|
||||
|
||||
The I8_MOVR32 format uses RY and REGR32.
|
||||
|
||||
The IR_MOV32R format uses REG32R and MOV32Z.
|
||||
|
||||
The I64 format uses IMM8.
|
||||
|
||||
The RI64 format uses RY and IMM5.
|
||||
*/
|
||||
|
||||
#define MIPS16OP_MASK_OP 0x1f
|
||||
#define MIPS16OP_SH_OP 11
|
||||
#define MIPS16OP_MASK_IMM11 0x7ff
|
||||
#define MIPS16OP_SH_IMM11 0
|
||||
#define MIPS16OP_MASK_RX 0x7
|
||||
#define MIPS16OP_SH_RX 8
|
||||
#define MIPS16OP_MASK_IMM8 0xff
|
||||
#define MIPS16OP_SH_IMM8 0
|
||||
#define MIPS16OP_MASK_RY 0x7
|
||||
#define MIPS16OP_SH_RY 5
|
||||
#define MIPS16OP_MASK_IMM5 0x1f
|
||||
#define MIPS16OP_SH_IMM5 0
|
||||
#define MIPS16OP_MASK_RZ 0x7
|
||||
#define MIPS16OP_SH_RZ 2
|
||||
#define MIPS16OP_MASK_IMM4 0xf
|
||||
#define MIPS16OP_SH_IMM4 0
|
||||
#define MIPS16OP_MASK_REGR32 0x1f
|
||||
#define MIPS16OP_SH_REGR32 0
|
||||
#define MIPS16OP_MASK_REG32R 0x1f
|
||||
#define MIPS16OP_SH_REG32R 3
|
||||
#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
|
||||
#define MIPS16OP_MASK_MOVE32Z 0x7
|
||||
#define MIPS16OP_SH_MOVE32Z 0
|
||||
#define MIPS16OP_MASK_IMM6 0x3f
|
||||
#define MIPS16OP_SH_IMM6 5
|
||||
|
||||
/* These are the characters which may appears in the args field of an
|
||||
instruction. They appear in the order in which the fields appear
|
||||
when the instruction is used. Commas and parentheses in the args
|
||||
string are ignored when assembling, and written into the output
|
||||
when disassembling.
|
||||
|
||||
"y" 3 bit register (MIPS16OP_*_RY)
|
||||
"x" 3 bit register (MIPS16OP_*_RX)
|
||||
"z" 3 bit register (MIPS16OP_*_RZ)
|
||||
"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
|
||||
"v" 3 bit same register as source and destination (MIPS16OP_*_RX)
|
||||
"w" 3 bit same register as source and destination (MIPS16OP_*_RY)
|
||||
"0" zero register ($0)
|
||||
"S" stack pointer ($sp or $29)
|
||||
"P" program counter
|
||||
"R" return address register ($ra or $31)
|
||||
"X" 5 bit MIPS register (MIPS16OP_*_REGR32)
|
||||
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
|
||||
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
|
||||
"a" 26 bit jump address
|
||||
"e" 11 bit extension value
|
||||
"l" register list for entry instruction
|
||||
"L" register list for exit instruction
|
||||
|
||||
The remaining codes may be extended. Except as otherwise noted,
|
||||
the full extended operand is a 16 bit signed value.
|
||||
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
|
||||
">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
|
||||
"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
|
||||
"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
|
||||
"4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
|
||||
"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
|
||||
"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
|
||||
"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
|
||||
"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
|
||||
"j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
|
||||
"8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
|
||||
"V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
|
||||
"C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
|
||||
"U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
|
||||
"k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
|
||||
"K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
|
||||
"p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
|
||||
"q" 11 bit branch address (MIPS16OP_*_IMM11)
|
||||
"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
|
||||
"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
|
||||
"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
|
||||
*/
|
||||
|
||||
/* For the mips16, we use the same opcode table format and a few of
|
||||
the same flags. However, most of the flags are different. */
|
||||
|
||||
/* Modifies the register in MIPS16OP_*_RX. */
|
||||
#define MIPS16_INSN_WRITE_X 0x00000001
|
||||
/* Modifies the register in MIPS16OP_*_RY. */
|
||||
#define MIPS16_INSN_WRITE_Y 0x00000002
|
||||
/* Modifies the register in MIPS16OP_*_RZ. */
|
||||
#define MIPS16_INSN_WRITE_Z 0x00000004
|
||||
/* Modifies the T ($24) register. */
|
||||
#define MIPS16_INSN_WRITE_T 0x00000008
|
||||
/* Modifies the SP ($29) register. */
|
||||
#define MIPS16_INSN_WRITE_SP 0x00000010
|
||||
/* Modifies the RA ($31) register. */
|
||||
#define MIPS16_INSN_WRITE_31 0x00000020
|
||||
/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
|
||||
#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
|
||||
/* Reads the register in MIPS16OP_*_RX. */
|
||||
#define MIPS16_INSN_READ_X 0x00000080
|
||||
/* Reads the register in MIPS16OP_*_RY. */
|
||||
#define MIPS16_INSN_READ_Y 0x00000100
|
||||
/* Reads the register in MIPS16OP_*_MOVE32Z. */
|
||||
#define MIPS16_INSN_READ_Z 0x00000200
|
||||
/* Reads the T ($24) register. */
|
||||
#define MIPS16_INSN_READ_T 0x00000400
|
||||
/* Reads the SP ($29) register. */
|
||||
#define MIPS16_INSN_READ_SP 0x00000800
|
||||
/* Reads the RA ($31) register. */
|
||||
#define MIPS16_INSN_READ_31 0x00001000
|
||||
/* Reads the program counter. */
|
||||
#define MIPS16_INSN_READ_PC 0x00002000
|
||||
/* Reads the general purpose register in MIPS16OP_*_REGR32. */
|
||||
#define MIPS16_INSN_READ_GPR_X 0x00004000
|
||||
/* Is a branch insn. */
|
||||
#define MIPS16_INSN_BRANCH 0x00010000
|
||||
|
||||
/* The following flags have the same value for the mips16 opcode
|
||||
table:
|
||||
INSN_UNCOND_BRANCH_DELAY
|
||||
INSN_COND_BRANCH_DELAY
|
||||
INSN_COND_BRANCH_LIKELY (never used)
|
||||
INSN_READ_HI
|
||||
INSN_READ_LO
|
||||
INSN_WRITE_HI
|
||||
INSN_WRITE_LO
|
||||
INSN_TRAP
|
||||
INSN_ISA3
|
||||
*/
|
||||
|
||||
extern const struct mips_opcode mips16_opcodes[];
|
||||
extern const int bfd_mips16_num_opcodes;
|
||||
|
||||
#endif /* _MIPS_H_ */
|
||||
Loading…
Reference in New Issue
Block a user