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- Fix a typo in a comment.

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- Use macros for MSR register indexes as well as the bitfields in the
  APICBASE MSR.
This commit is contained in:
jhb 2003-08-15 15:25:19 +00:00
parent df8434f4cc
commit b8d8a4046d
2 changed files with 14 additions and 14 deletions
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12
sys/i386/i386/initcpu.c
View File

@ -479,11 +479,11 @@ init_ppro(void)
u_int64_t apicbase;
/*
* Local APIC should be diabled in UP kernel.
* Local APIC should be disabled in UP kernel.
*/
apicbase = rdmsr(0x1b);
apicbase &= ~0x800LL;
wrmsr(0x1b, apicbase);
apicbase = rdmsr(MSR_APICBASE);
apicbase &= ~APICBASE_ENABLED;
wrmsr(MSR_APICBASE, apicbase);
#endif
}
@ -504,7 +504,7 @@ init_mendocino(void)
load_cr0(rcr0() | CR0_CD | CR0_NW);
wbinvd();
bbl_cr_ctl3 = rdmsr(0x11e);
bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3);
/* If the L2 cache is configured, do nothing. */
if (!(bbl_cr_ctl3 & 1)) {
@ -519,7 +519,7 @@ init_mendocino(void)
#else
bbl_cr_ctl3 |= 5 << 1;
#endif
wrmsr(0x11e, bbl_cr_ctl3);
wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3);
}
load_cr0(rcr0() & ~(CR0_CD | CR0_NW));

16
sys/i386/i386/perfmon.c
View File

@ -90,18 +90,18 @@ perfmon_init(void)
switch(cpu_class) {
case CPUCLASS_586:
perfmon_cpuok = 1;
msr_ctl[0] = 0x11;
msr_ctl[1] = 0x11;
msr_pmc[0] = 0x12;
msr_pmc[1] = 0x13;
msr_ctl[0] = MSR_P5_CESR;
msr_ctl[1] = MSR_P5_CESR;
msr_pmc[0] = MSR_P5_CTR0;
msr_pmc[1] = MSR_P5_CTR1;
writectl = writectl5;
break;
case CPUCLASS_686:
perfmon_cpuok = 1;
msr_ctl[0] = 0x186;
msr_ctl[1] = 0x187;
msr_pmc[0] = 0xc1;
msr_pmc[1] = 0xc2;
msr_ctl[0] = MSR_EVNTSEL0;
msr_ctl[1] = MSR_EVNTSEL1;
msr_pmc[0] = MSR_PERFCTR0;
msr_pmc[1] = MSR_PERFCTR1;
writectl = writectl6;
break;