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iwm: Add 9000-series RX register definitions.

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MFC after:	2 weeks
Sponsored by:	The FreeBSD Foundation
This commit is contained in:
markj 2019-11-07 23:34:41 +00:00
parent 12b86893ab
commit b97e1fe836
1 changed files with 46 additions and 0 deletions
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46
sys/dev/iwm/if_iwmreg.h
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@ -1527,6 +1527,52 @@ static inline unsigned int IWM_FH_MEM_CBBC_QUEUE(unsigned int chnl)
#define IWM_FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
/* 9000 rx series registers */
#define IWM_RFH_Q0_FRBDCB_BA_LSB 0xa08000
#define IWM_RFH_Q_FRBDCB_BA_LSB (IWM_RFH_Q0_FRBDCB_BA_LSB + (q) * 8)
/* Write index table */
#define IWM_RFH_Q0_FRBDCB_WIDX 0xa08080
#define IWM_RFH_Q_FRBDCB_WIDX (IWM_RFH_Q0_FRBDCB_WIDX + (q) * 4)
/* Write index table - shadow registers */
#define IWM_RFH_Q0_FRBDCB_WIDX_TRG 0x1c80
#define IWM_RFH_Q_FRBDCB_WIDX_TRG (IWM_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)
/* Read index table */
#define IWM_RFH_Q0_FRBDCB_RIDX 0xa080c0
#define IWM_RFH_Q_FRBDCB_RIDX (IWM_RFH_Q0_FRBDCB_RIDX + (q) * 4)
/* Used list table */
#define IWM_RFH_Q0_URBDCB_BA_LSB 0xa08100
#define IWM_RFH_Q_URBDCB_BA_LSB (IWM_RFH_Q0_URBDCB_BA_LSB + (q) * 8)
/* Write index table */
#define IWM_RFH_Q0_URBDCB_WIDX 0xa08180
#define IWM_RFH_Q_URBDCB_WIDX (IWM_RFH_Q0_URBDCB_WIDX + (q) * 4)
/* stts */
#define IWM_RFH_Q0_URBD_STTS_WPTR_LSB 0xa08200
#define IWM_RFH_Q_URBD_STTS_WPTR_LSB (IWM_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)
#define IWM_RFH_GEN_STATUS 0xa09808
#define IWM_RXF_DMA_IDLE 0x80000000
/* DMA configuration */
#define IWM_RFH_RXF_DMA_CFG 0xa09820
#define IWM_RFH_RXF_DMA_RB_SIZE_1K 0x00010000
#define IWM_RFH_RXF_DMA_RB_SIZE_2K 0x00020000
#define IWM_RFH_RXF_DMA_RB_SIZE_4K 0x00040000
#define IWM_RFH_RXF_DMA_RBDCB_SIZE_512 0x00900000
#define IWM_RFH_RXF_DMA_MIN_RB_4_8 0x03000000
#define IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK 0x04000000
#define IWM_RFH_DMA_EN_ENABLE_VAL 0x80000000
#define IWM_RFH_GEN_CFG 0xa09800
#define IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP 0x00000001
#define IWM_RFH_GEN_CFG_RFH_DMA_SNOOP 0x00000002
#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010
#define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000
#define IWM_RFH_RXF_RXQ_ACTIVE 0xa0980c
/* end of 9000 rx series registers */
/* TFDB Area - TFDs buffer table */
#define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
#define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)