From ba3af76df78a3e83492a592e50d4ab3246388d9c Mon Sep 17 00:00:00 2001 From: Bill Paul Date: Tue, 25 Oct 2005 04:53:29 +0000 Subject: [PATCH] Modify the pci_cfgdisable() routine to bring it more in line with other OSes (Solaris, Linux, VxWorks). It's not necessary to write a 0 to the config address register when using config mechanism 1 to turn off config access. In fact, it can be downright troublesome, since it seems to confuse the PCI-PCI bridge in the AMD8111 chipset and cause it to sporadically botch reads from some devices. This is the cause of the missing USP ports problem I was experiencing with my Sun Opteron system. Also correct the case for mechanism 2: it's only necessary to write a 0 to the ENABLE port. --- sys/amd64/pci/pci_cfgreg.c | 8 ++++++-- sys/i386/pci/pci_cfgreg.c | 10 +++++++--- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/sys/amd64/pci/pci_cfgreg.c b/sys/amd64/pci/pci_cfgreg.c index e4a5a2a80df1..35f25258741e 100644 --- a/sys/amd64/pci/pci_cfgreg.c +++ b/sys/amd64/pci/pci_cfgreg.c @@ -139,11 +139,15 @@ pci_cfgdisable(void) { switch (cfgmech) { case 1: - outl(CONF1_ADDR_PORT, 0); + /* + * Do nothing for the config mechanism 1 case. + * Writing a 0 to the address port can apparently + * confuse some bridges and cause spurious + * access failures. + */ break; case 2: outb(CONF2_ENABLE_PORT, 0); - outb(CONF2_FORWARD_PORT, 0); break; } } diff --git a/sys/i386/pci/pci_cfgreg.c b/sys/i386/pci/pci_cfgreg.c index adea6dc8037d..37003a741808 100644 --- a/sys/i386/pci/pci_cfgreg.c +++ b/sys/i386/pci/pci_cfgreg.c @@ -237,11 +237,15 @@ pci_cfgdisable(void) { switch (cfgmech) { case CFGMECH_1: - outl(CONF1_ADDR_PORT, 0); - break; + /* + * Do nothing for the config mechanism 1 case. + * Writing a 0 to the address port can apparently + * confuse some bridges and cause spurious + * access failures. + */ + break; case CFGMECH_2: outb(CONF2_ENABLE_PORT, 0); - outb(CONF2_FORWARD_PORT, 0); break; } }