MFi386: use the lapic timer for UP systems that are using the apic so that
IRQ0 and mixed mode isn't a problem anymore. This removes mixed mode support because nothing is left that uses it.
This commit is contained in:
Peter Wemm
parent
0501844603
commit
ba5f6b61da
@ -367,8 +367,6 @@ madt_setup_io(void)
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}
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/* First, we run through adding I/O APIC's. */
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if (madt->PCATCompat && !(acpi_quirks & ACPI_Q_MADT_IRQ0))
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ioapic_enable_mixed_mode();
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madt_walk_table(madt_parse_apics, NULL);
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/* Second, we run through the table tweaking interrupt sources. */
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@ -32,7 +32,6 @@ __FBSDID("$FreeBSD$");
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#include "opt_atpic.h"
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#include "opt_isa.h"
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#include "opt_no_mixed_mode.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -62,7 +61,6 @@ __FBSDID("$FreeBSD$");
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#define VECTOR_DISABLED 255
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#define DEST_NONE -1
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#define DEST_EXTINT -2
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#define TODO printf("%s: not implemented!\n", __func__)
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@ -83,15 +81,6 @@ static MALLOC_DEFINE(M_IOAPIC, "I/O APIC", "I/O APIC structures");
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* IO APIC has a contiguous chunk of the System Interrupt address space.
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*/
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/*
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* Direct the ExtINT pin on the first I/O APIC to a logical cluster of
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* CPUs rather than a physical destination of just the BSP.
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*
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* Note: This is disabled by default as test systems seem to croak with it
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* enabled.
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#define ENABLE_EXTINT_LOGICAL_DESTINATION
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*/
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struct ioapic_intsrc {
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struct intsrc io_intsrc;
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u_int io_intpin:8;
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@ -130,7 +119,6 @@ static void ioapic_suspend(struct intsrc *isrc);
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static void ioapic_resume(struct intsrc *isrc);
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static void ioapic_program_destination(struct ioapic_intsrc *intpin);
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static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
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static void ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin);
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static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
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struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
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@ -140,13 +128,7 @@ struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
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ioapic_config_intr };
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static int bsp_id, current_cluster, logical_clusters, next_ioapic_base;
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static u_int mixed_mode_enabled, next_id, program_logical_dest;
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#if defined(NO_MIXED_MODE) || !defined(DEV_ATPIC)
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static int mixed_mode_active = 0;
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#else
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static int mixed_mode_active = 1;
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#endif
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TUNABLE_INT("hw.apic.mixed_mode", &mixed_mode_active);
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static u_int next_id, program_logical_dest;
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static __inline void
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_ioapic_eoi_source(struct intsrc *isrc)
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@ -270,12 +252,8 @@ ioapic_program_intpin(struct ioapic_intsrc *intpin)
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struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
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uint32_t low, high, value;
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/*
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* For pins routed via mixed mode or disabled, just ensure that
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* they are masked.
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*/
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if (intpin->io_dest == DEST_EXTINT ||
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intpin->io_vector == VECTOR_DISABLED) {
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/* For disabled pins, just ensure that they are masked. */
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if (intpin->io_vector == VECTOR_DISABLED) {
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low = ioapic_read(io->io_addr,
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IOAPIC_REDTBL_LO(intpin->io_intpin));
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if ((low & IOART_INTMASK) == IOART_INTMCLR)
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@ -346,8 +324,6 @@ ioapic_program_destination(struct ioapic_intsrc *intpin)
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KASSERT(intpin->io_dest != DEST_NONE,
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("intpin not assigned to a cluster"));
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KASSERT(intpin->io_dest != DEST_EXTINT,
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("intpin routed via ExtINT"));
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if (bootverbose) {
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printf("ioapic%u: routing intpin %u (", io->io_id,
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intpin->io_intpin);
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@ -383,8 +359,6 @@ ioapic_enable_intr(struct intsrc *isrc)
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{
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struct ioapic_intsrc *intpin = (struct ioapic_intsrc *)isrc;
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KASSERT(intpin->io_dest != DEST_EXTINT,
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("ExtINT pin trying to use ioapic enable_intr method"));
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if (intpin->io_dest == DEST_NONE) {
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ioapic_assign_cluster(intpin);
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lapic_enable_intr(intpin->io_vector);
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@ -464,17 +438,6 @@ ioapic_resume(struct intsrc *isrc)
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ioapic_program_intpin((struct ioapic_intsrc *)isrc);
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}
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/*
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* APIC enumerators call this function to indicate that the 8259A AT PICs
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* are available and that mixed mode can be used.
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*/
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void
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ioapic_enable_mixed_mode(void)
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{
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mixed_mode_enabled = 1;
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}
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/*
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* Allocate and return a logical cluster ID. Note that the first time
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* this is called, it returns cluster 0. ioapic_enable_intr() treats
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@ -503,11 +466,20 @@ ioapic_create(uintptr_t addr, int32_t apic_id, int intbase)
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u_int numintr, i;
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uint32_t value;
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/* Map the register window so we can access the device. */
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apic = (ioapic_t *)pmap_mapdev(addr, IOAPIC_MEM_REGION);
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mtx_lock_spin(&icu_lock);
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numintr = ((ioapic_read(apic, IOAPIC_VER) & IOART_VER_MAXREDIR) >>
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MAXREDIRSHIFT) + 1;
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value = ioapic_read(apic, IOAPIC_VER);
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mtx_unlock_spin(&icu_lock);
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/* If it's version register doesn't seem to work, punt. */
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if (value == 0xffffff) {
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pmap_unmapdev((vm_offset_t)apic, IOAPIC_MEM_REGION);
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return (NULL);
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}
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/* Determine the number of vectors and set the APIC ID. */
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numintr = ((value & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1;
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io = malloc(sizeof(struct ioapic) +
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numintr * sizeof(struct ioapic_intsrc), M_IOAPIC, M_WAITOK);
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io->io_pic = ioapic_template;
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@ -547,12 +519,11 @@ ioapic_create(uintptr_t addr, int32_t apic_id, int intbase)
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intpin->io_vector = intbase + i;
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/*
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* Assume that pin 0 on the first I/O APIC is an ExtINT pin
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* if mixed mode is enabled and an ISA interrupt if not.
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* Assume that pin 0 on the first I/O APIC is an ExtINT pin.
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* Assume that pins 1-15 are ISA interrupts and that all
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* other pins are PCI interrupts.
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*/
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if (intpin->io_vector == 0 && mixed_mode_enabled)
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if (intpin->io_vector == 0)
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ioapic_set_extint(io, i);
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else if (intpin->io_vector < IOAPIC_ISA_INTS) {
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intpin->io_bus = APIC_BUS_ISA;
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@ -710,12 +681,7 @@ ioapic_set_extint(void *cookie, u_int pin)
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return (EINVAL);
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io->io_pins[pin].io_bus = APIC_BUS_UNKNOWN;
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io->io_pins[pin].io_vector = VECTOR_EXTINT;
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/* Enable this pin if mixed mode is available and active. */
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if (mixed_mode_enabled && mixed_mode_active)
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io->io_pins[pin].io_masked = 0;
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else
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io->io_pins[pin].io_masked = 1;
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io->io_pins[pin].io_masked = 1;
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io->io_pins[pin].io_edgetrigger = 1;
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io->io_pins[pin].io_activehi = 1;
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if (bootverbose)
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@ -790,15 +756,7 @@ ioapic_register(void *cookie)
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ioapic_program_intpin(pin);
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if (pin->io_vector >= NUM_IO_INTS)
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continue;
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/*
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* Route IRQ0 via the 8259A using mixed mode if mixed mode
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* is available and turned on.
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*/
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if (pin->io_vector == 0 && mixed_mode_active &&
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mixed_mode_enabled)
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ioapic_setup_mixed_mode(pin);
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else
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intr_register_source(&pin->io_intsrc);
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intr_register_source(&pin->io_intsrc);
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}
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}
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@ -815,38 +773,8 @@ ioapic_set_logical_destinations(void *arg __unused)
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program_logical_dest = 1;
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STAILQ_FOREACH(io, &ioapic_list, io_next)
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for (i = 0; i < io->io_numintr; i++)
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if (io->io_pins[i].io_dest != DEST_NONE &&
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io->io_pins[i].io_dest != DEST_EXTINT)
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if (io->io_pins[i].io_dest != DEST_NONE)
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ioapic_program_destination(&io->io_pins[i]);
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}
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SYSINIT(ioapic_destinations, SI_SUB_SMP, SI_ORDER_SECOND,
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ioapic_set_logical_destinations, NULL)
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/*
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* Support for mixed-mode interrupt sources. These sources route an ISA
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* IRQ through the 8259A's via the ExtINT on pin 0 of the I/O APIC that
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* routes the ISA interrupts. We just ignore the intpins that use this
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* mode and allow the atpic driver to register its interrupt source for
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* that IRQ instead.
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*/
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static void
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ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin)
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{
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struct ioapic_intsrc *extint;
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struct ioapic *io;
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/*
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* Mark the associated I/O APIC intpin as being delivered via
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* ExtINT and enable the ExtINT pin on the I/O APIC if needed.
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*/
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intpin->io_dest = DEST_EXTINT;
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io = (struct ioapic *)intpin->io_intsrc.is_pic;
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extint = &io->io_pins[0];
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if (extint->io_vector != VECTOR_EXTINT)
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panic("Can't find ExtINT pin to route through!");
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#ifdef ENABLE_EXTINT_LOGICAL_DESTINATION
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if (extint->io_dest == DEST_NONE)
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ioapic_assign_cluster(extint);
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#endif
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}
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@ -348,7 +348,6 @@ mptable_setup_io(void)
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busses[i].bus_type = NOBUS;
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/* Second, we run through adding I/O APIC's and busses. */
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ioapic_enable_mixed_mode();
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mptable_parse_apics_and_busses();
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/* Third, we run through the table tweaking interrupt sources. */
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@ -177,7 +177,6 @@ u_int apic_idt_to_irq(u_int vector);
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void apic_register_enumerator(struct apic_enumerator *enumerator);
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void *ioapic_create(uintptr_t addr, int32_t id, int intbase);
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int ioapic_disable_pin(void *cookie, u_int pin);
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void ioapic_enable_mixed_mode(void);
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int ioapic_get_vector(void *cookie, u_int pin);
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int ioapic_next_logical_cluster(void);
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void ioapic_register(void *cookie);
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