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Fix abuses of cpu_critical_{enter,exit} by converting to

Browse Source 
intr_{disable,restore} as well as providing an implemenation of
intr_{disable,restore}.

Reviewed by: jake, rwatson, jhb
This commit is contained in:
Warner Losh 2002-03-21 06:19:08 +00:00
parent b70c0e8b00
commit ba74981e71
12 changed files with 95 additions and 65 deletions
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24
sys/amd64/amd64/fpu.c
View File

@ -512,7 +512,7 @@ npxinit(control)
u_short control;
{
static union savefpu dummy;
critical_t savecrit;
register_t savecrit;
if (!npx_exists)
return;
@ -521,7 +521,7 @@ npxinit(control)
* fnsave to throw away any junk in the fpu. npxsave() initializes
* the fpu and sets fpcurthread = NULL as important side effects.
*/
savecrit = cpu_critical_enter();
savecrit = intr_disable();
npxsave(&dummy);
stop_emulating();
#ifdef CPU_ENABLE_SSE
@ -533,7 +533,7 @@ npxinit(control)
if (PCPU_GET(curpcb) != NULL)
fpusave(&PCPU_GET(curpcb)->pcb_save);
start_emulating();
cpu_critical_exit(savecrit);
intr_restore(savecrit);
}
/*
@ -543,12 +543,12 @@ void
npxexit(td)
struct thread *td;
{
critical_t savecrit;
register_t savecrit;
savecrit = cpu_critical_enter();
savecrit = intr_disable();
if (td == PCPU_GET(fpcurthread))
npxsave(&PCPU_GET(curpcb)->pcb_save);
cpu_critical_exit(savecrit);
intr_restore(savecrit);
#ifdef NPX_DEBUG
if (npx_exists) {
u_int masked_exceptions;
@ -759,7 +759,7 @@ static char fpetable[128] = {
int
npxtrap()
{
critical_t savecrit;
register_t savecrit;
u_short control, status;
u_long *exstat;
@ -768,7 +768,7 @@ npxtrap()
PCPU_GET(fpcurthread), curthread, npx_exists);
panic("npxtrap from nowhere");
}
savecrit = cpu_critical_enter();
savecrit = intr_disable();
/*
* Interrupt handling (for another interrupt) may have pushed the
@ -789,7 +789,7 @@ npxtrap()
GET_FPU_SW(curthread) &= ~0x80bf;
else
fnclex();
cpu_critical_exit(savecrit);
intr_restore(savecrit);
return (fpetable[status & ((~control & 0x3f) | 0x40)]);
}
@ -804,7 +804,7 @@ int
npxdna()
{
u_long *exstat;
critical_t s;
register_t s;
if (!npx_exists)
return (0);
@ -813,7 +813,7 @@ npxdna()
PCPU_GET(fpcurthread), curthread);
panic("npxdna");
}
s = cpu_critical_enter();
s = intr_disable();
stop_emulating();
/*
* Record new context early in case frstor causes an IRQ13.
@ -835,7 +835,7 @@ npxdna()
* first FPU instruction after a context switch.
*/
fpurstor(&PCPU_GET(curpcb)->pcb_save);
cpu_critical_exit(s);
intr_restore(s);
return (1);
}

7
sys/amd64/amd64/initcpu.c
View File

@ -657,14 +657,14 @@ void
enable_K5_wt_alloc(void)
{
u_int64_t msr;
critical_t savecrit;
register_t savecrit;
/*
* Write allocate is supported only on models 1, 2, and 3, with
* a stepping of 4 or greater.
*/
if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
savecrit = cpu_critical_enter();
savecrit = intr_disable();
msr = rdmsr(0x83); /* HWCR */
wrmsr(0x83, msr & !(0x10));
@ -695,8 +695,7 @@ enable_K5_wt_alloc(void)
msr=rdmsr(0x83);
wrmsr(0x83, msr|0x10); /* enable write allocate */
cpu_critical_exit(savecrit);
intr_restore(savecrit);
}
}

6
sys/amd64/amd64/sys_machdep.c
View File

@ -411,7 +411,7 @@ i386_set_ldt(td, args)
struct i386_ldt_args ua, *uap = &ua;
caddr_t old_ldt_base;
int old_ldt_len;
critical_t savecrit;
register_t savecrit;
if ((error = copyin(args, uap, sizeof(struct i386_ldt_args))) < 0)
return(error);
@ -532,13 +532,13 @@ i386_set_ldt(td, args)
}
/* Fill in range */
savecrit = cpu_critical_enter();
savecrit = intr_disable();
error = copyin(uap->descs,
&((union descriptor *)(pldt->ldt_base))[uap->start],
uap->num * sizeof(union descriptor));
if (!error)
td->td_retval[0] = uap->start;
cpu_critical_exit(savecrit);
intr_restore(savecrit);
return(error);
}

6
sys/amd64/amd64/vm_machdep.c
View File

@ -127,7 +127,7 @@ cpu_fork(td1, p2, td2, flags)
struct pcb *pcb2;
struct mdproc *mdp2;
#ifdef DEV_NPX
int savecrit;
register_t savecrit;
#endif
p1 = td1->td_proc;
@ -152,10 +152,10 @@ cpu_fork(td1, p2, td2, flags)
#ifdef DEV_NPX
if (td1 == curthread)
td1->td_pcb->pcb_gs = rgs();
savecrit = cpu_critical_enter();
savecrit = intr_disable();
if (PCPU_GET(fpcurthread) == td1)
npxsave(&td1->td_pcb->pcb_save);
cpu_critical_exit(savecrit);
intr_restore(savecrit);
#endif
/* Point the pcb to the top of the stack */

16
sys/amd64/include/cpufunc.h
View File

@ -578,6 +578,22 @@ cpu_critical_exit(critical_t eflags)
write_eflags(eflags);
}
static __inline register_t
intr_disable(void)
{
register_t eflags;
eflags = read_eflags();
disable_intr();
return (eflags);
}
static __inline void
intr_restore(register_t eflags)
{
write_eflags(eflags);
}
#else /* !__GNUC__ */
int breakpoint(void);

24
sys/amd64/isa/npx.c
View File

@ -512,7 +512,7 @@ npxinit(control)
u_short control;
{
static union savefpu dummy;
critical_t savecrit;
register_t savecrit;
if (!npx_exists)
return;
@ -521,7 +521,7 @@ npxinit(control)
* fnsave to throw away any junk in the fpu. npxsave() initializes
* the fpu and sets fpcurthread = NULL as important side effects.
*/
savecrit = cpu_critical_enter();
savecrit = intr_disable();
npxsave(&dummy);
stop_emulating();
#ifdef CPU_ENABLE_SSE
@ -533,7 +533,7 @@ npxinit(control)
if (PCPU_GET(curpcb) != NULL)
fpusave(&PCPU_GET(curpcb)->pcb_save);
start_emulating();
cpu_critical_exit(savecrit);
intr_restore(savecrit);
}
/*
@ -543,12 +543,12 @@ void
npxexit(td)
struct thread *td;
{
critical_t savecrit;
register_t savecrit;
savecrit = cpu_critical_enter();
savecrit = intr_disable();
if (td == PCPU_GET(fpcurthread))
npxsave(&PCPU_GET(curpcb)->pcb_save);
cpu_critical_exit(savecrit);
intr_restore(savecrit);
#ifdef NPX_DEBUG
if (npx_exists) {
u_int masked_exceptions;
@ -759,7 +759,7 @@ static char fpetable[128] = {
int
npxtrap()
{
critical_t savecrit;
register_t savecrit;
u_short control, status;
u_long *exstat;
@ -768,7 +768,7 @@ npxtrap()
PCPU_GET(fpcurthread), curthread, npx_exists);
panic("npxtrap from nowhere");
}
savecrit = cpu_critical_enter();
savecrit = intr_disable();
/*
* Interrupt handling (for another interrupt) may have pushed the
@ -789,7 +789,7 @@ npxtrap()
GET_FPU_SW(curthread) &= ~0x80bf;
else
fnclex();
cpu_critical_exit(savecrit);
intr_restore(savecrit);
return (fpetable[status & ((~control & 0x3f) | 0x40)]);
}
@ -804,7 +804,7 @@ int
npxdna()
{
u_long *exstat;
critical_t s;
register_t s;
if (!npx_exists)
return (0);
@ -813,7 +813,7 @@ npxdna()
PCPU_GET(fpcurthread), curthread);
panic("npxdna");
}
s = cpu_critical_enter();
s = intr_disable();
stop_emulating();
/*
* Record new context early in case frstor causes an IRQ13.
@ -835,7 +835,7 @@ npxdna()
* first FPU instruction after a context switch.
*/
fpurstor(&PCPU_GET(curpcb)->pcb_save);
cpu_critical_exit(s);
intr_restore(s);
return (1);
}

7
sys/i386/i386/initcpu.c
View File

@ -657,14 +657,14 @@ void
enable_K5_wt_alloc(void)
{
u_int64_t msr;
critical_t savecrit;
register_t savecrit;
/*
* Write allocate is supported only on models 1, 2, and 3, with
* a stepping of 4 or greater.
*/
if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
savecrit = cpu_critical_enter();
savecrit = intr_disable();
msr = rdmsr(0x83); /* HWCR */
wrmsr(0x83, msr & !(0x10));
@ -695,8 +695,7 @@ enable_K5_wt_alloc(void)
msr=rdmsr(0x83);
wrmsr(0x83, msr|0x10); /* enable write allocate */
cpu_critical_exit(savecrit);
intr_restore(savecrit);
}
}

18
sys/i386/i386/perfmon.c
View File

@ -134,18 +134,18 @@ perfmon_avail(void)
int
perfmon_setup(int pmc, unsigned int control)
{
critical_t savecrit;
register_t savecrit;
if (pmc < 0 || pmc >= NPMC)
return EINVAL;
perfmon_inuse |= (1 << pmc);
control &= ~(PMCF_SYS_FLAGS << 16);
savecrit = cpu_critical_enter();
savecrit = intr_disable();
ctl_shadow[pmc] = control;
writectl(pmc);
wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
cpu_critical_exit(savecrit);
intr_restore(savecrit);
return 0;
}
@ -180,17 +180,17 @@ perfmon_fini(int pmc)
int
perfmon_start(int pmc)
{
critical_t savecrit;
register_t savecrit;
if (pmc < 0 || pmc >= NPMC)
return EINVAL;
if (perfmon_inuse & (1 << pmc)) {
savecrit = cpu_critical_enter();
savecrit = intr_disable();
ctl_shadow[pmc] |= (PMCF_EN << 16);
wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
writectl(pmc);
cpu_critical_exit(savecrit);
intr_restore(savecrit);
return 0;
}
return EBUSY;
@ -199,17 +199,17 @@ perfmon_start(int pmc)
int
perfmon_stop(int pmc)
{
critical_t savecrit;
register_t savecrit;
if (pmc < 0 || pmc >= NPMC)
return EINVAL;
if (perfmon_inuse & (1 << pmc)) {
savecrit = cpu_critical_enter();
savecrit = intr_disable();
pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]) & 0xffffffffffULL;
ctl_shadow[pmc] &= ~(PMCF_EN << 16);
writectl(pmc);
cpu_critical_exit(savecrit);
intr_restore(savecrit);
return 0;
}
return EBUSY;

6
sys/i386/i386/sys_machdep.c
View File

@ -411,7 +411,7 @@ i386_set_ldt(td, args)
struct i386_ldt_args ua, *uap = &ua;
caddr_t old_ldt_base;
int old_ldt_len;
critical_t savecrit;
register_t savecrit;
if ((error = copyin(args, uap, sizeof(struct i386_ldt_args))) < 0)
return(error);
@ -532,13 +532,13 @@ i386_set_ldt(td, args)
}
/* Fill in range */
savecrit = cpu_critical_enter();
savecrit = intr_disable();
error = copyin(uap->descs,
&((union descriptor *)(pldt->ldt_base))[uap->start],
uap->num * sizeof(union descriptor));
if (!error)
td->td_retval[0] = uap->start;
cpu_critical_exit(savecrit);
intr_restore(savecrit);
return(error);
}

6
sys/i386/i386/vm_machdep.c
View File

@ -127,7 +127,7 @@ cpu_fork(td1, p2, td2, flags)
struct pcb *pcb2;
struct mdproc *mdp2;
#ifdef DEV_NPX
int savecrit;
register_t savecrit;
#endif
p1 = td1->td_proc;
@ -152,10 +152,10 @@ cpu_fork(td1, p2, td2, flags)
#ifdef DEV_NPX
if (td1 == curthread)
td1->td_pcb->pcb_gs = rgs();
savecrit = cpu_critical_enter();
savecrit = intr_disable();
if (PCPU_GET(fpcurthread) == td1)
npxsave(&td1->td_pcb->pcb_save);
cpu_critical_exit(savecrit);
intr_restore(savecrit);
#endif
/* Point the pcb to the top of the stack */

16
sys/i386/include/cpufunc.h
View File

@ -578,6 +578,22 @@ cpu_critical_exit(critical_t eflags)
write_eflags(eflags);
}
static __inline register_t
intr_disable(void)
{
register_t eflags;
eflags = read_eflags();
disable_intr();
return (eflags);
}
static __inline void
intr_restore(register_t eflags)
{
write_eflags(eflags);
}
#else /* !__GNUC__ */
int breakpoint(void);

24
sys/i386/isa/npx.c
View File

@ -512,7 +512,7 @@ npxinit(control)
u_short control;
{
static union savefpu dummy;
critical_t savecrit;
register_t savecrit;
if (!npx_exists)
return;
@ -521,7 +521,7 @@ npxinit(control)
* fnsave to throw away any junk in the fpu. npxsave() initializes
* the fpu and sets fpcurthread = NULL as important side effects.
*/
savecrit = cpu_critical_enter();
savecrit = intr_disable();
npxsave(&dummy);
stop_emulating();
#ifdef CPU_ENABLE_SSE
@ -533,7 +533,7 @@ npxinit(control)
if (PCPU_GET(curpcb) != NULL)
fpusave(&PCPU_GET(curpcb)->pcb_save);
start_emulating();
cpu_critical_exit(savecrit);
intr_restore(savecrit);
}
/*
@ -543,12 +543,12 @@ void
npxexit(td)
struct thread *td;
{
critical_t savecrit;
register_t savecrit;
savecrit = cpu_critical_enter();
savecrit = intr_disable();
if (td == PCPU_GET(fpcurthread))
npxsave(&PCPU_GET(curpcb)->pcb_save);
cpu_critical_exit(savecrit);
intr_restore(savecrit);
#ifdef NPX_DEBUG
if (npx_exists) {
u_int masked_exceptions;
@ -759,7 +759,7 @@ static char fpetable[128] = {
int
npxtrap()
{
critical_t savecrit;
register_t savecrit;
u_short control, status;
u_long *exstat;
@ -768,7 +768,7 @@ npxtrap()
PCPU_GET(fpcurthread), curthread, npx_exists);
panic("npxtrap from nowhere");
}
savecrit = cpu_critical_enter();
savecrit = intr_disable();
/*
* Interrupt handling (for another interrupt) may have pushed the
@ -789,7 +789,7 @@ npxtrap()
GET_FPU_SW(curthread) &= ~0x80bf;
else
fnclex();
cpu_critical_exit(savecrit);
intr_restore(savecrit);
return (fpetable[status & ((~control & 0x3f) | 0x40)]);
}
@ -804,7 +804,7 @@ int
npxdna()
{
u_long *exstat;
critical_t s;
register_t s;
if (!npx_exists)
return (0);
@ -813,7 +813,7 @@ npxdna()
PCPU_GET(fpcurthread), curthread);
panic("npxdna");
}
s = cpu_critical_enter();
s = intr_disable();
stop_emulating();
/*
* Record new context early in case frstor causes an IRQ13.
@ -835,7 +835,7 @@ npxdna()
* first FPU instruction after a context switch.
*/
fpurstor(&PCPU_GET(curpcb)->pcb_save);
cpu_critical_exit(s);
intr_restore(s);
return (1);
}