From ba9b8f5cfc005f6ee31fc335e9b1916a6e52a8e4 Mon Sep 17 00:00:00 2001 From: simokawa Date: Mon, 3 Mar 2003 04:10:56 +0000 Subject: [PATCH] Defer allowing async. requests after self ID's have received. This should fix some problem of SBP2 device probing. Prior to rev 1.41, we keep writing the register while bus reset phase. But in rev 1.41, we ignore successive bus reset events and some chips seem to clear the register after we write to it. Tested by: Michael Reifenberger --- sys/dev/firewire/fwohci.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/sys/dev/firewire/fwohci.c b/sys/dev/firewire/fwohci.c index 6a6addb4c06e..b6db99164de5 100644 --- a/sys/dev/firewire/fwohci.c +++ b/sys/dev/firewire/fwohci.c @@ -1783,13 +1783,6 @@ fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); #endif fw_busreset(fc); - - OWRITE(sc, OHCI_AREQHI, 1 << 31); - /* XXX insecure ?? */ - OWRITE(sc, OHCI_PREQHI, 0x7fffffff); - OWRITE(sc, OHCI_PREQLO, 0xffffffff); - OWRITE(sc, OHCI_PREQUPPER, 0x10000); - } busresetout: if((stat & OHCI_INT_DMA_IR )){ @@ -1857,6 +1850,12 @@ busresetout: #endif /* Enable bus reset interrupt */ OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R); + /* Allow async. request to us */ + OWRITE(sc, OHCI_AREQHI, 1 << 31); + /* XXX insecure ?? */ + OWRITE(sc, OHCI_PREQHI, 0x7fffffff); + OWRITE(sc, OHCI_PREQLO, 0xffffffff); + OWRITE(sc, OHCI_PREQUPPER, 0x10000); /* ** Checking whether the node is root or not. If root, turn on ** cycle master.