Implement AR933x polled IO uart bus code.
This implements the bus transmit/receive/sigchg/ipend methods with a polled interrupt handler (ipend) rather than enabling hardware interrupts. The FIFO is faked at 16 bytes deep for now, just so the transmit IO side doesn't suck too bad (the callout frequency limits how quickly IO is flushed to the sender, rather than scheduling the callout more frequently whilst there's active TX. But I digress.) Tested: * Atheros AP121 (AR9330) reference board, booting to multi-user interactive mode.
This commit is contained in:
adrian
parent
acae1cdab7
commit
ba9ca7951e
@ -80,72 +80,54 @@ ar933x_clrint(struct uart_bas *bas)
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}
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#endif
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#if 0
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static int
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ar933x_drain(struct uart_bas *bas, int what)
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{
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int delay, limit;
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delay = ar933x_delay(bas);
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int limit;
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if (what & UART_DRAIN_TRANSMITTER) {
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/*
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* Pick an arbitrary high limit to avoid getting stuck in
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* an infinite loop when the hardware is broken. Make the
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* limit high enough to handle large FIFOs.
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*/
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limit = 10*1024;
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while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
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DELAY(delay);
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/* Loop over until the TX FIFO shows entirely clear */
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while (--limit) {
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if ((ar933x_getreg(bas, AR933X_UART_CS_REG)
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& AR933X_UART_CS_TX_BUSY) == 0)
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break;
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}
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if (limit == 0) {
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/* printf("ns8250: transmitter appears stuck... "); */
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return (EIO);
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}
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}
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if (what & UART_DRAIN_RECEIVER) {
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/*
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* Pick an arbitrary high limit to avoid getting stuck in
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* an infinite loop when the hardware is broken. Make the
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* limit high enough to handle large FIFOs and integrated
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* UARTs. The HP rx2600 for example has 3 UARTs on the
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* management board that tend to get a lot of data send
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* to it when the UART is first activated.
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*/
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limit=10*4096;
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while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
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(void)uart_getreg(bas, REG_DATA);
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while (--limit) {
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/* XXX duplicated from ar933x_getc() */
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/* XXX TODO: refactor! */
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/* If there's nothing to read, stop! */
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if ((ar933x_getreg(bas, AR933X_UART_DATA_REG) &
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AR933X_UART_DATA_RX_CSR) == 0) {
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break;
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}
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/* Read the top of the RX FIFO */
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(void) ar933x_getreg(bas, AR933X_UART_DATA_REG);
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/* Remove that entry from said RX FIFO */
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ar933x_setreg(bas, AR933X_UART_DATA_REG,
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AR933X_UART_DATA_RX_CSR);
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uart_barrier(bas);
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DELAY(delay << 2);
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DELAY(2);
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}
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if (limit == 0) {
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/* printf("ns8250: receiver appears broken... "); */
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return (EIO);
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}
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}
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return (0);
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}
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#endif
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#if 0
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/*
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* We can only flush UARTs with FIFOs. UARTs without FIFOs should be
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* drained. WARNING: this function clobbers the FIFO setting!
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*/
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static void
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ar933x_flush(struct uart_bas *bas, int what)
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{
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uint8_t fcr;
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fcr = FCR_ENABLE;
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if (what & UART_FLUSH_TRANSMITTER)
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fcr |= FCR_XMT_RST;
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if (what & UART_FLUSH_RECEIVER)
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fcr |= FCR_RCV_RST;
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uart_setreg(bas, REG_FCR, fcr);
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uart_barrier(bas);
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}
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#endif
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/*
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* Calculate the baud from the given chip configuration parameters.
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@ -404,56 +386,12 @@ struct uart_class uart_ar933x_class = {
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static int
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ar933x_bus_attach(struct uart_softc *sc)
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{
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#if 0
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struct ar933x_softc *ns8250 = (struct ar933x_softc*)sc;
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struct uart_bas *bas;
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unsigned int ivar;
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/* XXX TODO: flush transmitter */
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bas = &sc->sc_bas;
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/* XXX TODO: enable RX interrupts to kick-start things */
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ns8250->mcr = uart_getreg(bas, REG_MCR);
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ns8250->fcr = FCR_ENABLE;
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if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
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&ivar)) {
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if (UART_FLAGS_FCR_RX_LOW(ivar))
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ns8250->fcr |= FCR_RX_LOW;
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else if (UART_FLAGS_FCR_RX_MEDL(ivar))
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ns8250->fcr |= FCR_RX_MEDL;
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else if (UART_FLAGS_FCR_RX_HIGH(ivar))
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ns8250->fcr |= FCR_RX_HIGH;
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else
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ns8250->fcr |= FCR_RX_MEDH;
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} else
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ns8250->fcr |= FCR_RX_MEDH;
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/* Get IER mask */
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ivar = 0xf0;
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resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
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&ivar);
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ns8250->ier_mask = (uint8_t)(ivar & 0xff);
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/* Get IER RX interrupt bits */
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ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
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resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
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&ivar);
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ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
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uart_setreg(bas, REG_FCR, ns8250->fcr);
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uart_barrier(bas);
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ar933x_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
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/* XXX TODO: enable the host interrupt now */
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if (ns8250->mcr & MCR_DTR)
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sc->sc_hwsig |= SER_DTR;
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if (ns8250->mcr & MCR_RTS)
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sc->sc_hwsig |= SER_RTS;
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ar933x_bus_getsig(sc);
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ar933x_clrint(bas);
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ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
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ns8250->ier |= ns8250->ier_rxbits;
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uart_setreg(bas, REG_IER, ns8250->ier);
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uart_barrier(bas);
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#endif
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return (0);
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}
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@ -472,54 +410,44 @@ ar933x_bus_detach(struct uart_softc *sc)
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uart_barrier(bas);
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ar933x_clrint(bas);
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#endif
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/* XXX TODO: Disable all interrupts */
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/* XXX TODO: Disable the host interrupt */
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return (0);
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}
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static int
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ar933x_bus_flush(struct uart_softc *sc, int what)
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{
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#if 0
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struct ar933x_softc *ns8250 = (struct ar933x_softc*)sc;
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struct uart_bas *bas;
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int error;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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if (sc->sc_rxfifosz > 1) {
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ar933x_flush(bas, what);
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uart_setreg(bas, REG_FCR, ns8250->fcr);
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uart_barrier(bas);
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error = 0;
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} else
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error = ar933x_drain(bas, what);
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ar933x_drain(bas, what);
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uart_unlock(sc->sc_hwmtx);
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return (error);
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#endif
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return (ENXIO);
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return (0);
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}
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static int
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ar933x_bus_getsig(struct uart_softc *sc)
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{
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#if 0
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uint32_t new, old, sig;
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uint8_t msr;
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uint32_t sig = sc->sc_hwsig;
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/*
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* For now, let's just return that DSR/DCD/CTS is asserted.
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*
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* XXX TODO: actually verify whether this is correct!
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*/
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SIGCHG(1, sig, SER_DSR, SER_DDSR);
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SIGCHG(1, sig, SER_CTS, SER_DCTS);
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SIGCHG(1, sig, SER_DCD, SER_DDCD);
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SIGCHG(1, sig, SER_RI, SER_DRI);
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sc->sc_hwsig = sig & ~SER_MASK_DELTA;
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do {
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old = sc->sc_hwsig;
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sig = old;
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uart_lock(sc->sc_hwmtx);
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msr = uart_getreg(&sc->sc_bas, REG_MSR);
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uart_unlock(sc->sc_hwmtx);
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SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
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SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
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SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
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SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI);
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new = sig & ~SER_MASK_DELTA;
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} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
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return (sig);
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#endif
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return (0);
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}
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static int
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@ -598,52 +526,47 @@ ar933x_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
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return (ENXIO);
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}
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/*
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* Bus interrupt handler.
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*
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* For now, system interrupts are disabled.
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* So this is just called from a callout in uart_core.c
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* to poll various state.
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*/
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static int
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ar933x_bus_ipend(struct uart_softc *sc)
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{
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#if 0
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struct uart_bas *bas;
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struct ar933x_softc *ns8250;
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int ipend;
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uint8_t iir, lsr;
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struct uart_bas *bas = &sc->sc_bas;
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int ipend = 0;
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ns8250 = (struct ar933x_softc *)sc;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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iir = uart_getreg(bas, REG_IIR);
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if (iir & IIR_NOPEND) {
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uart_unlock(sc->sc_hwmtx);
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return (0);
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/*
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* Always notify the upper layer if RX is ready.
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*/
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if (ar933x_rxready(bas)) {
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ipend |= SER_INT_RXREADY;
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}
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ipend = 0;
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if (iir & IIR_RXRDY) {
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lsr = uart_getreg(bas, REG_LSR);
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if (lsr & LSR_OE)
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ipend |= SER_INT_OVERRUN;
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if (lsr & LSR_BI)
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ipend |= SER_INT_BREAK;
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if (lsr & LSR_RXRDY)
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ipend |= SER_INT_RXREADY;
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} else {
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if (iir & IIR_TXRDY) {
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/*
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* Only signal TX idle if we're not busy transmitting.
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*/
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if (sc->sc_txbusy) {
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if ((ar933x_getreg(bas, AR933X_UART_DATA_REG)
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& AR933X_UART_DATA_TX_CSR)) {
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ipend |= SER_INT_TXIDLE;
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uart_setreg(bas, REG_IER, ns8250->ier);
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} else
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} else {
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ipend |= SER_INT_SIGCHG;
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}
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}
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if (ipend == 0)
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ar933x_clrint(bas);
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uart_unlock(sc->sc_hwmtx);
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return (ipend);
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#endif
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return (0);
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}
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static int
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ar933x_bus_param(struct uart_softc *sc, int baudrate, int databits,
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int stopbits, int parity)
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{
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#if 0
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struct uart_bas *bas;
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int error;
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@ -652,193 +575,63 @@ ar933x_bus_param(struct uart_softc *sc, int baudrate, int databits,
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error = ar933x_param(bas, baudrate, databits, stopbits, parity);
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uart_unlock(sc->sc_hwmtx);
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return (error);
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#endif
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return (ENXIO);
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}
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static int
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ar933x_bus_probe(struct uart_softc *sc)
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{
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#if 0
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struct ar933x_softc *ns8250;
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struct uart_bas *bas;
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int count, delay, error, limit;
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uint8_t lsr, mcr, ier;
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int error;
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ns8250 = (struct ar933x_softc *)sc;
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bas = &sc->sc_bas;
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error = ar933x_probe(bas);
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if (error)
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return (error);
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mcr = MCR_IE;
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if (sc->sc_sysdev == NULL) {
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/* By using ar933x_init() we also set DTR and RTS. */
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ar933x_init(bas, 115200, 8, 1, UART_PARITY_NONE);
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} else
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mcr |= MCR_DTR | MCR_RTS;
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error = ar933x_drain(bas, UART_DRAIN_TRANSMITTER);
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if (error)
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return (error);
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/*
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* Set loopback mode. This avoids having garbage on the wire and
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* also allows us send and receive data. We set DTR and RTS to
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* avoid the possibility that automatic flow-control prevents
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* any data from being sent.
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*/
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uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
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uart_barrier(bas);
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/*
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* Enable FIFOs. And check that the UART has them. If not, we're
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* done. Since this is the first time we enable the FIFOs, we reset
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* them.
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*/
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uart_setreg(bas, REG_FCR, FCR_ENABLE);
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uart_barrier(bas);
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if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
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/*
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* NS16450 or INS8250. We don't bother to differentiate
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* between them. They're too old to be interesting.
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*/
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uart_setreg(bas, REG_MCR, mcr);
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uart_barrier(bas);
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sc->sc_rxfifosz = sc->sc_txfifosz = 1;
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device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
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return (0);
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}
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uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
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uart_barrier(bas);
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count = 0;
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delay = ar933x_delay(bas);
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/* We have FIFOs. Drain the transmitter and receiver. */
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error = ar933x_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
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if (error) {
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uart_setreg(bas, REG_MCR, mcr);
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uart_setreg(bas, REG_FCR, 0);
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uart_barrier(bas);
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goto describe;
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}
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/*
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* We should have a sufficiently clean "pipe" to determine the
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* size of the FIFOs. We send as much characters as is reasonable
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* and wait for the overflow bit in the LSR register to be
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* asserted, counting the characters as we send them. Based on
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* that count we know the FIFO size.
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*/
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do {
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uart_setreg(bas, REG_DATA, 0);
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uart_barrier(bas);
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count++;
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limit = 30;
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lsr = 0;
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/*
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* LSR bits are cleared upon read, so we must accumulate
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* them to be able to test LSR_OE below.
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*/
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while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
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--limit)
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DELAY(delay);
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if (limit == 0) {
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ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
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uart_setreg(bas, REG_IER, ier);
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uart_setreg(bas, REG_MCR, mcr);
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uart_setreg(bas, REG_FCR, 0);
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uart_barrier(bas);
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count = 0;
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goto describe;
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}
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} while ((lsr & LSR_OE) == 0 && count < 130);
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count--;
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uart_setreg(bas, REG_MCR, mcr);
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/* Reset FIFOs. */
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ar933x_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
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ar933x_drain(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
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describe:
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if (count >= 14 && count <= 16) {
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sc->sc_rxfifosz = 16;
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device_set_desc(sc->sc_dev, "16550 or compatible");
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} else if (count >= 28 && count <= 32) {
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sc->sc_rxfifosz = 32;
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device_set_desc(sc->sc_dev, "16650 or compatible");
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} else if (count >= 56 && count <= 64) {
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sc->sc_rxfifosz = 64;
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device_set_desc(sc->sc_dev, "16750 or compatible");
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} else if (count >= 112 && count <= 128) {
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sc->sc_rxfifosz = 128;
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device_set_desc(sc->sc_dev, "16950 or compatible");
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} else {
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sc->sc_rxfifosz = 16;
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device_set_desc(sc->sc_dev,
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"Non-standard ns8250 class UART with FIFOs");
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}
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/*
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* Force the Tx FIFO size to 16 bytes for now. We don't program the
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* Tx trigger. Also, we assume that all data has been sent when the
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||||
* interrupt happens.
|
||||
*/
|
||||
/* XXX TODO: actually find out what the FIFO depth is! */
|
||||
sc->sc_rxfifosz = 16;
|
||||
sc->sc_txfifosz = 16;
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* XXX there are some issues related to hardware flow control and
|
||||
* it's likely that uart(4) is the cause. This basicly needs more
|
||||
* investigation, but we avoid using for hardware flow control
|
||||
* until then.
|
||||
*/
|
||||
/* 16650s or higher have automatic flow control. */
|
||||
if (sc->sc_rxfifosz > 16) {
|
||||
sc->sc_hwiflow = 1;
|
||||
sc->sc_hwoflow = 1;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ar933x_bus_receive(struct uart_softc *sc)
|
||||
{
|
||||
#if 0
|
||||
struct uart_bas *bas;
|
||||
struct uart_bas *bas = &sc->sc_bas;
|
||||
int xc;
|
||||
uint8_t lsr;
|
||||
|
||||
bas = &sc->sc_bas;
|
||||
uart_lock(sc->sc_hwmtx);
|
||||
lsr = uart_getreg(bas, REG_LSR);
|
||||
while (lsr & LSR_RXRDY) {
|
||||
|
||||
/* Loop over until we are full, or no data is available */
|
||||
while (ar933x_rxready(bas)) {
|
||||
if (uart_rx_full(sc)) {
|
||||
sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
|
||||
break;
|
||||
}
|
||||
xc = uart_getreg(bas, REG_DATA);
|
||||
if (lsr & LSR_FE)
|
||||
xc |= UART_STAT_FRAMERR;
|
||||
if (lsr & LSR_PE)
|
||||
xc |= UART_STAT_PARERR;
|
||||
|
||||
/* Read the top of the RX FIFO */
|
||||
xc = ar933x_getreg(bas, AR933X_UART_DATA_REG) & 0xff;
|
||||
|
||||
/* Remove that entry from said RX FIFO */
|
||||
ar933x_setreg(bas, AR933X_UART_DATA_REG,
|
||||
AR933X_UART_DATA_RX_CSR);
|
||||
|
||||
/* XXX frame, parity error */
|
||||
uart_rx_put(sc, xc);
|
||||
lsr = uart_getreg(bas, REG_LSR);
|
||||
}
|
||||
/* Discard everything left in the Rx FIFO. */
|
||||
while (lsr & LSR_RXRDY) {
|
||||
(void)uart_getreg(bas, REG_DATA);
|
||||
uart_barrier(bas);
|
||||
lsr = uart_getreg(bas, REG_LSR);
|
||||
}
|
||||
|
||||
/*
|
||||
* XXX TODO: Discard everything left in the Rx FIFO?
|
||||
* XXX only if we've hit an overrun condition?
|
||||
*/
|
||||
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
#endif
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -879,23 +672,26 @@ ar933x_bus_setsig(struct uart_softc *sc, int sig)
|
||||
static int
|
||||
ar933x_bus_transmit(struct uart_softc *sc)
|
||||
{
|
||||
#if 0
|
||||
struct ar933x_softc *ns8250 = (struct ar933x_softc*)sc;
|
||||
struct uart_bas *bas;
|
||||
struct uart_bas *bas = &sc->sc_bas;
|
||||
int i;
|
||||
|
||||
bas = &sc->sc_bas;
|
||||
uart_lock(sc->sc_hwmtx);
|
||||
while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
|
||||
;
|
||||
uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
|
||||
uart_barrier(bas);
|
||||
|
||||
/* XXX wait for FIFO to be ready? */
|
||||
|
||||
for (i = 0; i < sc->sc_txdatasz; i++) {
|
||||
uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
|
||||
uart_barrier(bas);
|
||||
/* Write the TX data */
|
||||
ar933x_setreg(bas, AR933X_UART_DATA_REG,
|
||||
(sc->sc_txbuf[i] & 0xff) | AR933X_UART_DATA_TX_CSR);
|
||||
}
|
||||
|
||||
/*
|
||||
* Inform the upper layer that we are presently transmitting
|
||||
* data to the hardware; this will be cleared when the
|
||||
* TXIDLE interrupt occurs.
|
||||
*/
|
||||
sc->sc_txbusy = 1;
|
||||
uart_unlock(sc->sc_hwmtx);
|
||||
#endif
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -14,7 +14,7 @@ hint.uart.0.at="apb0"
|
||||
# NB: This isn't an ns8250 UART
|
||||
hint.uart.0.maddr=0x18020000
|
||||
hint.uart.0.msize=0x18
|
||||
hint.uart.0.irq=3
|
||||
# hint.uart.0.irq=3
|
||||
|
||||
#ehci - note the 0x100 offset for the AR913x/AR724x
|
||||
hint.ehci.0.at="nexus0"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user