From bae78765ffc8c6de5f538d699cfd05f18d7bf1c8 Mon Sep 17 00:00:00 2001
From: adrian <adrian@FreeBSD.org>
Date: Sat, 30 Jul 2011 13:18:48 +0000
Subject: [PATCH] Fix the AR9280 initial AGC calibration code.

It looks like this was mixed up with the AR9285 calibration code.
This code is now more in line with what Linux ath9k and Atheros
reference drivers do.

Obtained from:	Atheros
Approved by:	re (kib)
---
 sys/dev/ath/ath_hal/ar5416/ar5416_cal.c | 45 ++++++++++++-------------
 1 file changed, 21 insertions(+), 24 deletions(-)

diff --git a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c
index 1356c7d1081b..af7b732183f4 100644
--- a/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c
+++ b/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c
@@ -186,36 +186,22 @@ ar5416RunInitCals(struct ath_hal *ah, int init_cal_count)
 }
 #endif
 
+
+/*
+ * AGC calibration for the AR5416, AR9130, AR9160, AR9280.
+ */
 HAL_BOOL
 ar5416InitCalHardware(struct ath_hal *ah, const struct ieee80211_channel *chan)
 {
+
 	if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
+		/* Disable ADC */
+		OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
+		    AR_PHY_ADC_CTL_OFF_PWDADC);
+
 		/* Enable Rx Filter Cal */
-		OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
 		OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
 		    AR_PHY_AGC_CONTROL_FLTR_CAL);
-
-		/* Clear the carrier leak cal bit */
-		OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
-
-		/* kick off the cal */
-		OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
-
-		/* Poll for offset calibration complete */
-		if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
-			HALDEBUG(ah, HAL_DEBUG_ANY,
-			    "%s: offset calibration failed to complete in 1ms; "
-			    "noisy environment?\n", __func__);
-			return AH_FALSE;
-		}
-
-		/* Set the cl cal bit and rerun the cal a 2nd time */
-		/* Enable Rx Filter Cal */
-		OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
-		OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
-		    AR_PHY_AGC_CONTROL_FLTR_CAL);
-
-		OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
 	} 	
 
 	/* Calibrate the AGC */
@@ -229,6 +215,16 @@ ar5416InitCalHardware(struct ath_hal *ah, const struct ieee80211_channel *chan)
 		return AH_FALSE;
 	}
 
+	if (AR_SREV_MERLIN_10_OR_LATER(ah)) {
+		/* Enable ADC */
+		OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL,
+		    AR_PHY_ADC_CTL_OFF_PWDADC);
+
+		/* Disable Rx Filter Cal */
+		OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
+		    AR_PHY_AGC_CONTROL_FLTR_CAL);
+	}
+
 	return AH_TRUE;
 }
 
@@ -247,7 +243,8 @@ ar5416InitCal(struct ath_hal *ah, const struct ieee80211_channel *chan)
 
 	/* Do initial chipset-specific calibration */
 	if (! AH5416(ah)->ah_cal_initcal(ah, chan)) {
-		HALDEBUG(ah, HAL_DEBUG_ANY, "%s: initial chipset calibration did "
+		HALDEBUG(ah, HAL_DEBUG_ANY,
+		    "%s: initial chipset calibration did "
 		    "not complete in time; noisy environment?\n", __func__);
 		return AH_FALSE;
 	}