Add register definitions for the status and command registers for AGP.
PR: 64846 Submitted by: Samy Al Bahra
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@ -46,6 +46,28 @@
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#define AGP_STATUS 0x4
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#define AGP_COMMAND 0x8
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#define AGP_STATUS_AGP3 0x0008
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#define AGP_STATUS_RQ_MASK 0xff000000
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#define AGP_COMMAND_RQ_MASK 0xff000000
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#define AGP_STATUS_ARQSZ_MASK 0xe000
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#define AGP_COMMAND_ARQSZ_MASK 0xe000
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#define AGP_STATUS_CAL_MASK 0x1c00
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#define AGP_COMMAND_CAL_MASK 0x1c00
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#define AGP_STATUS_ISOCH 0x10000
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#define AGP_STATUS_SBA 0x0200
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#define AGP_STATUS_ITA_COH 0x0100
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#define AGP_STATUS_GART64 0x0080
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#define AGP_STATUS_HTRANS 0x0040
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#define AGP_STATUS_64BIT 0x0020
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#define AGP_STATUS_FW 0x0010
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#define AGP_COMMAND_RQ_MASK 0xff000000
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#define AGP_COMMAND_ARQSZ_MASK 0xe000
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#define AGP_COMMAND_CAL_MASK 0x1c00
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#define AGP_COMMAND_SBA 0x0200
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#define AGP_COMMAND_AGP 0x0100
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#define AGP_COMMAND_GART64 0x0080
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#define AGP_COMMAND_64BIT 0x0020
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#define AGP_COMMAND_FW 0x0010
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/*
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* Config offsets for Intel AGP chipsets.
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@ -46,6 +46,28 @@
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#define AGP_STATUS 0x4
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#define AGP_COMMAND 0x8
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#define AGP_STATUS_AGP3 0x0008
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#define AGP_STATUS_RQ_MASK 0xff000000
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#define AGP_COMMAND_RQ_MASK 0xff000000
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#define AGP_STATUS_ARQSZ_MASK 0xe000
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#define AGP_COMMAND_ARQSZ_MASK 0xe000
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#define AGP_STATUS_CAL_MASK 0x1c00
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#define AGP_COMMAND_CAL_MASK 0x1c00
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#define AGP_STATUS_ISOCH 0x10000
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#define AGP_STATUS_SBA 0x0200
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#define AGP_STATUS_ITA_COH 0x0100
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#define AGP_STATUS_GART64 0x0080
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#define AGP_STATUS_HTRANS 0x0040
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#define AGP_STATUS_64BIT 0x0020
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#define AGP_STATUS_FW 0x0010
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#define AGP_COMMAND_RQ_MASK 0xff000000
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#define AGP_COMMAND_ARQSZ_MASK 0xe000
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#define AGP_COMMAND_CAL_MASK 0x1c00
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#define AGP_COMMAND_SBA 0x0200
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#define AGP_COMMAND_AGP 0x0100
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#define AGP_COMMAND_GART64 0x0080
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#define AGP_COMMAND_64BIT 0x0020
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#define AGP_COMMAND_FW 0x0010
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/*
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* Config offsets for Intel AGP chipsets.
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