Add jz4780 PDMA controller driver.
Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D8817
This commit is contained in:
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@ -19,6 +19,7 @@ mips/ingenic/jz4780_intr.c standard
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mips/ingenic/jz4780_gpio.c standard
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mips/ingenic/jz4780_machdep.c standard
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mips/ingenic/jz4780_nemc.c standard
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mips/ingenic/jz4780_pdma.c standard
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mips/ingenic/jz4780_pinctrl.c standard
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mips/ingenic/jz4780_timer.c standard
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@ -10,6 +10,7 @@ mips/ingenic/jz4780_clk_pll.c standard
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mips/ingenic/jz4780_intr.c standard
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mips/ingenic/jz4780_gpio.c standard
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mips/ingenic/jz4780_machdep.c standard
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mips/ingenic/jz4780_pdma.c standard
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mips/ingenic/jz4780_pinctrl.c standard
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mips/ingenic/jz4780_timer.c standard
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544
sys/mips/ingenic/jz4780_pdma.c
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544
sys/mips/ingenic/jz4780_pdma.c
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@ -0,0 +1,544 @@
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/*-
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* Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Ingenic JZ4780 PDMA Controller. */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/cache.h>
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#ifdef FDT
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#endif
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#include <dev/xdma/xdma.h>
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#include <mips/ingenic/jz4780_common.h>
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#include <mips/ingenic/jz4780_pdma.h>
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#include "xdma_if.h"
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struct pdma_softc {
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device_t dev;
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struct resource *res[2];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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void *ih;
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};
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struct pdma_fdt_data {
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int tx;
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int rx;
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int chan;
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};
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struct pdma_channel {
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xdma_channel_t *xchan;
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struct pdma_fdt_data data;
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int cur_desc;
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int used;
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int index;
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int flags;
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#define CHAN_DESCR_RELINK (1 << 0)
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};
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#define PDMA_NCHANNELS 32
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struct pdma_channel pdma_channels[PDMA_NCHANNELS];
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static struct resource_spec pdma_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int pdma_probe(device_t dev);
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static int pdma_attach(device_t dev);
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static int pdma_detach(device_t dev);
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static int chan_start(struct pdma_softc *sc, struct pdma_channel *chan);
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static void
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pdma_intr(void *arg)
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{
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struct pdma_channel *chan;
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struct pdma_softc *sc;
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xdma_channel_t *xchan;
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xdma_config_t *conf;
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int pending;
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int i;
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sc = arg;
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pending = READ4(sc, PDMA_DIRQP);
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/* Ack all the channels. */
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WRITE4(sc, PDMA_DIRQP, 0);
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for (i = 0; i < PDMA_NCHANNELS; i++) {
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if (pending & (1 << i)) {
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chan = &pdma_channels[i];
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xchan = chan->xchan;
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conf = &xchan->conf;
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/* TODO: check for AR, HLT error bits here. */
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/* Disable channel */
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WRITE4(sc, PDMA_DCS(chan->index), 0);
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if (chan->flags & CHAN_DESCR_RELINK) {
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/* Enable again */
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chan->cur_desc = (chan->cur_desc + 1) % \
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conf->block_num;
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chan_start(sc, chan);
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}
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xdma_callback(chan->xchan);
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}
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}
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}
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static int
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pdma_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-dma"))
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return (ENXIO);
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device_set_desc(dev, "Ingenic JZ4780 PDMA Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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pdma_attach(device_t dev)
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{
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struct pdma_softc *sc;
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phandle_t xref, node;
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int err;
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int reg;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, pdma_spec, sc->res)) {
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device_printf(dev, "could not allocate resources for device\n");
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return (ENXIO);
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}
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/* Memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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/* Setup interrupt handler */
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err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, pdma_intr, sc, &sc->ih);
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if (err) {
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device_printf(dev, "Unable to alloc interrupt resource.\n");
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return (ENXIO);
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}
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node = ofw_bus_get_node(dev);
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xref = OF_xref_from_node(node);
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OF_device_register_xref(xref, dev);
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reg = READ4(sc, PDMA_DMAC);
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reg &= ~(DMAC_HLT | DMAC_AR);
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reg |= (DMAC_DMAE);
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WRITE4(sc, PDMA_DMAC, reg);
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WRITE4(sc, PDMA_DMACP, 0);
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return (0);
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}
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static int
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pdma_detach(device_t dev)
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{
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struct pdma_softc *sc;
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sc = device_get_softc(dev);
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bus_release_resources(dev, pdma_spec, sc->res);
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return (0);
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}
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static int
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chan_start(struct pdma_softc *sc, struct pdma_channel *chan)
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{
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struct xdma_channel *xchan;
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xchan = chan->xchan;
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/* 8 byte descriptor. */
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WRITE4(sc, PDMA_DCS(chan->index), DCS_DES8);
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WRITE4(sc, PDMA_DDA(chan->index), xchan->descs_phys[chan->cur_desc].ds_addr);
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WRITE4(sc, PDMA_DDS, (1 << chan->index));
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/* Channel transfer enable. */
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WRITE4(sc, PDMA_DCS(chan->index), (DCS_DES8 | DCS_CTE));
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return (0);
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}
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static int
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chan_stop(struct pdma_softc *sc, struct pdma_channel *chan)
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{
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int timeout;
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WRITE4(sc, PDMA_DCS(chan->index), 0);
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timeout = 100;
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do {
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if ((READ4(sc, PDMA_DCS(chan->index)) & DCS_CTE) == 0) {
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break;
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}
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} while (timeout--);
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if (timeout == 0) {
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device_printf(sc->dev, "%s: Can't stop channel %d\n",
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__func__, chan->index);
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}
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return (0);
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}
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static int
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pdma_channel_alloc(device_t dev, struct xdma_channel *xchan)
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{
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struct pdma_channel *chan;
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struct pdma_softc *sc;
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int i;
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sc = device_get_softc(dev);
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xdma_assert_locked();
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for (i = 0; i < PDMA_NCHANNELS; i++) {
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chan = &pdma_channels[i];
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if (chan->used == 0) {
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chan->xchan = xchan;
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xchan->chan = (void *)chan;
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chan->used = 1;
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chan->index = i;
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return (0);
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}
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}
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return (-1);
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}
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static int
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pdma_channel_free(device_t dev, struct xdma_channel *xchan)
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{
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struct pdma_channel *chan;
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struct pdma_softc *sc;
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sc = device_get_softc(dev);
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xdma_assert_locked();
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chan = (struct pdma_channel *)xchan->chan;
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chan->used = 0;
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return (0);
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}
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static int
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pdma_channel_prep_memcpy(device_t dev, struct xdma_channel *xchan)
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{
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struct pdma_channel *chan;
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struct pdma_hwdesc *desc;
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struct pdma_softc *sc;
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xdma_config_t *conf;
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int ret;
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sc = device_get_softc(dev);
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chan = (struct pdma_channel *)xchan->chan;
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/* Ensure we are not in operation */
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chan_stop(sc, chan);
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ret = xdma_desc_alloc(xchan, sizeof(struct pdma_hwdesc), 8);
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if (ret != 0) {
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device_printf(sc->dev,
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"%s: Can't allocate descriptors.\n", __func__);
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return (-1);
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}
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conf = &xchan->conf;
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desc = (struct pdma_hwdesc *)xchan->descs;
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desc[0].dsa = conf->src_addr;
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desc[0].dta = conf->dst_addr;
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desc[0].drt = DRT_AUTO;
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desc[0].dcm = DCM_SAI | DCM_DAI;
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/* 4 byte copy for now. */
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desc[0].dtc = (conf->block_len / 4);
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desc[0].dcm |= DCM_SP_4 | DCM_DP_4 | DCM_TSZ_4;
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desc[0].dcm |= DCM_TIE;
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return (0);
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}
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static int
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access_width(xdma_config_t *conf, uint32_t *dcm, uint32_t *max_width)
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{
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*dcm = 0;
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*max_width = max(conf->src_width, conf->dst_width);
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switch (conf->src_width) {
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case 1:
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*dcm |= DCM_SP_1;
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break;
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case 2:
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*dcm |= DCM_SP_2;
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break;
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case 4:
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*dcm |= DCM_SP_4;
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break;
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default:
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return (-1);
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}
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switch (conf->dst_width) {
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case 1:
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*dcm |= DCM_DP_1;
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break;
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case 2:
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*dcm |= DCM_DP_2;
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break;
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case 4:
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*dcm |= DCM_DP_4;
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break;
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default:
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return (-1);
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}
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switch (*max_width) {
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case 1:
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*dcm |= DCM_TSZ_1;
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break;
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case 2:
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*dcm |= DCM_TSZ_2;
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break;
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case 4:
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*dcm |= DCM_TSZ_4;
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break;
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default:
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return (-1);
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};
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return (0);
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}
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static int
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pdma_channel_prep_cyclic(device_t dev, struct xdma_channel *xchan)
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{
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struct pdma_fdt_data *data;
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struct pdma_channel *chan;
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struct pdma_hwdesc *desc;
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xdma_controller_t *xdma;
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struct pdma_softc *sc;
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xdma_config_t *conf;
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int max_width;
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uint32_t reg;
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uint32_t dcm;
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int ret;
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int i;
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sc = device_get_softc(dev);
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conf = &xchan->conf;
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xdma = xchan->xdma;
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data = (struct pdma_fdt_data *)xdma->data;
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ret = xdma_desc_alloc(xchan, sizeof(struct pdma_hwdesc), 8);
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if (ret != 0) {
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device_printf(sc->dev,
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"%s: Can't allocate descriptors.\n", __func__);
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return (-1);
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}
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chan = (struct pdma_channel *)xchan->chan;
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/* Ensure we are not in operation */
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chan_stop(sc, chan);
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chan->flags = CHAN_DESCR_RELINK;
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chan->cur_desc = 0;
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desc = (struct pdma_hwdesc *)xchan->descs;
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for (i = 0; i < conf->block_num; i++) {
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if (conf->direction == XDMA_MEM_TO_DEV) {
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desc[i].dsa = conf->src_addr + (i * conf->block_len);
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desc[i].dta = conf->dst_addr;
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desc[i].drt = data->tx;
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desc[i].dcm = DCM_SAI;
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} else if (conf->direction == XDMA_DEV_TO_MEM) {
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desc[i].dsa = conf->src_addr;
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desc[i].dta = conf->dst_addr + (i * conf->block_len);
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desc[i].drt = data->rx;
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desc[i].dcm = DCM_DAI;
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} else if (conf->direction == XDMA_MEM_TO_MEM) {
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desc[i].dsa = conf->src_addr + (i * conf->block_len);
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desc[i].dta = conf->dst_addr + (i * conf->block_len);
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desc[i].drt = DRT_AUTO;
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desc[i].dcm = DCM_SAI | DCM_DAI;
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}
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if (access_width(conf, &dcm, &max_width) != 0) {
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device_printf(dev,
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"%s: can't configure access width\n", __func__);
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return (-1);
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}
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desc[i].dcm |= dcm | DCM_TIE;
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desc[i].dtc = (conf->block_len / max_width);
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/*
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* PDMA does not provide interrupt after processing each descriptor,
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* but after processing all the chain only.
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* As a workaround we do unlink descriptors here, so our chain will
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* consists of single descriptor only. And then we reconfigure channel
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* on each interrupt again.
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*/
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if ((chan->flags & CHAN_DESCR_RELINK) == 0) {
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if (i != (conf->block_num - 1)) {
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desc[i].dcm |= DCM_LINK;
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reg = ((i + 1) * sizeof(struct pdma_hwdesc));
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desc[i].dtc |= (reg >> 4) << 24;
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}
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}
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}
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return (0);
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}
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static int
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pdma_channel_control(device_t dev, xdma_channel_t *xchan, int cmd)
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{
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struct pdma_channel *chan;
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struct pdma_softc *sc;
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sc = device_get_softc(dev);
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chan = (struct pdma_channel *)xchan->chan;
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switch (cmd) {
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case XDMA_CMD_BEGIN:
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chan_start(sc, chan);
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break;
|
||||
case XDMA_CMD_TERMINATE:
|
||||
chan_stop(sc, chan);
|
||||
break;
|
||||
case XDMA_CMD_PAUSE:
|
||||
/* TODO: implement me */
|
||||
return (-1);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifdef FDT
|
||||
static int
|
||||
pdma_ofw_md_data(device_t dev, pcell_t *cells, int ncells, void **ptr)
|
||||
{
|
||||
struct pdma_fdt_data *data;
|
||||
|
||||
if (ncells != 3) {
|
||||
return (-1);
|
||||
}
|
||||
|
||||
data = malloc(sizeof(struct pdma_fdt_data), M_DEVBUF, (M_WAITOK | M_ZERO));
|
||||
if (data == NULL) {
|
||||
device_printf(dev, "%s: Cant allocate memory\n", __func__);
|
||||
return (-1);
|
||||
}
|
||||
|
||||
data->tx = cells[0];
|
||||
data->rx = cells[1];
|
||||
data->chan = cells[2];
|
||||
|
||||
*ptr = data;
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif
|
||||
|
||||
static device_method_t pdma_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, pdma_probe),
|
||||
DEVMETHOD(device_attach, pdma_attach),
|
||||
DEVMETHOD(device_detach, pdma_detach),
|
||||
|
||||
/* xDMA Interface */
|
||||
DEVMETHOD(xdma_channel_alloc, pdma_channel_alloc),
|
||||
DEVMETHOD(xdma_channel_free, pdma_channel_free),
|
||||
DEVMETHOD(xdma_channel_prep_cyclic, pdma_channel_prep_cyclic),
|
||||
DEVMETHOD(xdma_channel_prep_memcpy, pdma_channel_prep_memcpy),
|
||||
DEVMETHOD(xdma_channel_control, pdma_channel_control),
|
||||
#ifdef FDT
|
||||
DEVMETHOD(xdma_ofw_md_data, pdma_ofw_md_data),
|
||||
#endif
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t pdma_driver = {
|
||||
"pdma",
|
||||
pdma_methods,
|
||||
sizeof(struct pdma_softc),
|
||||
};
|
||||
|
||||
static devclass_t pdma_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(pdma, simplebus, pdma_driver, pdma_devclass, 0, 0,
|
||||
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
|
||||
Loading…
x
Reference in New Issue
Block a user