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Sponsored by:	The FreeBSD Foundation
This commit is contained in:
Glen Barber 2016-02-08 12:16:01 +00:00
commit bbb51924bb
247 changed files with 6271 additions and 7186 deletions
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11
Makefile
View File

@ -21,6 +21,7 @@
# kernel-toolchains - Build kernel-toolchain for all universe targets.
# doxygen - Build API documentation of the kernel, needs doxygen.
# update - Convenient way to update your source tree(s).
# checkworld - Run test suite on installed world.
# check-old - List obsolete directories/files/libraries.
# check-old-dirs - List obsolete directories.
# check-old-files - List obsolete files.
@ -112,8 +113,8 @@
.else
TGTS= all all-man buildenv buildenvvars buildkernel buildworld \
check-old check-old-dirs check-old-files check-old-libs \
checkdpadd clean cleandepend cleandir cleanworld \
check check-old check-old-dirs check-old-files check-old-libs \
checkdpadd checkworld clean cleandepend cleandir cleanworld \
delete-old delete-old-dirs delete-old-files delete-old-libs \
depend distribute distributekernel distributekernel.debug \
distributeworld distrib-dirs distribution doxygen \
@ -121,7 +122,7 @@ TGTS= all all-man buildenv buildenvvars buildkernel buildworld \
installkernel.debug packagekernel packageworld \
reinstallkernel reinstallkernel.debug \
installworld kernel-toolchain libraries lint maninstall \
obj objlink regress rerelease showconfig tags toolchain update \
obj objlink rerelease showconfig tags toolchain update \
_worldtmp _legacy _bootstrap-tools _cleanobj _obj \
_build-tools _cross-tools _includes _libraries _depend \
build32 builddtb distribute32 install32 xdev xdev-build xdev-install \
@ -330,6 +331,10 @@ bmake: .PHONY
${MMAKE} all; \
${MMAKE} install DESTDIR=${MYMAKE:H} BINDIR=
regress: .PHONY
@echo "'make regress' has been renamed 'make check'" | /usr/bin/fmt
@false
tinderbox toolchains kernel-toolchains kernels worlds: upgrade_checks
tinderbox:

23
Makefile.inc1
View File

@ -37,6 +37,7 @@
# The intended user-driven targets are:
# buildworld - rebuild *everything*, including glue to help do upgrades
# installworld- install everything built by "buildworld"
# checkworld - run test suite on installed world
# doxygen - build API documentation of the kernel
# update - convenient way to update your source tree (eg: svn/svnup)
#
@ -1121,16 +1122,14 @@ redistribute: .MAKE .PHONY
DISTRIBUTION=lib32
.endif
distrib-dirs: .MAKE .PHONY
${_+_}cd ${.CURDIR}/etc; ${CROSSENV} PATH=${TMPPATH} ${MAKE} \
${IMAKE_INSTALL} ${IMAKE_MTREE} METALOG=${METALOG} ${.TARGET}
distribution: .MAKE .PHONY
distrib-dirs distribution: .MAKE .PHONY
${_+_}cd ${.CURDIR}/etc; ${CROSSENV} PATH=${TMPPATH} ${MAKE} \
${IMAKE_INSTALL} ${IMAKE_MTREE} METALOG=${METALOG} ${.TARGET}
.if make(distribution)
${_+_}cd ${.CURDIR}; ${CROSSENV} PATH=${TMPPATH} \
${MAKE} -f Makefile.inc1 ${IMAKE_INSTALL} \
METALOG=${METALOG} installconfig
.endif
#
# buildkernel and installkernel
@ -1474,6 +1473,20 @@ create-kernel-packages: _pkgbootstrap
signpackages: _pkgbootstrap
@pkg -o ABI_FILE=${WSTAGEDIR}/bin/sh repo ${REPODIR}/$$(pkg -o ABI_FILE=${WSTAGEDIR}/bin/sh config ABI) ${PKGSIGNKEY}
#
#
# checkworld
#
# Run test suite on installed world.
#
checkworld: .PHONY
@if [ ! -x ${LOCALBASE}/bin/kyua ]; then \
echo "You need kyua (devel/kyua) to run the test suite." | /usr/bin/fmt; \
exit 1; \
fi
${_+_}${LOCALBASE}/bin/kyua test -k ${TESTSBASE}/Kyuafile
#
#
# doxygen
#

55
bin/csh/Makefile
View File

@ -51,41 +51,40 @@ FILESDIR= ${SHAREDIR}/examples/tcsh
FILES= complete.tcsh csh-mode.el
.endif
CATALOGS= et:et_EE.ISO8859-15 \
finnish:fi_FI.ISO8859-1 \
french:fr_FR.ISO8859-1 \
german:de_DE.ISO8859-1 \
greek:el_GR.ISO8859-7 \
italian:it_IT.ISO8859-1 \
ja:ja_JP.eucJP \
russian:ru_RU.KOI8-R \
spanish:es_ES.ISO8859-1 \
ukrainian:uk_UA.KOI8-U
CATALOGS= et:et_EE.UTF-8 \
finnish:fi_FI.UTF-8 \
french:fr_FR.UTF-8 \
german:de_DE.UTF-8 \
greek:el_GR.UTF-8 \
italian:it_IT.UTF-8 \
ja:ja_JP.UTF-8 \
russian:ru_RU.UTF-8 \
spanish:es_ES.UTF-8 \
ukrainian:uk_UA.UTF-8
NLSLINKS_fi_FI.ISO8859-1= fi_FI.ISO8859-15
NLSLINKS_fr_FR.ISO8859-1= fr_BE.ISO8859-1 fr_BE.ISO8859-15 \
fr_CA.ISO8859-1 fr_CA.ISO8859-15 fr_CH.ISO8859-1 \
fr_CH.ISO8859-15 fr_FR.ISO8859-15
NLSLINKS_de_DE.ISO8859-1= de_AT.ISO8859-1 de_AT.ISO8859-15 de_CH.ISO8859-1 \
de_CH.ISO8859-15 de_DE.ISO8859-15
NLSLINKS_it_IT.ISO8859-1= it_CH.ISO8859-1 it_CH.ISO8859-15 it_IT.ISO8859-15
NLSLINKS_es_ES.ISO8859-1= es_ES.ISO8859-15
NLSLINKS_de_DE.UTF-8 = de_AT.UTF-8 de_CH.UTF-8
NLSLINKS_fr_FR.UTF-8 = fr_BE.UTF-8 fr_CA.UTF-8 fr_CH.UTF-8
NLSLINKS_it_IT.UTF-8 = it_CH.UTF-8
.if ${MK_NLS_CATALOGS} == "no" || defined(RESCUE)
CFLAGS+= -DNO_NLS_CATALOGS
.else
CFLAGS+= -DHAVE_ICONV
.if ${MK_ICONV} != "no"
NLSLINKS_de_DE.ISO8859-1 += de_AT.UTF-8 de_CH.UTF-8 de_DE.UTF-8
NLSLINKS_el_GR.ISO8859-7 = el_GR.UTF-8
NLSLINKS_es_ES.ISO8859-1 += es_ES.UTF-8
NLSLINKS_et_EE.ISO8859-15 = et_EE.UTF-8
NLSLINKS_fi_FI.ISO8859-1 += fi_FI.UTF-8
NLSLINKS_fr_FR.ISO8859-1 += fr_BE.UTF-8 fr_CA.UTF-8 fr_CH.UTF-8 fr_FR.UTF-8
NLSLINKS_it_IT.ISO8859-1 += it_CH.UTF-8 it_IT.UTF-8
NLSLINKS_ja_JP.eucJP = ja_JP.SJIS ja_JP.UTF-8
NLSLINKS_ru_RU.KOI8-R = ru_RU.CP1251 ru_RU.CP866 ru_RU.ISO8859-5 ru_RU.UTF-8
NLSLINKS_uk_UA.KOI8-U = uk_UA.ISO8859-5 uk_UA.UTF-8
NLSLINKS_de_DE.UTF-8 += de_AT.ISO8859-1 de_AT.ISO8859-15 de_CH.ISO8859-1 \
de_CH.ISO8859-15 de_DE.ISO8859-1 de_DE.ISO8859-15
NLSLINKS_el_GR.UTF-8 = el_GR.ISO8859-7
NLSLINKS_es_ES.UTF-8 = es_ES.ISO8859-1 es_ES.ISO8859-15
NLSLINKS_et_EE.UTF-8 = et_EE.ISO8859-15
NLSLINKS_fi_FI.UTF-8 = fi_FI.ISO8859-1 fi_FI.ISO8859-15
NLSLINKS_fr_FR.UTF-8 += fr_BE.ISO8859-1 fr_BE.ISO8859-15 \
fr_CA.ISO8859-1 fr_CA.ISO8859-15 fr_CH.ISO8859-1 \
fr_CH.ISO8859-15 fr_FR.ISO8859-1 fr_FR.ISO8859-15
NLSLINKS_it_IT.UTF-8 += it_CH.ISO8859-1 it_CH.ISO8859-15 it_IT.ISO8859-1 \
it_IT.ISO8859-15
NLSLINKS_ja_JP.UTF-8 = ja_JP.SJIS ja_JP.eucJP
NLSLINKS_ru_RU.UTF-8 = ru_RU.CP1251 ru_RU.CP866 ru_RU.ISO8859-5 ru_RU.KOI8-R
NLSLINKS_uk_UA.UTF-8 = uk_UA.ISO8859-5 uk_UA.KOI8-U
.else
# Above links can be installed from ports/shells/tcsh_nls

90
bin/dd/args.c
View File

@ -360,6 +360,46 @@ c_conv(const void *a, const void *b)
((const struct conv *)b)->name));
}
static uintmax_t
postfix_to_mult(const char expr)
{
uintmax_t mult;
mult = 0;
switch (expr) {
case 'B':
case 'b':
mult = 512;
break;
case 'K':
case 'k':
mult = 1 << 10;
break;
case 'M':
case 'm':
mult = 1 << 20;
break;
case 'G':
case 'g':
mult = 1 << 30;
break;
case 'T':
case 't':
mult = (uintmax_t)1 << 40;
break;
case 'P':
case 'p':
mult = (uintmax_t)1 << 50;
break;
case 'W':
case 'w':
mult = sizeof(int);
break;
}
return (mult);
}
/*
* Convert an expression of the following forms to a uintmax_t.
* 1) A positive decimal number.
@ -386,31 +426,7 @@ get_num(const char *val)
if (expr == val) /* No valid digits. */
errx(1, "%s: illegal numeric value", oper);
mult = 0;
switch (*expr) {
case 'B':
case 'b':
mult = 512;
break;
case 'K':
case 'k':
mult = 1 << 10;
break;
case 'M':
case 'm':
mult = 1 << 20;
break;
case 'G':
case 'g':
mult = 1 << 30;
break;
case 'W':
case 'w':
mult = sizeof(int);
break;
default:
;
}
mult = postfix_to_mult(*expr);
if (mult != 0) {
prevnum = num;
@ -460,29 +476,7 @@ get_off_t(const char *val)
if (expr == val) /* No valid digits. */
errx(1, "%s: illegal numeric value", oper);
mult = 0;
switch (*expr) {
case 'B':
case 'b':
mult = 512;
break;
case 'K':
case 'k':
mult = 1 << 10;
break;
case 'M':
case 'm':
mult = 1 << 20;
break;
case 'G':
case 'g':
mult = 1 << 30;
break;
case 'W':
case 'w':
mult = sizeof(int);
break;
}
mult = postfix_to_mult(*expr);
if (mult != 0) {
prevnum = num;

7
bin/dd/dd.1
View File

@ -32,7 +32,7 @@
.\" @(#)dd.1 8.2 (Berkeley) 1/13/94
.\" $FreeBSD$
.\"
.Dd August 28, 2014
.Dd February 4, 2016
.Dt DD 1
.Os
.Sh NAME
@ -332,10 +332,13 @@ If the number ends with a
.Dq Li k ,
.Dq Li m ,
.Dq Li g ,
.Dq Li t ,
.Dq Li p ,
or
.Dq Li w ,
the
number is multiplied by 512, 1024 (1K), 1048576 (1M), 1073741824 (1G)
number is multiplied by 512, 1024 (1K), 1048576 (1M), 1073741824 (1G),
1099511627776 (1T), 1125899906842624 (1P)
or the number of bytes in an integer, respectively.
Two or more numbers may be separated by an
.Dq Li x

12
contrib/bsnmp/snmp_mibII/mibII.c
View File

@ -982,7 +982,7 @@ handle_rtmsg(struct rt_msghdr *rtm)
{
struct sockaddr *addrs[RTAX_MAX];
struct if_msghdr *ifm;
struct ifa_msghdr ifam;
struct ifa_msghdr ifam, *ifamp;
struct ifma_msghdr *ifmam;
#ifdef RTM_IFANNOUNCE
struct if_announcemsghdr *ifan;
@ -1002,8 +1002,9 @@ handle_rtmsg(struct rt_msghdr *rtm)
switch (rtm->rtm_type) {
case RTM_NEWADDR:
memcpy(&ifam, rtm, sizeof(ifam));
mib_extract_addrs(ifam.ifam_addrs, (u_char *)(&ifam + 1), addrs);
ifamp = (struct ifa_msghdr *)rtm;
memcpy(&ifam, ifamp, sizeof(ifam));
mib_extract_addrs(ifam.ifam_addrs, (u_char *)(ifamp + 1), addrs);
if (addrs[RTAX_IFA] == NULL || addrs[RTAX_NETMASK] == NULL)
break;
@ -1029,8 +1030,9 @@ handle_rtmsg(struct rt_msghdr *rtm)
break;
case RTM_DELADDR:
memcpy(&ifam, rtm, sizeof(ifam));
mib_extract_addrs(ifam.ifam_addrs, (u_char *)(&ifam + 1), addrs);
ifamp = (struct ifa_msghdr *)rtm;
memcpy(&ifam, ifamp, sizeof(ifam));
mib_extract_addrs(ifam.ifam_addrs, (u_char *)(ifamp + 1), addrs);
if (addrs[RTAX_IFA] == NULL)
break;

35
contrib/elftoolchain/readelf/readelf.c
View File

@ -1053,8 +1053,9 @@ static struct {
static const char *
r_type(unsigned int mach, unsigned int type)
{
static char s_type[32];
switch(mach) {
case EM_NONE: return "";
case EM_386:
case EM_IAMCU:
switch(type) {
@ -1089,8 +1090,8 @@ r_type(unsigned int mach, unsigned int type)
case 35: return "R_386_TLS_DTPMOD32";
case 36: return "R_386_TLS_DTPOFF32";
case 37: return "R_386_TLS_TPOFF32";
default: return "";
}
break;
case EM_AARCH64:
switch(type) {
case 0: return "R_AARCH64_NONE";
@ -1145,6 +1146,16 @@ r_type(unsigned int mach, unsigned int type)
case 311: return "R_AARCH64_ADR_GOT_PAGE";
case 312: return "R_AARCH64_LD64_GOT_LO12_NC";
case 313: return "R_AARCH64_LD64_GOTPAGE_LO15";
case 560: return "R_AARCH64_TLSDESC_LD_PREL19";
case 561: return "R_AARCH64_TLSDESC_ADR_PREL21";
case 562: return "R_AARCH64_TLSDESC_ADR_PAGE21";
case 563: return "R_AARCH64_TLSDESC_LD64_LO12";
case 564: return "R_AARCH64_TLSDESC_ADD_LO12";
case 565: return "R_AARCH64_TLSDESC_OFF_G1";
case 566: return "R_AARCH64_TLSDESC_OFF_G0_NC";
case 567: return "R_AARCH64_TLSDESC_LDR";
case 568: return "R_AARCH64_TLSDESC_ADD";
case 569: return "R_AARCH64_TLSDESC_CALL";
case 1024: return "R_AARCH64_COPY";
case 1025: return "R_AARCH64_GLOB_DAT";
case 1026: return "R_AARCH64_JUMP_SLOT";
@ -1154,8 +1165,8 @@ r_type(unsigned int mach, unsigned int type)
case 1030: return "R_AARCH64_TLS_TPREL64";
case 1031: return "R_AARCH64_TLSDESC";
case 1032: return "R_AARCH64_IRELATIVE";
default: return "";
}
break;
case EM_ARM:
switch(type) {
case 0: return "R_ARM_NONE";
@ -1206,8 +1217,8 @@ r_type(unsigned int mach, unsigned int type)
case 253: return "R_ARM_RABS32";
case 254: return "R_ARM_RPC24";
case 255: return "R_ARM_RBASE";
default: return "";
}
break;
case EM_IA_64:
switch(type) {
case 0: return "R_IA_64_NONE";
@ -1290,8 +1301,8 @@ r_type(unsigned int mach, unsigned int type)
case 182: return "R_IA_64_DTPREL64MSB";
case 183: return "R_IA_64_DTPREL64LSB";
case 186: return "R_IA_64_LTOFF_DTPREL22";
default: return "";
}
break;
case EM_MIPS:
switch(type) {
case 0: return "R_MIPS_NONE";
@ -1324,9 +1335,8 @@ r_type(unsigned int mach, unsigned int type)
case 48: return "R_MIPS_TLS_TPREL64";
case 49: return "R_MIPS_TLS_TPREL_HI16";
case 50: return "R_MIPS_TLS_TPREL_LO16";
default: return "";
}
break;
case EM_PPC:
switch(type) {
case 0: return "R_PPC_NONE";
@ -1406,8 +1416,8 @@ r_type(unsigned int mach, unsigned int type)
case 114: return "R_PPC_EMB_RELST_HA";
case 115: return "R_PPC_EMB_BIT_FLD";
case 116: return "R_PPC_EMB_RELSDA";
default: return "";
}
break;
case EM_RISCV:
switch(type) {
case 0: return "R_RISCV_NONE";
@ -1453,6 +1463,7 @@ r_type(unsigned int mach, unsigned int type)
case 44: return "R_RISCV_RVC_BRANCH";
case 45: return "R_RISCV_RVC_JUMP";
}
break;
case EM_SPARC:
case EM_SPARCV9:
switch(type) {
@ -1536,8 +1547,8 @@ r_type(unsigned int mach, unsigned int type)
case 77: return "R_SPARC_TLS_DTPOFF64";
case 78: return "R_SPARC_TLS_TPOFF32";
case 79: return "R_SPARC_TLS_TPOFF64";
default: return "";
}
break;
case EM_X86_64:
switch(type) {
case 0: return "R_X86_64_NONE";
@ -1578,10 +1589,12 @@ r_type(unsigned int mach, unsigned int type)
case 35: return "R_X86_64_TLSDESC_CALL";
case 36: return "R_X86_64_TLSDESC";
case 37: return "R_X86_64_IRELATIVE";
default: return "";
}
default: return "";
break;
}
snprintf(s_type, sizeof(s_type), "<unknown: %#x>", type);
return (s_type);
}
static const char *

13
etc/defaults/rc.conf
View File

@ -716,5 +716,18 @@ if [ -z "${source_rc_confs_defined}" ]; then
;;
esac
done
# Re-do process to pick up [possibly] redefined $rc_conf_files
for i in ${rc_conf_files}; do
case ${sourced_files} in
*:$i:*)
;;
*)
sourced_files="${sourced_files}:$i:"
if [ -r $i ]; then
. $i
fi
;;
esac
done
}
fi

10
etc/periodic/daily/800.scrub-zfs
View File

@ -63,6 +63,11 @@ case "$daily_scrub_zfs_enable" in
_last_scrub=$(zpool history ${pool} | \
sed -ne '2s/ .*$//p')
fi
if [ -z "${_last_scrub}" ]; then
echo " skipping scrubbing of pool '${pool}':"
echo " can't get last scrubbing date"
continue
fi
# Now minus last scrub (both in seconds) converted to days.
_scrub_diff=$(expr -e \( $(date +%s) - \
@ -73,11 +78,14 @@ case "$daily_scrub_zfs_enable" in
continue
fi
_status="$(zpool status ${pool} | grep scrub:)"
_status="$(zpool status ${pool} | grep scan:)"
case "${_status}" in
*"scrub in progress"*)
echo " scrubbing of pool '${pool}' already in progress, skipping:"
;;
*"resilver in progress"*)
echo " resilvering of pool '${pool}' is in progress, skipping:"
;;
*"none requested"*)
echo " starting first scrub (since reboot) of pool '${pool}':"
zpool scrub ${pool}

2
etc/rc.d/jail
View File

@ -563,7 +563,7 @@ jail_warn()
# To relieve confusion, show a warning message.
case $_confwarn in
1) warn "Per-jail configuration via jail_* variables " \
"is obsolete. Please consider to migrate to $jail_conf."
"is obsolete. Please consider migrating to $jail_conf."
;;
esac
}

10
lib/libc/sys/connect.2
View File

@ -28,7 +28,7 @@
.\" @(#)connect.2 8.1 (Berkeley) 6/4/93
.\" $FreeBSD$
.\"
.Dd September 29, 2014
.Dd February 4, 2016
.Dt CONNECT 2
.Os
.Sh NAME
@ -58,6 +58,14 @@ another socket.
The other socket is specified by
.Fa name ,
which is an address in the communications space of the socket.
.Fa namelen
indicates the amount of space pointed to by
.Fa name ,
in bytes; the
.Fa sa_len
member of
.Fa name
is ignored.
Each communications space interprets the
.Fa name
argument in its own way.

13
lib/libc/sys/semget.2
View File

@ -25,7 +25,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd September 12, 1995
.Dd February 7, 2016
.Dt SEMGET 2
.Os
.Sh NAME
@ -132,6 +132,17 @@ already exists.
.It Bq Er EINVAL
The number of semaphores requested exceeds the system imposed maximum
per set.
.It Bq Er EINVAL
A semaphore set corresponding to
.Fa key
already exists and contains fewer semaphores than
.Fa nsems .
.It Bq Er EINVAL
A semaphore set corresponding to
.Fa key
does not exist and
.Fa nsems
is 0 or negative.
.It Bq Er ENOSPC
Insufficiently many semaphores are available.
.It Bq Er ENOSPC

61
lib/libedit/editline.3
View File

@ -1,4 +1,4 @@
.\" $NetBSD: editline.3,v 1.84 2014/12/25 13:39:41 wiz Exp $
.\" $NetBSD: editline.3,v 1.85 2015/11/03 21:36:59 christos Exp $
.\"
.\" Copyright (c) 1997-2014 The NetBSD Foundation, Inc.
.\" All rights reserved.
@ -28,7 +28,7 @@
.\"
.\" $FreeBSD$
.\"
.Dd December 25, 2014
.Dd November 3, 2015
.Dt EDITLINE 3
.Os
.Sh NAME
@ -191,7 +191,7 @@ counterparts.
The following functions are available:
.Bl -tag -width 4n
.It Fn el_init
Initialise the line editor, and return a data structure
Initialize the line editor, and return a data structure
to be used by all other line editing functions, or
.Dv NULL
on failure.
@ -521,61 +521,68 @@ are supported, along with actual type of
.Fa result :
.Bl -tag -width 4n
.It Dv EL_PROMPT , Fa "char *(*f)(EditLine *)" , Fa "char *c"
Return a pointer to the function that displays the prompt in
Set
.Fa f .
to a pointer to the function that displays the prompt.
If
.Fa c
is not
.Dv NULL ,
return the start/stop literal prompt character in it.
set it to the start/stop literal prompt character.
.It Dv EL_RPROMPT , Fa "char *(*f)(EditLine *)" , Fa "char *c"
Return a pointer to the function that displays the prompt in
Set
.Fa f .
to a pointer to the function that displays the prompt.
If
.Fa c
is not
.Dv NULL ,
return the start/stop literal prompt character in it.
.It Dv EL_EDITOR , Fa "const char **"
Return the name of the editor, which will be one of
set it to the start/stop literal prompt character.
.It Dv EL_EDITOR , Fa "const char **n"
Set the name of the editor in
.Fa n ,
which will be one of
.Dq emacs
or
.Dq vi .
.It Dv EL_GETTC , Fa "const char *name" , Fa "void *value"
Return non-zero if
If
.Fa name
is a valid
.Xr termcap 5
capability
and set
capability set
.Fa value
to the current value of that capability.
.It Dv EL_SIGNAL , Fa "int *"
Return non-zero if
.It Dv EL_SIGNAL , Fa "int *s"
Set
.Fa s
to non zero if
.Nm
has installed private signal handlers (see
.Fn el_get
above).
.It Dv EL_EDITMODE , Fa "int *"
Return non-zero if editing is enabled.
.It Dv EL_EDITMODE , Fa "int *c"
Set
.Fa c
to non-zero if editing is enabled.
.It Dv EL_GETCFN , Fa "int (**f)(EditLine *, char *)"
Return a pointer to the function that read characters, which is equal to
.Dq Dv EL_BUILTIN_GETCFN
in the case of the default builtin function.
.It Dv EL_CLIENTDATA , Fa "void **data"
Retrieve
Set
.Fa data
previously registered with the corresponding
to the previously registered client data set by an
.Fn el_set
call.
.It Dv EL_UNBUFFERED , Fa "int"
Return non-zero if unbuffered mode is enabled.
.It Dv EL_PREP_TERM , Fa "int"
Sets or clears terminal editing mode.
.It Dv EL_UNBUFFERED , Fa "int *c"
Set
.Fa c
to non-zero if unbuffered mode is enabled.
.It Dv EL_GETFP , Fa "int fd", Fa "FILE **fp"
Return in
Set
.Fa fp
the current
to the current
.Nm editline
file pointer for
.Dq input
@ -593,7 +600,7 @@ or
.Dv 2 .
.El
.It Fn el_source
Initialise
Initialize
.Nm
by reading the contents of
.Fa file .
@ -671,7 +678,7 @@ and freed by
The following functions are available:
.Bl -tag -width 4n
.It Fn history_init
Initialise the history list, and return a data structure
Initialize the history list, and return a data structure
to be used by all other history list functions, or
.Dv NULL
on failure.
@ -810,7 +817,7 @@ and freed by
The following functions are available:
.Bl -tag -width 4n
.It Fn tok_init
Initialise the tokenizer, and return a data structure
Initialize the tokenizer, and return a data structure
to be used by all other tokenizer functions.
.Fa IFS
contains the Input Field Separators, which defaults to

7
lib/libedit/el.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: el.c,v 1.73 2014/06/18 18:12:28 christos Exp $ */
/* $NetBSD: el.c,v 1.74 2015/12/08 12:56:55 christos Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -37,7 +37,7 @@
#if 0
static char sccsid[] = "@(#)el.c 8.2 (Berkeley) 1/3/94";
#else
__RCSID("$NetBSD: el.c,v 1.73 2014/06/18 18:12:28 christos Exp $");
__RCSID("$NetBSD: el.c,v 1.74 2015/12/08 12:56:55 christos Exp $");
#endif
#endif /* not lint && not SCCSID */
#include <sys/cdefs.h>
@ -137,7 +137,8 @@ el_end(EditLine *el)
terminal_end(el);
keymacro_end(el);
map_end(el);
tty_end(el);
if (!(el->el_flags & NO_TTY))
tty_end(el);
ch_end(el);
search_end(el);
hist_end(el);

6
lib/libedit/hist.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: hist.h,v 1.14 2014/05/11 01:05:17 christos Exp $ */
/* $NetBSD: hist.h,v 1.15 2016/01/30 15:05:27 christos Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -47,10 +47,10 @@ typedef int (*hist_fun_t)(void *, TYPE(HistEvent) *, int, ...);
typedef struct el_history_t {
Char *buf; /* The history buffer */
size_t sz; /* Size of history buffer */
size_t sz; /* Size of history buffer */
Char *last; /* The last character */
int eventno; /* Event we are looking for */
void * ref; /* Argument for history fcns */
void *ref; /* Argument for history fcns */
hist_fun_t fun; /* Event access */
TYPE(HistEvent) ev; /* Event cookie */
} el_history_t;

4
lib/libedit/keymacro.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: keymacro.h,v 1.2 2011/07/28 03:44:36 christos Exp $ */
/* $NetBSD: keymacro.h,v 1.3 2016/01/29 19:59:11 christos Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -48,7 +48,7 @@ typedef union keymacro_value_t {
typedef struct keymacro_node_t keymacro_node_t;
typedef struct el_keymacromacro_t {
typedef struct el_keymacro_t {
Char *buf; /* Key print buffer */
keymacro_node_t *map; /* Key map */
keymacro_value_t val; /* Local conversion buffer */

6
lib/libedit/search.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: search.c,v 1.30 2011/10/04 15:27:04 christos Exp $ */
/* $NetBSD: search.c,v 1.31 2016/01/30 04:02:51 christos Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -37,7 +37,7 @@
#if 0
static char sccsid[] = "@(#)search.c 8.1 (Berkeley) 6/4/93";
#else
__RCSID("$NetBSD: search.c,v 1.30 2011/10/04 15:27:04 christos Exp $");
__RCSID("$NetBSD: search.c,v 1.31 2016/01/30 04:02:51 christos Exp $");
#endif
#endif /* not lint && not SCCSID */
#include <sys/cdefs.h>
@ -149,7 +149,7 @@ el_match(const Char *str, const Char *pat)
if (re_comp(ct_encode_string(pat, &conv)) != NULL)
return 0;
else
return re_exec(ct_encode_string(str, &conv) == 1);
return re_exec(ct_encode_string(str, &conv)) == 1;
#endif
}

6
lib/libedit/tokenizer.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tokenizer.c,v 1.21 2011/08/16 16:25:15 christos Exp $ */
/* $NetBSD: tokenizer.c,v 1.22 2016/01/30 04:02:51 christos Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -37,7 +37,7 @@
#if 0
static char sccsid[] = "@(#)tokenizer.c 8.1 (Berkeley) 6/4/93";
#else
__RCSID("$NetBSD: tokenizer.c,v 1.21 2011/08/16 16:25:15 christos Exp $");
__RCSID("$NetBSD: tokenizer.c,v 1.22 2016/01/30 04:02:51 christos Exp $");
#endif
#endif /* not lint && not SCCSID */
#include <sys/cdefs.h>
@ -448,5 +448,5 @@ FUN(tok,str)(TYPE(Tokenizer) *tok, const Char *line, int *argc,
memset(&li, 0, sizeof(li));
li.buffer = line;
li.cursor = li.lastchar = Strchr(line, '\0');
return FUN(tok,line(tok, &li, argc, argv, NULL, NULL));
return FUN(tok,line)(tok, &li, argc, argv, NULL, NULL);
}

7
lib/libedit/tty.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: tty.c,v 1.47 2015/05/14 10:44:15 christos Exp $ */
/* $NetBSD: tty.c,v 1.49 2015/12/08 16:53:27 gson Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -37,7 +37,7 @@
#if 0
static char sccsid[] = "@(#)tty.c 8.1 (Berkeley) 6/4/93";
#else
__RCSID("$NetBSD: tty.c,v 1.47 2015/05/14 10:44:15 christos Exp $");
__RCSID("$NetBSD: tty.c,v 1.49 2015/12/08 16:53:27 gson Exp $");
#endif
#endif /* not lint && not SCCSID */
#include <sys/cdefs.h>
@ -582,6 +582,9 @@ protected void
/*ARGSUSED*/
tty_end(EditLine *el)
{
if (el->el_flags & EDIT_DISABLED)
return;
if (tty_setty(el, TCSAFLUSH, &el->el_tty.t_or) == -1) {
#ifdef DEBUG_TTY
(void) fprintf(el->el_errfile,

1
lib/libmemstat/memstat_uma.c
View File

@ -29,6 +29,7 @@
#include <sys/param.h>
#include <sys/cpuset.h>
#include <sys/sysctl.h>
#include <sys/_task.h>
#include <vm/vm.h>
#include <vm/vm_page.h>

367
share/examples/jails/jib Executable file
View File

@ -0,0 +1,367 @@
#!/bin/sh
#-
# Copyright (c) 2016 Devin Teske
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# $FreeBSD$
#
############################################################ IDENT(1)
#
# $Title: if_bridge(4) management script for vnet jails $
#
############################################################ INFORMATION
#
# Use this tool with jail.conf(5) (or rc.conf(5) ``legacy'' configuration) to
# manage `vnet' interfaces. In jail.conf(5) format:
#
# ### BEGIN EXCERPT ###
#
# xxx {
# host.hostname = "xxx.yyy";
# path = "/vm/xxx";
#
# #
# # NB: Below 2-lines required
# # NB: The number of eNb_xxx interfaces should match the number of
# # arguments given to `jib addm xxx' in exec.prestart value.
# #
# vnet;
# vnet.interface = "e0b_xxx e1b_xxx ...";
#
# exec.clean;
# exec.system_user = "root";
# exec.jail_user = "root";
#
# #
# # NB: Below 2-lines required
# # NB: The number of arguments after `jib addm xxx' should match
# # the number of eNb_xxx arguments in vnet.interface value.
# #
# exec.prestart += "jib addm xxx em0 em1 ...";
# exec.poststop += "jib destroy xxx";
#
# # Standard recipe
# exec.start += "/bin/sh /etc/rc";
# exec.stop = "/bin/sh /etc/rc.shutdown";
# exec.consolelog = "/var/log/jail_xxx_console.log";
# mount.devfs;
#
# # Optional (default off)
# #allow.mount;
# #allow.set_hostname = 1;
# #allow.sysvipc = 1;
# #devfs_ruleset = "11"; # rule to unhide bpf for DHCP
# }
#
# ### END EXCERPT ###
#
# In rc.conf(5) ``legacy'' format (used when /etc/jail.conf does not exist):
#
# ### BEGIN EXCERPT ###
#
# jail_enable="YES"
# jail_list="xxx"
#
# #
# # Global presets for all jails
# #
# jail_devfs_enable="YES" # mount devfs
#
# #
# # Global options (default off)
# #
# #jail_mount_enable="YES" # mount /etc/fstab.{name}
# #jail_set_hostname_allow="YES" # Allow hostname to change
# #jail_sysvipc_allow="YES" # Allow SysV Interprocess Comm.
#
# # xxx
# jail_xxx_hostname="xxx.shxd.cx" # hostname
# jail_xxx_rootdir="/vm/xxx" # root directory
# jail_xxx_vnet_interfaces="e0b_xxx e1bxxx ..." # vnet interface(s)
# jail_xxx_exec_prestart0="jib addm xxx em0 em1 ..." # bridge interface(s)
# jail_xxx_exec_poststop0="jib destroy xxx" # destroy interface(s)
# #jail_xxx_mount_enable="YES" # mount /etc/fstab.xxx
# #jail_xxx_devfs_ruleset="11" # rule to unhide bpf for DHCP
#
# ### END EXCERPT ###
#
# Note that the legacy rc.conf(5) format is converted to
# /var/run/jail.{name}.conf by /etc/rc.d/jail if jail.conf(5) is missing.
#
# ASIDE: dhclient(8) inside a vnet jail...
#
# To allow dhclient(8) to work inside a vnet jail, make sure the following
# appears in /etc/devfs.rules (which should be created if it doesn't exist):
#
# [devfsrules_jail=11]
# add include $devfsrules_hide_all
# add include $devfsrules_unhide_basic
# add include $devfsrules_unhide_login
# add include $devfsrules_unhide_bpf
#
# And set ether devfs.ruleset="11" (jail.conf(5)) or
# jail_{name}_devfs_ruleset="11" (rc.conf(5)).
#
# NB: While this tool can't create every type of desirable topology, it should
# handle most setups, minus some which considered exotic or purpose-built.
#
############################################################ GLOBALS
pgm="${0##*/}" # Program basename
#
# Global exit status
#
SUCCESS=0
FAILURE=1
############################################################ FUNCTIONS
usage()
{
local action usage descr
exec >&2
echo "Usage: $pgm action [arguments]"
echo "Actions:"
for action in \
addm \
show \
show1 \
destroy \
; do
eval usage=\"\$jib_${action}_usage\"
[ "$usage" ] || continue
eval descr=\"\$jib_${action}_descr\"
printf "\t%s\n\t\t%s\n" "$usage" "$descr"
done
exit $FAILURE
}
action_usage()
{
local usage action="$1"
eval usage=\"\$jib_${action}_usage\"
echo "Usage: $pgm $usage" >&2
exit $FAILURE
}
mustberoot_to_continue()
{
if [ "$( id -u )" -ne 0 ]; then
echo "Must run as root!" >&2
exit $FAILURE
fi
}
jib_addm_usage="addm [-b BRIDGE_NAME] NAME interface0 [interface1 ...]"
jib_addm_descr="Creates e0b_NAME [e1b_NAME ...]"
jib_addm()
{
local OPTIND=1 OPTARG flag bridge=bridge
while getopts b: flag; do
case "$flag" in
b) bridge="${OPTARG:-bridge}" ;;
*) action_usage addm # NOTREACHED
esac
done
shift $(( $OPTIND - 1 ))
local name="$1"
[ "${name:-x}" = "${name#*[!0-9a-zA-Z_]}" -a $# -gt 1 ] ||
action_usage addm # NOTREACHED
shift 1 # name
mustberoot_to_continue
local iface iface_devid eiface_devid_a eiface_devid_b
local new num quad i=0
for iface in $*; do
# 1. Make sure the interface doesn't exist already
ifconfig "e${i}a_$name" > /dev/null 2>&1 && continue
# 2. Bring the interface up
ifconfig $iface up || return
# 3. Make sure the interface has been bridged
if ! ifconfig "$iface$bridge" > /dev/null 2>&1; then
new=$( ifconfig bridge create ) || return
ifconfig $new addm $iface || return
ifconfig $new name "$iface$bridge" || return
fi
# 4. Create a new interface to the bridge
new=$( ifconfig epair create ) || return
ifconfig "$iface$bridge" addm $new || return
# 5. Rename the new interface
ifconfig $new name "e${i}a_$name" || return
ifconfig ${new%a}b name "e${i}b_$name" || return
#
# 6. Set the MAC address of the new interface using a sensible
# algorithm to prevent conflicts on the network.
#
# The formula I'm using is ``SP:SS:SI:II:II:II'' where:
# + S denotes 16 bits of sum(1) data, split because P (below).
# + P denotes the special nibble whose value, if one of
# 2, 6, A, or E (but usually 2) denotes a privately
# administered MAC address (while remaining routable).
# + I denotes bits that are inherited from parent interface.
#
# The S bits are a CRC-16 checksum of NAME, allowing the jail
# to change the epair(4) generation order without affecting the
# MAC address. Meanwhile, if the jail NAME changes (e.g., it
# was duplicated and given a new name with no other changes),
# the underlying network interface changes, or the jail is
# moved to another host, the MAC address will be recalculated
# to a new, similarly unique value preventing conflict.
#
iface_devid=$( ifconfig $iface ether | awk '/ether/,$0=$2' )
eiface_devid_a=${iface_devid#??:??:?}
eiface_devid_b=${iface_devid#??:??:?}
num=$( set -- `echo -n $name | sum` && echo $1 )
quad=$(( $num & 15 ))
case "$quad" in
10) quad=a ;; 11) quad=b ;; 12) quad=c ;;
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
eiface_devid_a=:$quad$eiface_devid_a
eiface_devid_b=:$quad$eiface_devid_b
num=$(( $num >> 4 ))
quad=$(( $num & 15 ))
case "$quad" in
10) quad=a ;; 11) quad=b ;; 12) quad=c ;;
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
eiface_devid_a=$quad$eiface_devid_a
eiface_devid_b=$quad$eiface_devid_b
num=$(( $num >> 4 ))
quad=$(( $num & 15 ))
case "$quad" in
10) quad=a ;; 11) quad=b ;; 12) quad=c ;;
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
eiface_devid_a=2:$quad$eiface_devid_a
eiface_devid_b=6:$quad$eiface_devid_b
num=$(( $num >> 4 ))
quad=$(( $num & 15 ))
case "$quad" in
10) quad=a ;; 11) quad=b ;; 12) quad=c ;;
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
eiface_devid_a=$quad$eiface_devid_a
eiface_devid_b=$quad$eiface_devid_b
ifconfig "e${i}a_$name" ether $eiface_devid_a > /dev/null 2>&1
ifconfig "e${i}b_$name" ether $eiface_devid_b > /dev/null 2>&1
i=$(( $i + 1 )) # on to next ng{i}_name
done # for iface
}
jib_show_usage="show"
jib_show_descr="List possible NAME values for \`show NAME'"
jib_show1_usage="show NAME"
jib_show1_descr="Lists ng0_NAME [ng1_NAME ...]"
jib_show2_usage="show [NAME]"
jib_show()
{
local OPTIND=1 OPTARG flag
while getopts "" flag; do
case "$flag" in
*) action_usage show2 # NOTREACHED
esac
done
shift $(( $OPTIND - 1 ))
if [ $# -eq 0 ]; then
ifconfig | awk '
/^[^:[:space:]]+:/ {
iface = $1
sub(/:.*/, "", iface)
next
}
$1 == "groups:" {
for (n = split($0, group); n > 1; n--) {
if (group[n] != "bridge") continue
print iface
next
}
}' |
xargs -rn1 ifconfig |
awk '$1 == "member:" &&
sub(/^e[[:digit:]]+a_/, "", $2), $0 = $2' |
sort -u
return
fi
ifconfig | awk -v name="$1" '
match($0, /^e[[:digit:]]+a_/) && sub(/:.*/, "") &&
substr($1, RSTART + RLENGTH) == name
' | sort
}
jib_destroy_usage="destroy NAME"
jib_destroy_descr="Destroy e0b_NAME [e1b_NAME ...]"
jib_destroy()
{
local OPTIND=1 OPTARG flag
while getopts "" flag; do
case "$flag" in
*) action_usage destroy # NOTREACHED
esac
done
shift $(( $OPTIND -1 ))
local name="$1"
[ "${name:-x}" = "${name#*[!0-9a-zA-Z_]}" -a $# -eq 1 ] ||
action_usage destroy # NOTREACHED
mustberoot_to_continue
jib_show "$name" | xargs -rn1 -I eiface ifconfig eiface destroy
}
############################################################ MAIN
#
# Command-line arguments
#
action="$1"
[ "$action" ] || usage # NOTREACHED
#
# Validate action argument
#
if [ "$BASH_VERSION" ]; then
type="$( type -t "jib_$action" )" || usage # NOTREACHED
else
type="$( type "jib_$action" 2> /dev/null )" || usage # NOTREACHED
fi
case "$type" in
*function)
shift 1 # action
eval "jib_$action" \"\$@\"
;;
*) usage # NOTREACHED
esac
################################################################################
# END
################################################################################

416
share/examples/jails/jng Executable file
View File

@ -0,0 +1,416 @@
#!/bin/sh
#-
# Copyright (c) 2016 Devin Teske
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#
# $FreeBSD$
#
############################################################ IDENT(1)
#
# $Title: netgraph(4) management script for vnet jails $
#
############################################################ INFORMATION
#
# Use this tool with jail.conf(5) (or rc.conf(5) ``legacy'' configuration) to
# manage `vnet' interfaces. In jail.conf(5) format:
#
# ### BEGIN EXCERPT ###
#
# xxx {
# host.hostname = "xxx.yyy";
# path = "/vm/xxx";
#
# #
# # NB: Below 2-lines required
# # NB: The number of ngN_xxx interfaces should match the number of
# # arguments given to `jng bridge xxx' in exec.prestart value.
# #
# vnet;
# vnet.interface = "ng0_xxx ng1_xxx ...";
#
# exec.clean;
# exec.system_user = "root";
# exec.jail_user = "root";
#
# #
# # NB: Below 2-lines required
# # NB: The number of arguments after `jng bridge xxx' should match
# # the number of ngN_xxx arguments in vnet.interface value.
# #
# exec.prestart += "jng bridge xxx em0 em1 ...";
# exec.poststop += "jng shutdown xxx";
#
# # Standard recipe
# exec.start += "/bin/sh /etc/rc";
# exec.stop = "/bin/sh /etc/rc.shutdown";
# exec.consolelog = "/var/log/jail_xxx_console.log";
# mount.devfs;
#
# # Optional (default off)
# #allow.mount;
# #allow.set_hostname = 1;
# #allow.sysvipc = 1;
# #devfs_ruleset = "11"; # rule to unhide bpf for DHCP
# }
#
# ### END EXCERPT ###
#
# In rc.conf(5) ``legacy'' format (used when /etc/jail.conf does not exist):
#
# ### BEGIN EXCERPT ###
#
# jail_enable="YES"
# jail_list="xxx"
#
# #
# # Global presets for all jails
# #
# jail_devfs_enable="YES" # mount devfs
#
# #
# # Global options (default off)
# #
# #jail_mount_enable="YES" # mount /etc/fstab.{name}
# #jail_set_hostname_allow="YES" # Allow hostname to change
# #jail_sysvipc_allow="YES" # Allow SysV Interprocess Comm.
#
# # xxx
# jail_xxx_hostname="xxx.shxd.cx" # hostname
# jail_xxx_rootdir="/vm/xxx" # root directory
# jail_xxx_vnet_interfaces="ng0_xxx ng1xxx ..." # vnet interface(s)
# jail_xxx_exec_prestart0="jng bridge xxx em0 em1 ..." # bridge interface(s)
# jail_xxx_exec_poststop0="jng shutdown xxx" # destroy interface(s)
# #jail_xxx_mount_enable="YES" # mount /etc/fstab.xxx
# #jail_xxx_devfs_ruleset="11" # rule to unhide bpf for DHCP
#
# ### END EXCERPT ###
#
# Note that the legacy rc.conf(5) format is converted to
# /var/run/jail.{name}.conf by /etc/rc.d/jail if jail.conf(5) is missing.
#
# ASIDE: dhclient(8) inside a vnet jail...
#
# To allow dhclient(8) to work inside a vnet jail, make sure the following
# appears in /etc/devfs.rules (which should be created if it doesn't exist):
#
# [devfsrules_jail=11]
# add include $devfsrules_hide_all
# add include $devfsrules_unhide_basic
# add include $devfsrules_unhide_login
# add include $devfsrules_unhide_bpf
#
# And set ether devfs.ruleset="11" (jail.conf(5)) or
# jail_{name}_devfs_ruleset="11" (rc.conf(5)).
#
# NB: While this tool can't create every type of desirable topology, it should
# handle most setups, minus some which considered exotic or purpose-built.
#
############################################################ GLOBALS
pgm="${0##*/}" # Program basename
#
# Global exit status
#
SUCCESS=0
FAILURE=1
############################################################ FUNCTIONS
usage()
{
local action usage descr
exec >&2
echo "Usage: $pgm action [arguments]"
echo "Actions:"
for action in \
bridge \
graph \
show \
show1 \
shutdown \
; do
eval usage=\"\$jng_${action}_usage\"
[ "$usage" ] || continue
eval descr=\"\$jng_${action}_descr\"
printf "\t%s\n\t\t%s\n" "$usage" "$descr"
done
exit $FAILURE
}
action_usage()
{
local usage action="$1"
eval usage=\"\$jng_${action}_usage\"
echo "Usage: $pgm $usage" >&2
exit $FAILURE
}
mustberoot_to_continue()
{
if [ "$( id -u )" -ne 0 ]; then
echo "Must run as root!" >&2
exit $FAILURE
fi
}
jng_bridge_usage="bridge [-b BRIDGE_NAME] NAME interface0 [interface1 ...]"
jng_bridge_descr="Create ng0_NAME [ng1_NAME ...]"
jng_bridge()
{
local OPTIND=1 OPTARG flag bridge=bridge
while getopts b: flag; do
case "$flag" in
b) bridge="$OPTARG"
[ "$bridge" ] || action_usage bridge ;; # NOTREACHED
*) action_usage bridge # NOTREACHED
esac
done
shift $(( $OPTIND - 1 ))
local name="$1"
[ "${name:-x}" = "${name#*[!0-9a-zA-Z_]}" -a $# -gt 1 ] ||
action_usage bridge # NOTREACHED
shift 1 # name
mustberoot_to_continue
local iface iface_devid eiface eiface_devid
local new num quad i=0
for iface in $*; do
# 0. Make sure the interface doesn't exist already
eiface=ng${i}_$name
ngctl msg "$eiface:" getifname > /dev/null 2>&1 && continue
# 1. Bring the interface up
ifconfig $iface up || return
# 2. Set promiscuous mode and don't overwrite src addr
ngctl msg $iface: setpromisc 1 || return
ngctl msg $iface: setautosrc 0 || return
# 3. Make sure the interface has been bridged
if ! ngctl info ${iface}bridge: > /dev/null 2>&1; then
ngctl mkpeer $iface: bridge lower link0 || return
ngctl connect $iface: $iface:lower upper link1 ||
return
ngctl name $iface:lower ${iface}bridge || return
fi
# 3.5. Optionally create a secondary bridge
if [ "$bridge" != "bridge" ] &&
! ngctl info "$iface$bridge:" > /dev/null 2>&1
then
num=2
while ngctl msg ${iface}bridge: getstats $num \
> /dev/null 2>&1
do
num=$(( $num + 1 ))
done
ngctl mkpeer $iface:lower bridge link$num link1 ||
return
ngctl name ${iface}bridge:link$num "$iface$bridge" ||
return
fi
# 4. Create a new interface to the bridge
num=2
while ngctl msg "$iface$bridge:" getstats $num > /dev/null 2>&1
do
num=$(( $num + 1 ))
done
ngctl mkpeer "$iface$bridge:" eiface link$num ether || return
# 5. Rename the new interface
while [ ${#eiface} -gt 15 ]; do # OS limitation
eiface=${eiface%?}
done
new=$( set -- `ngctl show -n "$iface$bridge:link$num"` &&
echo $2 ) || return
ngctl name "$iface$bridge:link$num" $eiface || return
ifconfig $new name $eiface || return
#
# 6. Set the MAC address of the new interface using a sensible
# algorithm to prevent conflicts on the network.
#
# The formula I'm using is ``SP:SS:SI:II:II:II'' where:
# + S denotes 16 bits of sum(1) data, split because P (below).
# + P denotes the special nibble whose value, if one of
# 2, 6, A, or E (but usually 2) denotes a privately
# administered MAC address (while remaining routable).
# + I denotes bits that are inherited from parent interface.
#
# The S bits are a CRC-16 checksum of NAME, allowing the jail
# to change link numbers in ng_bridge(4) without affecting the
# MAC address. Meanwhile, if the jail NAME changes (e.g., it
# was duplicated and given a new name with no other changes),
# the underlying network interface changes, or the jail is
# moved to another host, the MAC address will be recalculated
# to a new, similarly unique value preventing conflict.
#
iface_devid=$( ifconfig $iface ether | awk '/ether/,$0=$2' )
eiface_devid=${iface_devid#??:??:?}
num=$( set -- `echo -n $name | sum` && echo $1 )
quad=$(( $num & 15 ))
case "$quad" in
10) quad=a ;; 11) quad=b ;; 12) quad=c ;;
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
eiface_devid=:$quad$eiface_devid
num=$(( $num >> 4 ))
quad=$(( $num & 15 ))
case "$quad" in
10) quad=a ;; 11) quad=b ;; 12) quad=c ;;
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
eiface_devid=$quad$eiface_devid
num=$(( $num >> 4 ))
quad=$(( $num & 15 ))
case "$quad" in
10) quad=a ;; 11) quad=b ;; 12) quad=c ;;
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
eiface_devid=2:$quad$eiface_devid
num=$(( $num >> 4 ))
quad=$(( $num & 15 ))
case "$quad" in
10) quad=a ;; 11) quad=b ;; 12) quad=c ;;
13) quad=d ;; 14) quad=e ;; 15) quad=f ;;
esac
eiface_devid=$quad$eiface_devid
ifconfig $eiface ether $eiface_devid > /dev/null 2>&1
i=$(( $i + 1 )) # on to next ng{i}_name
done # for iface
}
jng_graph_usage="graph [-f] [-T type] [-o output]"
jng_graph_descr="Generate network graph (default output is \`jng.svg')"
jng_graph()
{
local OPTIND=1 OPTARG flag
local output=jng.svg output_type= force=
while getopts fo:T: flag; do
case "$flag" in
f) force=1 ;;
o) output="$OPTARG" ;;
T) output_type="$OPTARG" ;;
*) action_usage graph # NOTREACHED
esac
done
shift $(( $OPTIND - 1 ))
[ $# -eq 0 -a "$output" ] || action_usage graph # NOTREACHED
mustberoot_to_continue
if [ -e "$output" -a ! "$force" ]; then
echo "$output: Already exists (use \`-f' to overwrite)" >&2
return $FAILURE
fi
if [ ! "$output_type" ]; then
local valid suffix
valid=$( dot -Txxx 2>&1 )
for suffix in ${valid##*:}; do
[ "$output" != "${output%.$suffix}" ] || continue
output_type=$suffix
break
done
fi
ngctl dot | dot ${output_type:+-T "$output_type"} -o "$output"
}
jng_show_usage="show"
jng_show_descr="List possible NAME values for \`show NAME'"
jng_show1_usage="show NAME"
jng_show1_descr="Lists ng0_NAME [ng1_NAME ...]"
jng_show2_usage="show [NAME]"
jng_show()
{
local OPTIND=1 OPTARG flag
while getopts "" flag; do
case "$flag" in
*) action_usage show2 # NOTREACHED
esac
done
shift $(( $OPTIND - 1 ))
mustberoot_to_continue
if [ $# -eq 0 ]; then
ngctl ls | awk '$4=="bridge",$0=$2' |
xargs -rn1 -Ibridge ngctl show bridge: |
awk 'sub(/^ng[[:digit:]]+_/, "", $2), $0 = $2' |
sort -u
return
fi
ngctl ls | awk -v name="$1" '
match($2, /^ng[[:digit:]]+_/) &&
substr($2, RSTART + RLENGTH) == name &&
$4 == "eiface", $0 = $2
' | sort
}
jng_shutdown_usage="shutdown NAME"
jng_shutdown_descr="Shutdown ng0_NAME [ng1_NAME ...]"
jng_shutdown()
{
local OPTIND=1 OPTARG flag
while getopts "" flag; do
case "$flag" in
*) action_usage shutdown # NOTREACHED
esac
done
shift $(( $OPTIND -1 ))
local name="$1"
[ "${name:-x}" = "${name#*[!0-9a-zA-Z_]}" -a $# -eq 1 ] ||
action_usage shutdown # NOTREACHED
mustberoot_to_continue
jng_show "$name" | xargs -rn1 -I eiface ngctl shutdown eiface:
}
############################################################ MAIN
#
# Command-line arguments
#
action="$1"
[ "$action" ] || usage # NOTREACHED
#
# Validate action argument
#
if [ "$BASH_VERSION" ]; then
type="$( type -t "jng_$action" )" || usage # NOTREACHED
else
type="$( type "jng_$action" 2> /dev/null )" || usage # NOTREACHED
fi
case "$type" in
*function)
shift 1 # action
eval "jng_$action" \"\$@\"
;;
*) usage # NOTREACHED
esac
################################################################################
# END
################################################################################

8
share/i18n/esdb/MISC/MISC.alias
View File

@ -29,10 +29,10 @@ JISX0208:1990 x0208
JOHAB cp1361
SHIFT_JIS csshiftjis
SHIFT_JIS ms_kanji
SHIFT_JIS sjis
Shift_JIS csshiftjis
Shift_JIS ms_kanji
Shift_JIS sjis
SHIFT_JIS-2004 shift_jisx0213
Shift_JIS-2004 shift_jisx0213
TDS565 iso-ir-230

4
share/man/man4/bridge.4
View File

@ -425,8 +425,8 @@ cloned_interfaces="bridge0"
ifconfig_bridge0="addm wlan0 addm fxp0 up"
.Ed
.Pp
For the bridge to forward packets all member interfaces and the bridge need
to be up.
For the bridge to forward packets,
all member interfaces and the bridge need to be up.
The above example would also require:
.Bd -literal -offset indent
create_args_wlan0="wlanmode hostap"

26
share/man/man4/inet.4
View File

@ -28,7 +28,7 @@
.\" From: @(#)inet.4 8.1 (Berkeley) 6/5/93
.\" $FreeBSD$
.\"
.Dd April 7, 2015
.Dd Feb 4, 2016
.Dt INET 4
.Os
.Sh NAME
@ -164,33 +164,11 @@ MIB.
In addition to the variables supported by the transport protocols
(for which the respective manual pages may be consulted),
the following general variables are defined:
.Bl -tag -width IPCTL_FASTFORWARDING
.Bl -tag -width IPCTL_ACCEPTSOURCEROUTE
.It Dv IPCTL_FORWARDING
.Pq ip.forwarding
Boolean: enable/disable forwarding of IP packets.
Defaults to off.
.It Dv IPCTL_FASTFORWARDING
.Pq ip.fastforwarding
Boolean: enable/disable the use of
.Tn fast IP forwarding
code.
Defaults to off.
When
.Tn fast IP forwarding
is enabled, IP packets are forwarded directly to the appropriate network
interface with direct processing to completion, which greatly improves
the throughput.
All packets for local IP addresses, non-unicast, or with IP options are
handled by the normal IP input processing path.
All features of the normal (slow) IP forwarding path are supported
including firewall (through
.Xr pfil 9
hooks) checking, except
.Xr ipsec 4
tunnel brokering.
The
.Tn IP fastforwarding
path does not generate ICMP redirect or source quench messages.
.It Dv IPCTL_SENDREDIRECTS
.Pq ip.redirect
Boolean: enable/disable sending of ICMP redirects in response to

13
share/man/man7/build.7
View File

@ -107,6 +107,16 @@ section below, and by the variables documented in
The following list provides the names and actions for the targets
supported by the build system:
.Bl -tag -width ".Cm cleandepend"
.It Cm check
Run tests for a given subdirectory.
The default directory used is
.Pa ${.OBJDIR} ,
but the check directory can be changed with
.Pa ${CHECKDIR} .
.It Cm checkworld
Run the
.Fx
test suite on installed world.
.It Cm clean
Remove any files created during the build process.
.It Cm cleandepend
@ -653,6 +663,7 @@ make TARGET=sparc64 DESTDIR=/clients/sparc64 installworld
.Xr mergemaster 8 ,
.Xr portsnap 8 ,
.Xr reboot 8 ,
.Xr shutdown 8
.Xr shutdown 8 ,
.Xr tests 7
.Sh AUTHORS
.An Mike W. Meyer Aq Mt mwm@mired.org

21
share/mk/bsd.README
View File

@ -448,6 +448,17 @@ It has seven targets:
all:
build the test programs.
check:
runs the test programs from CHECKDIR with kyua test.
The beforecheck and aftercheck targets will be invoked, if
defined, to execute commands before and after the realcheck
target has been executed, respectively.
The devel/kyua package must be installed before invoking this
target.
See CHECKDIR for more details.
clean:
remove the test programs and any object files.
cleandir:
@ -466,12 +477,6 @@ It has seven targets:
run lint on the source files.
tags:
create a tags file for the source files.
test:
runs the test programs from the object directory; if the
Makefile does not itself define the target test, the
targets beforetest and aftertest may also be used to
cause actions immediately before and after the test
target is executed.
It sets/uses the following variables, among many others:
@ -485,6 +490,10 @@ TESTSDIR Path to the installed tests. Must be a subdirectory of
${TESTSBASE}/${RELDIR:H} , e.g. /usr/tests/bin/ls when
included from bin/ls/tests .
CHECKDIR The directory that 'make check' executes tests from.
The value of CHECKDIR defaults to .OBJDIR.
KYUAFILE If 'auto' (the default), generate a Kyuafile out of the
test programs defined in the Makefile. If 'yes', then a
manually-crafted Kyuafile must be supplied with the

4
share/mk/bsd.incs.mk
View File

@ -87,8 +87,8 @@ _${group}INS: ${_${group}INCS}
.if defined(INCSLINKS) && !empty(INCSLINKS)
installincludes:
.for s t in ${INCSLINKS}
@${ECHO} "$t -> $s" ; \
${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},development} $s ${DESTDIR}$t
@${ECHO} "${DESTDIR}${t} -> ${s}" ; \
${INSTALL_SYMLINK} ${TAG_ARGS:D${TAG_ARGS},development} ${s} ${DESTDIR}${t}
.endfor
.endif
.endif # !target(installincludes)

8
share/mk/bsd.links.mk
View File

@ -15,10 +15,10 @@ afterinstall: _installlinks
.ORDER: realinstall _installlinks
_installlinks:
.for s t in ${LINKS}
@${ECHO} "$t -> $s" ;\
${INSTALL_LINK} ${TAG_ARGS} ${DESTDIR}$s ${DESTDIR}$t
@${ECHO} "${t} -> ${s}" ;\
${INSTALL_LINK} ${TAG_ARGS} ${DESTDIR}${s} ${DESTDIR}${t}
.endfor
.for s t in ${SYMLINKS}
@${ECHO} "$t -> $s" ;\
${INSTALL_SYMLINK} ${TAG_ARGS} $s ${DESTDIR}/$t
@${ECHO} "${t} -> ${s}" ;\
${INSTALL_SYMLINK} ${TAG_ARGS} ${s} ${DESTDIR}/${t}
.endfor

32
share/mk/bsd.man.mk
View File

@ -172,6 +172,17 @@ ${__target}: ${__page}
.endif # ${MK_MANCOMPRESS} == "no"
.if !defined(NO_MLINKS) && defined(MLINKS) && !empty(MLINKS)
.for _oname _osect _dname _dsect in ${MLINKS:C/\.([^.]*)$/.\1 \1/}
_MANLINKS+= ${MANDIR}${_osect}${MANSUBDIR}/${_oname} \
${MANDIR}${_dsect}${MANSUBDIR}/${_dname}
.if defined(MANBUILDCAT) && !empty(MANBUILDCAT)
_MANLINKS+= ${CATDIR}${_osect}${MANSUBDIR}/${_oname} \
${CATDIR}${_dsect}${MANSUBDIR}/${_dname}
.endif
.endfor
.endif
maninstall: _maninstall
_maninstall:
.if defined(MAN) && !empty(MAN)
@ -216,25 +227,10 @@ _maninstall: ${MAN}
.endfor
.endif # ${MK_MANCOMPRESS} == "no"
.endif
.if !defined(NO_MLINKS) && defined(MLINKS) && !empty(MLINKS)
.for _oname _osect _dname _dsect in ${MLINKS:C/\.([^.]*)$/.\1 \1/}
@l=${DESTDIR}${MANDIR}${_osect}${MANSUBDIR}/${_oname}; \
t=${DESTDIR}${MANDIR}${_dsect}${MANSUBDIR}/${_dname}; \
${ECHO} $${t}${ZEXT} -\> $${l}${ZEXT}; \
rm -f $${t} $${t}${MCOMPRESS_EXT}; \
${INSTALL_LINK} ${TAG_ARGS} $${l}${ZEXT} $${t}${ZEXT}
.for l t in ${_MANLINKS}
rm -f ${DESTDIR}${t} ${DESTDIR}${t}${MCOMPRESS_EXT}; \
${INSTALL_LINK} ${TAG_ARGS} ${DESTDIR}${l}${ZEXT} ${DESTDIR}${t}${ZEXT}
.endfor
.if defined(MANBUILDCAT) && !empty(MANBUILDCAT)
.for _oname _osect _dname _dsect in ${MLINKS:C/\.([^.]*)$/.\1 \1/}
@l=${DESTDIR}${MANDIR}${_osect}${MANSUBDIR}/${_oname}; \
t=${DESTDIR}${MANDIR}${_dsect}${MANSUBDIR}/${_dname}; \
${ECHO} $${t}${ZEXT} -\> $${l}${ZEXT}; \
rm -f $${t} $${t}${MCOMPRESS_EXT}; \
${INSTALL_LINK} ${TAG_ARGS} $${l}${ZEXT} $${t}${ZEXT}
.endfor
.endif
.endif
manlint:
.if defined(MAN) && !empty(MAN)

3
share/mk/bsd.nls.mk
View File

@ -73,6 +73,9 @@ SYMLINKS+= ${NLSSYMLINKS}
.for file in ${NLS}
NLSNAME_${file:T}= ${file:T:R}/${NLSNAME}.cat
.if defined(NLSLINKS_${file:R}) && !empty(NLSLINKS_${file:R})
.if !empty(NLSLINKS_${file:R}:M${file:R})
.error NLSLINKS_${file:R} contains itself: ${file:R}
.endif
NLSLINKS+= ${file:R}
.endif
.for dst in ${NLSLINKS_${file:R}}

4
share/mk/bsd.subdir.mk
View File

@ -43,11 +43,11 @@ SUBDIR_TARGETS+= \
checkdpadd clean cleandepend cleandir cleanilinks \
cleanobj depend distribute files includes installconfig \
installfiles installincludes realinstall lint maninstall \
manlint obj objlink regress tags \
manlint obj objlink tags \
# Described above.
STANDALONE_SUBDIR_TARGETS+= \
obj checkdpadd clean cleandepend cleandir \
obj check checkdpadd clean cleandepend cleandir \
cleanilinks cleanobj installconfig \
.include <bsd.init.mk>

6
share/mk/bsd.sys.mk
View File

@ -178,11 +178,11 @@ CXXFLAGS+= ${CXXFLAGS.${COMPILER_TYPE}}
# or expect to ever be up-to-date.
PHONY_NOTMAIN = afterdepend afterinstall all beforedepend beforeinstall \
beforelinking build build-tools buildconfig buildfiles \
buildincludes checkdpadd clean cleandepend cleandir cleanobj \
configure depend dependall distclean distribute exe \
buildincludes check checkdpadd clean cleandepend cleandir \
cleanobj configure depend dependall distclean distribute exe \
files html includes install installconfig installfiles \
installincludes lint obj objlink objs objwarn realall \
realdepend realinstall regress subdir-all subdir-depend \
realdepend realinstall subdir-all subdir-depend \
subdir-install tags whereobj
# we don't want ${PROG} to be PHONY

19
share/mk/bsd.test.mk
View File

@ -61,11 +61,15 @@ _TESTS=
.include <plain.test.mk>
.include <tap.test.mk>
# kyua automatically descends directories; only run make check on the
# top-level directory
.if !make(check)
.for ts in ${TESTS_SUBDIRS}
.if empty(SUBDIR:M${ts})
SUBDIR+= ${ts}
.endif
.endfor
.endif
# it is rare for test cases to have man pages
.if !defined(MAN)
@ -80,19 +84,14 @@ PROGS_TARGETS+= install
.include <suite.test.mk>
.endif
.if !target(realtest)
realtest: .PHONY
.if !target(realcheck)
realcheck: .PHONY
@echo "$@ not defined; skipping"
.endif
test: .PHONY
.ORDER: beforetest realtest
test: beforetest realtest
.if target(aftertest)
.ORDER: realtest aftertest
test: aftertest
.endif
beforecheck realcheck aftercheck check: .PHONY
.ORDER: beforecheck realcheck aftercheck
check: beforecheck realcheck aftercheck
.ifdef PROG
# we came here via bsd.progs.mk below

53
share/mk/suite.test.mk
View File

@ -50,15 +50,12 @@ FILES+= Kyuafile
FILESDIR_Kyuafile= ${TESTSDIR}
.endif
.if ${KYUAFILE:tl} == "auto"
CLEANFILES+= Kyuafile Kyuafile.tmp
.endif
.for _T in ${_TESTS}
_TEST_METADATA.${_T}= ${TEST_METADATA} ${TEST_METADATA.${_T}}
.endfor
.if ${KYUAFILE:tl} == "auto"
CLEANFILES+= Kyuafile Kyuafile.tmp
Kyuafile: Makefile
@{ \
echo '-- Automatically generated by bsd.test.mk.'; \
@ -78,9 +75,11 @@ Kyuafile: Makefile
@mv ${.TARGET}.tmp ${.TARGET}
.endif
CHECKDIR?= ${DESTDIR}${TESTSDIR}
KYUA= ${LOCALBASE}/bin/kyua
.if exists(${KYUA})
# Definition of the "make test" target and supporting variables.
# Definition of the "make check" target and supporting variables.
#
# This target, by necessity, can only work for native builds (i.e. a FreeBSD
# host building a release for the same system). The target runs Kyua, which is
@ -89,35 +88,15 @@ KYUA= ${LOCALBASE}/bin/kyua
# Due to the dependencies of the binaries built by the source tree and how they
# are used by tests, it is highly possible for a execution of "make test" to
# report bogus results unless the new binaries are put in place.
realtest: .PHONY
@echo "*** WARNING: make test is experimental"
@echo "***"
@echo "*** Using this test does not preclude you from running the tests"
@echo "*** installed in ${TESTSBASE}. This test run may raise false"
@echo "*** positives and/or false negatives."
@echo
@${KYUA} test -k ${DESTDIR}${TESTSDIR}/Kyuafile; \
result=0; \
echo; \
echo "*** Once again, note that "make test" is unsupported."; \
test $${result} -eq 0
.endif
beforetest: .PHONY
.if defined(TESTSDIR)
.if ${TESTSDIR} == ${TESTSBASE}
# Forbid running from ${TESTSBASE}. It can cause false positives/negatives and
# it does not cover all the tests (e.g. it misses testing software in external).
@echo "*** Sorry, you cannot use make test from src/tests. Install the"
@echo "*** tests into their final location and run them from ${TESTSBASE}"
@false
.else
@echo "*** Using this test does not preclude you from running the tests"
@echo "*** installed in ${TESTSBASE}. This test run may raise false"
@echo "*** positives and/or false negatives."
.endif
.else
@echo "*** No TESTSDIR defined; nothing to do."
@false
.endif
@echo
realcheck: .PHONY
@if [ ! -x ${KYUA} ]; then \
echo; \
echo "kyua binary not installed at expected location (${.TARGET})"; \
echo; \
echo "Please install via pkg install, or specify the path to the kyua"; \
echo "package via the \$${LOCALBASE} variable, e.g. "; \
echo "LOCALBASE=\"${LOCALBASE}\""; \
false; \
fi
@${KYUA} test -k ${CHECKDIR}/Kyuafile

1
sys/amd64/amd64/uma_machdep.c
View File

@ -32,6 +32,7 @@ __FBSDID("$FreeBSD$");
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/systm.h>
#include <sys/taskqueue.h>
#include <vm/vm.h>
#include <vm/vm_page.h>
#include <vm/vm_pageout.h>

4
sys/arm/allwinner/a20/a20_mp.c
View File

@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@ -101,8 +102,7 @@ platform_mp_start_ap(void)
&cpucfg) != 0)
panic("Couldn't map the CPUCFG\n");
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
dcache_wbinv_poc_all();
bus_space_write_4(fdtbus_bs_tag, cpucfg, CPUCFG_P_REG0,
pmap_kextract((vm_offset_t)mpentry));

4
sys/arm/altera/socfpga/socfpga_mp.c
View File

@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@ -162,8 +163,7 @@ platform_mp_start_ap(void)
bus_space_write_region_4(fdtbus_bs_tag, ram, 0,
(uint32_t *)&socfpga_trampoline, 8);
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
dcache_wbinv_poc_all();
/* Put CPU1 out from reset */
bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0);

3
sys/arm/amlogic/aml8726/aml8726_mp.c
View File

@ -53,6 +53,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/cpu.h>
#include <machine/bus.h>
#include <machine/smp.h>
#include <machine/fdt.h>
@ -485,7 +486,7 @@ platform_mp_start_ap(void)
value |= AML_SCU_CONTROL_ENABLE;
SCU_WRITE_4(AML_SCU_CONTROL_REG, value);
SCU_BARRIER(AML_SCU_CONTROL_REG);
cpu_idcache_wbinv_all();
dcache_wbinv_poc_all();
/* Set the boot address and power on each AP. */
paddr = pmap_kextract((vm_offset_t)mpentry);

174
sys/arm/arm/cpufunc.c
View File

@ -60,18 +60,7 @@ __FBSDID("$FreeBSD$");
#include <machine/cpuconf.h>
#include <machine/cpufunc.h>
#if defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219)
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#endif
/*
* Some definitions in i81342reg.h clash with i80321reg.h.
* This only happens for the LINT kernel. As it happens,
* we don't need anything from i81342reg.h that we already
* got from somewhere else during a LINT compile.
*/
#if defined(CPU_XSCALE_81342) && !defined(COMPILING_LINT)
#if defined(CPU_XSCALE_81342)
#include <arm/xscale/i8134x/i81342reg.h>
#endif
@ -99,8 +88,6 @@ u_int arm_cache_level;
u_int arm_cache_type[14];
u_int arm_cache_loc;
int ctrl;
#ifdef CPU_ARM9
struct cpu_functions arm9_cpufuncs = {
/* CPU functions */
@ -121,7 +108,6 @@ struct cpu_functions arm9_cpufuncs = {
/* Cache operations */
arm9_icache_sync_all, /* icache_sync_all */
arm9_icache_sync_range, /* icache_sync_range */
arm9_dcache_wbinv_all, /* dcache_wbinv_all */
@ -173,7 +159,6 @@ struct cpu_functions armv5_ec_cpufuncs = {
/* Cache operations */
armv5_ec_icache_sync_all, /* icache_sync_all */
armv5_ec_icache_sync_range, /* icache_sync_range */
armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */
@ -224,7 +209,6 @@ struct cpu_functions sheeva_cpufuncs = {
/* Cache operations */
armv5_ec_icache_sync_all, /* icache_sync_all */
armv5_ec_icache_sync_range, /* icache_sync_range */
armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */
@ -275,7 +259,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
armv7_tlb_flushID_SE, /* tlb_flushD_SE */
/* Cache operations */
armv7_idcache_wbinv_all, /* icache_sync_all */
armv7_icache_sync_range, /* icache_sync_range */
armv7_dcache_wbinv_all, /* dcache_wbinv_all */
@ -306,9 +289,7 @@ struct cpu_functions pj4bv7_cpufuncs = {
};
#endif /* CPU_MV_PJ4B */
#if defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
struct cpu_functions xscale_cpufuncs = {
/* CPU functions */
@ -329,7 +310,6 @@ struct cpu_functions xscale_cpufuncs = {
/* Cache operations */
xscale_cache_syncI, /* icache_sync_all */
xscale_cache_syncI_rng, /* icache_sync_range */
xscale_cache_purgeD, /* dcache_wbinv_all */
@ -359,8 +339,7 @@ struct cpu_functions xscale_cpufuncs = {
xscale_setup /* cpu setup */
};
#endif
/* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
CPU_XSCALE_80219 */
/* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
#ifdef CPU_XSCALE_81342
struct cpu_functions xscalec3_cpufuncs = {
@ -382,7 +361,6 @@ struct cpu_functions xscalec3_cpufuncs = {
/* Cache operations */
xscalec3_cache_syncI, /* icache_sync_all */
xscalec3_cache_syncI_rng, /* icache_sync_range */
xscalec3_cache_purgeD, /* dcache_wbinv_all */
@ -434,7 +412,6 @@ struct cpu_functions fa526_cpufuncs = {
/* Cache operations */
fa526_icache_sync_all, /* icache_sync_all */
fa526_icache_sync_range, /* icache_sync_range */
fa526_dcache_wbinv_all, /* dcache_wbinv_all */
@ -486,7 +463,6 @@ struct cpu_functions arm1176_cpufuncs = {
/* Cache operations */
arm11x6_icache_sync_all, /* icache_sync_all */
arm11x6_icache_sync_range, /* icache_sync_range */
arm11x6_dcache_wbinv_all, /* dcache_wbinv_all */
@ -542,7 +518,6 @@ struct cpu_functions cortexa_cpufuncs = {
/* Cache operations */
armv7_icache_sync_all, /* icache_sync_all */
armv7_icache_sync_range, /* icache_sync_range */
armv7_dcache_wbinv_all, /* dcache_wbinv_all */
@ -588,10 +563,10 @@ u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
#if defined(CPU_ARM9) || \
defined (CPU_ARM9E) || \
defined(CPU_ARM1176) || defined(CPU_XSCALE_80321) || \
defined(CPU_ARM1176) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_FA526) || defined(CPU_MV_PJ4B) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
defined(CPU_XSCALE_81342) || \
defined(CPU_CORTEXA) || defined(CPU_KRAIT)
/* Global cache line sizes, use 32 as default */
@ -829,18 +804,6 @@ set_cpufuncs()
}
#endif /* CPU_FA526 */
#if defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219)
if (cputype == CPU_ID_80321_400 || cputype == CPU_ID_80321_600 ||
cputype == CPU_ID_80321_400_B0 || cputype == CPU_ID_80321_600_B0 ||
cputype == CPU_ID_80219_400 || cputype == CPU_ID_80219_600) {
cpufuncs = xscale_cpufuncs;
cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
get_cachetype_cp15();
pmap_pte_init_xscale();
goto out;
}
#endif /* CPU_XSCALE_80321 */
#if defined(CPU_XSCALE_81342)
if (cputype == CPU_ID_81342) {
cpufuncs = xscalec3_cpufuncs;
@ -924,7 +887,6 @@ arm9_setup(void)
/* Set the control register */
cpu_control(cpuctrlmask, cpuctrl);
ctrl = cpuctrl;
}
#endif /* CPU_ARM9 */
@ -963,7 +925,6 @@ arm10_setup(void)
cpuctrl |= CPU_CONTROL_VECRELOC;
/* Set the control register */
ctrl = cpuctrl;
cpu_control(0xffffffff, cpuctrl);
/* And again. */
@ -1005,47 +966,12 @@ cpu_scc_setup_ccnt(void)
void
arm11x6_setup(void)
{
int cpuctrl, cpuctrl_wax;
uint32_t auxctrl, auxctrl_wax;
uint32_t tmp, tmp2;
uint32_t sbz=0;
uint32_t cpuid;
cpuid = cpu_ident();
cpuctrl =
CPU_CONTROL_MMU_ENABLE |
CPU_CONTROL_DC_ENABLE |
CPU_CONTROL_WBUF_ENABLE |
CPU_CONTROL_32BP_ENABLE |
CPU_CONTROL_32BD_ENABLE |
CPU_CONTROL_LABT_ENABLE |
CPU_CONTROL_SYST_ENABLE |
CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_UNAL_ENABLE;
/*
* "write as existing" bits
* inverse of this is mask
*/
cpuctrl_wax =
(3 << 30) | /* SBZ */
(1 << 29) | /* FA */
(1 << 28) | /* TR */
(3 << 26) | /* SBZ */
(3 << 19) | /* SBZ */
(1 << 17); /* SBZ */
cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
#ifdef __ARMEB__
cpuctrl |= CPU_CONTROL_BEND_ENABLE;
#endif
if (vector_page == ARM_VECTORS_HIGH)
cpuctrl |= CPU_CONTROL_VECRELOC;
auxctrl = 0;
auxctrl_wax = ~0;
@ -1057,19 +983,6 @@ arm11x6_setup(void)
auxctrl_wax = ~ARM1176_AUXCTL_PHD;
}
/* Clear out the cache */
cpu_idcache_wbinv_all();
/* Now really make sure they are clean. */
__asm volatile ("mcr\tp15, 0, %0, c7, c7, 0" : : "r"(sbz));
/* Allow detection code to find the VFP if it's fitted. */
cp15_cpacr_set(0x0fffffff);
/* Set the control register */
ctrl = cpuctrl;
cpu_control(~cpuctrl_wax, cpuctrl);
tmp = cp15_actlr_get();
tmp2 = tmp;
tmp &= auxctrl_wax;
@ -1077,9 +990,6 @@ arm11x6_setup(void)
if (tmp != tmp2)
cp15_actlr_set(tmp);
/* And again. */
cpu_idcache_wbinv_all();
cpu_scc_setup_ccnt();
}
#endif /* CPU_ARM1176 */
@ -1088,33 +998,8 @@ arm11x6_setup(void)
void
pj4bv7_setup(void)
{
int cpuctrl;
pj4b_config();
cpuctrl = CPU_CONTROL_MMU_ENABLE;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
cpuctrl |= CPU_CONTROL_DC_ENABLE;
cpuctrl |= (0xf << 3);
cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
cpuctrl |= CPU_CONTROL_IC_ENABLE;
if (vector_page == ARM_VECTORS_HIGH)
cpuctrl |= CPU_CONTROL_VECRELOC;
cpuctrl |= (0x5 << 16) | (1 < 22);
cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
/* Clear out the cache */
cpu_idcache_wbinv_all();
/* Set the control register */
ctrl = cpuctrl;
cpu_control(0xFFFFFFFF, cpuctrl);
/* And again. */
cpu_idcache_wbinv_all();
cpu_scc_setup_ccnt();
}
#endif /* CPU_MV_PJ4B */
@ -1124,45 +1009,6 @@ pj4bv7_setup(void)
void
cortexa_setup(void)
{
int cpuctrl, cpuctrlmask;
cpuctrlmask = CPU_CONTROL_MMU_ENABLE | /* MMU enable [0] */
CPU_CONTROL_AFLT_ENABLE | /* Alignment fault [1] */
CPU_CONTROL_DC_ENABLE | /* DCache enable [2] */
CPU_CONTROL_BPRD_ENABLE | /* Branch prediction [11] */
CPU_CONTROL_IC_ENABLE | /* ICache enable [12] */
CPU_CONTROL_VECRELOC; /* Vector relocation [13] */
cpuctrl = CPU_CONTROL_MMU_ENABLE |
CPU_CONTROL_IC_ENABLE |
CPU_CONTROL_DC_ENABLE |
CPU_CONTROL_BPRD_ENABLE;
#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
#endif
/* Switch to big endian */
#ifdef __ARMEB__
cpuctrl |= CPU_CONTROL_BEND_ENABLE;
#endif
/* Check if the vector page is at the high address (0xffff0000) */
if (vector_page == ARM_VECTORS_HIGH)
cpuctrl |= CPU_CONTROL_VECRELOC;
/* Clear out the cache */
cpu_idcache_wbinv_all();
/* Set the control register */
ctrl = cpuctrl;
cpu_control(cpuctrlmask, cpuctrl);
/* And again. */
cpu_idcache_wbinv_all();
#if defined(SMP) && !defined(ARM_NEW_PMAP)
armv7_auxctrl((1 << 6) | (1 << 0), (1 << 6) | (1 << 0)); /* Enable SMP + TLB broadcasting */
#endif
cpu_scc_setup_ccnt();
}
@ -1202,14 +1048,12 @@ fa526_setup(void)
cpu_idcache_wbinv_all();
/* Set the control register */
ctrl = cpuctrl;
cpu_control(0xffffffff, cpuctrl);
}
#endif /* CPU_FA526 */
#if defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_81342)
void
xscale_setup(void)
{
@ -1257,7 +1101,6 @@ xscale_setup(void)
* Set the control register. Note that bits 6:3 must always
* be set to 1.
*/
ctrl = cpuctrl;
/* cpu_control(cpuctrlmask, cpuctrl);*/
cpu_control(0xffffffff, cpuctrl);
@ -1276,5 +1119,4 @@ xscale_setup(void)
__asm __volatile("mcr p15, 0, %0, c1, c0, 1"
: : "r" (auxctl));
}
#endif /* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
CPU_XSCALE_80219 */
#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */

6
sys/arm/arm/cpufunc_asm_arm11x6.S
View File

@ -132,12 +132,6 @@ ENTRY_NP(arm11x6_dcache_wbinv_all)
RET
END(arm11x6_dcache_wbinv_all)
ENTRY_NP(arm11x6_icache_sync_all)
Flush_D_cache(r0)
Invalidate_I_cache(r0, r1)
RET
END(arm11x6_icache_sync_all)
ENTRY_NP(arm11x6_icache_sync_range)
add r1, r1, r0
sub r1, r1, #1

4
sys/arm/arm/cpufunc_asm_arm9.S
View File

@ -85,9 +85,7 @@ ENTRY_NP(arm9_icache_sync_range)
subs r1, r1, ip
bhi .Larm9_sync_next
mov pc, lr
END(arm9_icache_sync_range)
ENTRY_NP(arm9_icache_sync_all)
.Larm9_icache_sync_all:
/*
* We assume that the code here can never be out of sync with the
@ -109,7 +107,7 @@ ENTRY_NP(arm9_icache_sync_all)
subs s_max, s_max, s_inc
bhs .Lnext_set /* Next set */
mov pc, lr
END(arm9_icache_sync_all)
END(arm9_icache_sync_range)
.Larm9_line_size:
.word _C_LABEL(arm_pdcache_line_size)

4
sys/arm/arm/cpufunc_asm_armv5_ec.S
View File

@ -91,9 +91,7 @@ ENTRY_NP(armv5_ec_icache_sync_range)
bpl 1b
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv5_ec_icache_sync_range)
ENTRY_NP(armv5_ec_icache_sync_all)
.Larmv5_ec_icache_sync_all:
/*
* We assume that the code here can never be out of sync with the
@ -109,7 +107,7 @@ ENTRY_NP(armv5_ec_icache_sync_all)
bne 1b /* More to do? */
mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
RET
END(armv5_ec_icache_sync_all)
END(armv5_ec_icache_sync_range)
.Larmv5_ec_line_size:
.word _C_LABEL(arm_pdcache_line_size)

10
sys/arm/arm/cpufunc_asm_armv7.S
View File

@ -252,16 +252,6 @@ ENTRY(armv7_idcache_wbinv_range)
RET
END(armv7_idcache_wbinv_range)
ENTRY_NP(armv7_icache_sync_all)
#ifdef SMP
mcr CP15_ICIALLUIS
#else
mcr CP15_ICIALLU
#endif
dsb /* data synchronization barrier */
isb /* instruction synchronization barrier */
RET
END(armv7_icache_sync_all)
ENTRY_NP(armv7_icache_sync_range)
ldr ip, .Larmv7_icache_line_size

13
sys/arm/arm/cpufunc_asm_fa526.S
View File

@ -83,12 +83,6 @@ ENTRY(fa526_idcache_wbinv_all)
mov pc, lr
END(fa526_idcache_wbinv_all)
ENTRY(fa526_icache_sync_all)
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */
mov pc, lr
END(fa526_icache_sync_all)
ENTRY(fa526_dcache_wbinv_all)
mov r0, #0
mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */
@ -170,7 +164,7 @@ END(fa526_idcache_wbinv_range)
ENTRY(fa526_icache_sync_range)
cmp r1, #0x4000
bhs _C_LABEL(fa526_icache_sync_all)
bhs .Lfa526_icache_sync_all
and r2, r0, #(CACHELINE_SIZE - 1)
add r1, r1, r2
@ -184,6 +178,11 @@ ENTRY(fa526_icache_sync_range)
2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
mov pc, lr
.Lfa526_icache_sync_all:
mov r0, #0
mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */
mov pc, lr
END(fa526_icache_sync_range)
ENTRY(fa526_context_switch)

19
sys/arm/arm/cpufunc_asm_xscale.S
View File

@ -80,9 +80,6 @@ __FBSDID("$FreeBSD$");
*/
#define DCACHE_SIZE 0x00008000
.Lblock_userspace_access:
.word _C_LABEL(block_userspace_access)
/*
* CPWAIT -- Canonical method to wait for CP15 update.
* From: Intel 80200 manual, section 2.3.3.
@ -137,11 +134,6 @@ ENTRY(xscale_setttb)
mrs r3, cpsr
orr r1, r3, #(PSR_I | PSR_F)
msr cpsr_fsxc, r1
#else
ldr r3, .Lblock_userspace_access
ldr r2, [r3]
orr r1, r2, #1
str r1, [r3]
#endif
stmfd sp!, {r0-r3, lr}
bl _C_LABEL(xscale_cache_cleanID)
@ -165,8 +157,6 @@ ENTRY(xscale_setttb)
#ifdef CACHE_CLEAN_BLOCK_INTR
msr cpsr_fsxc, r3
#else
str r2, [r3]
#endif
RET
END(xscale_setttb)
@ -273,14 +263,9 @@ _C_LABEL(xscale_minidata_clean_size):
#define XSCALE_CACHE_CLEAN_UNBLOCK \
msr cpsr_fsxc, r3
#else
#define XSCALE_CACHE_CLEAN_BLOCK \
ldr r3, .Lblock_userspace_access ; \
ldr ip, [r3] ; \
orr r0, ip, #1 ; \
str r0, [r3]
#define XSCALE_CACHE_CLEAN_BLOCK
#define XSCALE_CACHE_CLEAN_UNBLOCK \
str ip, [r3]
#define XSCALE_CACHE_CLEAN_UNBLOCK
#endif /* CACHE_CLEAN_BLOCK_INTR */
#define XSCALE_CACHE_CLEAN_PROLOGUE \

20
sys/arm/arm/cpufunc_asm_xscale_c3.S
View File

@ -82,9 +82,6 @@ __FBSDID("$FreeBSD$");
*/
#define DCACHE_SIZE 0x00008000
.Lblock_userspace_access:
.word _C_LABEL(block_userspace_access)
/*
* CPWAIT -- Canonical method to wait for CP15 update.
* From: Intel 80200 manual, section 2.3.3.
@ -130,16 +127,8 @@ __FBSDID("$FreeBSD$");
msr cpsr_fsxc, r4 ; \
ldmfd sp!, {r4}
#else
#define XSCALE_CACHE_CLEAN_BLOCK \
stmfd sp!, {r4} ; \
ldr r4, .Lblock_userspace_access ; \
ldr ip, [r4] ; \
orr r0, ip, #1 ; \
str r0, [r4]
#define XSCALE_CACHE_CLEAN_UNBLOCK \
str ip, [r3] ; \
ldmfd sp!, {r4}
#define XSCALE_CACHE_CLEAN_BLOCK
#define XSCALE_CACHE_CLEAN_UNBLOCK
#endif /* CACHE_CLEAN_BLOCK_INTR */
@ -352,11 +341,6 @@ ENTRY(xscalec3_setttb)
mrs r3, cpsr
orr r1, r3, #(PSR_I | PSR_F)
msr cpsr_fsxc, r1
#else
ldr r3, .Lblock_userspace_access
ldr r2, [r3]
orr r1, r2, #1
str r1, [r3]
#endif
stmfd sp!, {r0-r3, lr}
bl _C_LABEL(xscalec3_cache_cleanID)

7
sys/arm/arm/cpuinfo.c
View File

@ -31,8 +31,8 @@ __FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <machine/cpu.h>
#include <machine/cpuinfo.h>
#include <machine/cpu-v6.h>
struct cpuinfo cpuinfo =
{
@ -83,14 +83,16 @@ cpuinfo_init(void)
/* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */
cpuinfo.ctr = cp15_ctr_get();
cpuinfo.tcmtr = cp15_tcmtr_get();
#if __ARM_ARCH >= 6
cpuinfo.tlbtr = cp15_tlbtr_get();
cpuinfo.mpidr = cp15_mpidr_get();
cpuinfo.revidr = cp15_revidr_get();
#endif
/* if CPU is not v7 cpu id scheme */
if (cpuinfo.architecture != 0xF)
return;
#if __ARM_ARCH >= 6
cpuinfo.id_pfr0 = cp15_id_pfr0_get();
cpuinfo.id_pfr1 = cp15_id_pfr1_get();
cpuinfo.id_dfr0 = cp15_id_dfr0_get();
@ -144,6 +146,7 @@ cpuinfo_init(void)
}
cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1;
cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1;
#endif
}
/*

10
sys/arm/arm/db_interface.c
View File

@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$");
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/cons.h>
#include <sys/proc.h>
#include <sys/reboot.h>
#include <sys/systm.h> /* just for boothowto */
@ -53,9 +54,9 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_extern.h>
#include <machine/db_machdep.h>
#include <machine/cpu.h>
#include <machine/machdep.h>
#include <machine/vmparam.h>
#include <machine/cpu.h>
#include <ddb/ddb.h>
#include <ddb/db_access.h>
@ -63,7 +64,7 @@ __FBSDID("$FreeBSD$");
#include <ddb/db_output.h>
#include <ddb/db_variables.h>
#include <ddb/db_sym.h>
#include <sys/cons.h>
static int nil = 0;
@ -245,11 +246,10 @@ db_write_bytes(vm_offset_t addr, size_t size, char *data)
}
/* make sure the caches and memory are in sync */
cpu_icache_sync_range(addr, size);
icache_sync(addr, size);
/* In case the current page tables have been modified ... */
cpu_tlb_flushID();
cpu_cpwait();
tlb_flush_all();
return (0);
}

2
sys/arm/arm/debug_monitor.c
View File

@ -845,8 +845,10 @@ dbg_arch_supported(void)
{
switch (dbg_model) {
#ifdef not_yet
case ID_DFR0_CP_DEBUG_M_V6:
case ID_DFR0_CP_DEBUG_M_V6_1:
#endif
case ID_DFR0_CP_DEBUG_M_V7:
case ID_DFR0_CP_DEBUG_M_V7_1: /* fall through */
return (TRUE);

5
sys/arm/arm/devmap.c
View File

@ -40,7 +40,9 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/vm_extern.h>
#include <vm/pmap.h>
#ifdef __arm__
#include <machine/acle-compat.h>
#endif
#include <machine/armreg.h>
#include <machine/devmap.h>
#include <machine/vmparam.h>
@ -53,9 +55,6 @@ static boolean_t devmap_bootstrap_done = false;
#define PTE_DEVICE VM_MEMATTR_DEVICE
#elif defined(__arm__)
#define MAX_VADDR ARM_VECTORS_HIGH
#if __ARM_ARCH >= 6
#define PTE_DEVICE VM_MEMATTR_DEVICE
#endif
#endif
/*

3
sys/arm/arm/dump_machdep.c
View File

@ -59,8 +59,7 @@ dumpsys_wbinv_all(void)
* have already been stopped, and their flush/invalidate was done as
* part of stopping.
*/
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
dcache_wbinv_poc_all();
#ifdef __XSCALE__
xscale_cache_clean_minidata();
#endif

2
sys/arm/arm/elf_machdep.c
View File

@ -282,7 +282,7 @@ elf_cpu_load_file(linker_file_t lf)
#else
cpu_dcache_wb_range((vm_offset_t)lf->address, (vm_size_t)lf->size);
cpu_l2cache_wb_range((vm_offset_t)lf->address, (vm_size_t)lf->size);
cpu_icache_sync_all();
cpu_icache_sync_range((vm_offset_t)lf->address, (vm_size_t)lf->size);
#endif
return (0);
}

5
sys/arm/arm/elf_trampoline.c
View File

@ -67,9 +67,7 @@ extern void fa526_idcache_wbinv_all(void);
extern void armv5_ec_idcache_wbinv_all(void);
#elif defined(CPU_ARM1176)
#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
#elif defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
#elif defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
#define cpu_idcache_wbinv_all xscale_cache_purgeID
extern void xscale_cache_purgeID(void);
#elif defined(CPU_XSCALE_81342)
@ -127,7 +125,6 @@ static int arm_dcache_l2_assoc;
static int arm_dcache_l2_linesize;
int block_userspace_access = 0;
extern int arm9_dcache_sets_inc;
extern int arm9_dcache_sets_max;
extern int arm9_dcache_index_max;

2
sys/arm/arm/fiq.c
View File

@ -81,8 +81,8 @@ fiq_installhandler(void *func, size_t size)
#if !defined(__ARM_FIQ_INDIRECT)
vector_page_setprot(VM_PROT_READ);
cpu_icache_sync_range((vm_offset_t) fiqvector, size);
#endif
icache_sync((vm_offset_t) fiqvector, size);
}
/*

91
sys/arm/arm/fusu.S
View File

@ -183,51 +183,10 @@ END(fusword)
*/
ENTRY(fuswintr)
ldr r3, =(VM_MAXUSER_ADDRESS-1)
cmp r0, r3
mvncs r0, #0
RETc(cs)
ldr r2, Lblock_userspace_access
ldr r2, [r2]
teq r2, #0
mvnne r0, #0x00000000
RETne
GET_PCB(r2)
ldr r2, [r2]
#ifdef DIAGNOSTIC
teq r2, #0x00000000
beq .Lfusupcbfault
#endif
adr r1, _C_LABEL(fusubailout)
str r1, [r2, #PCB_ONFAULT]
ldrbt r3, [r0], #1
ldrbt ip, [r0]
#ifdef __ARMEB__
orr r0, ip, r3, asl #8
#else
orr r0, r3, ip, asl #8
#endif
mov r1, #0x00000000
str r1, [r2, #PCB_ONFAULT]
mov r0, #-1
RET
END(fuswintr)
Lblock_userspace_access:
.word _C_LABEL(block_userspace_access)
.data
.align 2
.global _C_LABEL(block_userspace_access)
_C_LABEL(block_userspace_access):
.word 0
.text
/*
* fubyte(caddr_t uaddr);
* Fetch a byte from the user's address space.
@ -268,20 +227,6 @@ END(fubyte)
mvn r0, #0x00000000
RET
/*
* Handle faults from [fs]u*(). Clean up and return -1. This differs from
* fusufault() in that trap() will recognise it and return immediately rather
* than trying to page fault.
*/
/* label must be global as fault.c references it */
.global _C_LABEL(fusubailout)
_C_LABEL(fusubailout):
mov r0, #0x00000000
str r0, [r2, #PCB_ONFAULT]
mvn r0, #0x00000000
RET
#ifdef DIAGNOSTIC
/*
* Handle earlier faults from [fs]u*(), due to no pcb
@ -335,39 +280,7 @@ END(suword)
*/
ENTRY(suswintr)
ldr r3, =(VM_MAXUSER_ADDRESS-1)
cmp r0, r3
mvncs r0, #0
RETc(cs)
ldr r2, Lblock_userspace_access
ldr r2, [r2]
teq r2, #0
mvnne r0, #0x00000000
RETne
GET_PCB(r2)
ldr r2, [r2]
#ifdef DIAGNOSTIC
teq r2, #0x00000000
beq .Lfusupcbfault
#endif
adr r3, _C_LABEL(fusubailout)
str r3, [r2, #PCB_ONFAULT]
#ifdef __ARMEB__
mov ip, r1, lsr #8
strbt ip, [r0], #1
#else
strbt r1, [r0], #1
mov r1, r1, lsr #8
#endif
strbt r1, [r0]
mov r0, #0x00000000
str r0, [r2, #PCB_ONFAULT]
mov r0, #-1
RET
END(suswintr)

16
sys/arm/arm/genassym.c
View File

@ -45,7 +45,6 @@ __FBSDID("$FreeBSD$");
#include <machine/frame.h>
#include <machine/pcb.h>
#include <machine/cpu.h>
#include <machine/cpu-v6.h>
#include <machine/proc.h>
#include <machine/cpufunc.h>
#include <machine/cpuinfo.h>
@ -59,7 +58,6 @@ __FBSDID("$FreeBSD$");
#include <netinet/ip_var.h>
ASSYM(KERNBASE, KERNBASE);
ASSYM(PCB_NOALIGNFLT, PCB_NOALIGNFLT);
#if __ARM_ARCH >= 6
ASSYM(CPU_ASID_KERNEL,CPU_ASID_KERNEL);
#endif
@ -67,7 +65,6 @@ ASSYM(PCB_ONFAULT, offsetof(struct pcb, pcb_onfault));
#if __ARM_ARCH < 6
ASSYM(PCB_DACR, offsetof(struct pcb, pcb_dacr));
#endif
ASSYM(PCB_FLAGS, offsetof(struct pcb, pcb_flags));
ASSYM(PCB_PAGEDIR, offsetof(struct pcb, pcb_pagedir));
#if __ARM_ARCH < 6
ASSYM(PCB_L1VEC, offsetof(struct pcb, pcb_l1vec));
@ -93,24 +90,15 @@ ASSYM(M_DATA, offsetof(struct mbuf, m_data));
ASSYM(M_NEXT, offsetof(struct mbuf, m_next));
ASSYM(IP_SRC, offsetof(struct ip, ip_src));
ASSYM(IP_DST, offsetof(struct ip, ip_dst));
ASSYM(CF_SETTTB, offsetof(struct cpu_functions, cf_setttb));
ASSYM(CF_CONTROL, offsetof(struct cpu_functions, cf_control));
ASSYM(CF_CONTEXT_SWITCH, offsetof(struct cpu_functions, cf_context_switch));
ASSYM(CF_DCACHE_WB_RANGE, offsetof(struct cpu_functions, cf_dcache_wb_range));
ASSYM(CF_L2CACHE_WB_RANGE, offsetof(struct cpu_functions, cf_l2cache_wb_range));
ASSYM(CF_IDCACHE_WBINV_ALL, offsetof(struct cpu_functions, cf_idcache_wbinv_all));
ASSYM(CF_L2CACHE_WBINV_ALL, offsetof(struct cpu_functions, cf_l2cache_wbinv_all));
ASSYM(CF_TLB_FLUSHID_SE, offsetof(struct cpu_functions, cf_tlb_flushID_SE));
ASSYM(CF_ICACHE_SYNC, offsetof(struct cpu_functions, cf_icache_sync_all));
ASSYM(V_TRAP, offsetof(struct vmmeter, v_trap));
ASSYM(V_SOFT, offsetof(struct vmmeter, v_soft));
ASSYM(V_INTR, offsetof(struct vmmeter, v_intr));
ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
ASSYM(TD_FLAGS, offsetof(struct thread, td_flags));
ASSYM(TD_PROC, offsetof(struct thread, td_proc));
ASSYM(TD_FRAME, offsetof(struct thread, td_frame));
ASSYM(TD_MD, offsetof(struct thread, td_md));
ASSYM(TD_LOCK, offsetof(struct thread, td_lock));
ASSYM(MD_TP, offsetof(struct mdthread, md_tp));
@ -147,10 +135,6 @@ ASSYM(PMAP_INCLUDE_PTE_SYNC, 1);
#endif
ASSYM(TDF_ASTPENDING, TDF_ASTPENDING);
ASSYM(TDF_NEEDRESCHED, TDF_NEEDRESCHED);
ASSYM(P_TRACED, P_TRACED);
ASSYM(P_SIGEVENT, P_SIGEVENT);
ASSYM(P_PROFIL, P_PROFIL);
ASSYM(TRAPFRAMESIZE, sizeof(struct trapframe));
ASSYM(MAXCOMLEN, MAXCOMLEN);
ASSYM(MAXCPU, MAXCPU);

4
sys/arm/arm/identcpu.c
View File

@ -321,7 +321,6 @@ print_enadis(int enadis, char *s)
printf(" %s %sabled", s, (enadis == 0) ? "dis" : "en");
}
extern int ctrl;
enum cpu_class cpu_class = CPU_CLASS_NONE;
u_int cpu_pfr(int num)
@ -388,9 +387,10 @@ void
identify_arm_cpu(void)
{
u_int cpuid, reg, size, sets, ways;
u_int8_t type, linesize;
u_int8_t type, linesize, ctrl;
int i;
ctrl = cpu_get_control();
cpuid = cpu_ident();
if (cpuid == 0) {

4
sys/arm/arm/locore-v6.S
View File

@ -132,9 +132,9 @@ ASENTRY_NP(_start)
bic r7, #CPU_CONTROL_DC_ENABLE
bic r7, #CPU_CONTROL_MMU_ENABLE
bic r7, #CPU_CONTROL_IC_ENABLE
bic r7, #CPU_CONTROL_UNAL_ENABLE
bic r7, #CPU_CONTROL_BPRD_ENABLE
bic r7, #CPU_CONTROL_SW_ENABLE
orr r7, #CPU_CONTROL_UNAL_ENABLE
orr r7, #CPU_CONTROL_AFLT_ENABLE
orr r7, #CPU_CONTROL_VECRELOC
mcr CP15_SCTLR(r7)
@ -456,9 +456,9 @@ ASENTRY_NP(mpentry)
bic r0, #CPU_CONTROL_MMU_ENABLE
bic r0, #CPU_CONTROL_DC_ENABLE
bic r0, #CPU_CONTROL_IC_ENABLE
bic r0, #CPU_CONTROL_UNAL_ENABLE
bic r0, #CPU_CONTROL_BPRD_ENABLE
bic r0, #CPU_CONTROL_SW_ENABLE
orr r0, #CPU_CONTROL_UNAL_ENABLE
orr r0, #CPU_CONTROL_AFLT_ENABLE
orr r0, #CPU_CONTROL_VECRELOC
mcr CP15_SCTLR(r0)

16
sys/arm/arm/machdep.c
View File

@ -123,7 +123,6 @@ __FBSDID("$FreeBSD$");
#include <ddb/ddb.h>
#if __ARM_ARCH >= 6
#include <machine/cpu-v6.h>
DB_SHOW_COMMAND(cp15, db_show_cp15)
{
@ -397,7 +396,7 @@ arm_vector_init(vm_offset_t va, int which)
}
/* Now sync the vectors. */
cpu_icache_sync_range(va, (ARM_NVEC * 2) * sizeof(u_int));
icache_sync(va, (ARM_NVEC * 2) * sizeof(u_int));
vector_page = va;
@ -479,12 +478,7 @@ void
cpu_flush_dcache(void *ptr, size_t len)
{
cpu_dcache_wb_range((uintptr_t)ptr, len);
#ifdef ARM_L2_PIPT
cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len);
#else
cpu_l2cache_wb_range((uintptr_t)ptr, len);
#endif
dcache_wb_poc((vm_offset_t)ptr, (vm_paddr_t)vtophys(ptr), len);
}
/* Get current clock frequency for the given cpu id. */
@ -1622,7 +1616,7 @@ initarm(struct arm_boot_params *abp)
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT);
pmap_pa = kernel_l1pt.pv_pa;
setttb(kernel_l1pt.pv_pa);
cpu_setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2));
@ -1675,7 +1669,7 @@ initarm(struct arm_boot_params *abp)
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* dirty data in the cache. This will have happened in cpu_setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
@ -1867,7 +1861,7 @@ initarm(struct arm_boot_params *abp)
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* dirty data in the cache. This will have happened in cpu_setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.

7
sys/arm/arm/minidump_machdep.c
View File

@ -45,11 +45,11 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/atomic.h>
#include <machine/cpu.h>
#include <machine/elf.h>
#include <machine/md_var.h>
#include <machine/vmparam.h>
#include <machine/minidump.h>
#include <machine/cpufunc.h>
#include <machine/vmparam.h>
CTASSERT(sizeof(struct kerneldumpheader) == 512);
@ -203,8 +203,7 @@ minidumpsys(struct dumperinfo *di)
* by time we get to here, all that remains is to flush the L1 for the
* current CPU, then the L2.
*/
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
dcache_wbinv_poc_all();
counter = 0;
/* Walk page table pages, set bits in vm_page_dump */

8
sys/arm/arm/mp_machdep.c
View File

@ -123,9 +123,7 @@ cpu_mp_start(void)
dpcpu[i] = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE,
M_WAITOK | M_ZERO);
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
cpu_idcache_wbinv_all();
dcache_wbinv_poc_all();
/* Initialize boot code and start up processors */
platform_mp_start_ap();
@ -283,7 +281,7 @@ ipi_stop(void *dummy __unused)
* stop will do the l2 cache flush after all other cores
* have done their l1 flushes and stopped.
*/
cpu_idcache_wbinv_all();
dcache_wbinv_poc_all();
/* Indicate we are stopped */
CPU_SET_ATOMIC(cpu, &stopped_cpus);
@ -381,7 +379,7 @@ ipi_handler(void *arg)
* stop will do the l2 cache flush after all other cores
* have done their l1 flushes and stopped.
*/
cpu_idcache_wbinv_all();
dcache_wbinv_poc_all();
/* Indicate we are stopped */
CPU_SET_ATOMIC(cpu, &stopped_cpus);

142
sys/arm/arm/pmap-v6.c
View File

@ -3,8 +3,8 @@
* Copyright (c) 1994 John S. Dyson
* Copyright (c) 1994 David Greenman
* Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
* Copyright (c) 2014 Svatopluk Kraus <onwahe@gmail.com>
* Copyright (c) 2014 Michal Meloun <meloun@miracle.cz>
* Copyright (c) 2014-2016 Svatopluk Kraus <skra@FreeBSD.org>
* Copyright (c) 2014-2016 Michal Meloun <mmel@FreeBSD.org>
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
@ -141,7 +141,6 @@ __FBSDID("$FreeBSD$");
#include <machine/md_var.h>
#include <machine/pmap_var.h>
#include <machine/cpu.h>
#include <machine/cpu-v6.h>
#include <machine/pcb.h>
#include <machine/sf_buf.h>
#ifdef SMP
@ -223,11 +222,14 @@ int pmap_debug_level = 1;
/*
* PTE2 descriptors creation macros.
*/
#define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, pt_memattr)
#define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, pt_memattr)
#define PTE2_ATTR_DEFAULT vm_memattr_to_pte2(VM_MEMATTR_DEFAULT)
#define PTE2_ATTR_PT vm_memattr_to_pte2(pt_memattr)
#define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_NORMAL)
#define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_NORMAL)
#define PTE2_KPT(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
#define PTE2_KPT_NG(pa) PTE2_KERN_NG(pa, PTE2_AP_KRW, PTE2_ATTR_PT)
#define PTE2_KRW(pa) PTE2_KERN(pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT)
#define PTE2_KRO(pa) PTE2_KERN(pa, PTE2_AP_KR, PTE2_ATTR_DEFAULT)
#define PV_STATS
#ifdef PV_STATS
@ -262,10 +264,6 @@ static uint32_t ttb_flags;
static vm_memattr_t pt_memattr;
ttb_entry_t pmap_kern_ttb;
/* XXX use converion function*/
#define PTE2_ATTR_NORMAL VM_MEMATTR_DEFAULT
#define PTE1_ATTR_NORMAL ATTR_TO_L1(PTE2_ATTR_NORMAL)
struct pmap kernel_pmap_store;
LIST_HEAD(pmaplist, pmap);
static struct pmaplist allpmaps;
@ -399,6 +397,37 @@ static uint32_t tex_class[8] = {
};
#undef TEX
static uint32_t pte2_attr_tab[8] = {
PTE2_ATTR_WB_WA, /* 0 - VM_MEMATTR_WB_WA */
PTE2_ATTR_NOCACHE, /* 1 - VM_MEMATTR_NOCACHE */
PTE2_ATTR_DEVICE, /* 2 - VM_MEMATTR_DEVICE */
PTE2_ATTR_SO, /* 3 - VM_MEMATTR_SO */
PTE2_ATTR_WT, /* 4 - VM_MEMATTR_WRITE_THROUGH */
0, /* 5 - NOT USED YET */
0, /* 6 - NOT USED YET */
0 /* 7 - NOT USED YET */
};
CTASSERT(VM_MEMATTR_WB_WA == 0);
CTASSERT(VM_MEMATTR_NOCACHE == 1);
CTASSERT(VM_MEMATTR_DEVICE == 2);
CTASSERT(VM_MEMATTR_SO == 3);
CTASSERT(VM_MEMATTR_WRITE_THROUGH == 4);
static inline uint32_t
vm_memattr_to_pte2(vm_memattr_t ma)
{
KASSERT((u_int)ma < 5, ("%s: bad vm_memattr_t %d", __func__, ma));
return (pte2_attr_tab[(u_int)ma]);
}
static inline uint32_t
vm_page_pte2_attr(vm_page_t m)
{
return (vm_memattr_to_pte2(m->md.pat_mode));
}
/*
* Convert TEX definition entry to TTB flags.
*/
@ -713,7 +742,7 @@ pmap_bootstrap_prepare(vm_paddr_t last)
pt1_entry_t *pte1p;
pt2_entry_t *pte2p;
u_int i;
uint32_t actlr_mask, actlr_set;
uint32_t actlr_mask, actlr_set, l1_attr;
/*
* Now, we are going to make real kernel mapping. Note that we are
@ -776,10 +805,10 @@ pmap_bootstrap_prepare(vm_paddr_t last)
pte1_store(pte1p++, PTE1_LINK(pa));
/* Make section mappings for kernel. */
l1_attr = ATTR_TO_L1(PTE2_ATTR_DEFAULT);
pte1p = kern_pte1(KERNBASE);
for (pa = KERNEL_V2P(KERNBASE); pa < last; pa += PTE1_SIZE)
pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW,
ATTR_TO_L1(PTE2_ATTR_WB_WA)));
pte1_store(pte1p++, PTE1_KERN(pa, PTE1_AP_KRW, l1_attr));
/*
* Get free and aligned space for PT2MAP and make L1 page table links
@ -988,13 +1017,14 @@ pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
vm_prot_t prot, vm_memattr_t attr)
{
u_int num;
u_int l1_attr, l1_prot, l2_prot;
u_int l1_attr, l1_prot, l2_prot, l2_attr;
pt1_entry_t *pte1p;
pt2_entry_t *pte2p;
l2_prot = prot & VM_PROT_WRITE ? PTE2_AP_KRW : PTE2_AP_KR;
l2_attr = vm_memattr_to_pte2(attr);
l1_prot = ATTR_TO_L1(l2_prot);
l1_attr = ATTR_TO_L1(attr);
l1_attr = ATTR_TO_L1(l2_attr);
/* Map all the pages. */
num = round_page(size);
@ -1007,7 +1037,7 @@ pmap_preboot_map_attr(vm_paddr_t pa, vm_offset_t va, vm_size_t size,
num -= PTE1_SIZE;
} else {
pte2p = pmap_preboot_vtopte2(va);
pte2_store(pte2p, PTE2_KERN(pa, l2_prot, attr));
pte2_store(pte2p, PTE2_KERN(pa, l2_prot, l2_attr));
va += PAGE_SIZE;
pa += PAGE_SIZE;
num -= PAGE_SIZE;
@ -1247,7 +1277,7 @@ PMAP_INLINE void
pmap_kenter(vm_offset_t va, vm_paddr_t pa)
{
pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_NORMAL);
pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEFAULT);
}
/*
@ -1320,7 +1350,8 @@ pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
vm_offset_t va, sva;
vm_paddr_t pte1_offset;
pt1_entry_t npte1;
u_int l1prot,l2prot;
uint32_t l1prot, l2prot;
uint32_t l1attr, l2attr;
PDEBUG(1, printf("%s: virt = %#x, start = %#x, end = %#x (size = %#x),"
" prot = %d\n", __func__, *virt, start, end, end - start, prot));
@ -1329,6 +1360,9 @@ pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
l2prot |= (prot & VM_PROT_EXECUTE) ? PTE2_X : PTE2_NX;
l1prot = ATTR_TO_L1(l2prot);
l2attr = PTE2_ATTR_DEFAULT;
l1attr = ATTR_TO_L1(l2attr);
va = *virt;
/*
* Does the physical address range's size and alignment permit at
@ -1351,13 +1385,12 @@ pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
if ((start & PTE1_OFFSET) == 0 && end - start >= PTE1_SIZE) {
KASSERT((va & PTE1_OFFSET) == 0,
("%s: misaligned va %#x", __func__, va));
npte1 = PTE1_KERN(start, l1prot, PTE1_ATTR_NORMAL);
npte1 = PTE1_KERN(start, l1prot, l1attr);
pmap_kenter_pte1(va, npte1);
va += PTE1_SIZE;
start += PTE1_SIZE;
} else {
pmap_kenter_prot_attr(va, start, l2prot,
PTE2_ATTR_NORMAL);
pmap_kenter_prot_attr(va, start, l2prot, l2attr);
va += PAGE_SIZE;
start += PAGE_SIZE;
}
@ -1527,7 +1560,7 @@ pmap_page_init(vm_page_t m)
TAILQ_INIT(&m->md.pv_list);
pt2_wirecount_init(m);
m->md.pat_mode = PTE2_ATTR_NORMAL;
m->md.pat_mode = VM_MEMATTR_DEFAULT;
}
/*
@ -1562,7 +1595,7 @@ pmap_pt2pg_zero(vm_page_t m)
if (pte2_load(sysmaps->CMAP2) != 0)
panic("%s: CMAP2 busy", __func__);
pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(pa, PTE2_AP_KRW,
m->md.pat_mode));
vm_page_pte2_attr(m)));
/* Even VM_ALLOC_ZERO request is only advisory. */
if ((m->flags & PG_ZERO) == 0)
pagezero(sysmaps->CADDR2);
@ -1586,7 +1619,7 @@ pmap_pt2pg_init(pmap_t pmap, vm_offset_t va, vm_page_t m)
pt2_entry_t *pte2p;
/* Check page attributes. */
if (pmap_page_get_memattr(m) != pt_memattr)
if (m->md.pat_mode != pt_memattr)
pmap_page_set_memattr(m, pt_memattr);
/* Zero page and init wire counts. */
@ -1717,10 +1750,10 @@ pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
pa = VM_PAGE_TO_PHYS(m);
pte2 = pte2_load(pte2p);
if ((pte2_pa(pte2) != pa) ||
(pte2_attr(pte2) != m->md.pat_mode)) {
(pte2_attr(pte2) != vm_page_pte2_attr(m))) {
anychanged++;
pte2_store(pte2p, PTE2_KERN(pa, PTE2_AP_KRW,
m->md.pat_mode));
vm_page_pte2_attr(m)));
}
pte2p++;
}
@ -3770,7 +3803,7 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
/*
* Now validate mapping with desired protection/wiring.
*/
npte2 = PTE2(pa, PTE2_NM, m->md.pat_mode);
npte2 = PTE2(pa, PTE2_NM, vm_page_pte2_attr(m));
if (prot & VM_PROT_WRITE) {
if (pte2_is_managed(npte2))
vm_page_aflag_set(m, PGA_WRITEABLE);
@ -3795,7 +3828,7 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
*/
if ((opte2 & ~(PTE2_NM | PTE2_A)) != (npte2 & ~(PTE2_NM | PTE2_A))) {
/*
* Sync icache if exec permission and attribute PTE2_ATTR_WB_WA
* Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
* is set. Do it now, before the mapping is stored and made
* valid for hardware table walk. If done later, there is a race
* for other threads of current process in lazy loading case.
@ -3810,7 +3843,7 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
* (2) Now, we do it on a page basis.
*/
if ((prot & VM_PROT_EXECUTE) && pmap != kernel_pmap &&
m->md.pat_mode == PTE2_ATTR_WB_WA &&
m->md.pat_mode == VM_MEMATTR_WB_WA &&
(opa != pa || (opte2 & PTE2_NX)))
cache_icache_sync_fresh(va, pa, PAGE_SIZE);
@ -4410,14 +4443,14 @@ pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
l2prot |= PTE2_U | PTE2_NG;
if ((prot & VM_PROT_EXECUTE) == 0)
l2prot |= PTE2_NX;
else if (m->md.pat_mode == PTE2_ATTR_WB_WA && pmap != kernel_pmap) {
else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
/*
* Sync icache if exec permission and attribute PTE2_ATTR_WB_WA
* Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
* is set. QQQ: For more info, see comments in pmap_enter().
*/
cache_icache_sync_fresh(va, pa, PAGE_SIZE);
}
pte2_store(pte2p, PTE2(pa, l2prot, m->md.pat_mode));
pte2_store(pte2p, PTE2(pa, l2prot, vm_page_pte2_attr(m)));
return (mpt2pg);
}
@ -4481,14 +4514,14 @@ pmap_enter_pte1(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
l1prot |= PTE1_U | PTE1_NG;
if ((prot & VM_PROT_EXECUTE) == 0)
l1prot |= PTE1_NX;
else if (m->md.pat_mode == PTE2_ATTR_WB_WA && pmap != kernel_pmap) {
else if (m->md.pat_mode == VM_MEMATTR_WB_WA && pmap != kernel_pmap) {
/*
* Sync icache if exec permission and attribute PTE2_ATTR_WB_WA
* Sync icache if exec permission and attribute VM_MEMATTR_WB_WA
* is set. QQQ: For more info, see comments in pmap_enter().
*/
cache_icache_sync_fresh(va, pa, PTE1_SIZE);
}
pte1_store(pte1p, PTE1(pa, l1prot, ATTR_TO_L1(m->md.pat_mode)));
pte1_store(pte1p, PTE1(pa, l1prot, ATTR_TO_L1(vm_page_pte2_attr(m))));
pmap_pte1_mappings++;
CTR3(KTR_PMAP, "%s: success for va %#lx in pmap %p", __func__, va,
@ -4552,7 +4585,7 @@ pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
pt1_entry_t *pte1p;
vm_paddr_t pa, pte2_pa;
vm_page_t p;
int pat_mode;
vm_memattr_t pat_mode;
u_int l1attr, l1prot;
VM_OBJECT_ASSERT_WLOCKED(object);
@ -4598,7 +4631,7 @@ pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
* is done here, so readonly mapping must be done elsewhere.
*/
l1prot = PTE1_U | PTE1_NG | PTE1_RW | PTE1_M | PTE1_A;
l1attr = ATTR_TO_L1(pat_mode);
l1attr = ATTR_TO_L1(vm_memattr_to_pte2(pat_mode));
PMAP_LOCK(pmap);
for (pa = pte2_pa; pa < pte2_pa + size; pa += PTE1_SIZE) {
pte1p = pmap_pte1(pmap, addr);
@ -5492,7 +5525,8 @@ pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
mtx_lock(&sysmaps->lock);
if (*sysmaps->CMAP2)
panic("%s: CMAP2 busy", __func__);
pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(pa, PTE2_AP_KRW, ma));
pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(pa, PTE2_AP_KRW,
vm_memattr_to_pte2(ma)));
dcache_wbinv_poc((vm_offset_t)sysmaps->CADDR2, pa, PAGE_SIZE);
pte2_clear(sysmaps->CMAP2);
tlb_flush((vm_offset_t)sysmaps->CADDR2);
@ -5583,7 +5617,7 @@ pmap_zero_page(vm_page_t m)
if (pte2_load(sysmaps->CMAP2) != 0)
panic("%s: CMAP2 busy", __func__);
pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
m->md.pat_mode));
vm_page_pte2_attr(m)));
pagezero(sysmaps->CADDR2);
pte2_clear(sysmaps->CMAP2);
tlb_flush((vm_offset_t)sysmaps->CADDR2);
@ -5608,7 +5642,7 @@ pmap_zero_page_area(vm_page_t m, int off, int size)
if (pte2_load(sysmaps->CMAP2) != 0)
panic("%s: CMAP2 busy", __func__);
pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
m->md.pat_mode));
vm_page_pte2_attr(m)));
if (off == 0 && size == PAGE_SIZE)
pagezero(sysmaps->CADDR2);
else
@ -5633,7 +5667,7 @@ pmap_zero_page_idle(vm_page_t m)
panic("%s: CMAP3 busy", __func__);
sched_pin();
pte2_store(CMAP3, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
m->md.pat_mode));
vm_page_pte2_attr(m)));
pagezero(CADDR3);
pte2_clear(CMAP3);
tlb_flush((vm_offset_t)CADDR3);
@ -5659,9 +5693,9 @@ pmap_copy_page(vm_page_t src, vm_page_t dst)
if (pte2_load(sysmaps->CMAP2) != 0)
panic("%s: CMAP2 busy", __func__);
pte2_store(sysmaps->CMAP1, PTE2_KERN_NG(VM_PAGE_TO_PHYS(src),
PTE2_AP_KR | PTE2_NM, src->md.pat_mode));
PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(src)));
pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(dst),
PTE2_AP_KRW, dst->md.pat_mode));
PTE2_AP_KRW, vm_page_pte2_attr(dst)));
bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
pte2_clear(sysmaps->CMAP1);
tlb_flush((vm_offset_t)sysmaps->CADDR1);
@ -5698,10 +5732,10 @@ pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
b_pg_offset = b_offset & PAGE_MASK;
cnt = min(cnt, PAGE_SIZE - b_pg_offset);
pte2_store(sysmaps->CMAP1, PTE2_KERN_NG(VM_PAGE_TO_PHYS(a_pg),
PTE2_AP_KR | PTE2_NM, a_pg->md.pat_mode));
PTE2_AP_KR | PTE2_NM, vm_page_pte2_attr(a_pg)));
tlb_flush_local((vm_offset_t)sysmaps->CADDR1);
pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(b_pg),
PTE2_AP_KRW, b_pg->md.pat_mode));
PTE2_AP_KRW, vm_page_pte2_attr(b_pg)));
tlb_flush_local((vm_offset_t)sysmaps->CADDR2);
a_cp = sysmaps->CADDR1 + a_pg_offset;
b_cp = sysmaps->CADDR2 + b_pg_offset;
@ -5731,7 +5765,7 @@ pmap_quick_enter_page(vm_page_t m)
KASSERT(pte2_load(pte2p) == 0, ("%s: PTE2 busy", __func__));
pte2_store(pte2p, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
pmap_page_get_memattr(m)));
vm_page_pte2_attr(m)));
return (qmap_addr);
}
@ -5993,13 +6027,15 @@ void
pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
{
vm_offset_t sva;
uint32_t l2attr;
KASSERT((size & PAGE_MASK) == 0,
("%s: device mapping not page-sized", __func__));
sva = va;
l2attr = vm_memattr_to_pte2(VM_MEMATTR_DEVICE);
while (size != 0) {
pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, PTE2_ATTR_DEVICE);
pmap_kenter_prot_attr(va, pa, PTE2_AP_KRW, l2attr);
va += PAGE_SIZE;
pa += PAGE_SIZE;
size -= PAGE_SIZE;
@ -6037,7 +6073,7 @@ pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
* The range must be within a single page.
*/
static void
pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, uint32_t attr)
{
struct sysmaps *sysmaps;
@ -6049,7 +6085,7 @@ pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
mtx_lock(&sysmaps->lock);
if (*sysmaps->CMAP3)
panic("%s: CMAP3 busy", __func__);
pte2_store(sysmaps->CMAP3, PTE2_KERN_NG(pa, PTE2_AP_KRW, ma));
pte2_store(sysmaps->CMAP3, PTE2_KERN_NG(pa, PTE2_AP_KRW, attr));
dcache_wb_pou((vm_offset_t)sysmaps->CADDR3 + (pa & PAGE_MASK), size);
pte2_clear(sysmaps->CMAP3);
tlb_flush((vm_offset_t)sysmaps->CADDR3);
@ -6073,7 +6109,7 @@ cache_icache_sync_fresh(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
m = PHYS_TO_VM_PAGE(pa);
KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
__func__, pa));
pmap_dcache_wb_pou(pa, len, m->md.pat_mode);
pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
}
/*
* I-cache is VIPT. Only way how to flush all virtual mappings
@ -6101,7 +6137,7 @@ pmap_sync_icache(pmap_t pmap, vm_offset_t va, vm_size_t size)
m = PHYS_TO_VM_PAGE(pa);
KASSERT(m != NULL, ("%s: vm_page_t is null for %#x",
__func__, pa));
pmap_dcache_wb_pou(pa, len, m->md.pat_mode);
pmap_dcache_wb_pou(pa, len, vm_page_pte2_attr(m));
}
}
/*
@ -6298,7 +6334,7 @@ pmap_zero_page_check(vm_page_t m)
if (pte2_load(sysmaps->CMAP2) != 0)
panic("%s: CMAP2 busy", __func__);
pte2_store(sysmaps->CMAP2, PTE2_KERN_NG(VM_PAGE_TO_PHYS(m), PTE2_AP_KRW,
m->md.pat_mode));
vm_page_pte2_attr(m)));
end = (uint32_t*)(sysmaps->CADDR2 + PAGE_SIZE);
for (p = (uint32_t*)sysmaps->CADDR2; p < end; p++)
if (*p != 0)

9
sys/arm/arm/sys_machdep.c
View File

@ -45,7 +45,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_extern.h>
#include <machine/acle-compat.h>
#include <machine/cpu-v6.h>
#include <machine/cpu.h>
#include <machine/sysarch.h>
#include <machine/vmparam.h>
@ -153,8 +153,13 @@ arm32_drain_writebuf(struct thread *td, void *args)
{
/* No args. */
td->td_retval[0] = 0;
#if __ARM_ARCH < 6
cpu_drain_writebuf();
#else
dsb();
cpu_l2cache_drain_writebuf();
#endif
td->td_retval[0] = 0;
return (0);
}

47
sys/arm/arm/trap-v6.c
View File

@ -55,7 +55,6 @@ __FBSDID("$FreeBSD$");
#include <machine/acle-compat.h>
#include <machine/cpu.h>
#include <machine/cpu-v6.h>
#include <machine/frame.h>
#include <machine/machdep.h>
#include <machine/pcb.h>
@ -70,7 +69,6 @@ __FBSDID("$FreeBSD$");
#include <sys/dtrace_bsd.h>
#endif
extern char fusubailout[];
extern char cachebailout[];
#ifdef DEBUG
@ -293,7 +291,10 @@ abort_handler(struct trapframe *tf, int prefetch)
#ifdef INVARIANTS
void *onfault;
#endif
PCPU_INC(cnt.v_trap);
td = curthread;
fsr = (prefetch) ? cp15_ifsr_get(): cp15_dfsr_get();
#if __ARM_ARCH >= 7
far = (prefetch) ? cp15_ifar_get() : cp15_dfar_get();
@ -334,24 +335,23 @@ abort_handler(struct trapframe *tf, int prefetch)
* they are not from KVA space. Thus, no action is needed here.
*/
/*
* (1) Handle access and R/W hardware emulation aborts.
* (2) Check that abort is not on pmap essential address ranges.
* There is no way how to fix it, so we don't even try.
*/
rv = pmap_fault(PCPU_GET(curpmap), far, fsr, idx, usermode);
if (rv == KERN_SUCCESS)
return;
if (rv == KERN_INVALID_ADDRESS)
goto nogo;
/*
* Now, when we handled imprecise and debug aborts, the rest of
* aborts should be really related to mapping.
*/
PCPU_INC(cnt.v_trap);
#ifdef KDB
if (kdb_active) {
kdb_reenter();
goto out;
}
#endif
if (rv == KERN_INVALID_ADDRESS)
goto nogo;
if (__predict_false((td->td_pflags & TDP_NOFAULTING) != 0)) {
/*
* Due to both processor errata and lazy TLB invalidation when
@ -417,6 +417,14 @@ abort_handler(struct trapframe *tf, int prefetch)
goto out;
}
/*
* At this point, we're dealing with one of the following aborts:
*
* FAULT_ICACHE - I-cache maintenance
* FAULT_TRAN_xx - Translation
* FAULT_PERM_xx - Permission
*/
/*
* Don't pass faulting cache operation to vm_fault(). We don't want
* to handle all vm stuff at this moment.
@ -435,23 +443,6 @@ abort_handler(struct trapframe *tf, int prefetch)
goto out;
}
/*
* At this point, we're dealing with one of the following aborts:
*
* FAULT_TRAN_xx - Translation
* FAULT_PERM_xx - Permission
*
* These are the main virtual memory-related faults signalled by
* the MMU.
*/
/* fusubailout is used by [fs]uswintr to avoid page faulting. */
if (__predict_false(pcb->pcb_onfault == fusubailout)) {
tf->tf_r0 = EFAULT;
tf->tf_pc = (register_t)pcb->pcb_onfault;
return;
}
va = trunc_page(far);
if (va >= KERNBASE) {
/*

9
sys/arm/arm/trap.c
View File

@ -111,8 +111,6 @@ __FBSDID("$FreeBSD$");
#define ReadWord(a) (*((volatile unsigned int *)(a)))
extern char fusubailout[];
#ifdef DEBUG
int last_fault_code; /* For the benefit of pmap_fault_fixup() */
#endif
@ -255,13 +253,6 @@ abort_handler(struct trapframe *tf, int type)
* the MMU.
*/
/* fusubailout is used by [fs]uswintr to avoid page faulting */
if (__predict_false(pcb->pcb_onfault == fusubailout)) {
tf->tf_r0 = EFAULT;
tf->tf_pc = (register_t)(intptr_t) pcb->pcb_onfault;
return;
}
/*
* Make sure the Program Counter is sane. We could fall foul of
* someone executing Thumb code, in which case the PC might not

1
sys/arm/arm/vm_machdep.c
View File

@ -54,6 +54,7 @@ __FBSDID("$FreeBSD$");
#include <sys/sysctl.h>
#include <sys/sysent.h>
#include <sys/unistd.h>
#include <sys/taskqueue.h>
#include <machine/acle-compat.h>
#include <machine/cpu.h>

4
sys/arm/at91/at91_machdep.c
View File

@ -566,7 +566,7 @@ initarm(struct arm_boot_params *abp)
arm_devmap_bootstrap(l1pagetable, at91_devmap);
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2));
@ -612,7 +612,7 @@ initarm(struct arm_boot_params *abp)
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* dirty data in the cache. This will have happened in cpu_setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.

4
sys/arm/broadcom/bcm2835/bcm2836_mp.c
View File

@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/bus.h>
#include <machine/fdt.h>
@ -123,8 +124,7 @@ platform_mp_start_ap(void)
BSWR4(MBOX3CLR_CORE(i), 0xffffffff);
}
wmb();
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
dcache_wbinv_poc_all();
/* boot secondary CPUs */
for (i = 1; i < mp_ncpus; i++) {

4
sys/arm/cavium/cns11xx/econa_machdep.c
View File

@ -275,7 +275,7 @@ initarm(struct arm_boot_params *abp)
arm_devmap_bootstrap(l1pagetable, econa_devmap);
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
cninit();
@ -297,7 +297,7 @@ initarm(struct arm_boot_params *abp)
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* dirty data in the cache. This will have happened in cpu_setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.

2
sys/arm/conf/NOTES
View File

@ -5,8 +5,6 @@ machine arm
cpu CPU_ARM9
cpu CPU_ARM9E
cpu CPU_FA526
cpu CPU_XSCALE_80219
cpu CPU_XSCALE_80321
cpu CPU_XSCALE_81342
cpu CPU_XSCALE_IXP425
cpu CPU_XSCALE_IXP435

3
sys/arm/freescale/imx/imx6_mp.c
View File

@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@ -149,7 +150,7 @@ platform_mp_start_ap(void)
val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
val | SCU_CONTROL_ENABLE);
cpu_idcache_wbinv_all();
dcache_wbinv_poc_all();
/*
* For each AP core, set the entry point address and argument registers,

186
sys/arm/include/cpu-v4.h Normal file
View File

@ -0,0 +1,186 @@
/*-
* Copyright 2016 Svatopluk Kraus <skra@FreeBSD.org>
* Copyright 2016 Michal Meloun <mmel@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef MACHINE_CPU_V4_H
#define MACHINE_CPU_V4_H
/* There are no user serviceable parts here, they may change without notice */
#ifndef _KERNEL
#error Only include this file in the kernel
#endif
#include <machine/acle-compat.h>
#include <machine/atomic.h>
#include <machine/cpufunc.h>
#include <machine/cpuinfo.h>
#include <machine/sysreg.h>
#if __ARM_ARCH >= 6
#error Never include this file for ARMv6
#else
#define CPU_ASID_KERNEL 0
/*
* Macros to generate CP15 (system control processor) read/write functions.
*/
#define _FX(s...) #s
#define _RF0(fname, aname...) \
static __inline register_t \
fname(void) \
{ \
register_t reg; \
__asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \
return(reg); \
}
#define _R64F0(fname, aname) \
static __inline uint64_t \
fname(void) \
{ \
uint64_t reg; \
__asm __volatile("mrrc\t" _FX(aname): "=r" (reg)); \
return(reg); \
}
#define _WF0(fname, aname...) \
static __inline void \
fname(void) \
{ \
__asm __volatile("mcr\t" _FX(aname)); \
}
#define _WF1(fname, aname...) \
static __inline void \
fname(register_t reg) \
{ \
__asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \
}
/*
* Publicly accessible functions
*/
/* Various control registers */
_RF0(cp15_cpacr_get, CP15_CPACR(%0))
_WF1(cp15_cpacr_set, CP15_CPACR(%0))
_RF0(cp15_dfsr_get, CP15_DFSR(%0))
_RF0(cp15_ttbr_get, CP15_TTBR0(%0))
_RF0(cp15_dfar_get, CP15_DFAR(%0))
/* XScale */
_RF0(cp15_actlr_get, CP15_ACTLR(%0))
_WF1(cp15_actlr_set, CP15_ACTLR(%0))
/*CPU id registers */
_RF0(cp15_midr_get, CP15_MIDR(%0))
_RF0(cp15_ctr_get, CP15_CTR(%0))
_RF0(cp15_tcmtr_get, CP15_TCMTR(%0))
_RF0(cp15_tlbtr_get, CP15_TLBTR(%0))
#undef _FX
#undef _RF0
#undef _WF0
#undef _WF1
/*
* armv4/5 compatibility shims.
*
* These functions provide armv4 cache maintenance using the new armv6 names.
* Included here are just the functions actually used now in common code; it may
* be necessary to add things here over time.
*
* The callers of the dcache functions expect these routines to handle address
* and size values which are not aligned to cacheline boundaries; the armv4 and
* armv5 asm code handles that.
*/
static __inline void
tlb_flush_all(void)
{
cpu_tlb_flushID();
cpu_cpwait();
}
static __inline void
icache_sync(vm_offset_t va, vm_size_t size)
{
cpu_icache_sync_range(va, size);
}
static __inline void
dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
cpu_dcache_inv_range(va, size);
#ifdef ARM_L2_PIPT
cpu_l2cache_inv_range(pa, size);
#else
cpu_l2cache_inv_range(va, size);
#endif
}
static __inline void
dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
/* See armv6 code, above, for why we do L2 before L1 in this case. */
#ifdef ARM_L2_PIPT
cpu_l2cache_inv_range(pa, size);
#else
cpu_l2cache_inv_range(va, size);
#endif
cpu_dcache_inv_range(va, size);
}
static __inline void
dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
cpu_dcache_wb_range(va, size);
#ifdef ARM_L2_PIPT
cpu_l2cache_wb_range(pa, size);
#else
cpu_l2cache_wb_range(va, size);
#endif
}
static __inline void
dcache_wbinv_poc_all(void)
{
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
}
#endif /* _KERNEL */
#endif /* MACHINE_CPU_V4_H */

71
sys/arm/include/cpu-v6.h
View File

@ -32,19 +32,32 @@
/* There are no user serviceable parts here, they may change without notice */
#ifndef _KERNEL
#error Only include this file in the kernel
#else
#endif
#include <machine/acle-compat.h>
#include "machine/atomic.h"
#include "machine/cpufunc.h"
#include "machine/cpuinfo.h"
#include "machine/sysreg.h"
#include <machine/atomic.h>
#include <machine/cpufunc.h>
#include <machine/cpuinfo.h>
#include <machine/sysreg.h>
#if __ARM_ARCH < 6
#error Only include this file for ARMv6
#else
#define CPU_ASID_KERNEL 0
void dcache_wbinv_poc_all(void); /* !!! NOT SMP coherent function !!! */
vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
#ifdef DEV_PMU
#include <sys/pcpu.h>
#define PMU_OVSR_C 0x80000000 /* Cycle Counter */
extern uint32_t ccnt_hi[MAXCPU];
extern int pmu_attched;
#endif /* DEV_PMU */
/*
* Macros to generate CP15 (system control processor) read/write functions.
*/
@ -277,12 +290,6 @@ _W64F1(cp15_cnthp_cval_set, CP15_CNTHP_CVAL(%Q0, %R0))
#undef _WF0
#undef _WF1
#if __ARM_ARCH >= 6
/*
* Cache and TLB maintenance operations for armv6+ code. The #else block
* provides armv4/v5 implementations for a few of these used in common code.
*/
/*
* TLB maintenance operations.
*/
@ -577,48 +584,6 @@ cp15_ttbr_set(uint32_t reg)
isb();
tlb_flush_all_ng_local();
}
#else /* ! __ARM_ARCH >= 6 */
/*
* armv4/5 compatibility shims.
*
* These functions provide armv4 cache maintenance using the new armv6 names.
* Included here are just the functions actually used now in common code; it may
* be necessary to add things here over time.
*
* The callers of the dcache functions expect these routines to handle address
* and size values which are not aligned to cacheline boundaries; the armv4 and
* armv5 asm code handles that.
*/
static __inline void
dcache_inv_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
cpu_dcache_inv_range(va, size);
cpu_l2cache_inv_range(va, size);
}
static __inline void
dcache_inv_poc_dma(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
/* See armv6 code, above, for why we do L2 before L1 in this case. */
cpu_l2cache_inv_range(va, size);
cpu_dcache_inv_range(va, size);
}
static __inline void
dcache_wb_poc(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
{
cpu_dcache_wb_range(va, size);
cpu_l2cache_wb_range(va, size);
}
#endif /* __ARM_ARCH >= 6 */
#endif /* _KERNEL */
#endif /* !MACHINE_CPU_V6_H */

8
sys/arm/include/cpu.h
View File

@ -14,12 +14,8 @@ void swi_vm(void *);
#ifdef _KERNEL
#if __ARM_ARCH >= 6
#include <machine/cpu-v6.h>
#ifdef DEV_PMU
#include <sys/pcpu.h>
#define PMU_OVSR_C 0x80000000 /* Cycle Counter */
extern uint32_t ccnt_hi[MAXCPU];
extern int pmu_attched;
#endif /* DEV_PMU */
#else
#include <machine/cpu-v4.h>
#endif /* __ARM_ARCH >= 6 */
static __inline uint64_t

14
sys/arm/include/cpuconf.h
View File

@ -53,7 +53,6 @@
#define CPU_NTYPES (defined(CPU_ARM9) + \
defined(CPU_ARM9E) + \
defined(CPU_ARM1176) + \
defined(CPU_XSCALE_80321) + \
defined(CPU_XSCALE_PXA2X0) + \
defined(CPU_FA526) + \
defined(CPU_XSCALE_IXP425)) + \
@ -71,8 +70,7 @@
#endif
#if (defined(CPU_ARM9E) || \
defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
defined(CPU_XSCALE_81342) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
#define ARM_ARCH_5 1
#else
@ -163,9 +161,8 @@
#define ARM_MMU_V7 0
#endif
#if (defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
#if (defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_81342))
#define ARM_MMU_XSCALE 1
#else
#define ARM_MMU_XSCALE 0
@ -180,11 +177,10 @@
/*
* Step 4: Define features that may be present on a subset of CPUs
*
* ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321
* ARM_XSCALE_PMU Performance Monitoring Unit on 81342
*/
#if (defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
#if (defined(CPU_XSCALE_81342))
#define ARM_XSCALE_PMU 1
#else
#define ARM_XSCALE_PMU 0

33
sys/arm/include/cpufunc.h
View File

@ -79,7 +79,6 @@ struct cpu_functions {
*
* We define the following primitives:
*
* icache_sync_all Synchronize I-cache
* icache_sync_range Synchronize I-cache range
*
* dcache_wbinv_all Write-back and Invalidate D-cache
@ -104,7 +103,7 @@ struct cpu_functions {
* state (such as when it may have lines tagged as valid
* that belong to a previous set of mappings).
*
* I-cache Synch (all or range):
* I-cache Sync range:
* The goal is to synchronize the instruction stream,
* so you may beed to write-back dirty D-cache blocks
* first. If a range is requested, and you can't
@ -130,7 +129,6 @@ struct cpu_functions {
* Valid virtual addresses must be passed to each
* cache operation.
*/
void (*cf_icache_sync_all) (void);
void (*cf_icache_sync_range) (vm_offset_t, vm_size_t);
void (*cf_dcache_wbinv_all) (void);
@ -163,9 +161,12 @@ struct cpu_functions {
extern struct cpu_functions cpufuncs;
extern u_int cputype;
#if __ARM_ARCH < 6
#define cpu_cpwait() cpufuncs.cf_cpwait()
#endif
#define cpu_control(c, e) cpufuncs.cf_control(c, e)
#if __ARM_ARCH < 6
#define cpu_setttb(t) cpufuncs.cf_setttb(t)
#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
@ -173,7 +174,6 @@ extern u_int cputype;
#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
@ -184,13 +184,16 @@ extern u_int cputype;
#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all()
#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
#endif
#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
#define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
#if __ARM_ARCH < 6
#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
#endif
#define cpu_sleep(m) cpufuncs.cf_sleep(m)
#define cpu_setup() cpufuncs.cf_setup()
@ -205,6 +208,7 @@ u_int cpufunc_control (u_int clear, u_int bic);
void cpu_domains (u_int domains);
u_int cpu_faultstatus (void);
u_int cpu_faultaddress (void);
u_int cpu_get_control (void);
u_int cpu_pfr (int);
#if defined(CPU_FA526)
@ -214,7 +218,6 @@ void fa526_context_switch (void);
void fa526_cpu_sleep (int);
void fa526_tlb_flushID_SE (u_int);
void fa526_icache_sync_all (void);
void fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
void fa526_dcache_wbinv_all (void);
void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
@ -231,8 +234,7 @@ void arm9_tlb_flushID_SE (u_int va);
void arm9_context_switch (void);
#endif
#if defined(CPU_ARM9)
void arm9_icache_sync_all (void);
#if defined(CPU_ARM9)
void arm9_icache_sync_range (vm_offset_t, vm_size_t);
void arm9_dcache_wbinv_all (void);
@ -275,7 +277,6 @@ void armv6_idcache_wbinv_all (void);
void armv7_setttb (u_int);
void armv7_tlb_flushID (void);
void armv7_tlb_flushID_SE (u_int);
void armv7_icache_sync_all (void);
void armv7_icache_sync_range (vm_offset_t, vm_size_t);
void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t);
void armv7_idcache_inv_all (void);
@ -319,7 +320,6 @@ void armv6_idcache_inv_all (void);
void arm11x6_setttb (u_int);
void arm11x6_idcache_wbinv_all (void);
void arm11x6_dcache_wbinv_all (void);
void arm11x6_icache_sync_all (void);
void arm11x6_icache_sync_range (vm_offset_t, vm_size_t);
void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t);
void arm11x6_setup (void);
@ -329,7 +329,6 @@ void arm11x6_sleep (int); /* no ref. for errata */
#if defined(CPU_ARM9E)
void armv5_ec_setttb(u_int);
void armv5_ec_icache_sync_all(void);
void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
void armv5_ec_dcache_wbinv_all(void);
@ -342,10 +341,9 @@ void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
#endif
#if defined(CPU_ARM9) || defined(CPU_ARM9E) || \
defined(CPU_XSCALE_80321) || \
defined(CPU_FA526) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
defined(CPU_XSCALE_81342)
void armv4_tlb_flushID (void);
void armv4_tlb_flushD (void);
@ -355,9 +353,8 @@ void armv4_drain_writebuf (void);
void armv4_idcache_inv_all (void);
#endif
#if defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
#if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_81342)
void xscale_cpwait (void);
void xscale_cpu_sleep (int mode);
@ -395,8 +392,7 @@ void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
void xscale_context_switch (void);
void xscale_setup (void);
#endif /* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
CPU_XSCALE_80219 */
#endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
#ifdef CPU_XSCALE_81342
@ -423,9 +419,6 @@ void xscalec3_context_switch (void);
#endif /* CPU_XSCALE_81342 */
#define setttb cpu_setttb
#define drain_writebuf cpu_drain_writebuf
/*
* Macros for manipulating CPU interrupts
*/

6
sys/arm/include/kdb.h
View File

@ -29,10 +29,10 @@
#ifndef _MACHINE_KDB_H_
#define _MACHINE_KDB_H_
#include <machine/cpu.h>
#include <machine/db_machdep.h>
#include <machine/frame.h>
#include <machine/psl.h>
#include <machine/cpufunc.h>
#include <machine/db_machdep.h>
#define KDB_STOPPEDPCB(pc) &stoppcbs[pc->pc_cpuid]
@ -56,7 +56,7 @@ static __inline void
kdb_cpu_sync_icache(unsigned char *addr, size_t size)
{
cpu_icache_sync_range((vm_offset_t)addr, size);
icache_sync((vm_offset_t)addr, size);
}
static __inline void

6
sys/arm/include/pmap-v6.h
View File

@ -115,7 +115,7 @@ struct pv_chunk;
struct md_page {
TAILQ_HEAD(,pv_entry) pv_list;
uint16_t pt2_wirecount[4];
int pat_mode;
vm_memattr_t pat_mode;
};
struct pmap {
@ -173,7 +173,7 @@ struct pv_chunk {
struct pcb;
extern ttb_entry_t pmap_kern_ttb; /* TTB for kernel pmap */
#define pmap_page_get_memattr(m) ((vm_memattr_t)(m)->md.pat_mode)
#define pmap_page_get_memattr(m) ((m)->md.pat_mode)
#define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0)
/*
@ -250,6 +250,8 @@ void pmap_preboot_map_attr(vm_paddr_t, vm_offset_t, vm_size_t, vm_prot_t,
*/
void vector_page_setprot(int);
#define PTE_DEVICE VM_MEMATTR_DEVICE
#endif /* _KERNEL */
// -----------------------------------------------------------------------------

10
sys/arm/include/vm.h
View File

@ -34,11 +34,11 @@
#if __ARM_ARCH >= 6
#include <machine/pte-v6.h>
#define VM_MEMATTR_WB_WA ((vm_memattr_t)PTE2_ATTR_WB_WA)
#define VM_MEMATTR_NOCACHE ((vm_memattr_t)PTE2_ATTR_NOCACHE)
#define VM_MEMATTR_DEVICE ((vm_memattr_t)PTE2_ATTR_DEVICE)
#define VM_MEMATTR_SO ((vm_memattr_t)PTE2_ATTR_SO)
#define VM_MEMATTR_WRITE_THROUGH ((vm_memattr_t)PTE2_ATTR_WT)
#define VM_MEMATTR_WB_WA ((vm_memattr_t)0)
#define VM_MEMATTR_NOCACHE ((vm_memattr_t)1)
#define VM_MEMATTR_DEVICE ((vm_memattr_t)2)
#define VM_MEMATTR_SO ((vm_memattr_t)3)
#define VM_MEMATTR_WRITE_THROUGH ((vm_memattr_t)4)
#define VM_MEMATTR_DEFAULT VM_MEMATTR_WB_WA
#define VM_MEMATTR_UNCACHEABLE VM_MEMATTR_SO /* misused by DMA */

5
sys/arm/mv/armada38x/pmsu.c
View File

@ -36,10 +36,12 @@ __FBSDID("$FreeBSD$");
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/resource.h>
#include <sys/systm.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/cpu.h>
#include <machine/fdt.h>
#include <machine/smp.h>
@ -143,8 +145,7 @@ pmsu_boot_secondary_cpu(void)
bus_space_write_4(fdtbus_bs_tag, vaddr, PMSU_BOOT_ADDR_REDIRECT_OFFSET(1),
pmap_kextract((vm_offset_t)mpentry));
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
dcache_wbinv_poc_all();
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, vaddr, MV_PMSU_REGS_LEN);

3
sys/arm/mv/armadaxp/armadaxp_mp.c
View File

@ -40,6 +40,7 @@
#include <dev/fdt/fdt_common.h>
#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/armreg.h>
@ -174,7 +175,7 @@ platform_mp_start_ap(void)
bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT,
pmap_kextract((vm_offset_t)mpentry));
cpu_idcache_wbinv_all();
dcache_wbinv_poc_all();
for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0);

4
sys/arm/rockchip/rk30xx_mp.c
View File

@ -36,6 +36,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@ -171,8 +172,7 @@ platform_mp_start_ap(void)
bus_space_write_region_4(fdtbus_bs_tag, imem, 0,
(uint32_t *)&rk30xx_boot2, 8);
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
dcache_wbinv_poc_all();
/* Start all cores */
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);

4
sys/arm/samsung/exynos/exynos5_mp.c
View File

@ -36,6 +36,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@ -135,8 +136,7 @@ platform_mp_start_ap(void)
bus_space_write_4(fdtbus_bs_tag, sysram, 0x0,
pmap_kextract((vm_offset_t)mpentry));
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
dcache_wbinv_poc_all();
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, sysram, 0x100);

5
sys/arm/ti/omap4/omap4_mp.c
View File

@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@ -72,8 +73,8 @@ platform_mp_start_ap(void)
/* Enable the SCU */
*(volatile unsigned int *)scu_addr |= 1;
//*(volatile unsigned int *)(scu_addr + 0x30) |= 1;
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
dcache_wbinv_poc_all();
ti_smc0(0x200, 0xfffffdff, MODIFY_AUX_CORE_0);
ti_smc0(pmap_kextract((vm_offset_t)mpentry), 0, WRITE_AUX_CORE_1);
armv7_sev();

4
sys/arm/xilinx/zy7_mp.c
View File

@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/cpu.h>
#include <machine/smp.h>
#include <machine/fdt.h>
#include <machine/intr.h>
@ -104,8 +105,7 @@ platform_mp_start_ap(void)
* magic location, 0xfffffff0, isn't in the SCU's filtering range so it
* needs a write-back too.
*/
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
dcache_wbinv_poc_all();
/* Wake up CPU1. */
armv7_sev();

402
sys/arm/xscale/i80321/ep80219_machdep.c
View File

@ -1,402 +0,0 @@
/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */
/*-
* Copyright (c) 1994-1998 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* machdep.c
*
* Machine dependant functions for kernel setup
*
* This file needs a lot of work.
*
* Created : 17/09/94
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_kstack_pages.h"
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sysproto.h>
#include <sys/signalvar.h>
#include <sys/imgact.h>
#include <sys/kernel.h>
#include <sys/ktr.h>
#include <sys/linker.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/pcpu.h>
#include <sys/proc.h>
#include <sys/ptrace.h>
#include <sys/cons.h>
#include <sys/bio.h>
#include <sys/bus.h>
#include <sys/buf.h>
#include <sys/exec.h>
#include <sys/kdb.h>
#include <sys/msgbuf.h>
#include <machine/reg.h>
#include <machine/cpu.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
#include <machine/devmap.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
#include <machine/machdep.h>
#include <machine/metadata.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/physmem.h>
#include <sys/reboot.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/iq80321reg.h>
#include <arm/xscale/i80321/obiovar.h>
#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
#define KERNEL_PT_IOPXS 1
#define KERNEL_PT_BEFOREKERN 2
#define KERNEL_PT_AFKERNEL 3 /* L2 table for mapping after kernel */
#define KERNEL_PT_AFKERNEL_NUM 9
/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
/* Physical and virtual addresses for some global pages */
struct pv_addr systempage;
struct pv_addr msgbufpv;
struct pv_addr irqstack;
struct pv_addr undstack;
struct pv_addr abtstack;
struct pv_addr kernelstack;
struct pv_addr minidataclean;
/* #define IQ80321_OBIO_BASE 0xfe800000UL */
/* #define IQ80321_OBIO_SIZE 0x00100000UL */
/* Static device mappings. */
static const struct arm_devmap_entry ep80219_devmap[] = {
/*
* Map the on-board devices VA == PA so that we can access them
* with the MMU on or off.
*/
{
IQ80321_OBIO_BASE,
IQ80321_OBIO_BASE,
IQ80321_OBIO_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_DEVICE,
},
{
IQ80321_IOW_VBASE,
VERDE_OUT_XLATE_IO_WIN0_BASE,
VERDE_OUT_XLATE_IO_WIN_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_DEVICE,
},
{
IQ80321_80321_VBASE,
VERDE_PMMR_BASE,
VERDE_PMMR_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_DEVICE,
},
{
0,
0,
0,
0,
0,
}
};
extern vm_offset_t xscale_cache_clean_addr;
void *
initarm(struct arm_boot_params *abp)
{
struct pv_addr kernel_l1pt;
struct pv_addr dpcpu;
int loop, i;
u_int l1pagetable;
vm_offset_t freemempos;
vm_offset_t freemem_pt;
vm_offset_t afterkern;
vm_offset_t freemem_after;
vm_offset_t lastaddr;
uint32_t memsize, memstart;
lastaddr = parse_boot_param(abp);
arm_physmem_kernaddr = abp->abp_physaddr;
set_cpufuncs();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
/* Do basic tuning, hz etc */
init_param1();
freemempos = 0xa0200000;
/* Define a macro to simplify memory allocation */
#define valloc_pages(var, np) \
alloc_pages((var).pv_pa, (np)); \
(var).pv_va = (var).pv_pa + 0x20000000;
#define alloc_pages(var, np) \
freemempos -= (np * PAGE_SIZE); \
(var) = freemempos; \
memset((char *)(var), 0, ((np) * PAGE_SIZE));
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
freemempos -= PAGE_SIZE;
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
valloc_pages(kernel_pt_table[loop],
L2_TABLE_SIZE / PAGE_SIZE);
} else {
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa + 0x20000000;
}
}
freemem_pt = freemempos;
freemempos = 0xa0100000;
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
valloc_pages(systempage, 1);
/* Allocate dynamic per-cpu area. */
valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
dpcpu_init((void *)dpcpu.pv_va, 0);
/* Allocate stacks for all modes */
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, kstack_pages);
alloc_pages(minidataclean.pv_pa, 1);
valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
/*
* Allocate memory for the l1 and l2 page tables. The scheme to avoid
* wasting memory by allocating the l1pt on the first 16k memory was
* taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
* this to work (which is supposed to be the case).
*/
/*
* Now we start construction of the L1 page table
* We start by mapping the L2 page tables into the L1.
* This means that we can replace L1 mappings later on if necessary
*/
l1pagetable = kernel_l1pt.pv_va;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
&kernel_pt_table[KERNEL_PT_SYS]);
pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE,
&kernel_pt_table[KERNEL_PT_IOPXS]);
pmap_link_l2pt(l1pagetable, KERNBASE,
&kernel_pt_table[KERNEL_PT_BEFOREKERN]);
pmap_map_chunk(l1pagetable, KERNBASE, IQ80321_SDRAM_START, 0x100000,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, IQ80321_SDRAM_START + 0x100000,
0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, IQ80321_SDRAM_START + 0x200000,
(((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
- 1));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
/* Map the Mini-Data cache clean area. */
xscale_setup_minidata(l1pagetable, afterkern,
minidataclean.pv_pa);
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
arm_devmap_bootstrap(l1pagetable, ep80219_devmap);
/*
* Give the XScale global cache clean code an appropriately
* sized chunk of unmapped VA space starting at 0xff000000
* (our device mappings end before this address).
*/
xscale_cache_clean_addr = 0xff000000U;
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
set_stackptrs(0);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross relocations of the kernel thus
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
cpu_setup();
/*
* Fetch the SDRAM start/size from the i80321 SDRAM configration
* registers.
*/
i80321_calibrate_delay();
i80321_sdram_bounds(obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE,
&memstart, &memsize);
physmem = memsize / PAGE_SIZE;
cninit();
undefined_init();
init_proc0(kernelstack.pv_va);
/* Enable MMU, I-cache, D-cache, write buffer. */
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
vm_max_kernel_address = 0xe0000000;
pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, msgbufsize);
mutex_init();
/*
* Add the physical ram we have available.
*
* Exclude the kernel (and all the things we allocated which immediately
* follow the kernel) from the VM allocation pool but not from crash
* dumps. virtual_avail is a global variable which tracks the kva we've
* "allocated" while setting up pmaps.
*
* Prepare the list of physical memory available to the vm subsystem.
*/
arm_physmem_hardware_region(IQ80321_SDRAM_START, memsize);
arm_physmem_exclude_region(freemem_pt, abp->abp_physaddr -
freemem_pt, EXFLAG_NOALLOC);
arm_physmem_exclude_region(freemempos, abp->abp_physaddr - 0x100000 -
freemempos, EXFLAG_NOALLOC);
arm_physmem_exclude_region(abp->abp_physaddr,
virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
arm_physmem_init_kernel_globals();
init_param2(physmem);
kdb_init();
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb)));
}
extern int
machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin)
{
int bus;
int device;
int func;
uint32_t busno;
struct i80321_pci_softc *sc = device_get_softc(pcib);
bus = pci_get_bus(dev);
device = pci_get_slot(dev);
func = pci_get_function(dev);
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
if (bus != busno)
goto no_mapping;
switch (device) {
/* EP80219 PCI */
case 1: /* Ethernet i82555 10/100 */
printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(0));
return (ICU_INT_XINT(0));
case 2: /* UART */
printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(1));
return (ICU_INT_XINT(1));
case 3:
/*
* The S-ATA chips are behind the bridge, and all of
* the S-ATA interrupts are wired together.
*/
printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(2));
return (ICU_INT_XINT(2));
case 4: /* MINI-PIC_INT */
printf("Device %d routed to irq %d\n", device, ICU_INT_XINT(3));
return( ICU_INT_XINT(3));
default:
no_mapping:
printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin);
}
return (0);
}

11
sys/arm/xscale/i80321/files.ep80219
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@ -1,11 +0,0 @@
#$FreeBSD$
#
#
# EP80219 Board Specific
#
arm/xscale/i80321/iq80321.c standard
arm/xscale/i80321/ep80219_machdep.c standard
arm/xscale/i80321/obio.c standard
arm/xscale/i80321/uart_cpu_i80321.c optional uart
arm/xscale/i80321/uart_bus_i80321.c optional uart
dev/uart/uart_dev_ns8250.c optional uart

11
sys/arm/xscale/i80321/files.i80219
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@ -1,11 +0,0 @@
#$FreeBSD$
#
# IOP Specific
#
arm/xscale/i80321/i80321.c standard
arm/xscale/i80321/i80321_dma.c optional dma
arm/xscale/i80321/i80321_mcu.c standard
arm/xscale/i80321/i80321_pci.c optional pci
arm/xscale/i80321/i80321_space.c standard
arm/xscale/i80321/i80321_timer.c standard
arm/xscale/i80321/i80321_wdog.c optional iopwdog

9
sys/arm/xscale/i80321/files.i80321
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@ -1,9 +0,0 @@
#$FreeBSD$
arm/xscale/i80321/i80321.c standard
arm/xscale/i80321/i80321_aau.c optional aau
arm/xscale/i80321/i80321_dma.c optional dma
arm/xscale/i80321/i80321_mcu.c standard
arm/xscale/i80321/i80321_pci.c optional pci
arm/xscale/i80321/i80321_space.c standard
arm/xscale/i80321/i80321_timer.c standard
arm/xscale/i80321/i80321_wdog.c optional iopwdog

8
sys/arm/xscale/i80321/files.iq31244
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@ -1,8 +0,0 @@
#$FreeBSD$
arm/xscale/i80321/iq80321.c standard
arm/xscale/i80321/iq31244_machdep.c standard
arm/xscale/i80321/iq31244_7seg.c optional iq31244_7seg
arm/xscale/i80321/obio.c standard
arm/xscale/i80321/uart_cpu_i80321.c optional uart
arm/xscale/i80321/uart_bus_i80321.c optional uart
dev/uart/uart_dev_ns8250.c optional uart

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sys/arm/xscale/i80321/i80321.c
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@ -1,250 +0,0 @@
/* $NetBSD: i80321.c,v 1.15 2003/10/06 16:06:05 thorpej Exp $ */
/*-
* Copyright (c) 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Autoconfiguration support for the Intel i80321 I/O Processor.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#define _ARM32_BUS_DMA_PRIVATE
#include <machine/bus.h>
#include <machine/intr.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/i80321_intr.h>
#include <dev/pci/pcireg.h>
volatile uint32_t intr_enabled;
uint32_t intr_steer = 0;
/*
* Statically-allocated bus_space stucture used to access the
* i80321's own registers.
*/
struct bus_space i80321_bs_tag;
/*
* There can be only one i80321, so we keep a global pointer to
* the softc, so board-specific code can use features of the
* i80321 without having to have a handle on the softc itself.
*/
struct i80321_softc *i80321_softc;
#define PCI_MAPREG_MEM_ADDR(x) ((x) & 0xfffffff0)
/*
* i80321_attach:
*
* Board-independent attach routine for the i80321.
*/
void
i80321_attach(struct i80321_softc *sc)
{
i80321_softc = sc;
uint32_t preg;
/* We expect the Memory Controller to be already sliced off. */
/*
* Program the Inbound windows.
*/
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0,
(0xffffffff - (sc->sc_iwin[0].iwin_size - 1)) & 0xffffffc0);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR0,
sc->sc_iwin[0].iwin_xlate);
if (sc->sc_is_host) {
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_BARS, sc->sc_iwin[0].iwin_base_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_BARS + 0x04, sc->sc_iwin[0].iwin_base_hi);
} else {
sc->sc_iwin[0].iwin_base_lo = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_BARS);
sc->sc_iwin[0].iwin_base_hi = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_BARS + 0x04);
sc->sc_iwin[0].iwin_base_lo =
PCI_MAPREG_MEM_ADDR(sc->sc_iwin[0].iwin_base_lo);
}
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1,
(0xffffffff - (sc->sc_iwin[1].iwin_size - 1)) & 0xffffffc0);
/* no xlate for window 1 */
if (sc->sc_is_host) {
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_BARS + 0x08, sc->sc_iwin[1].iwin_base_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_BARS + 0x0c, sc->sc_iwin[1].iwin_base_hi);
} else {
sc->sc_iwin[1].iwin_base_lo = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_BARS + 0x08);
sc->sc_iwin[1].iwin_base_hi = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_BARS + 0x0c);
sc->sc_iwin[1].iwin_base_lo =
PCI_MAPREG_MEM_ADDR(sc->sc_iwin[1].iwin_base_lo);
}
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2,
(0xffffffff - (sc->sc_iwin[2].iwin_size - 1)) & 0xffffffc0);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR2,
sc->sc_iwin[2].iwin_xlate);
if (sc->sc_is_host) {
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_BARS + 0x10, sc->sc_iwin[2].iwin_base_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_BARS + 0x14, sc->sc_iwin[2].iwin_base_hi);
} else {
sc->sc_iwin[2].iwin_base_lo = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_BARS + 0x10);
sc->sc_iwin[2].iwin_base_hi = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, PCIR_BARS + 0x14);
sc->sc_iwin[2].iwin_base_lo =
PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo);
}
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR3,
(0xffffffff - (sc->sc_iwin[3].iwin_size - 1)) & 0xffffffc0);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR3,
sc->sc_iwin[3].iwin_xlate);
if (sc->sc_is_host) {
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_IABAR3, sc->sc_iwin[3].iwin_base_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_IAUBAR3, sc->sc_iwin[3].iwin_base_hi);
} else {
sc->sc_iwin[3].iwin_base_lo = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, ATU_IABAR3);
sc->sc_iwin[3].iwin_base_hi = bus_space_read_4(sc->sc_st,
sc->sc_atu_sh, ATU_IAUBAR3);
sc->sc_iwin[3].iwin_base_lo =
PCI_MAPREG_MEM_ADDR(sc->sc_iwin[3].iwin_base_lo);
}
/*
* Mask (disable) the ATU interrupt sources.
* XXX May want to revisit this if we encounter
* XXX an application that wants it.
*/
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_ATUIMR,
ATUIMR_IMW1BU|ATUIMR_ISCEM|ATUIMR_RSCEM|ATUIMR_PST|
ATUIMR_DPE|ATUIMR_P_SERR_ASRT|ATUIMR_PMA|ATUIMR_PTAM|
ATUIMR_PTAT|ATUIMR_PMPE);
/*
* Program the outbound windows.
*/
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_OIOWTVR, sc->sc_ioout_xlate);
if (!sc->sc_is_host) {
sc->sc_owin[0].owin_xlate_lo = sc->sc_iwin[1].iwin_base_lo;
sc->sc_owin[0].owin_xlate_hi = sc->sc_iwin[1].iwin_base_hi;
}
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_OMWTVR0, sc->sc_owin[0].owin_xlate_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_OUMWTVR0, sc->sc_owin[0].owin_xlate_hi);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_OMWTVR1, sc->sc_owin[1].owin_xlate_lo);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
ATU_OUMWTVR1, sc->sc_owin[1].owin_xlate_hi);
/*
* Set up the ATU configuration register. All we do
* right now is enable Outbound Windows.
*/
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUCR,
ATUCR_OUT_EN);
/*
* Enable bus mastering, memory access, SERR, and parity
* checking on the ATU.
*/
if (sc->sc_is_host) {
preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
PCIR_COMMAND);
preg |= PCIM_CMD_MEMEN |
PCIM_CMD_BUSMASTEREN | PCIM_CMD_PERRESPEN |
PCIM_CMD_SERRESPEN;
bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
PCIR_COMMAND, preg);
}
/* Initialize the bus space tags. */
i80321_io_bs_init(&sc->sc_pci_iot, sc);
i80321_mem_bs_init(&sc->sc_pci_memt, sc);
intr_enabled = 0;
i80321_set_intrmask();
i80321_set_intrsteer();
}
static __inline uint32_t
i80321_iintsrc_read(void)
{
uint32_t iintsrc;
__asm __volatile("mrc p6, 0, %0, c8, c0, 0"
: "=r" (iintsrc));
/*
* The IINTSRC register shows bits that are active even
* if they are masked in INTCTL, so we have to mask them
* off with the interrupts we consider enabled.
*/
return (iintsrc & intr_enabled);
}
int
arm_get_next_irq(int last __unused)
{
int irq;
if ((irq = i80321_iintsrc_read()))
return (ffs(irq) - 1);
return (-1);
}

292
sys/arm/xscale/i80321/i80321_aau.c
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@ -1,292 +0,0 @@
/*-
* Copyright (c) 2005 Olivier Houchard. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/rman.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/proc.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_map.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/md_var.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/iq80321reg.h>
#include <arm/xscale/i80321/iq80321var.h>
#include <arm/xscale/i80321/i80321_intr.h>
typedef struct i80321_aaudesc_s {
vm_paddr_t next_desc;
uint32_t sar[4];
vm_paddr_t local_addr;
vm_size_t count;
uint32_t descr_ctrl;
} __packed i80321_aaudesc_t;
typedef struct i80321_aauring_s {
i80321_aaudesc_t *desc;
vm_paddr_t phys_addr;
bus_dmamap_t map;
} i80321_aauring_t;
#define AAU_RING_SIZE 64
struct i80321_aau_softc {
bus_space_tag_t sc_st;
bus_space_handle_t sc_aau_sh;
bus_dma_tag_t dmatag;
i80321_aauring_t aauring[AAU_RING_SIZE];
int flags;
#define BUSY 0x1
int unit;
struct mtx mtx;
};
static int
i80321_aau_probe(device_t dev)
{
device_set_desc(dev, "I80321 AAU");
return (0);
}
static struct i80321_aau_softc *aau_softc;
static void
i80321_mapphys(void *arg, bus_dma_segment_t *segs, int nseg, int error)
{
vm_paddr_t *addr = (vm_paddr_t *)arg;
*addr = segs->ds_addr;
}
#define AAU_REG_WRITE(softc, reg, val) \
bus_space_write_4((softc)->sc_st, (softc)->sc_aau_sh, \
(reg), (val))
#define AAU_REG_READ(softc, reg) \
bus_space_read_4((softc)->sc_st, (softc)->sc_aau_sh, \
(reg))
static int aau_bzero(void *, int, int);
static int
i80321_aau_attach(device_t dev)
{
struct i80321_aau_softc *softc = device_get_softc(dev);
struct i80321_softc *sc = device_get_softc(device_get_parent(dev));
struct i80321_aaudesc_s *aaudescs;
mtx_init(&softc->mtx, "AAU mtx", NULL, MTX_SPIN);
softc->sc_st = sc->sc_st;
if (bus_space_subregion(softc->sc_st, sc->sc_sh, VERDE_AAU_BASE,
VERDE_AAU_SIZE, &softc->sc_aau_sh) != 0)
panic("%s: unable to subregion AAU registers",
device_get_name(dev));
if (bus_dma_tag_create(NULL, sizeof(i80321_aaudesc_t), 0,
BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
AAU_RING_SIZE * sizeof(i80321_aaudesc_t),
1, sizeof(i80321_aaudesc_t), BUS_DMA_ALLOCNOW, busdma_lock_mutex,
&Giant, &softc->dmatag))
panic("Couldn't create a dma tag");
if (bus_dmamem_alloc(softc->dmatag, (void **)&aaudescs,
BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &softc->aauring[0].map))
panic("Couldn't alloc dma memory");
for (int i = 0; i < AAU_RING_SIZE; i++) {
if (i > 0)
if (bus_dmamap_create(softc->dmatag, 0,
&softc->aauring[i].map))
panic("Couldn't create dma map");
softc->aauring[i].desc = &aaudescs[i];
bus_dmamap_load(softc->dmatag, softc->aauring[i].map,
softc->aauring[i].desc, sizeof(i80321_aaudesc_t),
i80321_mapphys, &softc->aauring[i].phys_addr, 0);
bzero(softc->aauring[i].desc, sizeof(i80321_aaudesc_t));
}
aau_softc = softc;
_arm_bzero = aau_bzero;
_min_bzero_size = 1024;
return (0);
}
static __inline void
test_virt_addr(void *addr, int len)
{
int to_nextpage;
while (len > 0) {
*(char *)addr = 0;
to_nextpage = ((vm_offset_t)addr & ~PAGE_MASK) +
PAGE_SIZE - (vm_offset_t)addr;
if (to_nextpage >= len)
break;
len -= to_nextpage;
addr = (void *)((vm_offset_t)addr + to_nextpage);
}
}
static int
aau_bzero(void *dst, int len, int flags)
{
struct i80321_aau_softc *sc = aau_softc;
i80321_aaudesc_t *desc;
int ret;
int csr;
int descnb = 0;
int tmplen = len;
int to_nextpagedst;
int min_hop;
vm_paddr_t pa, tmppa;
if (!sc)
return (-1);
mtx_lock_spin(&sc->mtx);
if (sc->flags & BUSY) {
mtx_unlock_spin(&sc->mtx);
return (-1);
}
sc->flags |= BUSY;
mtx_unlock_spin(&sc->mtx);
desc = sc->aauring[0].desc;
if (flags & IS_PHYSICAL) {
desc->local_addr = (vm_paddr_t)dst;
desc->next_desc = 0;
desc->count = len;
desc->descr_ctrl = 2 << 1 | 1 << 31; /* Fill, enable dest write */
bus_dmamap_sync(sc->dmatag, sc->aauring[0].map,
BUS_DMASYNC_PREWRITE);
} else {
test_virt_addr(dst, len);
if ((vm_offset_t)dst & (31))
cpu_dcache_wb_range((vm_offset_t)dst & ~31, 32);
if (((vm_offset_t)dst + len) & 31)
cpu_dcache_wb_range(((vm_offset_t)dst + len) & ~31,
32);
cpu_dcache_inv_range((vm_offset_t)dst, len);
while (tmplen > 0) {
pa = vtophys(dst);
to_nextpagedst = ((vm_offset_t)dst & ~PAGE_MASK) +
PAGE_SIZE - (vm_offset_t)dst;
while (to_nextpagedst < tmplen) {
tmppa = vtophys((vm_offset_t)dst +
to_nextpagedst);
if (tmppa != pa + to_nextpagedst)
break;
to_nextpagedst += PAGE_SIZE;
}
min_hop = to_nextpagedst;
if (min_hop < 64) {
tmplen -= min_hop;
bzero(dst, min_hop);
cpu_dcache_wbinv_range((vm_offset_t)dst,
min_hop);
dst = (void *)((vm_offset_t)dst + min_hop);
if (tmplen <= 0 && descnb > 0) {
sc->aauring[descnb - 1].desc->next_desc
= 0;
bus_dmamap_sync(sc->dmatag,
sc->aauring[descnb - 1].map,
BUS_DMASYNC_PREWRITE);
}
continue;
}
desc->local_addr = pa;
desc->count = tmplen > min_hop ? min_hop : tmplen;
desc->descr_ctrl = 2 << 1 | 1 << 31; /* Fill, enable dest write */;
if (min_hop < tmplen) {
tmplen -= min_hop;
dst = (void *)((vm_offset_t)dst + min_hop);
} else
tmplen = 0;
if (descnb + 1 >= AAU_RING_SIZE) {
mtx_lock_spin(&sc->mtx);
sc->flags &= ~BUSY;
mtx_unlock_spin(&sc->mtx);
return (-1);
}
if (tmplen > 0) {
desc->next_desc = sc->aauring[descnb + 1].
phys_addr;
bus_dmamap_sync(sc->dmatag,
sc->aauring[descnb].map,
BUS_DMASYNC_PREWRITE);
desc = sc->aauring[descnb + 1].desc;
descnb++;
} else {
desc->next_desc = 0;
bus_dmamap_sync(sc->dmatag,
sc->aauring[descnb].map,
BUS_DMASYNC_PREWRITE);
}
}
}
AAU_REG_WRITE(sc, 0x0c /* Descriptor addr */,
sc->aauring[0].phys_addr);
AAU_REG_WRITE(sc, 0 /* Control register */, 1 << 0/* Start transfer */);
while ((csr = AAU_REG_READ(sc, 0x4)) & (1 << 10));
/* Wait until it's done. */
if (csr & (1 << 5)) /* error */
ret = -1;
else
ret = 0;
/* Clear the interrupt. */
AAU_REG_WRITE(sc, 0x4, csr);
/* Stop the AAU. */
AAU_REG_WRITE(sc, 0, 0);
mtx_lock_spin(&sc->mtx);
sc->flags &= ~BUSY;
mtx_unlock_spin(&sc->mtx);
return (ret);
}
static device_method_t i80321_aau_methods[] = {
DEVMETHOD(device_probe, i80321_aau_probe),
DEVMETHOD(device_attach, i80321_aau_attach),
{0, 0},
};
static driver_t i80321_aau_driver = {
"i80321_aau",
i80321_aau_methods,
sizeof(struct i80321_aau_softc),
};
static devclass_t i80321_aau_devclass;
DRIVER_MODULE(i80321_aau, iq, i80321_aau_driver, i80321_aau_devclass, 0, 0);

351
sys/arm/xscale/i80321/i80321_dma.c
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@ -1,351 +0,0 @@
/*-
* Copyright (c) 2005 Olivier Houchard. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/rman.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/proc.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_map.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/md_var.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/iq80321reg.h>
#include <arm/xscale/i80321/iq80321var.h>
#include <arm/xscale/i80321/i80321_intr.h>
typedef struct i80321_dmadesc_s {
vm_paddr_t next_desc;
vm_paddr_t low_pciaddr;
vm_paddr_t high_pciaddr;
vm_paddr_t local_addr;
vm_size_t count;
uint32_t descr_ctrl;
uint64_t unused;
} __packed i80321_dmadesc_t;
typedef struct i80321_dmaring_s {
i80321_dmadesc_t *desc;
vm_paddr_t phys_addr;
bus_dmamap_t map;
} i80321_dmaring_t;
#define DMA_RING_SIZE 64
struct i80321_dma_softc {
bus_space_tag_t sc_st;
bus_space_handle_t sc_dma_sh;
bus_dma_tag_t dmatag;
i80321_dmaring_t dmaring[DMA_RING_SIZE];
int flags;
#define BUSY 0x1
int unit;
struct mtx mtx;
};
static int
i80321_dma_probe(device_t dev)
{
device_set_desc(dev, "I80321 DMA Unit");
return (0);
}
static struct i80321_dma_softc *softcs[2]; /* XXX */
static void
i80321_mapphys(void *arg, bus_dma_segment_t *segs, int nseg, int error)
{
vm_paddr_t *addr = (vm_paddr_t *)arg;
*addr = segs->ds_addr;
}
#define DMA_REG_WRITE(softc, reg, val) \
bus_space_write_4((softc)->sc_st, (softc)->sc_dma_sh, \
(reg), (val))
#define DMA_REG_READ(softc, reg) \
bus_space_read_4((softc)->sc_st, (softc)->sc_dma_sh, \
(reg))
#define DMA_CLEAN_MASK (0x2|0x4|0x8|0x20|0x100|0x200)
static int dma_memcpy(void *, void *, int, int);
static int
i80321_dma_attach(device_t dev)
{
struct i80321_dma_softc *softc = device_get_softc(dev);
struct i80321_softc *sc = device_get_softc(device_get_parent(dev));
int unit = device_get_unit(dev);
i80321_dmadesc_t *dmadescs;
mtx_init(&softc->mtx, "DMA engine mtx", NULL, MTX_SPIN);
softc->sc_st = sc->sc_st;
if (bus_space_subregion(softc->sc_st, sc->sc_sh, unit == 0 ?
VERDE_DMA_BASE0 : VERDE_DMA_BASE1, VERDE_DMA_SIZE,
&softc->sc_dma_sh) != 0)
panic("%s: unable to subregion DMA registers",
device_get_name(dev));
if (bus_dma_tag_create(NULL, sizeof(i80321_dmadesc_t),
0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
DMA_RING_SIZE * sizeof(i80321_dmadesc_t), 1,
sizeof(i80321_dmadesc_t), BUS_DMA_ALLOCNOW, busdma_lock_mutex,
&Giant, &softc->dmatag))
panic("Couldn't create a dma tag");
DMA_REG_WRITE(softc, 0, 0);
if (bus_dmamem_alloc(softc->dmatag, (void **)&dmadescs,
BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &softc->dmaring[0].map))
panic("Couldn't alloc dma memory");
for (int i = 0; i < DMA_RING_SIZE; i++) {
if (i > 0)
if (bus_dmamap_create(softc->dmatag, 0,
&softc->dmaring[i].map))
panic("Couldn't alloc dmamap");
softc->dmaring[i].desc = &dmadescs[i];
bus_dmamap_load(softc->dmatag, softc->dmaring[i].map,
softc->dmaring[i].desc, sizeof(i80321_dmadesc_t),
i80321_mapphys, &softc->dmaring[i].phys_addr, 0);
}
softc->unit = unit;
softcs[unit] = softc;
_arm_memcpy = dma_memcpy;
_min_memcpy_size = 1024;
return (0);
}
static __inline int
virt_addr_is_valid(void *addr, int len, int write, int is_kernel)
{
int to_nextpage;
char tmp = 0;
while (len > 0) {
if (write) {
if (is_kernel)
*(char *)addr = 0;
else if (subyte(addr, 0) != 0) {
return (0);
}
} else {
if (is_kernel)
badaddr_read(addr, 1, &tmp);
else if (fubyte(addr) == -1) {
return (0);
}
}
to_nextpage = ((vm_offset_t)addr & ~PAGE_MASK) +
PAGE_SIZE - (vm_offset_t)addr;
if (to_nextpage >= len)
break;
len -= to_nextpage;
addr = (void *)((vm_offset_t)addr + to_nextpage);
}
return (1);
}
static int
dma_memcpy(void *dst, void *src, int len, int flags)
{
struct i80321_dma_softc *sc;
i80321_dmadesc_t *desc;
int ret;
int csr;
int descnb = 0;
int tmplen = len;
int to_nextpagesrc, to_nextpagedst;
int min_hop;
vm_paddr_t pa, pa2, tmppa;
pmap_t pmap = vmspace_pmap(curthread->td_proc->p_vmspace);
if (!softcs[0] || !softcs[1])
return (-1);
mtx_lock_spin(&softcs[0]->mtx);
if (softcs[0]->flags & BUSY) {
mtx_unlock_spin(&softcs[0]->mtx);
mtx_lock_spin(&softcs[1]->mtx);
if (softcs[1]->flags & BUSY) {
mtx_unlock(&softcs[1]->mtx);
return (-1);
}
sc = softcs[1];
} else
sc = softcs[0];
sc->flags |= BUSY;
mtx_unlock_spin(&sc->mtx);
desc = sc->dmaring[0].desc;
if (flags & IS_PHYSICAL) {
desc->next_desc = 0;
desc->low_pciaddr = (vm_paddr_t)src;
desc->high_pciaddr = 0;
desc->local_addr = (vm_paddr_t)dst;
desc->count = len;
desc->descr_ctrl = 1 << 6; /* Local memory to local memory. */
bus_dmamap_sync(sc->dmatag,
sc->dmaring[0].map,
BUS_DMASYNC_PREWRITE);
} else {
if (!virt_addr_is_valid(dst, len, 1, !(flags & DST_IS_USER)) ||
!virt_addr_is_valid(src, len, 0, !(flags & SRC_IS_USER))) {
mtx_lock_spin(&sc->mtx);
sc->flags &= ~BUSY;
mtx_unlock_spin(&sc->mtx);
return (-1);
}
cpu_dcache_wb_range((vm_offset_t)src, len);
if ((vm_offset_t)dst & (31))
cpu_dcache_wb_range((vm_offset_t)dst & ~31, 32);
if (((vm_offset_t)dst + len) & 31)
cpu_dcache_wb_range(((vm_offset_t)dst + len) & ~31,
32);
cpu_dcache_inv_range((vm_offset_t)dst, len);
while (tmplen > 0) {
pa = (flags & SRC_IS_USER) ?
pmap_extract(pmap, (vm_offset_t)src) :
vtophys(src);
pa2 = (flags & DST_IS_USER) ?
pmap_extract(pmap, (vm_offset_t)dst) :
vtophys(dst);
to_nextpagesrc = ((vm_offset_t)src & ~PAGE_MASK) +
PAGE_SIZE - (vm_offset_t)src;
to_nextpagedst = ((vm_offset_t)dst & ~PAGE_MASK) +
PAGE_SIZE - (vm_offset_t)dst;
while (to_nextpagesrc < tmplen) {
tmppa = (flags & SRC_IS_USER) ?
pmap_extract(pmap, (vm_offset_t)src +
to_nextpagesrc) :
vtophys((vm_offset_t)src +
to_nextpagesrc);
if (tmppa != pa + to_nextpagesrc)
break;
to_nextpagesrc += PAGE_SIZE;
}
while (to_nextpagedst < tmplen) {
tmppa = (flags & DST_IS_USER) ?
pmap_extract(pmap, (vm_offset_t)dst +
to_nextpagedst) :
vtophys((vm_offset_t)dst +
to_nextpagedst);
if (tmppa != pa2 + to_nextpagedst)
break;
to_nextpagedst += PAGE_SIZE;
}
min_hop = to_nextpagedst > to_nextpagesrc ?
to_nextpagesrc : to_nextpagedst;
if (min_hop < 64) {
tmplen -= min_hop;
memcpy(dst, src, min_hop);
cpu_dcache_wbinv_range((vm_offset_t)dst,
min_hop);
src = (void *)((vm_offset_t)src + min_hop);
dst = (void *)((vm_offset_t)dst + min_hop);
if (tmplen <= 0 && descnb > 0) {
sc->dmaring[descnb - 1].desc->next_desc
= 0;
bus_dmamap_sync(sc->dmatag,
sc->dmaring[descnb - 1].map,
BUS_DMASYNC_PREWRITE);
}
continue;
}
desc->low_pciaddr = pa;
desc->high_pciaddr = 0;
desc->local_addr = pa2;
desc->count = tmplen > min_hop ? min_hop : tmplen;
desc->descr_ctrl = 1 << 6;
if (min_hop < tmplen) {
tmplen -= min_hop;
src = (void *)((vm_offset_t)src + min_hop);
dst = (void *)((vm_offset_t)dst + min_hop);
} else
tmplen = 0;
if (descnb + 1 >= DMA_RING_SIZE) {
mtx_lock_spin(&sc->mtx);
sc->flags &= ~BUSY;
mtx_unlock_spin(&sc->mtx);
return (-1);
}
if (tmplen > 0) {
desc->next_desc = sc->dmaring[descnb + 1].
phys_addr;
bus_dmamap_sync(sc->dmatag,
sc->dmaring[descnb].map,
BUS_DMASYNC_PREWRITE);
desc = sc->dmaring[descnb + 1].desc;
descnb++;
} else {
desc->next_desc = 0;
bus_dmamap_sync(sc->dmatag,
sc->dmaring[descnb].map,
BUS_DMASYNC_PREWRITE);
}
}
}
DMA_REG_WRITE(sc, 4 /* Status register */,
DMA_REG_READ(sc, 4) | DMA_CLEAN_MASK);
DMA_REG_WRITE(sc, 0x10 /* Descriptor addr */,
sc->dmaring[0].phys_addr);
DMA_REG_WRITE(sc, 0 /* Control register */, 1 | 2/* Start transfer */);
while ((csr = DMA_REG_READ(sc, 0x4)) & (1 << 10));
/* Wait until it's done. */
if (csr & 0x2e) /* error */
ret = -1;
else
ret = 0;
DMA_REG_WRITE(sc, 0, 0);
mtx_lock_spin(&sc->mtx);
sc->flags &= ~BUSY;
mtx_unlock_spin(&sc->mtx);
return (ret);
}
static device_method_t i80321_dma_methods[] = {
DEVMETHOD(device_probe, i80321_dma_probe),
DEVMETHOD(device_attach, i80321_dma_attach),
{0, 0},
};
static driver_t i80321_dma_driver = {
"i80321_dma",
i80321_dma_methods,
sizeof(struct i80321_dma_softc),
};
static devclass_t i80321_dma_devclass;
DRIVER_MODULE(i80321_dma, iq, i80321_dma_driver, i80321_dma_devclass, 0, 0);

165
sys/arm/xscale/i80321/i80321_intr.h
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@ -1,165 +0,0 @@
/* $NetBSD: i80321_intr.h,v 1.5 2004/01/12 10:25:06 scw Exp $ */
/*-
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _I80321_INTR_H_
#define _I80321_INTR_H_
#define ARM_IRQ_HANDLER _C_LABEL(i80321_intr_dispatch)
#ifndef _LOCORE
#include <machine/armreg.h>
#include <machine/cpufunc.h>
#include <arm/xscale/i80321/i80321reg.h>
void i80321_do_pending(void);
extern __volatile uint32_t intr_enabled;
extern uint32_t intr_steer;
static __inline void __attribute__((__unused__))
i80321_set_intrmask(void)
{
__asm __volatile("mcr p6, 0, %0, c0, c0, 0"
:
: "r" (intr_enabled & ICU_INT_HWMASK));
}
static __inline void
i80321_set_intrsteer(void)
{
__asm __volatile("mcr p6, 0, %0, c4, c0, 0"
:
: "r" (intr_steer & ICU_INT_HWMASK));
}
#if defined ( CPU_XSCALE_80219 )
#define INT_SWMASK \
((1U << ICU_INT_bit26) | \
(1U << ICU_INT_bit25) | \
(1U << ICU_INT_bit23) | \
(1U << ICU_INT_bit22) | \
(1U << ICU_INT_bit7) | \
(1U << ICU_INT_bit6) | \
(1U << ICU_INT_bit5) | \
(1U << ICU_INT_bit4))
#else
#define INT_SWMASK \
((1U << ICU_INT_bit26) | (1U << ICU_INT_bit22) | \
(1U << ICU_INT_bit5) | (1U << ICU_INT_bit4))
#endif
#if 0
static __inline void __attribute__((__unused__))
i80321_splx(int new)
{
extern __volatile uint32_t intr_enabled;
extern __volatile int current_spl_level;
extern __volatile int i80321_ipending;
extern void i80321_do_pending(void);
int oldirqstate, hwpend;
/* Don't let the compiler re-order this code with preceding code */
__insn_barrier();
current_spl_level = new;
hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new;
if (hwpend != 0) {
oldirqstate = disable_interrupts(PSR_I);
intr_enabled |= hwpend;
i80321_set_intrmask();
restore_interrupts(oldirqstate);
}
if ((i80321_ipending & INT_SWMASK) & ~new)
i80321_do_pending();
}
static __inline int __attribute__((__unused__))
i80321_splraise(int ipl)
{
extern __volatile int current_spl_level;
extern int i80321_imask[];
int old;
old = current_spl_level;
current_spl_level |= i80321_imask[ipl];
/* Don't let the compiler re-order this code with subsequent code */
__insn_barrier();
return (old);
}
static __inline int __attribute__((__unused__))
i80321_spllower(int ipl)
{
extern __volatile int current_spl_level;
extern int i80321_imask[];
int old = current_spl_level;
i80321_splx(i80321_imask[ipl]);
return(old);
}
#endif
#if !defined(EVBARM_SPL_NOINLINE)
#define splx(new) i80321_splx(new)
#define _spllower(ipl) i80321_spllower(ipl)
#define _splraise(ipl) i80321_splraise(ipl)
void _setsoftintr(int);
#else
int _splraise(int);
int _spllower(int);
void splx(int);
void _setsoftintr(int);
#endif /* ! EVBARM_SPL_NOINLINE */
#endif /* _LOCORE */
#endif /* _I80321_INTR_H_ */

90
sys/arm/xscale/i80321/i80321_mcu.c
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@ -1,90 +0,0 @@
/* $NetBSD: i80321_mcu.c,v 1.2 2003/07/15 00:24:54 lukem Exp $ */
/*-
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Intel i80321 I/O Processor memory controller support.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
/*
* i80321_sdram_bounds:
*
* Retrieve the start and size of SDRAM.
*/
void
i80321_sdram_bounds(bus_space_tag_t st, bus_space_handle_t sh,
vm_paddr_t *start, vm_size_t *size)
{
uint32_t sdbr, sbr0, sbr1;
uint32_t bank0, bank1;
sdbr = bus_space_read_4(st, sh, MCU_SDBR);
sbr0 = bus_space_read_4(st, sh, MCU_SBR0);
sbr1 = bus_space_read_4(st, sh, MCU_SBR1);
#ifdef VERBOSE_INIT_ARM
printf("i80321: SBDR = 0x%08x SBR0 = 0x%08x SBR1 = 0x%08x\n",
sdbr, sbr0, sbr1);
#endif
*start = sdbr;
sdbr = (sdbr >> 25) & 0x1f;
sbr0 &= 0x3f;
sbr1 &= 0x3f;
bank0 = (sbr0 - sdbr) << 25;
bank1 = (sbr1 - sbr0) << 25;
#ifdef VERBOSE_INIT_ARM
printf("i80321: BANK0 = 0x%08x BANK1 = 0x%08x\n", bank0, bank1);
#endif
*size = bank0 + bank1;
}

401
sys/arm/xscale/i80321/i80321_pci.c
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@ -1,401 +0,0 @@
/* $NetBSD: i80321_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
/*-
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* PCI configuration support for i80321 I/O Processor chip.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/pcb.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_extern.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/i80321_intr.h>
#include <dev/pci/pcib_private.h>
#include "pcib_if.h"
#include <dev/pci/pcireg.h>
extern struct i80321_softc *i80321_softc;
static int
i80321_pci_probe(device_t dev)
{
device_set_desc(dev, "i80321 PCI bus");
return (0);
}
static int
i80321_pci_attach(device_t dev)
{
uint32_t busno;
struct i80321_pci_softc *sc = device_get_softc(dev);
sc->sc_st = i80321_softc->sc_st;
sc->sc_atu_sh = i80321_softc->sc_atu_sh;
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
sc->sc_dev = dev;
sc->sc_busno = busno;
sc->sc_pciio = &i80321_softc->sc_pci_iot;
sc->sc_pcimem = &i80321_softc->sc_pci_memt;
sc->sc_mem = i80321_softc->sc_owin[0].owin_xlate_lo +
VERDE_OUT_XLATE_MEM_WIN_SIZE;
sc->sc_io = i80321_softc->sc_iow_vaddr;
/* Initialize memory and i/o rmans. */
sc->sc_io_rman.rm_type = RMAN_ARRAY;
sc->sc_io_rman.rm_descr = "I80321 PCI I/O Ports";
if (rman_init(&sc->sc_io_rman) != 0 ||
rman_manage_region(&sc->sc_io_rman,
sc->sc_io,
sc->sc_io +
VERDE_OUT_XLATE_IO_WIN_SIZE) != 0) {
panic("i80321_pci_probe: failed to set up I/O rman");
}
sc->sc_mem_rman.rm_type = RMAN_ARRAY;
sc->sc_mem_rman.rm_descr = "I80321 PCI Memory";
if (rman_init(&sc->sc_mem_rman) != 0 ||
rman_manage_region(&sc->sc_mem_rman,
0, VERDE_OUT_XLATE_MEM_WIN_SIZE) != 0) {
panic("i80321_pci_probe: failed to set up memory rman");
}
sc->sc_irq_rman.rm_type = RMAN_ARRAY;
sc->sc_irq_rman.rm_descr = "i80321 PCI IRQs";
if (rman_init(&sc->sc_irq_rman) != 0 ||
rman_manage_region(&sc->sc_irq_rman, 26, 32) != 0)
panic("i80321_pci_probe: failed to set up IRQ rman");
device_add_child(dev, "pci", -1);
return (bus_generic_attach(dev));
}
static int
i80321_pci_maxslots(device_t dev)
{
return (PCI_SLOTMAX);
}
static int
i80321_pci_conf_setup(struct i80321_pci_softc *sc, int bus, int slot, int func,
int reg, uint32_t *addr)
{
uint32_t busno;
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
/*
* If the bus # is the same as our own, then use Type 0 cycles,
* else use Type 1.
*
* XXX We should filter out all non-private devices here!
* XXX How does private space interact with PCI-PCI bridges?
*/
if (bus == busno) {
if (slot > (31 - 16))
return (1);
/*
* NOTE: PCI-X requires that that devices updated their
* PCIXSR on every config write with the device number
* specified in AD[15:11]. If we don't set this field,
* each device could end of thinking it is at device 0,
* which can cause a number of problems. Doing this
* unconditionally should be OK when only PCI devices
* are present.
*/
bus &= 0xff;
slot &= 0x1f;
func &= 0x07;
*addr = (1U << (slot + 16)) |
(slot << 11) | (func << 8) | reg;
} else {
*addr = (bus << 16) | (slot << 11) | (func << 8) | reg | 1;
}
return (0);
}
static u_int32_t
i80321_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
u_int reg, int bytes)
{
struct i80321_pci_softc *sc = device_get_softc(dev);
uint32_t isr;
uint32_t addr;
u_int32_t ret = 0;
vm_offset_t va;
int err = 0;
if (i80321_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
return (-1);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
addr);
va = sc->sc_atu_sh;
switch (bytes) {
case 1:
err = badaddr_read((void*)(va + ATU_OCCDR + (reg & 3)), 1, &ret);
break;
case 2:
err = badaddr_read((void*)(va + ATU_OCCDR + (reg & 3)), 2, &ret);
break;
case 4:
err = badaddr_read((void *)(va + ATU_OCCDR), 4, &ret);
break;
default:
printf("i80321_read_config: invalid size %d\n", bytes);
ret = -1;
}
if (err) {
isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR);
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUISR,
isr & (ATUISR_P_SERR_DET|ATUISR_PMA|ATUISR_PTAM|
ATUISR_PTAT|ATUISR_PMPE));
return (-1);
}
return (ret);
}
static void
i80321_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
u_int reg, u_int32_t data, int bytes)
{
struct i80321_pci_softc *sc = device_get_softc(dev);
uint32_t addr;
if (i80321_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
return;
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
addr);
switch (bytes) {
case 1:
bus_space_write_1(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR +
(reg & 3), data);
break;
case 2:
bus_space_write_2(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR +
(reg & 3), data);
break;
case 4:
bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, data);
break;
default:
printf("i80321_pci_write_config: Invalid size : %d\n", bytes);
}
}
static int
i80321_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{
struct i80321_pci_softc *sc = device_get_softc(dev);
switch (which) {
case PCIB_IVAR_DOMAIN:
*result = 0;
return (0);
case PCIB_IVAR_BUS:
*result = sc->sc_busno;
return (0);
}
return (ENOENT);
}
static int
i80321_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
{
struct i80321_pci_softc * sc = device_get_softc(dev);
switch (which) {
case PCIB_IVAR_DOMAIN:
return (EINVAL);
case PCIB_IVAR_BUS:
sc->sc_busno = result;
return (0);
}
return (ENOENT);
}
static struct resource *
i80321_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags)
{
struct i80321_pci_softc *sc = device_get_softc(bus);
struct resource *rv;
struct rman *rm;
bus_space_tag_t bt = NULL;
bus_space_handle_t bh = 0;
switch (type) {
case SYS_RES_IRQ:
rm = &sc->sc_irq_rman;
break;
case SYS_RES_MEMORY:
rm = &sc->sc_mem_rman;
bt = sc->sc_pcimem;
bh = (start >= 0x80000000 && start < 0x84000000) ? 0x80000000 :
sc->sc_mem;
start &= (0x1000000 - 1);
end &= (0x1000000 - 1);
break;
case SYS_RES_IOPORT:
rm = &sc->sc_io_rman;
bt = sc->sc_pciio;
bh = sc->sc_io;
if (start < sc->sc_io) {
start = start - 0x90000000 + sc->sc_io;
end = end - 0x90000000 + sc->sc_io;
}
break;
default:
return (NULL);
}
rv = rman_reserve_resource(rm, start, end, count, flags, child);
if (rv == NULL)
return (NULL);
rman_set_rid(rv, *rid);
if (type != SYS_RES_IRQ) {
if (type == SYS_RES_MEMORY)
bh += (rman_get_start(rv));
rman_set_bustag(rv, bt);
rman_set_bushandle(rv, bh);
if (flags & RF_ACTIVE) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
}
return (rv);
}
static int
i80321_pci_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
u_long p;
int error;
if (type == SYS_RES_MEMORY) {
error = bus_space_map(rman_get_bustag(r),
rman_get_bushandle(r), rman_get_size(r), 0, &p);
if (error)
return (error);
rman_set_bushandle(r, p);
}
return (rman_activate_resource(r));
}
static int
i80321_pci_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
{
return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
filt, intr, arg, cookiep));
}
static int
i80321_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
void *cookie)
{
return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie));
}
static device_method_t i80321_pci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, i80321_pci_probe),
DEVMETHOD(device_attach, i80321_pci_attach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
/* Bus interface */
DEVMETHOD(bus_read_ivar, i80321_read_ivar),
DEVMETHOD(bus_write_ivar, i80321_write_ivar),
DEVMETHOD(bus_alloc_resource, i80321_pci_alloc_resource),
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
DEVMETHOD(bus_activate_resource, i80321_pci_activate_resource),
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
DEVMETHOD(bus_setup_intr, i80321_pci_setup_intr),
DEVMETHOD(bus_teardown_intr, i80321_pci_teardown_intr),
/* pcib interface */
DEVMETHOD(pcib_maxslots, i80321_pci_maxslots),
DEVMETHOD(pcib_read_config, i80321_pci_read_config),
DEVMETHOD(pcib_write_config, i80321_pci_write_config),
DEVMETHOD(pcib_route_interrupt, machdep_pci_route_interrupt),
DEVMETHOD_END
};
static driver_t i80321_pci_driver = {
"pcib",
i80321_pci_methods,
sizeof(struct i80321_pci_softc),
};
static devclass_t i80321_pci_devclass;
DRIVER_MODULE(ipci, iq, i80321_pci_driver, i80321_pci_devclass, 0, 0);

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sys/arm/xscale/i80321/i80321_space.c
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@ -1,209 +0,0 @@
/* $NetBSD: i80321_space.c,v 1.6 2003/10/06 15:43:35 thorpej Exp $ */
/*-
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* bus_space functions for i80321 I/O Processor.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <machine/pcb.h>
#include <vm/vm.h>
#include <vm/vm_kern.h>
#include <vm/pmap.h>
#include <vm/vm_page.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
/* Prototypes for all the bus_space structure functions */
bs_protos(i80321);
bs_protos(i80321_io);
bs_protos(i80321_mem);
void
i80321_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = *arm_base_bs_tag;
bs->bs_privdata = cookie;
}
void
i80321_io_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = *arm_base_bs_tag;
bs->bs_privdata = cookie;
bs->bs_map = i80321_io_bs_map;
bs->bs_unmap = i80321_io_bs_unmap;
bs->bs_alloc = i80321_io_bs_alloc;
bs->bs_free = i80321_io_bs_free;
}
void
i80321_mem_bs_init(bus_space_tag_t bs, void *cookie)
{
*bs = *arm_base_bs_tag;
bs->bs_privdata = cookie;
bs->bs_map = i80321_mem_bs_map;
bs->bs_unmap = i80321_mem_bs_unmap;
bs->bs_alloc = i80321_mem_bs_alloc;
bs->bs_free = i80321_mem_bs_free;
}
/* *** Routines shared by i80321, PCI IO, and PCI MEM. *** */
int
i80321_bs_subregion(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t size, bus_space_handle_t *nbshp)
{
*nbshp = bsh + offset;
return (0);
}
void
i80321_bs_barrier(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t offset,
bus_size_t len, int flags)
{
/* Nothing to do. */
}
/* *** Routines for PCI IO. *** */
extern struct i80321_softc *i80321_softc;
int
i80321_io_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int flags,
bus_space_handle_t *bshp)
{
struct i80321_softc *sc = i80321_softc;
vm_offset_t winvaddr;
uint32_t busbase;
if (bpa >= sc->sc_ioout_xlate &&
bpa < (sc->sc_ioout_xlate + VERDE_OUT_XLATE_IO_WIN_SIZE)) {
busbase = sc->sc_ioout_xlate;
winvaddr = sc->sc_iow_vaddr;
} else
return (EINVAL);
if ((bpa + size) >= (busbase + VERDE_OUT_XLATE_IO_WIN_SIZE))
return (EINVAL);
/*
* Found the window -- PCI I/O space is mapped at a fixed
* virtual address by board-specific code. Translate the
* bus address to the virtual address.
*/
*bshp = winvaddr + (bpa - busbase);
return (0);
}
void
i80321_io_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size)
{
/* Nothing to do. */
}
int
i80321_io_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend,
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
bus_addr_t *bpap, bus_space_handle_t *bshp)
{
panic("i80321_io_bs_alloc(): not implemented");
}
void
i80321_io_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size)
{
panic("i80321_io_bs_free(): not implemented");
}
/* *** Routines for PCI MEM. *** */
extern int badaddr_read(void *, int, void *);
int
i80321_mem_bs_map(bus_space_tag_t tag, bus_addr_t bpa, bus_size_t size, int flags,
bus_space_handle_t *bshp)
{
*bshp = (vm_offset_t)pmap_mapdev(bpa, size);
return (0);
}
void
i80321_mem_bs_unmap(bus_space_tag_t tag, bus_space_handle_t h, bus_size_t size)
{
pmap_unmapdev((vm_offset_t)h, size);
}
int
i80321_mem_bs_alloc(bus_space_tag_t tag, bus_addr_t rstart, bus_addr_t rend,
bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
bus_addr_t *bpap, bus_space_handle_t *bshp)
{
panic("i80321_mem_bs_alloc(): not implemented");
}
void
i80321_mem_bs_free(bus_space_tag_t tag, bus_space_handle_t bsh, bus_size_t size)
{
panic("i80321_mem_bs_free(): not implemented");
}

390
sys/arm/xscale/i80321/iq31244_7seg.c
View File

@ -1,390 +0,0 @@
/* $NetBSD: iq31244_7seg.c,v 1.2 2003/07/15 00:25:01 lukem Exp $ */
/*-
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Support for the 7-segment display on the Intel IQ31244.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/sysctl.h>
#include <machine/bus.h>
#include <arm/xscale/i80321/iq80321reg.h>
#include <arm/xscale/i80321/iq80321var.h>
#define WRITE(x, v) *((__volatile uint8_t *) (x)) = (v)
static int snakestate;
/*
* The 7-segment display looks like so:
*
* A
* +-----+
* | |
* F | | B
* | G |
* +-----+
* | |
* E | | C
* | D |
* +-----+ o DP
*
* Setting a bit clears the corresponding segment on the
* display.
*/
#define SEG_A (1 << 0)
#define SEG_B (1 << 1)
#define SEG_C (1 << 2)
#define SEG_D (1 << 3)
#define SEG_E (1 << 4)
#define SEG_F (1 << 5)
#define SEG_G (1 << 6)
#define SEG_DP (1 << 7)
static const uint8_t digitmap[] = {
/* +#####+
* # #
* # #
* # #
* +-----+
* # #
* # #
* # #
* +#####+
*/
SEG_G,
/* +-----+
* | #
* | #
* | #
* +-----+
* | #
* | #
* | #
* +-----+
*/
SEG_A|SEG_D|SEG_E|SEG_F|SEG_G,
/* +#####+
* | #
* | #
* | #
* +#####+
* # |
* # |
* # |
* +#####+
*/
SEG_C|SEG_F,
/* +#####+
* | #
* | #
* | #
* +#####+
* | #
* | #
* | #
* +#####+
*/
SEG_E|SEG_F,
/* +-----+
* # #
* # #
* # #
* +#####+
* | #
* | #
* | #
* +-----+
*/
SEG_A|SEG_D|SEG_E,
/* +#####+
* # |
* # |
* # |
* +#####+
* | #
* | #
* | #
* +#####+
*/
SEG_B|SEG_E,
/* +#####+
* # |
* # |
* # |
* +#####+
* # #
* # #
* # #
* +#####+
*/
SEG_B,
/* +#####+
* | #
* | #
* | #
* +-----+
* | #
* | #
* | #
* +-----+
*/
SEG_D|SEG_E|SEG_F,
/* +#####+
* # #
* # #
* # #
* +#####+
* # #
* # #
* # #
* +#####+
*/
0,
/* +#####+
* # #
* # #
* # #
* +#####+
* | #
* | #
* | #
* +-----+
*/
SEG_D|SEG_E,
};
static uint8_t
iq80321_7seg_xlate(char c)
{
uint8_t rv;
if (c >= '0' && c <= '9')
rv = digitmap[c - '0'];
else if (c == '.')
rv = (uint8_t) ~SEG_DP;
else
rv = 0xff;
return (rv);
}
void
iq80321_7seg(char a, char b)
{
uint8_t msb, lsb;
msb = iq80321_7seg_xlate(a);
lsb = iq80321_7seg_xlate(b);
snakestate = 0;
WRITE(IQ80321_7SEG_MSB, msb);
WRITE(IQ80321_7SEG_LSB, lsb);
}
static const uint8_t snakemap[][2] = {
/* +#####+ +#####+
* | | | |
* | | | |
* | | | |
* +-----+ +-----+
* | | | |
* | | | |
* | | | |
* +-----+ +-----+
*/
{ ~SEG_A, ~SEG_A },
/* +-----+ +-----+
* # | | #
* # | | #
* # | | #
* +-----+ +-----+
* | | | |
* | | | |
* | | | |
* +-----+ +-----+
*/
{ ~SEG_F, ~SEG_B },
/* +-----+ +-----+
* | | | |
* | | | |
* | | | |
* +#####+ +#####+
* | | | |
* | | | |
* | | | |
* +-----+ +-----+
*/
{ ~SEG_G, ~SEG_G },
/* +-----+ +-----+
* | | | |
* | | | |
* | | | |
* +-----+ +-----+
* | # # |
* | # # |
* | # # |
* +-----+ +-----+
*/
{ ~SEG_C, ~SEG_E },
/* +-----+ +-----+
* | | | |
* | | | |
* | | | |
* +-----+ +-----+
* | | | |
* | | | |
* | | | |
* +#####+ +#####+
*/
{ ~SEG_D, ~SEG_D },
/* +-----+ +-----+
* | | | |
* | | | |
* | | | |
* +-----+ +-----+
* # | | #
* # | | #
* # | | #
* +-----+ +-----+
*/
{ ~SEG_E, ~SEG_C },
/* +-----+ +-----+
* | | | |
* | | | |
* | | | |
* +#####+ +#####+
* | | | |
* | | | |
* | | | |
* +-----+ +-----+
*/
{ ~SEG_G, ~SEG_G },
/* +-----+ +-----+
* | # # |
* | # # |
* | # # |
* +-----+ +-----+
* | | | |
* | | | |
* | | | |
* +-----+ +-----+
*/
{ ~SEG_B, ~SEG_F },
};
static SYSCTL_NODE(_hw, OID_AUTO, sevenseg, CTLFLAG_RD, 0, "7 seg");
static int freq = 20;
SYSCTL_INT(_hw_sevenseg, OID_AUTO, freq, CTLFLAG_RW, &freq, 0,
"7 Seg update frequency");
static void
iq31244_7seg_snake(void)
{
static int snakefreq;
int cur = snakestate;
snakefreq++;
if ((snakefreq % freq))
return;
WRITE(IQ80321_7SEG_MSB, snakemap[cur][0]);
WRITE(IQ80321_7SEG_LSB, snakemap[cur][1]);
snakestate = (cur + 1) & 7;
}
struct iq31244_7seg_softc {
device_t dev;
};
static int
iq31244_7seg_probe(device_t dev)
{
device_set_desc(dev, "IQ31244 7seg");
return (0);
}
extern void (*i80321_hardclock_hook)(void);
static int
iq31244_7seg_attach(device_t dev)
{
i80321_hardclock_hook = iq31244_7seg_snake;
return (0);
}
static device_method_t iq31244_7seg_methods[] = {
DEVMETHOD(device_probe, iq31244_7seg_probe),
DEVMETHOD(device_attach, iq31244_7seg_attach),
{0, 0},
};
static driver_t iq31244_7seg_driver = {
"iqseg",
iq31244_7seg_methods,
sizeof(struct iq31244_7seg_softc),
};
static devclass_t iq31244_7seg_devclass;
DRIVER_MODULE(iqseg, iq, iq31244_7seg_driver, iq31244_7seg_devclass, 0, 0);

416
sys/arm/xscale/i80321/iq31244_machdep.c
View File

@ -1,416 +0,0 @@
/* $NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $ */
/*-
* Copyright (c) 1994-1998 Mark Brinicombe.
* Copyright (c) 1994 Brini.
* All rights reserved.
*
* This code is derived from software written for Brini by Mark Brinicombe
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Brini.
* 4. The name of the company nor the name of the author may be used to
* endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* machdep.c
*
* Machine dependant functions for kernel setup
*
* This file needs a lot of work.
*
* Created : 17/09/94
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_kstack_pages.h"
#define _ARM32_BUS_DMA_PRIVATE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sysproto.h>
#include <sys/signalvar.h>
#include <sys/imgact.h>
#include <sys/kernel.h>
#include <sys/ktr.h>
#include <sys/linker.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/pcpu.h>
#include <sys/proc.h>
#include <sys/ptrace.h>
#include <sys/cons.h>
#include <sys/bio.h>
#include <sys/bus.h>
#include <sys/buf.h>
#include <sys/exec.h>
#include <sys/kdb.h>
#include <sys/msgbuf.h>
#include <machine/reg.h>
#include <machine/cpu.h>
#include <machine/physmem.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <vm/vm_map.h>
#include <machine/devmap.h>
#include <machine/vmparam.h>
#include <machine/pcb.h>
#include <machine/undefined.h>
#include <machine/machdep.h>
#include <machine/metadata.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <sys/reboot.h>
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
#include <arm/xscale/i80321/iq80321reg.h>
#include <arm/xscale/i80321/obiovar.h>
#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
#define KERNEL_PT_IOPXS 1
#define KERNEL_PT_BEFOREKERN 2
#define KERNEL_PT_AFKERNEL 3 /* L2 table for mapping after kernel */
#define KERNEL_PT_AFKERNEL_NUM 9
/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
/* Physical and virtual addresses for some global pages */
struct pv_addr systempage;
struct pv_addr msgbufpv;
struct pv_addr irqstack;
struct pv_addr undstack;
struct pv_addr abtstack;
struct pv_addr kernelstack;
struct pv_addr minidataclean;
#define IQ80321_OBIO_BASE 0xfe800000UL
#define IQ80321_OBIO_SIZE 0x00100000UL
/* Static device mappings. */
static const struct arm_devmap_entry iq80321_devmap[] = {
/*
* Map the on-board devices VA == PA so that we can access them
* with the MMU on or off.
*/
{
IQ80321_OBIO_BASE,
IQ80321_OBIO_BASE,
IQ80321_OBIO_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_DEVICE,
},
{
IQ80321_IOW_VBASE,
VERDE_OUT_XLATE_IO_WIN0_BASE,
VERDE_OUT_XLATE_IO_WIN_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_DEVICE,
},
{
IQ80321_80321_VBASE,
VERDE_PMMR_BASE,
VERDE_PMMR_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_DEVICE,
},
{
0,
0,
0,
0,
0,
}
};
#define SDRAM_START 0xa0000000
extern vm_offset_t xscale_cache_clean_addr;
void *
initarm(struct arm_boot_params *abp)
{
struct pv_addr kernel_l1pt;
struct pv_addr dpcpu;
int loop, i;
u_int l1pagetable;
vm_offset_t freemempos;
vm_offset_t freemem_pt;
vm_offset_t afterkern;
vm_offset_t freemem_after;
vm_offset_t lastaddr;
uint32_t memsize, memstart;
lastaddr = parse_boot_param(abp);
arm_physmem_kernaddr = abp->abp_physaddr;
set_cpufuncs();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
/* Do basic tuning, hz etc */
init_param1();
freemempos = 0xa0200000;
/* Define a macro to simplify memory allocation */
#define valloc_pages(var, np) \
alloc_pages((var).pv_pa, (np)); \
(var).pv_va = (var).pv_pa + 0x20000000;
#define alloc_pages(var, np) \
freemempos -= (np * PAGE_SIZE); \
(var) = freemempos; \
memset((char *)(var), 0, ((np) * PAGE_SIZE));
while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
freemempos -= PAGE_SIZE;
valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
valloc_pages(kernel_pt_table[loop],
L2_TABLE_SIZE / PAGE_SIZE);
} else {
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa + 0x20000000;
}
}
freemem_pt = freemempos;
freemempos = 0xa0100000;
/*
* Allocate a page for the system page mapped to V0x00000000
* This page will just contain the system vectors and can be
* shared by all processes.
*/
valloc_pages(systempage, 1);
/* Allocate dynamic per-cpu area. */
valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
dpcpu_init((void *)dpcpu.pv_va, 0);
/* Allocate stacks for all modes */
valloc_pages(irqstack, IRQ_STACK_SIZE);
valloc_pages(abtstack, ABT_STACK_SIZE);
valloc_pages(undstack, UND_STACK_SIZE);
valloc_pages(kernelstack, kstack_pages);
alloc_pages(minidataclean.pv_pa, 1);
valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
/*
* Allocate memory for the l1 and l2 page tables. The scheme to avoid
* wasting memory by allocating the l1pt on the first 16k memory was
* taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
* this to work (which is supposed to be the case).
*/
/*
* Now we start construction of the L1 page table
* We start by mapping the L2 page tables into the L1.
* This means that we can replace L1 mappings later on if necessary
*/
l1pagetable = kernel_l1pt.pv_va;
/* Map the L2 pages tables in the L1 page table */
pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & ~(0x00100000 - 1),
&kernel_pt_table[KERNEL_PT_SYS]);
pmap_link_l2pt(l1pagetable, IQ80321_IOPXS_VBASE,
&kernel_pt_table[KERNEL_PT_IOPXS]);
pmap_link_l2pt(l1pagetable, KERNBASE,
&kernel_pt_table[KERNEL_PT_BEFOREKERN]);
pmap_map_chunk(l1pagetable, KERNBASE, SDRAM_START, 0x100000,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x100000, SDRAM_START + 0x100000,
0x100000, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
pmap_map_chunk(l1pagetable, KERNBASE + 0x200000, SDRAM_START + 0x200000,
(((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
- 1));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
/* Map the Mini-Data cache clean area. */
xscale_setup_minidata(l1pagetable, afterkern,
minidataclean.pv_pa);
/* Map the vector page. */
pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
arm_devmap_bootstrap(l1pagetable, iq80321_devmap);
/*
* Give the XScale global cache clean code an appropriately
* sized chunk of unmapped VA space starting at 0xff000000
* (our device mappings end before this address).
*/
xscale_cache_clean_addr = 0xff000000U;
cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
setttb(kernel_l1pt.pv_pa);
cpu_tlb_flushID();
cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
/*
* Pages were allocated during the secondary bootstrap for the
* stacks for different CPU modes.
* We must now set the r13 registers in the different CPU modes to
* point to these stacks.
* Since the ARM stacks use STMFD etc. we must set r13 to the top end
* of the stack memory.
*/
set_stackptrs(0);
/*
* We must now clean the cache again....
* Cleaning may be done by reading new data to displace any
* dirty data in the cache. This will have happened in setttb()
* but since we are boot strapping the addresses used for the read
* may have just been remapped and thus the cache could be out
* of sync. A re-clean after the switch will cure this.
* After booting there are no gross relocations of the kernel thus
* this problem will not occur after initarm().
*/
cpu_idcache_wbinv_all();
cpu_setup();
/*
* Fetch the SDRAM start/size from the i80321 SDRAM configration
* registers.
*/
i80321_calibrate_delay();
i80321_sdram_bounds(obio_bs_tag, IQ80321_80321_VBASE + VERDE_MCU_BASE,
&memstart, &memsize);
physmem = memsize / PAGE_SIZE;
cninit();
undefined_init();
init_proc0(kernelstack.pv_va);
/* Enable MMU, I-cache, D-cache, write buffer. */
arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
pmap_curmaxkvaddr = afterkern + PAGE_SIZE;
vm_max_kernel_address = 0xe0000000;
pmap_bootstrap(pmap_curmaxkvaddr, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, msgbufsize);
mutex_init();
/*
* Add the physical ram we have available.
*
* Exclude the kernel (and all the things we allocated which immediately
* follow the kernel) from the VM allocation pool but not from crash
* dumps. virtual_avail is a global variable which tracks the kva we've
* "allocated" while setting up pmaps.
*
* Prepare the list of physical memory available to the vm subsystem.
*/
arm_physmem_hardware_region(SDRAM_START, memsize);
arm_physmem_exclude_region(freemem_pt, abp->abp_physaddr -
freemem_pt, EXFLAG_NOALLOC);
arm_physmem_exclude_region(freemempos, abp->abp_physaddr - 0x100000 -
freemempos, EXFLAG_NOALLOC);
arm_physmem_exclude_region(abp->abp_physaddr,
virtual_avail - KERNVIRTADDR, EXFLAG_NOALLOC);
arm_physmem_init_kernel_globals();
init_param2(physmem);
kdb_init();
return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
sizeof(struct pcb)));
}
extern int
machdep_pci_route_interrupt(device_t pcib, device_t dev, int pin)
{
int bus;
int device;
int func;
uint32_t busno;
struct i80321_pci_softc *sc = device_get_softc(pcib);
bus = pci_get_bus(dev);
device = pci_get_slot(dev);
func = pci_get_function(dev);
busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
busno = PCIXSR_BUSNO(busno);
if (busno == 0xff)
busno = 0;
if (bus != busno)
goto no_mapping;
switch (device) {
/* IQ31244 PCI */
case 1: /* PCIX-PCIX bridge */
/*
* The S-ATA chips are behind the bridge, and all of
* the S-ATA interrupts are wired together.
*/
return (ICU_INT_XINT(2));
case 2: /* PCI slot */
/* All pins are wired together. */
return (ICU_INT_XINT(3));
case 3: /* i82546 dual Gig-E */
if (pin == 1 || pin == 2)
return (ICU_INT_XINT(0));
goto no_mapping;
/* IQ80321 PCI */
case 4: /* i82544 Gig-E */
case 8: /*
* Apparently you can set the device for the ethernet adapter
* to 8 with a jumper, so handle that as well
*/
if (pin == 1)
return (ICU_INT_XINT(0));
goto no_mapping;
case 6: /* S-PCI-X slot */
if (pin == 1)
return (ICU_INT_XINT(2));
if (pin == 2)
return (ICU_INT_XINT(3));
goto no_mapping;
default:
no_mapping:
printf("No mapping for %d/%d/%d/%c\n", bus, device, func, pin);
}
return (0);
}

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