- Add pci bus space that translates byte order to little endian,

may be it will be merged with bus_space_reversed later
- Handle memory resources close to bus in order to control
    bus_space_tag

sys/mips/atheros/ar71xx_pci.c

@@ -52,7 +52,8 @@ __FBSDID("$FreeBSD$");
 #include <dev/pci/pcib_private.h>
 #include "pcib_if.h"
 
-#include "mips/atheros/ar71xxreg.h"
+#include <mips/atheros/ar71xxreg.h>
+#include <mips/atheros/ar71xx_pci_bus_space.h>
 
 #undef AR71XX_PCI_DEBUG
 #ifdef AR71XX_PCI_DEBUG
@@ -354,7 +355,7 @@ ar71xx_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
 {
 
 	struct ar71xx_pci_softc *sc = device_get_softc(bus);	
-	struct resource *rv = NULL;
+	struct resource *rv;
 	struct rman *rm;
 
 	switch (type) {
@@ -382,9 +383,32 @@ ar71xx_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
 		}
 	} 
 
+
 	return (rv);
 }
 
+
+static int
+ar71xx_pci_activate_resource(device_t bus, device_t child, int type, int rid,
+    struct resource *r)
+{
+	int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
+	    child, type, rid, r));
+
+	if (!res) {
+		switch(type) {
+		case SYS_RES_MEMORY:
+		case SYS_RES_IOPORT:
+			rman_set_bustag(r, ar71xx_bus_space_pcimem);
+			break;
+		}
+	}
+
+	return (res);
+}
+
+
+
 static int
 ar71xx_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
 		int flags, driver_filter_t *filt, driver_intr_t *handler,
@@ -495,7 +519,7 @@ static device_method_t ar71xx_pci_methods[] = {
 	DEVMETHOD(bus_write_ivar,	ar71xx_pci_write_ivar),
 	DEVMETHOD(bus_alloc_resource,	ar71xx_pci_alloc_resource),
 	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
-	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
+	DEVMETHOD(bus_activate_resource, ar71xx_pci_activate_resource),
 	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
 	DEVMETHOD(bus_setup_intr,	ar71xx_pci_setup_intr),
 	DEVMETHOD(bus_teardown_intr,	ar71xx_pci_teardown_intr),

sys/mips/atheros/ar71xx_pci_bus_space.c

@@ -0,0 +1,198 @@
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/endian.h>
+
+#include <machine/bus.h>
+#include <mips/atheros/ar71xx_pci_bus_space.h>
+
+static bs_r_1_s_proto(pcimem);
+static bs_r_2_s_proto(pcimem);
+static bs_r_4_s_proto(pcimem);
+static bs_w_1_s_proto(pcimem);
+static bs_w_2_s_proto(pcimem);
+static bs_w_4_s_proto(pcimem);
+
+/*
+ * Bus space that handles offsets in word for 1/2 bytes read/write access.
+ * Byte order of values is handled by device drivers itself. 
+ */
+static struct bus_space bus_space_pcimem = {
+	/* cookie */
+	(void *) 0,
+
+	/* mapping/unmapping */
+	generic_bs_map,
+	generic_bs_unmap,
+	generic_bs_subregion,
+
+	/* allocation/deallocation */
+	NULL,
+	NULL,
+
+	/* barrier */
+	generic_bs_barrier,
+
+	/* read (single) */
+	generic_bs_r_1,
+	generic_bs_r_2,
+	generic_bs_r_4,
+	NULL,
+
+	/* read multiple */
+	generic_bs_rm_1,
+	generic_bs_rm_2,
+	generic_bs_rm_4,
+	NULL,
+
+	/* read region */
+	generic_bs_rr_1,
+	generic_bs_rr_2,
+	generic_bs_rr_4,
+	NULL,
+
+	/* write (single) */
+	generic_bs_w_1,
+	generic_bs_w_2,
+	generic_bs_w_4,
+	NULL,
+
+	/* write multiple */
+	generic_bs_wm_1,
+	generic_bs_wm_2,
+	generic_bs_wm_4,
+	NULL,
+
+	/* write region */
+	NULL,
+	generic_bs_wr_2,
+	generic_bs_wr_4,
+	NULL,
+
+	/* set multiple */
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+
+	/* set region */
+	NULL,
+	generic_bs_sr_2,
+	generic_bs_sr_4,
+	NULL,
+
+	/* copy */
+	NULL,
+	generic_bs_c_2,
+	NULL,
+	NULL,
+
+	/* read (single) stream */
+	pcimem_bs_r_1_s,
+	pcimem_bs_r_2_s,
+	pcimem_bs_r_4_s,
+	NULL,
+
+	/* read multiple stream */
+	generic_bs_rm_1,
+	generic_bs_rm_2,
+	generic_bs_rm_4,
+	NULL,
+
+	/* read region stream */
+	generic_bs_rr_1,
+	generic_bs_rr_2,
+	generic_bs_rr_4,
+	NULL,
+
+	/* write (single) stream */
+	pcimem_bs_w_1_s,
+	pcimem_bs_w_2_s,
+	pcimem_bs_w_4_s,
+	NULL,
+
+	/* write multiple stream */
+	generic_bs_wm_1,
+	generic_bs_wm_2,
+	generic_bs_wm_4,
+	NULL,
+
+	/* write region stream */
+	NULL,
+	generic_bs_wr_2,
+	generic_bs_wr_4,
+	NULL,
+};
+
+bus_space_tag_t ar71xx_bus_space_pcimem = &bus_space_pcimem;
+
+static uint8_t
+pcimem_bs_r_1_s(void *t, bus_space_handle_t h, bus_size_t o)
+{
+
+	return readb(h + (o &~ 3) + (3 - (o & 3)));
+}
+
+static void
+pcimem_bs_w_1_s(void *t, bus_space_handle_t h, bus_size_t o, u_int8_t v)
+{
+
+	writeb(h + (o &~ 3) + (3 - (o & 3)), v);
+}
+
+static uint16_t
+pcimem_bs_r_2_s(void *t, bus_space_handle_t h, bus_size_t o)
+{
+
+	return readw(h + (o &~ 3) + (2 - (o & 3)));
+}
+
+static void
+pcimem_bs_w_2_s(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v)
+{
+
+	writew(h + (o &~ 3) + (2 - (o & 3)), v);
+}
+
+static uint32_t
+pcimem_bs_r_4_s(void *t, bus_space_handle_t h, bus_size_t o)
+{
+	
+	return le32toh(readl(h + o));
+}
+
+static void
+pcimem_bs_w_4_s(void *t, bus_space_handle_t h, bus_size_t o, uint32_t v)
+{
+
+	writel(h + o, htole32(v));
+}

sys/mips/atheros/ar71xx_pci_bus_space.h

@@ -0,0 +1,33 @@
+/*-
+ * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice unmodified, this list of conditions, and the following
+ *    disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef __AR71XX_PCI_BUS_SPACEH__
+#define __AR71XX_PCI_BUS_SPACEH__
+
+extern bus_space_tag_t ar71xx_bus_space_pcimem;
+
+#endif /* __AR71XX_PCI_BUS_SPACEH__ */

sys/mips/atheros/files.ar71xx

@@ -5,6 +5,7 @@ mips/atheros/ar71xx_machdep.c	standard
 mips/atheros/ar71xx_ehci.c	optional ehci
 mips/atheros/ar71xx_ohci.c	optional ohci
 mips/atheros/ar71xx_pci.c	optional pci
+mips/atheros/ar71xx_pci_bus_space.c	optional pci
 mips/atheros/if_arge.c		optional arge
 mips/atheros/uart_bus_ar71xx.c	optional uart
 mips/atheros/uart_cpu_ar71xx.c	optional uart