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Whitespace fix.

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This commit is contained in:
yongari 2008-11-25 00:48:05 +00:00
parent 0f05178369
commit bcd9806bd1
3 changed files with 25 additions and 25 deletions
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34
sys/dev/fxp/if_fxp.c
View File

@ -526,7 +526,7 @@ fxp_attach(device_t dev)
* Systems based on the ICH2/ICH2-M chip from Intel, and possibly
* some systems based a normal 82559 design, have a defect where
* the chip can cause a PCI protocol violation if it receives
* a CU_RESUME command when it is entering the IDLE state. The
* a CU_RESUME command when it is entering the IDLE state. The
* workaround is to disable Dynamic Standby Mode, so the chip never
* deasserts CLKRUN#, and always remains in an active state.
*
@ -805,7 +805,7 @@ fxp_attach(device_t dev)
ifp->if_snd.ifq_drv_maxlen = FXP_NTXCB - 1;
IFQ_SET_READY(&ifp->if_snd);
/*
/*
* Hook our interrupt after all initialization is complete.
*/
error = bus_setup_intr(dev, sc->fxp_res[1], INTR_TYPE_NET | INTR_MPSAFE,
@ -899,7 +899,7 @@ fxp_detach(device_t dev)
struct fxp_softc *sc = device_get_softc(dev);
#ifdef DEVICE_POLLING
if (sc->ifp->if_capenable & IFCAP_POLLING)
if (sc->ifp->if_capenable & IFCAP_POLLING)
ether_poll_deregister(sc->ifp);
#endif
@ -964,7 +964,7 @@ fxp_suspend(device_t dev)
FXP_LOCK(sc);
fxp_stop(sc);
sc->suspended = 1;
FXP_UNLOCK(sc);
@ -996,7 +996,7 @@ fxp_resume(device_t dev)
return (0);
}
static void
static void
fxp_eeprom_shiftin(struct fxp_softc *sc, int data, int length)
{
uint16_t reg;
@ -1185,7 +1185,7 @@ fxp_start(struct ifnet *ifp)
}
/*
* Start packet transmission on the interface.
* Start packet transmission on the interface.
* This routine must be called with the softc lock held, and is an
* internal entry point only.
*/
@ -1511,10 +1511,10 @@ fxp_intr(void *xsc)
while ((statack = CSR_READ_1(sc, FXP_CSR_SCB_STATACK)) != 0) {
/*
* It should not be possible to have all bits set; the
* FXP_SCB_INTR_SWI bit always returns 0 on a read. If
* FXP_SCB_INTR_SWI bit always returns 0 on a read. If
* all bits are set, this may indicate that the card has
* been physically ejected, so ignore it.
*/
*/
if (statack == 0xff) {
FXP_UNLOCK(sc);
return;
@ -1770,7 +1770,7 @@ fxp_tick(void *xsc)
* with external storage to be released in a timely manner rather
* than being defered for a potentially long time. This limits
* the delay to a maximum of one second.
*/
*/
fxp_txeof(sc);
/*
@ -2203,11 +2203,11 @@ fxp_ifmedia_upd(struct ifnet *ifp)
mii = device_get_softc(sc->miibus);
FXP_LOCK(sc);
if (mii->mii_instance) {
struct mii_softc *miisc;
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
mii_phy_reset(miisc);
}
if (mii->mii_instance) {
struct mii_softc *miisc;
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
mii_phy_reset(miisc);
}
mii_mediachg(mii);
FXP_UNLOCK(sc);
return (0);
@ -2260,7 +2260,7 @@ fxp_add_rfabuf(struct fxp_softc *sc, struct fxp_rx *rxp, struct mbuf *oldm)
m = oldm;
m->m_data = m->m_ext.ext_buf;
/*
* return error so the receive loop will
* return error so the receive loop will
* not pass the packet to upper layer
*/
reused_mbuf = EAGAIN;
@ -2688,7 +2688,7 @@ fxp_load_ucode(struct fxp_softc *sc)
bus_dmamap_sync(sc->cbl_tag, sc->cbl_map, BUS_DMASYNC_POSTWRITE);
device_printf(sc->dev,
"Microcode loaded, int_delay: %d usec bundle_max: %d\n",
sc->tunable_int_delay,
sc->tunable_int_delay,
uc->bundle_max_offset == 0 ? 0 : sc->tunable_bundle_max);
sc->flags |= FXP_FLAG_UCODE;
}
@ -2710,7 +2710,7 @@ sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
/*
* Interrupt delay is expressed in microseconds, a multiplier is used
* to convert this to the appropriate clock ticks before using.
* to convert this to the appropriate clock ticks before using.
*/
static int
sysctl_hw_fxp_int_delay(SYSCTL_HANDLER_ARGS)

4
sys/dev/fxp/if_fxpreg.h
View File

@ -287,7 +287,7 @@ struct fxp_cb_tx {
/*
* The following structure isn't actually part of the TxCB,
* unless the extended TxCB feature is being used. In this
* case, the first two elements of the structure below are
* case, the first two elements of the structure below are
* fetched along with the TxCB.
*/
union {
@ -420,7 +420,7 @@ struct fxp_stats {
};
#define FXP_STATS_DUMP_COMPLETE 0xa005
#define FXP_STATS_DR_COMPLETE 0xa007
/*
* Serial EEPROM control register bits
*/

12
sys/dev/fxp/if_fxpvar.h
View File

@ -1,13 +1,13 @@
/*-
* Copyright (c) 1995, David Greenman
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice unmodified, this list of conditions, and the following
* disclaimer.
* disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
@ -86,16 +86,16 @@
/*
* Default maximum time, in microseconds, that an interrupt may be delayed
* in an attempt to coalesce interrupts. This is only effective if the Intel
* in an attempt to coalesce interrupts. This is only effective if the Intel
* microcode is loaded, and may be changed via either loader tunables or
* sysctl. See also the CPUSAVER_DWORD entry in rcvbundl.h.
*/
#define TUNABLE_INT_DELAY 1000
/*
* Default number of packets that will be bundled, before an interrupt is
* Default number of packets that will be bundled, before an interrupt is
* generated. This is only effective if the Intel microcode is loaded, and
* may be changed via either loader tunables or sysctl. This may not be
* may be changed via either loader tunables or sysctl. This may not be
* present in all microcode revisions, see also the CPUSAVER_BUNDLE_MAX_DWORD
* entry in rcvbundl.h.
*/