Fix support for _PDC by using the proper version/length format for the
buffer. Also, reference the Intel document where the _PDC values were found. This now supports ACPI-assisted SpeedStep on my borrowed T42.
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@ -247,7 +247,8 @@ static int
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acpi_cpu_attach(device_t dev)
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{
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ACPI_BUFFER buf;
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ACPI_OBJECT *obj;
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ACPI_OBJECT arg, *obj;
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ACPI_OBJECT_LIST arglist;
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struct pcpu *pcpu_data;
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struct acpi_cpu_softc *sc;
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struct acpi_softc *acpi_sc;
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@ -255,6 +256,7 @@ acpi_cpu_attach(device_t dev)
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u_int features;
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int cpu_id, drv_count, i;
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driver_t **drivers;
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uint32_t cap_set[3];
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ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
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@ -295,6 +297,7 @@ acpi_cpu_attach(device_t dev)
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* Before calling any CPU methods, collect child driver feature hints
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* and notify ACPI of them.
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*/
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sc->cpu_features = 0;
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if (devclass_get_drivers(acpi_cpu_devclass, &drivers, &drv_count) == 0) {
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for (i = 0; i < drv_count; i++) {
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if (ACPI_GET_FEATURES(drivers[i], &features) == 0)
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@ -302,8 +305,24 @@ acpi_cpu_attach(device_t dev)
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}
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free(drivers, M_TEMP);
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}
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if (sc->cpu_features)
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acpi_SetInteger(sc->cpu_dev, "_PDC", sc->cpu_features);
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/*
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* CPU capabilities are specified as a buffer of 32-bit integers:
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* revision, count, and one or more capabilities. The revision of
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* "1" is not specified anywhere but seems to match Linux. We should
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* also support _OSC here.
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*/
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if (sc->cpu_features) {
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arglist.Pointer = &arg;
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arglist.Count = 1;
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arg.Type = ACPI_TYPE_BUFFER;
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arg.Buffer.Length = sizeof(cap_set);
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arg.Buffer.Pointer = (uint8_t *)cap_set;
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cap_set[0] = 1; /* revision */
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cap_set[1] = 1; /* number of capabilities integers */
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cap_set[2] = sc->cpu_features;
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AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL);
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}
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/*
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* Probe for Cx state support. If it isn't present, free up unused
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@ -168,6 +168,8 @@ extern struct mtx acpi_mutex;
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/*
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* Various features and capabilities for the acpi_get_features() method.
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* In particular, these are used for the ACPI 3.0 _PDC and _OSC methods.
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* See the Intel document titled "Processor Driver Capabilities Bit
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* Definitions", number 302223-002.
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*/
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#define ACPI_CAP_PERF_MSRS (1 << 0) /* Intel SpeedStep PERF_CTL MSRs */
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#define ACPI_CAP_C1_IO_HALT (1 << 1) /* Intel C1 "IO then halt" sequence */
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