d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add SOC_ALTERA_* kernel options per each SoC and use it to

Browse Source 
conditionally compile the code.

Reviewed by:	andrew
Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D9836
This commit is contained in:
br 2017-02-28 16:20:33 +00:00
parent 277b21915c
commit bd315f5918
4 changed files with 65 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
sys/arm/altera/socfpga/socfpga_machdep.c
View File

@ -54,6 +54,7 @@ __FBSDID("$FreeBSD$");
#include "platform_if.h"
#if defined(SOC_ALTERA_CYCLONE5)
static int
socfpga_devmap_init(platform_t plat)
{
@ -82,7 +83,9 @@ socfpga_devmap_init(platform_t plat)
return (0);
}
#endif
#if defined(SOC_ALTERA_ARRIA10)
static int
socfpga_a10_devmap_init(platform_t plat)
{
@ -101,9 +104,10 @@ socfpga_a10_devmap_init(platform_t plat)
return (0);
}
#endif
static void
_socfpga_cpu_reset(platform_t plat, uint32_t reg)
_socfpga_cpu_reset(bus_size_t reg)
{
uint32_t paddr;
bus_addr_t vaddr;
@ -127,20 +131,25 @@ _socfpga_cpu_reset(platform_t plat, uint32_t reg)
while (1);
}
#if defined(SOC_ALTERA_CYCLONE5)
static void
socfpga_cpu_reset(platform_t plat)
{
_socfpga_cpu_reset(plat, RSTMGR_CTRL);
_socfpga_cpu_reset(RSTMGR_CTRL);
}
#endif
#if defined(SOC_ALTERA_ARRIA10)
static void
socfpga_a10_cpu_reset(platform_t plat)
{
_socfpga_cpu_reset(plat, RSTMGR_A10_CTRL);
_socfpga_cpu_reset(RSTMGR_A10_CTRL);
}
#endif
#if defined(SOC_ALTERA_CYCLONE5)
static platform_method_t socfpga_methods[] = {
PLATFORMMETHOD(platform_devmap_init, socfpga_devmap_init),
PLATFORMMETHOD(platform_cpu_reset, socfpga_cpu_reset),
@ -151,7 +160,9 @@ static platform_method_t socfpga_methods[] = {
PLATFORMMETHOD_END,
};
FDT_PLATFORM_DEF(socfpga, "socfpga", 0, "altr,socfpga-cyclone5", 200);
#endif
#if defined(SOC_ALTERA_ARRIA10)
static platform_method_t socfpga_a10_methods[] = {
PLATFORMMETHOD(platform_devmap_init, socfpga_a10_devmap_init),
PLATFORMMETHOD(platform_cpu_reset, socfpga_a10_cpu_reset),
@ -162,3 +173,4 @@ static platform_method_t socfpga_a10_methods[] = {
PLATFORMMETHOD_END,
};
FDT_PLATFORM_DEF(socfpga_a10, "socfpga", 0, "altr,socfpga-arria10", 200);
#endif

60
sys/arm/altera/socfpga/socfpga_mp.c
View File

@ -75,8 +75,8 @@ __FBSDID("$FreeBSD$");
#define RAM_PHYSBASE 0x0
#define RAM_SIZE 0x1000
#define SOCFPGA_SOCKIT 1
#define SOCFPGA_SOCDK 2
#define SOCFPGA_ARRIA10 1
#define SOCFPGA_CYCLONE5 2
extern char *mpentry_addr;
static void socfpga_trampoline(void);
@ -112,22 +112,31 @@ socfpga_mp_setmaxid(platform_t plat)
mp_maxid = ncpu - 1;
}
static void
_socfpga_mp_start_ap(platform_t plat, uint32_t platid)
_socfpga_mp_start_ap(uint32_t platid)
{
bus_space_handle_t scu, rst, ram;
int reg;
if (platid == SOCFPGA_SOCDK) {
switch (platid) {
#if defined(SOC_ALTERA_ARRIA10)
case SOCFPGA_ARRIA10:
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10,
SCU_SIZE, 0, &scu) != 0)
panic("Couldn't map the SCU\n");
} else {
panic("Couldn't map the SCU\n");
break;
#endif
#if defined(SOC_ALTERA_CYCLONE5)
case SOCFPGA_CYCLONE5:
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
SCU_SIZE, 0, &scu) != 0)
panic("Couldn't map the SCU\n");
panic("Couldn't map the SCU\n");
break;
#endif
default:
panic("Unknown platform id %d\n", platid);
}
if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
RSTMGR_SIZE, 0, &rst) != 0)
panic("Couldn't map the reset manager (RSTMGR)\n");
@ -149,12 +158,21 @@ _socfpga_mp_start_ap(platform_t plat, uint32_t platid)
bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
/* Put CPU1 to reset state */
if (platid == SOCFPGA_SOCDK) {
switch (platid) {
#if defined(SOC_ALTERA_ARRIA10)
case SOCFPGA_ARRIA10:
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1);
} else {
break;
#endif
#if defined(SOC_ALTERA_CYCLONE5)
case SOCFPGA_CYCLONE5:
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_MPUMODRST, MPUMODRST_CPU1);
break;
#endif
default:
panic("Unknown platform id %d\n", platid);
}
/* Enable the SCU, then clean the cache on this core */
@ -170,12 +188,21 @@ _socfpga_mp_start_ap(platform_t plat, uint32_t platid)
dcache_wbinv_poc_all();
/* Put CPU1 out from reset */
if (platid == SOCFPGA_SOCDK) {
switch (platid) {
#if defined(SOC_ALTERA_ARRIA10)
case SOCFPGA_ARRIA10:
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_A10_MPUMODRST, 0);
} else {
break;
#endif
#if defined(SOC_ALTERA_CYCLONE5)
case SOCFPGA_CYCLONE5:
bus_space_write_4(fdtbus_bs_tag, rst,
RSTMGR_MPUMODRST, 0);
break;
#endif
default:
panic("Unknown platform id %d\n", platid);
}
dsb();
@ -186,17 +213,20 @@ _socfpga_mp_start_ap(platform_t plat, uint32_t platid)
bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
}
#if defined(SOC_ALTERA_ARRIA10)
void
socfpga_a10_mp_start_ap(platform_t plat)
{
_socfpga_mp_start_ap(plat, SOCFPGA_SOCDK);
_socfpga_mp_start_ap(SOCFPGA_ARRIA10);
}
#endif
#if defined(SOC_ALTERA_CYCLONE5)
void
socfpga_mp_start_ap(platform_t plat)
{
_socfpga_mp_start_ap(plat, SOCFPGA_SOCKIT);
_socfpga_mp_start_ap(SOCFPGA_CYCLONE5);
}
#endif

3
sys/arm/conf/SOCFPGA
View File

@ -32,6 +32,9 @@ options PLATFORM_SMP
options SMP # Enable multiple cores
options MULTIDELAY
options SOC_ALTERA_ARRIA10
options SOC_ALTERA_CYCLONE5
# NFS root from boopt/dhcp
#options BOOTP
#options BOOTP_NFSROOT

2
sys/conf/options.arm
View File

@ -50,6 +50,8 @@ SOC_ALLWINNER_A31S opt_global.h
SOC_ALLWINNER_A33 opt_global.h
SOC_ALLWINNER_A83T opt_global.h
SOC_ALLWINNER_H3 opt_global.h
SOC_ALTERA_ARRIA10 opt_global.h
SOC_ALTERA_CYCLONE5 opt_global.h
SOC_BCM2835 opt_global.h
SOC_BCM2836 opt_global.h
SOC_IMX51 opt_global.h