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Migrate the sample rate module to the new ath_hal_gettxcompletionrates() API.

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This removes the chipset-dependent TX DMA completion descriptor groveling.
It should now be (more) portable to other, later atheros chipsets when the
time comes.
This commit is contained in:
Adrian Chadd 2011-01-20 08:19:23 +00:00
parent 82d2927d95
commit bd97c52a22
2 changed files with 35 additions and 98 deletions
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92
sys/dev/ath/ath_rate/sample/sample.c
View File

@ -600,38 +600,16 @@ ath_rate_tx_complete(struct ath_softc *sc, struct ath_node *an,
0, 0,
short_tries, long_tries, ts->ts_status);
} else {
int hwrate0, rix0, tries0;
int hwrate1, rix1, tries1;
int hwrate2, rix2, tries2;
int hwrate3, rix3, tries3;
int hwrates[4], tries[4], rix[4];
int finalTSIdx = ts->ts_finaltsi;
int i;
/*
* Process intermediate rates that failed.
*/
if (sc->sc_ah->ah_magic != 0x20065416) {
hwrate0 = MS(ds0->ds_ctl3, AR_XmitRate0);
hwrate1 = MS(ds0->ds_ctl3, AR_XmitRate1);
hwrate2 = MS(ds0->ds_ctl3, AR_XmitRate2);
hwrate3 = MS(ds0->ds_ctl3, AR_XmitRate3);
} else {
hwrate0 = MS(ds0->ds_ctl3, AR5416_XmitRate0);
hwrate1 = MS(ds0->ds_ctl3, AR5416_XmitRate1);
hwrate2 = MS(ds0->ds_ctl3, AR5416_XmitRate2);
hwrate3 = MS(ds0->ds_ctl3, AR5416_XmitRate3);
}
rix0 = rt->rateCodeToIndex[hwrate0];
tries0 = MS(ds0->ds_ctl2, AR_XmitDataTries0);
rix1 = rt->rateCodeToIndex[hwrate1];
tries1 = MS(ds0->ds_ctl2, AR_XmitDataTries1);
rix2 = rt->rateCodeToIndex[hwrate2];
tries2 = MS(ds0->ds_ctl2, AR_XmitDataTries2);
rix3 = rt->rateCodeToIndex[hwrate3];
tries3 = MS(ds0->ds_ctl2, AR_XmitDataTries3);
ath_hal_gettxcompletionrates(sc->sc_ah, ds0, hwrates, tries);
for (i = 0; i < 4; i++)
rix[i] = rt->rateCodeToIndex[hwrates[i]];
IEEE80211_NOTE(an->an_node.ni_vap, IEEE80211_MSG_RATECTL,
&an->an_node,
@ -641,19 +619,19 @@ ath_rate_tx_complete(struct ath_softc *sc, struct ath_node *an,
finalTSIdx,
long_tries,
ts->ts_status ? "FAIL" : "OK",
rix0, tries0,
rix1, tries1,
rix2, tries2,
rix3, tries3);
rix[0], tries[0],
rix[1], tries[1],
rix[2], tries[2],
rix[3], tries[3]);
if (tries0 && !IS_RATE_DEFINED(sn, rix0))
badrate(ifp, 0, hwrate0, tries0, ts->ts_status);
if (tries1 && !IS_RATE_DEFINED(sn, rix1))
badrate(ifp, 1, hwrate1, tries1, ts->ts_status);
if (tries2 && !IS_RATE_DEFINED(sn, rix2))
badrate(ifp, 2, hwrate2, tries2, ts->ts_status);
if (tries3 && !IS_RATE_DEFINED(sn, rix3))
badrate(ifp, 3, hwrate3, tries3, ts->ts_status);
if (tries[0] && !IS_RATE_DEFINED(sn, rix[0]))
badrate(ifp, 0, hwrates[0], tries[0], ts->ts_status);
if (tries[1] && !IS_RATE_DEFINED(sn, rix[1]))
badrate(ifp, 1, hwrates[1], tries[1], ts->ts_status);
if (tries[2] && !IS_RATE_DEFINED(sn, rix[2]))
badrate(ifp, 2, hwrates[2], tries[2], ts->ts_status);
if (tries[3] && !IS_RATE_DEFINED(sn, rix[3]))
badrate(ifp, 3, hwrates[3], tries[3], ts->ts_status);
/*
* NB: series > 0 are not penalized for failure
@ -662,42 +640,42 @@ ath_rate_tx_complete(struct ath_softc *sc, struct ath_node *an,
* sample higher rates 1 try at a time doing so
* may unfairly penalize them.
*/
if (tries0) {
if (tries[0]) {
update_stats(sc, an, frame_size,
rix0, tries0,
rix1, tries1,
rix2, tries2,
rix3, tries3,
rix[0], tries[0],
rix[1], tries[1],
rix[2], tries[2],
rix[3], tries[3],
short_tries, long_tries,
long_tries > tries0);
long_tries -= tries0;
long_tries > tries[0]);
long_tries -= tries[0];
}
if (tries1 && finalTSIdx > 0) {
if (tries[1] && finalTSIdx > 0) {
update_stats(sc, an, frame_size,
rix1, tries1,
rix2, tries2,
rix3, tries3,
rix[1], tries[1],
rix[2], tries[2],
rix[3], tries[3],
0, 0,
short_tries, long_tries,
ts->ts_status);
long_tries -= tries1;
long_tries -= tries[1];
}
if (tries2 && finalTSIdx > 1) {
if (tries[2] && finalTSIdx > 1) {
update_stats(sc, an, frame_size,
rix2, tries2,
rix3, tries3,
rix[2], tries[2],
rix[3], tries[3],
0, 0,
0, 0,
short_tries, long_tries,
ts->ts_status);
long_tries -= tries2;
long_tries -= tries[2];
}
if (tries3 && finalTSIdx > 2) {
if (tries[3] && finalTSIdx > 2) {
update_stats(sc, an, frame_size,
rix3, tries3,
rix[3], tries[3],
0, 0,
0, 0,
0, 0,

41
sys/dev/ath/ath_rate/sample/sample.h
View File

@ -110,47 +110,6 @@ struct sample_node {
#define WIFI_CW_MIN 31
#define WIFI_CW_MAX 1023
/*
* Definitions for pulling the rate and trie counts from
* a 5212 h/w descriptor. These Don't belong here; the
* driver should record this information so the rate control
* code doesn't go groveling around in the descriptor bits.
*/
#define ds_ctl2 ds_hw[0]
#define ds_ctl3 ds_hw[1]
/* TX ds_ctl2 */
#define AR_XmitDataTries0 0x000f0000 /* series 0 max attempts */
#define AR_XmitDataTries0_S 16
#define AR_XmitDataTries1 0x00f00000 /* series 1 max attempts */
#define AR_XmitDataTries1_S 20
#define AR_XmitDataTries2 0x0f000000 /* series 2 max attempts */
#define AR_XmitDataTries2_S 24
#define AR_XmitDataTries3 0xf0000000 /* series 3 max attempts */
#define AR_XmitDataTries3_S 28
/* TX ds_ctl3 */
#define AR_XmitRate0 0x0000001f /* series 0 tx rate */
#define AR_XmitRate0_S 0
#define AR_XmitRate1 0x000003e0 /* series 1 tx rate */
#define AR_XmitRate1_S 5
#define AR_XmitRate2 0x00007c00 /* series 2 tx rate */
#define AR_XmitRate2_S 10
#define AR_XmitRate3 0x000f8000 /* series 3 tx rate */
#define AR_XmitRate3_S 15
/* TX ds_ctl3 for 5416 */
#define AR5416_XmitRate0 0x000000ff /* series 0 tx rate */
#define AR5416_XmitRate0_S 0
#define AR5416_XmitRate1 0x0000ff00 /* series 1 tx rate */
#define AR5416_XmitRate1_S 8
#define AR5416_XmitRate2 0x00ff0000 /* series 2 tx rate */
#define AR5416_XmitRate2_S 16
#define AR5416_XmitRate3 0xff000000 /* series 3 tx rate */
#define AR5416_XmitRate3_S 24
#define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
/*
* Calculate the transmit duration of a frame.
*/