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Introduce IA64_ID_PAGE_{MASK|SHIFT|SIZE} and LOG2_ID_PAGE_SIZE. The

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latter is a kernel option for IA64_ID_PAGE_SHIFT, which in turn
determines IA64_ID_PAGE_MASK and IA64_ID_PAGE_SIZE.

The constants are used instead of the literal hardcoding (in its
various forms) of the size of the direct mappings created in region
6 and 7. The default and probably only workable size is still 256M,
but for kicks we use 128M for LINT.
This commit is contained in:
marcel 2003-09-09 05:59:09 +00:00
parent 53db1769f3
commit bdbd90ef2b
6 changed files with 26 additions and 8 deletions
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5
sys/ia64/conf/NOTES
View File

@ -23,6 +23,11 @@ cpu ITANIUM2
# ia64. It is based on the ia32 emulation in the processor.
options IA32
# option: LOG2_ID_PAGE_SIZE
# Specify the log2 size of the identity (direct) mappings in regions 6 and 7
# of the virtual address space.
options LOG2_ID_PAGE_SIZE=27 # 128M
# option: LOG2_PAGE_SIZE
# Specify the log2 size of the page to be used for virtual memory management.
# The page size being equal to 1<<LOG2_PAGE_SIZE.

2
sys/ia64/ia64/genassym.c
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@ -76,6 +76,8 @@ ASSYM(ERESTART, ERESTART);
ASSYM(FRAME_SYSCALL, FRAME_SYSCALL);
ASSYM(IA64_ID_PAGE_SHIFT, IA64_ID_PAGE_SHIFT);
ASSYM(KSTACK_PAGES, KSTACK_PAGES);
ASSYM(MC_PRESERVED, offsetof(mcontext_t, mc_preserved));

6
sys/ia64/ia64/locore.S
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@ -177,20 +177,20 @@ ENTRY(os_boot_rendez,0)
mov rr[r17] = r16
;;
srlz.d
mov r16 = (6<<8)|(28<<2)
mov r16 = (6<<8)|(IA64_ID_PAGE_SHIFT<<2)
movl r17 = 6<<61
;;
mov rr[r17] = r16
;;
srlz.d
mov r16 = (7<<8)|(28<<2)
mov r16 = (7<<8)|(IA64_ID_PAGE_SHIFT<<2)
movl r17 = 7<<61
;;
mov rr[r17] = r16
;;
srlz.d
mov r16 = (PTE_P|PTE_MA_WB|PTE_A|PTE_D|PTE_PL_KERN|PTE_AR_RWX)
mov r18 = 28<<2
mov r18 = IA64_ID_PAGE_SHIFT<<2
;;
mov cr.ifa = r17

6
sys/ia64/ia64/machdep.c
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@ -361,14 +361,14 @@ map_pal_code(void)
pte.pte_ppn = ia64_pal_base >> 12;
__asm __volatile("ptr.d %0,%1; ptr.i %0,%1" ::
"r"(IA64_PHYS_TO_RR7(ia64_pal_base)), "r"(28 << 2));
"r"(IA64_PHYS_TO_RR7(ia64_pal_base)), "r"(IA64_ID_PAGE_SHIFT<<2));
__asm __volatile("mov %0=psr" : "=r"(psr));
__asm __volatile("rsm psr.ic|psr.i");
__asm __volatile("srlz.i");
__asm __volatile("mov cr.ifa=%0" ::
"r"(IA64_PHYS_TO_RR7(ia64_pal_base)));
__asm __volatile("mov cr.itir=%0" :: "r"(28 << 2));
__asm __volatile("mov cr.itir=%0" :: "r"(IA64_ID_PAGE_SHIFT << 2));
__asm __volatile("itr.d dtr[%0]=%1" :: "r"(1), "r"(*(u_int64_t*)&pte));
__asm __volatile("srlz.d"); /* XXX not needed. */
__asm __volatile("itr.i itr[%0]=%1" :: "r"(1), "r"(*(u_int64_t*)&pte));
@ -562,7 +562,7 @@ ia64_init(void)
/* OUTPUT NOW ALLOWED */
if (ia64_pal_base != 0) {
ia64_pal_base &= ~((1 << 28) - 1);
ia64_pal_base &= ~IA64_ID_PAGE_MASK;
/*
* We use a TR to map the first 256M of memory - this might
* cover the palcode too.

4
sys/ia64/ia64/pmap.c
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@ -483,8 +483,8 @@ pmap_bootstrap()
* handlers. Here we just make sure that they have the largest
* possible page size to minimise TLB usage.
*/
ia64_set_rr(IA64_RR_BASE(6), (6 << 8) | (28 << 2));
ia64_set_rr(IA64_RR_BASE(7), (7 << 8) | (28 << 2));
ia64_set_rr(IA64_RR_BASE(6), (6 << 8) | (IA64_ID_PAGE_SHIFT << 2));
ia64_set_rr(IA64_RR_BASE(7), (7 << 8) | (IA64_ID_PAGE_SHIFT << 2));
/*
* Reserve some memory for allocating pvs while bootstrapping

11
sys/ia64/include/vmparam.h
View File

@ -133,6 +133,17 @@
#define IA64_PHYS_TO_RR6(x) ((x) | IA64_RR_BASE(6))
#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7))
/*
* Page size of the identity mappings in region 7.
*/
#ifndef LOG2_ID_PAGE_SIZE
#define LOG2_ID_PAGE_SIZE 28 /* 256M */
#endif
#define IA64_ID_PAGE_SHIFT (LOG2_ID_PAGE_SIZE)
#define IA64_ID_PAGE_SIZE (1<<(LOG2_ID_PAGE_SIZE))
#define IA64_ID_PAGE_MASK (IA64_ID_PAGE_SIZE-1)
/*
* Mach derived constants
*/