powerpc/mpc85xx: Add MSI support for Freescale PowerPC SoCs
Freescale SoCs use a set of IRQs at the high end of the OpenPIC IRQ list, not counted in the NIRQs of the Feature reporting register. Some SoCs include a MSI inbound window in the PCIe controller configuration registers as well, but some don't. Currently, this only handles the SoCs *with* the MSI window. There are 256 MSIs per MSI bank (32 per MSI IRQ, 8 IRQs per MSI bank). The P5020 has 3 banks, yielding up to 768 MSIs; older SoCs have only one bank.
This commit is contained in:
jhibbits
parent
8dc188276e
commit
bdcbfe133b
@ -35,6 +35,7 @@
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#define OPENPIC_IRQMAX 256 /* h/w allows more */
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#define OPENPIC_QUIRK_SINGLE_BIND 1 /* Bind interrupts to only 1 CPU */
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#define OPENPIC_QUIRK_HIDDEN_IRQS 2 /* May have IRQs beyond FRR[NIRQ] */
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/* Names match the macros in openpicreg.h. */
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struct openpic_timer {
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@ -51,8 +51,10 @@ __FBSDID("$FreeBSD$");
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/queue.h>
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#include <sys/rman.h>
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#include <sys/endian.h>
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#include <sys/vmem.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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@ -67,6 +69,7 @@ __FBSDID("$FreeBSD$");
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#include "ofw_bus_if.h"
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#include "pcib_if.h"
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#include "pic_if.h"
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#include <machine/resource.h>
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#include <machine/bus.h>
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@ -80,6 +83,12 @@ __FBSDID("$FreeBSD$");
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#define REG_CFG_DATA 0x0004
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#define REG_INT_ACK 0x0008
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#define REG_PEX_IP_BLK_REV1 0x0bf8
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#define IP_MJ_M 0x0000ff00
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#define IP_MJ_S 8
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#define IP_MN_M 0x000000ff
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#define IP_MN_S 0
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#define REG_POTAR(n) (0x0c00 + 0x20 * (n))
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#define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
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#define REG_POWBAR(n) (0x0c08 + 0x20 * (n))
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@ -89,6 +98,12 @@ __FBSDID("$FreeBSD$");
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#define REG_PIWBAR(n) (0x0e08 - 0x20 * (n))
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#define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n))
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#define REG_PIWAR(n) (0x0e10 - 0x20 * (n))
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#define PIWAR_EN 0x80000000
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#define PIWAR_PF 0x40000000
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#define PIWAR_TRGT_M 0x00f00000
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#define PIWAR_TRGT_S 20
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#define PIWAR_TRGT_CCSR 0xe
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#define PIWAR_TRGT_LOCAL 0xf
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#define REG_PEX_MES_DR 0x0020
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#define REG_PEX_MES_IER 0x0028
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@ -123,10 +138,14 @@ __FBSDID("$FreeBSD$");
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#define DEVFN(b, s, f) ((b << 16) | (s << 8) | f)
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#define FSL_NUM_MSIS 256 /* 8 registers of 32 bits (8 hardware IRQs) */
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struct fsl_pcib_softc {
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struct ofw_pci_softc pci_sc;
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device_t sc_dev;
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struct mtx sc_cfg_mtx;
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int sc_ip_maj;
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int sc_ip_min;
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int sc_iomem_target;
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bus_addr_t sc_iomem_start, sc_iomem_end;
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@ -151,6 +170,14 @@ struct fsl_pcib_err_dr {
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uint32_t err_dr_mask;
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};
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struct fsl_msi_map {
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SLIST_ENTRY(fsl_msi_map) slist;
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uint32_t irq_base;
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bus_addr_t target;
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};
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SLIST_HEAD(msi_head, fsl_msi_map) fsl_msis = SLIST_HEAD_INITIALIZER(msi_head);
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static const struct fsl_pcib_err_dr pci_err[] = {
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{"ME", REG_PEX_ERR_DR_ME},
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{"PCT", REG_PEX_ERR_DR_PCT},
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@ -195,6 +222,16 @@ static int fsl_pcib_maxslots(device_t);
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static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
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static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
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uint32_t, int);
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static int fsl_pcib_alloc_msi(device_t dev, device_t child,
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int count, int maxcount, int *irqs);
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static int fsl_pcib_release_msi(device_t dev, device_t child,
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int count, int *irqs);
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static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq);
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static int fsl_pcib_release_msix(device_t dev, device_t child, int irq);
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static int fsl_pcib_map_msi(device_t dev, device_t child,
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int irq, uint64_t *addr, uint32_t *data);
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static vmem_t *msi_vmem; /* Global MSI vmem, holds all MSI ranges. */
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/*
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* Bus interface definitions.
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@ -209,6 +246,11 @@ static device_method_t fsl_pcib_methods[] = {
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DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots),
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DEVMETHOD(pcib_read_config, fsl_pcib_read_config),
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DEVMETHOD(pcib_write_config, fsl_pcib_write_config),
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DEVMETHOD(pcib_alloc_msi, fsl_pcib_alloc_msi),
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DEVMETHOD(pcib_release_msi, fsl_pcib_release_msi),
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DEVMETHOD(pcib_alloc_msix, fsl_pcib_alloc_msix),
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DEVMETHOD(pcib_release_msix, fsl_pcib_release_msix),
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DEVMETHOD(pcib_map_msi, fsl_pcib_map_msi),
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DEVMETHOD_END
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};
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@ -272,7 +314,7 @@ fsl_pcib_attach(device_t dev)
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{
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struct fsl_pcib_softc *sc;
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phandle_t node;
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uint32_t cfgreg, brctl;
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uint32_t cfgreg, brctl, ipreg;
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int error, rid;
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uint8_t ltssm, capptr;
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@ -290,6 +332,9 @@ fsl_pcib_attach(device_t dev)
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sc->sc_bsh = rman_get_bushandle(sc->sc_res);
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sc->sc_busnr = 0;
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ipreg = bus_read_4(sc->sc_res, REG_PEX_IP_BLK_REV1);
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sc->sc_ip_min = (ipreg & IP_MN_M) >> IP_MN_S;
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sc->sc_ip_maj = (ipreg & IP_MJ_M) >> IP_MJ_S;
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mtx_init(&sc->sc_cfg_mtx, "pcicfg", NULL, MTX_SPIN);
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cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2);
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@ -533,14 +578,16 @@ fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, uint64_t start,
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KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__));
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attr = PIWAR_EN;
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switch (tgt) {
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/* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */
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case OCP85XX_TGTIF_RAM1_85XX:
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case OCP85XX_TGTIF_RAM1_QORIQ:
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attr = 0xa0f55000 | (ffsl(size) - 2);
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case -1:
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attr &= ~PIWAR_EN;
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break;
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case PIWAR_TRGT_LOCAL:
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attr |= (ffsl(size) - 2);
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default:
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attr = 0;
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attr |= (tgt << PIWAR_TRGT_S);
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break;
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}
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tar = start >> 12;
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@ -702,8 +749,209 @@ fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc)
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fsl_pcib_inbound(sc, 1, -1, 0, 0, 0);
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fsl_pcib_inbound(sc, 2, -1, 0, 0, 0);
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fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0,
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2U * 1024U * 1024U * 1024U, 0);
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fsl_pcib_inbound(sc, 3, PIWAR_TRGT_LOCAL, 0,
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ptoa(Maxmem), 0);
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/* Direct-map the CCSR for MSIs. */
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/* Freescale PCIe 2.x has a dedicated MSI window. */
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/* inbound window 8 makes it hit 0xD00 offset, the MSI window. */
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if (sc->sc_ip_maj >= 2)
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fsl_pcib_inbound(sc, 8, PIWAR_TRGT_CCSR, ccsrbar_pa,
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ccsrbar_size, ccsrbar_pa);
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else
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fsl_pcib_inbound(sc, 1, PIWAR_TRGT_CCSR, ccsrbar_pa,
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ccsrbar_size, ccsrbar_pa);
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return (0);
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}
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static int fsl_pcib_alloc_msi(device_t dev, device_t child,
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int count, int maxcount, int *irqs)
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{
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struct fsl_pcib_softc *sc;
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vmem_addr_t start;
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int err, i;
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sc = device_get_softc(dev);
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if (msi_vmem == NULL)
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return (ENODEV);
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err = vmem_xalloc(msi_vmem, count, powerof2(count), 0, 0,
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VMEM_ADDR_MIN, VMEM_ADDR_MAX, M_BESTFIT | M_WAITOK, &start);
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if (err)
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return (err);
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for (i = 0; i < count; i++)
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irqs[i] = start + i;
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return (0);
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}
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static int fsl_pcib_release_msi(device_t dev, device_t child,
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int count, int *irqs)
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{
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if (msi_vmem == NULL)
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return (ENODEV);
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vmem_xfree(msi_vmem, irqs[0], count);
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return (0);
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}
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static int fsl_pcib_alloc_msix(device_t dev, device_t child, int *irq)
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{
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return (fsl_pcib_alloc_msi(dev, child, 1, 1, irq));
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}
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static int fsl_pcib_release_msix(device_t dev, device_t child, int irq)
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{
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return (fsl_pcib_release_msi(dev, child, 1, &irq));
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}
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static int fsl_pcib_map_msi(device_t dev, device_t child,
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int irq, uint64_t *addr, uint32_t *data)
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{
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struct fsl_msi_map *mp;
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SLIST_FOREACH(mp, &fsl_msis, slist) {
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if (irq >= mp->irq_base && irq < mp->irq_base + FSL_NUM_MSIS)
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break;
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}
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if (mp == NULL)
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return (ENODEV);
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*data = (irq & 255);
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*addr = ccsrbar_pa + mp->target;
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return (0);
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}
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/*
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* Linux device trees put the msi@<x> as children of the SoC, with ranges based
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* on the CCSR. Since rman doesn't permit overlapping or sub-ranges between
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* devices (bus_space_subregion(9) could do it, but let's not touch the PIC
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* driver just to allocate a subregion for a sibling driver). This driver will
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* use ccsr_write() and ccsr_read() instead.
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*/
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#define FSL_NUM_IRQS 8
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#define FSL_NUM_MSI_PER_IRQ 32
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#define FSL_MSI_TARGET 0x140
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struct fsl_msi_softc {
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vm_offset_t sc_base;
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vm_offset_t sc_target;
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int sc_msi_base_irq;
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struct fsl_msi_map sc_map;
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struct fsl_msi_irq {
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/* This struct gets passed as the filter private data. */
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struct fsl_msi_softc *sc_ptr; /* Pointer back to softc. */
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struct resource *res;
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int irq;
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void *cookie;
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int vectors[FSL_NUM_MSI_PER_IRQ];
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vm_offset_t reg;
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} sc_msi_irq[FSL_NUM_IRQS];
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};
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static int
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fsl_msi_intr_filter(void *priv)
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{
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struct fsl_msi_irq *data = priv;
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uint32_t reg;
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int i;
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reg = ccsr_read4(ccsrbar_va + data->reg);
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i = 0;
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while (reg != 0) {
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if (reg & 1)
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powerpc_dispatch_intr(data->vectors[i], NULL);
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reg >>= 1;
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i++;
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}
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return (FILTER_HANDLED);
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}
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static int
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fsl_msi_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "fsl,mpic-msi"))
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return (ENXIO);
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device_set_desc(dev, "Freescale MSI");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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fsl_msi_attach(device_t dev)
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{
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struct fsl_msi_softc *sc;
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struct fsl_msi_irq *irq;
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int i;
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sc = device_get_softc(dev);
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if (msi_vmem == NULL)
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msi_vmem = vmem_create("MPIC MSI", 0, 0, 1, 1, M_BESTFIT | M_WAITOK);
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/* Manually play with resource entries. */
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sc->sc_base = bus_get_resource_start(dev, SYS_RES_MEMORY, 0);
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sc->sc_map.target = bus_get_resource_start(dev, SYS_RES_MEMORY, 1);
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if (sc->sc_map.target == 0)
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sc->sc_map.target = sc->sc_base + FSL_MSI_TARGET;
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for (i = 0; i < FSL_NUM_IRQS; i++) {
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irq = &sc->sc_msi_irq[i];
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irq->irq = i;
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irq->reg = sc->sc_base + 16 * i;
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irq->res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
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&irq->irq, RF_ACTIVE);
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bus_setup_intr(dev, irq->res, INTR_TYPE_MISC | INTR_MPSAFE,
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fsl_msi_intr_filter, NULL, irq, &irq->cookie);
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}
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sc->sc_map.irq_base = powerpc_register_pic(dev, ofw_bus_get_node(dev),
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FSL_NUM_MSIS, 0, 0);
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/* Let vmem and the IRQ subsystem work their magic for allocations. */
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vmem_add(msi_vmem, sc->sc_map.irq_base, FSL_NUM_MSIS, M_WAITOK);
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SLIST_INSERT_HEAD(&fsl_msis, &sc->sc_map, slist);
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return (0);
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}
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static void
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fsl_msi_enable(device_t dev, u_int irq, u_int vector, void **priv)
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{
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struct fsl_msi_softc *sc;
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struct fsl_msi_irq *irqd;
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sc = device_get_softc(dev);
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irqd = &sc->sc_msi_irq[irq / FSL_NUM_MSI_PER_IRQ];
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irqd->vectors[irq % FSL_NUM_MSI_PER_IRQ] = vector;
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}
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static device_method_t fsl_msi_methods[] = {
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DEVMETHOD(device_probe, fsl_msi_probe),
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DEVMETHOD(device_attach, fsl_msi_attach),
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DEVMETHOD(pic_enable, fsl_msi_enable),
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DEVMETHOD_END
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};
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static devclass_t fsl_msi_devclass;
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static driver_t fsl_msi_driver = {
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"fsl_msi",
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fsl_msi_methods,
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sizeof(struct fsl_msi_softc)
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};
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EARLY_DRIVER_MODULE(fsl_msi, simplebus, fsl_msi_driver, fsl_msi_devclass, 0, 0,
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BUS_PASS_INTERRUPT + 1);
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@ -139,8 +139,10 @@ openpic_ofw_attach(device_t dev)
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OF_getencprop(node, "linux,phandle", &xref, sizeof(xref)) == -1)
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xref = node;
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if (ofw_bus_is_compatible(dev, "fsl,mpic"))
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if (ofw_bus_is_compatible(dev, "fsl,mpic")) {
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sc->sc_quirks = OPENPIC_QUIRK_SINGLE_BIND;
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sc->sc_quirks |= OPENPIC_QUIRK_HIDDEN_IRQS;
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}
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return (openpic_common_attach(dev, xref));
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}
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@ -52,6 +52,8 @@
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#include "pic_if.h"
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#define OPENPIC_NIPIS 4
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devclass_t openpic_devclass;
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/*
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@ -182,6 +184,14 @@ openpic_common_attach(device_t dev, uint32_t node)
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"Version %s, supports %d CPUs and %d irqs\n",
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sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
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/*
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* Allow more IRQs than what the PIC says it handles. Some Freescale PICs
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* have MSIs that show up above the PIC's self-described 196 IRQs
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* (P5020 starts MSI IRQs at 224).
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*/
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if (sc->sc_quirks & OPENPIC_QUIRK_HIDDEN_IRQS)
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sc->sc_nirq = OPENPIC_IRQMAX - OPENPIC_NIPIS;
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for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
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openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 15);
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@ -196,7 +206,7 @@ openpic_common_attach(device_t dev, uint32_t node)
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}
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/* Reset and disable all IPIs. */
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for (ipi = 0; ipi < 4; ipi++) {
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for (ipi = 0; ipi < OPENPIC_NIPIS; ipi++) {
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x = sc->sc_nirq + ipi;
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x |= OPENPIC_IMASK;
|
||||
x |= 15 << OPENPIC_PRIORITY_SHIFT;
|
||||
@ -221,7 +231,7 @@ openpic_common_attach(device_t dev, uint32_t node)
|
||||
for (cpu = 0; cpu < sc->sc_ncpu; cpu++)
|
||||
openpic_write(sc, OPENPIC_PCPU_TPR(cpu), 0);
|
||||
|
||||
powerpc_register_pic(dev, node, sc->sc_nirq, 4, FALSE);
|
||||
powerpc_register_pic(dev, node, sc->sc_nirq, OPENPIC_NIPIS, FALSE);
|
||||
|
||||
/* If this is not a cascaded PIC, it must be the root PIC */
|
||||
if (sc->sc_intr == NULL)
|
||||
@ -411,7 +421,7 @@ openpic_suspend(device_t dev)
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
|
||||
for (i = 0; i < 4; i++) {
|
||||
for (i = 0; i < OPENPIC_NIPIS; i++) {
|
||||
sc->sc_saved_ipis[i] = bus_read_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i));
|
||||
}
|
||||
|
||||
@ -442,7 +452,7 @@ openpic_resume(device_t dev)
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
sc->sc_saved_config = bus_read_4(sc->sc_memr, OPENPIC_CONFIG);
|
||||
for (i = 0; i < 4; i++) {
|
||||
for (i = 0; i < OPENPIC_NIPIS; i++) {
|
||||
bus_write_4(sc->sc_memr, OPENPIC_IPI_VECTOR(i), sc->sc_saved_ipis[i]);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user