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gitv3_its: fixes for multiple GIC ITS blocks

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First pass of support for multiple GIC ITS blocks with ACPI.
Changes are to:
 * register the correct subset of interrupts with pic_register
   in case of ACPI.
 * initialize just the cpu interface for the first ITS, when
   domain information is not avialable. This has to be done
   until we split the per-CPU init to do LPI setup just once.
 * remove duplicate check for the GIC ITS domain, the sc_cpus
   are setup from domain, so the check again in per-CPU init
   seems unnecessary.

Reviewed by:	andrew
Differential Revision:	https://reviews.freebsd.org/D17841
This commit is contained in:
Jayachandran C. 2018-11-19 03:52:56 +00:00
parent bd158cddc4
commit be7af100ad
1 changed files with 7 additions and 12 deletions
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19
sys/arm64/arm64/gicv3_its.c
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@ -580,18 +580,11 @@ its_init_cpu(device_t dev, struct gicv3_its_softc *sc)
uint64_t xbaser, tmp;
uint32_t ctlr;
u_int cpuid;
int domain;
if (!CPU_ISSET(PCPU_GET(cpuid), &sc->sc_cpus))
return (0);
if (bus_get_domain(dev, &domain) == 0) {
if (PCPU_GET(domain) != domain)
return (0);
}
gicv3 = device_get_parent(dev);
cpuid = PCPU_GET(cpuid);
if (!CPU_ISSET(cpuid, &sc->sc_cpus))
return (0);
/* Check if the ITS is enabled on this CPU */
if ((gic_r_read_4(gicv3, GICR_TYPER) & GICR_TYPER_PLPIS) == 0) {
@ -729,12 +722,14 @@ gicv3_its_attach(device_t dev)
/* Protects access to the ITS command circular buffer. */
mtx_init(&sc->sc_its_cmd_lock, "ITS cmd lock", NULL, MTX_SPIN);
CPU_ZERO(&sc->sc_cpus);
if (bus_get_domain(dev, &domain) == 0) {
CPU_ZERO(&sc->sc_cpus);
if (domain < MAXMEMDOM)
CPU_COPY(&cpuset_domain[domain], &sc->sc_cpus);
} else {
CPU_COPY(&all_cpus, &sc->sc_cpus);
/* XXX : cannot handle more than one ITS per cpu */
if (device_get_unit(dev) == 0)
CPU_COPY(&all_cpus, &sc->sc_cpus);
}
/* Allocate the command circular buffer */
@ -1737,7 +1732,7 @@ gicv3_its_acpi_attach(device_t dev)
sc->sc_pic = intr_pic_register(dev,
device_get_unit(dev) + ACPI_MSI_XREF);
intr_pic_add_handler(device_get_parent(dev), sc->sc_pic,
gicv3_its_intr, sc, GIC_FIRST_LPI, LPI_NIRQS);
gicv3_its_intr, sc, sc->sc_irq_base, sc->sc_irq_length);
/* Register this device to handle MSI interrupts */
intr_msi_register(dev, device_get_unit(dev) + ACPI_MSI_XREF);