Add an abstraction layer to the 64-bit AIM MMU's page table manipulation
logic to support modifying the page table through a hypervisor. This uses KOBJ inheritance to provide subclasses of the base 64-bit AIM MMU class with additional methods for page table manipulation. Many thanks to Peter Grehan for suggesting this design and implementing the MMU KOBJ inheritance mechanism.
This commit is contained in:
Nathan Whitehorn
parent
aa8dea58c6
commit
bef5da7f98
@ -83,6 +83,8 @@ powerpc/aim/locore.S optional aim no-obj
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powerpc/aim/machdep.c optional aim
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powerpc/aim/mmu_oea.c optional aim powerpc
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powerpc/aim/mmu_oea64.c optional aim
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powerpc/aim/moea64_if.m optional aim
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powerpc/aim/moea64_native.c optional aim
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powerpc/aim/mp_cpudep.c optional aim smp
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powerpc/aim/nexus.c optional aim
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powerpc/aim/ofwmagic.S optional aim
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@ -161,24 +161,6 @@ __FBSDID("$FreeBSD$");
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#define VSID_TO_SR(vsid) ((vsid) & 0xf)
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#define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
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#define PVO_PTEGIDX_MASK 0x007 /* which PTEG slot */
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#define PVO_PTEGIDX_VALID 0x008 /* slot is valid */
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#define PVO_WIRED 0x010 /* PVO entry is wired */
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#define PVO_MANAGED 0x020 /* PVO entry is managed */
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#define PVO_EXECUTABLE 0x040 /* PVO entry is executable */
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#define PVO_BOOTSTRAP 0x080 /* PVO entry allocated during
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bootstrap */
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#define PVO_FAKE 0x100 /* fictitious phys page */
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#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF)
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#define PVO_ISEXECUTABLE(pvo) ((pvo)->pvo_vaddr & PVO_EXECUTABLE)
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#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE)
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#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK)
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#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID)
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#define PVO_PTEGIDX_CLR(pvo) \
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((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK)))
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#define PVO_PTEGIDX_SET(pvo, i) \
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((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID))
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#define MOEA_PVO_CHECK(pvo)
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struct ofw_map {
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File diff suppressed because it is too large
Load Diff
77
sys/powerpc/aim/mmu_oea64.h
Normal file
77
sys/powerpc/aim/mmu_oea64.h
Normal file
@ -0,0 +1,77 @@
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/*-
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* Copyright (C) 2010 Nathan Whitehorn
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _POWERPC_AIM_MMU_OEA64_H
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#define _POWERPC_AIM_MMU_OEA64_H
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#include <machine/mmuvar.h>
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extern mmu_def_t oea64_mmu;
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/*
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* Helper routines
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*/
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/* Allocate physical memory for use in moea64_bootstrap. */
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vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int);
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/*
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* Bootstrap subroutines
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*
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* An MMU_BOOTSTRAP() implementation looks like this:
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* moea64_early_bootstrap();
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* Allocate Page Table
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* moea64_mid_bootstrap();
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* Add mappings for MMU resources
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* moea64_late_bootstrap();
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*/
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void moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart,
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vm_offset_t kernelend);
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void moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart,
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vm_offset_t kernelend);
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void moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart,
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vm_offset_t kernelend);
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/*
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* Statistics
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*/
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extern u_int moea64_pte_valid;
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extern u_int moea64_pte_overflow;
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/*
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* State variables
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*/
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extern struct pvo_head *moea64_pvo_table;
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extern int moea64_large_page_shift;
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extern u_int moea64_pteg_count;
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extern u_int moea64_pteg_mask;
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#endif /* _POWERPC_AIM_MMU_OEA64_H */
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115
sys/powerpc/aim/moea64_if.m
Normal file
115
sys/powerpc/aim/moea64_if.m
Normal file
@ -0,0 +1,115 @@
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#-
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# Copyright (c) 2010 Nathan Whitehorn
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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#
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# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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# SUCH DAMAGE.
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#
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# $FreeBSD$
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#
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#include <sys/param.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/systm.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <machine/mmuvar.h>
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/**
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* MOEA64 kobj methods for 64-bit Book-S page table
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* manipulation routines used, for example, by hypervisors.
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*/
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INTERFACE moea64;
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/**
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* Copy ref/changed bits from PTE referenced by _pt_cookie to _pvo_pt.
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*/
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METHOD void pte_synch {
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mmu_t _mmu;
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uintptr_t _pt_cookie;
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struct lpte *_pvo_pt;
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};
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/**
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* Clear bits ptebit (a mask) from the low word of the PTE referenced by
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* _pt_cookie. Note that _pvo_pt is for reference use only -- the bit should
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* NOT be cleared there.
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*/
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METHOD void pte_clear {
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mmu_t _mmu;
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uintptr_t _pt_cookie;
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struct lpte *_pvo_pt;
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uint64_t _vpn;
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uint64_t _ptebit;
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};
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/**
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* Invalidate the PTE referenced by _pt_cookie, synchronizing its validity
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* and ref/changed bits after completion.
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*/
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METHOD void pte_unset {
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mmu_t _mmu;
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uintptr_t _pt_cookie;
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struct lpte *_pvo_pt;
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uint64_t _vpn;
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};
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/**
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* Update the PTE referenced by _pt_cookie with the values in _pvo_pt,
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* making sure that the values of ref/changed bits are preserved and
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* synchronized back to _pvo_pt.
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*/
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METHOD void pte_change {
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mmu_t _mmu;
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uintptr_t _pt_cookie;
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struct lpte *_pvo_pt;
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uint64_t _vpn;
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};
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/**
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* Insert the PTE _pvo_pt into the PTEG group _ptegidx, returning the index
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* of the PTE in its group at completion, or -1 if no slots were free. Must
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* not replace PTEs marked LPTE_WIRED or LPTE_LOCKED, and must set LPTE_HID
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* and LPTE_VALID appropriately in _pvo_pt.
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*/
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METHOD int pte_insert {
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mmu_t _mmu;
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u_int _ptegidx;
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struct lpte *_pvo_pt;
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};
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/**
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* Return the page table reference cookie corresponding to _pvo, or -1 if
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* the _pvo is not currently in the page table.
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*/
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METHOD uintptr_t pvo_to_pte {
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mmu_t _mmu;
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const struct pvo_entry *_pvo;
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};
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637
sys/powerpc/aim/moea64_native.c
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637
sys/powerpc/aim/moea64_native.c
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@ -0,0 +1,637 @@
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
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*/
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/*-
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* Copyright (C) 2001 Benno Rice.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Native 64-bit page table operations for running without a hypervisor.
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*/
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <sys/kdb.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_page.h>
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#include <vm/vm_map.h>
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#include <vm/vm_object.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_pageout.h>
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#include <vm/vm_pager.h>
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#include <machine/md_var.h>
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#include <machine/mmuvar.h>
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#include "mmu_oea64.h"
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#include "mmu_if.h"
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#include "moea64_if.h"
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#define PTESYNC() __asm __volatile("ptesync");
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#define TLBSYNC() __asm __volatile("tlbsync; ptesync");
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#define SYNC() __asm __volatile("sync");
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#define EIEIO() __asm __volatile("eieio");
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#define VSID_HASH_MASK 0x0000007fffffffffULL
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/*
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* The tlbie instruction must be executed in 64-bit mode
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* so we have to twiddle MSR[SF] around every invocation.
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* Just to add to the fun, exceptions must be off as well
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* so that we can't trap in 64-bit mode. What a pain.
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*/
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struct mtx tlbie_mutex;
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static __inline void
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TLBIE(uint64_t vpn) {
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#ifndef __powerpc64__
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register_t vpn_hi, vpn_lo;
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register_t msr;
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register_t scratch;
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#endif
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vpn <<= ADDR_PIDX_SHFT;
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vpn &= ~(0xffffULL << 48);
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mtx_lock_spin(&tlbie_mutex);
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#ifdef __powerpc64__
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__asm __volatile("\
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ptesync; \
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tlbie %0; \
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eieio; \
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tlbsync; \
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ptesync;"
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:: "r"(vpn) : "memory");
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#else
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vpn_hi = (uint32_t)(vpn >> 32);
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vpn_lo = (uint32_t)vpn;
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__asm __volatile("\
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mfmsr %0; \
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mr %1, %0; \
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insrdi %1,%5,1,0; \
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mtmsrd %1; isync; \
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ptesync; \
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\
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sld %1,%2,%4; \
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or %1,%1,%3; \
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tlbie %1; \
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\
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mtmsrd %0; isync; \
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eieio; \
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tlbsync; \
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ptesync;"
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: "=r"(msr), "=r"(scratch) : "r"(vpn_hi), "r"(vpn_lo), "r"(32), "r"(1)
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: "memory");
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#endif
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mtx_unlock_spin(&tlbie_mutex);
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}
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#define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR); isync()
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#define ENABLE_TRANS(msr) mtmsr(msr); isync()
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/*
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* PTEG data.
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*/
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static struct lpteg *moea64_pteg_table;
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/*
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* PTE calls.
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*/
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static int moea64_pte_insert_native(mmu_t, u_int, struct lpte *);
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||||
static uintptr_t moea64_pvo_to_pte_native(mmu_t, const struct pvo_entry *);
|
||||
static void moea64_pte_synch_native(mmu_t, uintptr_t pt,
|
||||
struct lpte *pvo_pt);
|
||||
static void moea64_pte_clear_native(mmu_t, uintptr_t pt,
|
||||
struct lpte *pvo_pt, uint64_t vpn, uint64_t ptebit);
|
||||
static void moea64_pte_change_native(mmu_t, uintptr_t pt,
|
||||
struct lpte *pvo_pt, uint64_t vpn);
|
||||
static void moea64_pte_unset_native(mmu_t mmu, uintptr_t pt,
|
||||
struct lpte *pvo_pt, uint64_t vpn);
|
||||
|
||||
/*
|
||||
* Utility routines.
|
||||
*/
|
||||
static void moea64_bootstrap_native(mmu_t mmup,
|
||||
vm_offset_t kernelstart, vm_offset_t kernelend);
|
||||
static void moea64_cpu_bootstrap_native(mmu_t, int ap);
|
||||
static void tlbia(void);
|
||||
|
||||
static mmu_method_t moea64_native_methods[] = {
|
||||
/* Internal interfaces */
|
||||
MMUMETHOD(mmu_bootstrap, moea64_bootstrap_native),
|
||||
MMUMETHOD(mmu_cpu_bootstrap, moea64_cpu_bootstrap_native),
|
||||
|
||||
MMUMETHOD(moea64_pte_synch, moea64_pte_synch_native),
|
||||
MMUMETHOD(moea64_pte_clear, moea64_pte_clear_native),
|
||||
MMUMETHOD(moea64_pte_unset, moea64_pte_unset_native),
|
||||
MMUMETHOD(moea64_pte_change, moea64_pte_change_native),
|
||||
MMUMETHOD(moea64_pte_insert, moea64_pte_insert_native),
|
||||
MMUMETHOD(moea64_pvo_to_pte, moea64_pvo_to_pte_native),
|
||||
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
MMU_DEF_INHERIT(oea64_mmu_native, MMU_TYPE_G5, moea64_native_methods,
|
||||
0, oea64_mmu);
|
||||
|
||||
static __inline u_int
|
||||
va_to_pteg(uint64_t vsid, vm_offset_t addr, int large)
|
||||
{
|
||||
uint64_t hash;
|
||||
int shift;
|
||||
|
||||
shift = large ? moea64_large_page_shift : ADDR_PIDX_SHFT;
|
||||
hash = (vsid & VSID_HASH_MASK) ^ (((uint64_t)addr & ADDR_PIDX) >>
|
||||
shift);
|
||||
return (hash & moea64_pteg_mask);
|
||||
}
|
||||
|
||||
static void
|
||||
moea64_pte_synch_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt)
|
||||
{
|
||||
struct lpte *pt = (struct lpte *)pt_cookie;
|
||||
|
||||
pvo_pt->pte_lo |= pt->pte_lo & (LPTE_REF | LPTE_CHG);
|
||||
}
|
||||
|
||||
static void
|
||||
moea64_pte_clear_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt,
|
||||
uint64_t vpn, uint64_t ptebit)
|
||||
{
|
||||
struct lpte *pt = (struct lpte *)pt_cookie;
|
||||
|
||||
/*
|
||||
* As shown in Section 7.6.3.2.3
|
||||
*/
|
||||
pt->pte_lo &= ~ptebit;
|
||||
TLBIE(vpn);
|
||||
}
|
||||
|
||||
static void
|
||||
moea64_pte_set_native(struct lpte *pt, struct lpte *pvo_pt)
|
||||
{
|
||||
|
||||
pvo_pt->pte_hi |= LPTE_VALID;
|
||||
|
||||
/*
|
||||
* Update the PTE as defined in section 7.6.3.1.
|
||||
* Note that the REF/CHG bits are from pvo_pt and thus should have
|
||||
* been saved so this routine can restore them (if desired).
|
||||
*/
|
||||
pt->pte_lo = pvo_pt->pte_lo;
|
||||
EIEIO();
|
||||
pt->pte_hi = pvo_pt->pte_hi;
|
||||
PTESYNC();
|
||||
moea64_pte_valid++;
|
||||
}
|
||||
|
||||
static void
|
||||
moea64_pte_unset_native(mmu_t mmu, uintptr_t pt_cookie, struct lpte *pvo_pt,
|
||||
uint64_t vpn)
|
||||
{
|
||||
struct lpte *pt = (struct lpte *)pt_cookie;
|
||||
|
||||
pvo_pt->pte_hi &= ~LPTE_VALID;
|
||||
|
||||
/*
|
||||
* Force the reg & chg bits back into the PTEs.
|
||||
*/
|
||||
SYNC();
|
||||
|
||||
/*
|
||||
* Invalidate the pte.
|
||||
*/
|
||||
pt->pte_hi &= ~LPTE_VALID;
|
||||
TLBIE(vpn);
|
||||
|
||||
/*
|
||||
* Save the reg & chg bits.
|
||||
*/
|
||||
moea64_pte_synch_native(mmu, pt_cookie, pvo_pt);
|
||||
moea64_pte_valid--;
|
||||
}
|
||||
|
||||
static void
|
||||
moea64_pte_change_native(mmu_t mmu, uintptr_t pt, struct lpte *pvo_pt,
|
||||
uint64_t vpn)
|
||||
{
|
||||
|
||||
/*
|
||||
* Invalidate the PTE
|
||||
*/
|
||||
moea64_pte_unset_native(mmu, pt, pvo_pt, vpn);
|
||||
moea64_pte_set_native((struct lpte *)pt, pvo_pt);
|
||||
}
|
||||
|
||||
static void
|
||||
moea64_cpu_bootstrap_native(mmu_t mmup, int ap)
|
||||
{
|
||||
int i = 0;
|
||||
#ifdef __powerpc64__
|
||||
struct slb *slb = PCPU_GET(slb);
|
||||
register_t seg0;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initialize segment registers and MMU
|
||||
*/
|
||||
|
||||
mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); isync();
|
||||
|
||||
/*
|
||||
* Install kernel SLB entries
|
||||
*/
|
||||
|
||||
#ifdef __powerpc64__
|
||||
__asm __volatile ("slbia");
|
||||
__asm __volatile ("slbmfee %0,%1; slbie %0;" : "=r"(seg0) :
|
||||
"r"(0));
|
||||
|
||||
for (i = 0; i < 64; i++) {
|
||||
if (!(slb[i].slbe & SLBE_VALID))
|
||||
continue;
|
||||
|
||||
__asm __volatile ("slbmte %0, %1" ::
|
||||
"r"(slb[i].slbv), "r"(slb[i].slbe));
|
||||
}
|
||||
#else
|
||||
for (i = 0; i < 16; i++)
|
||||
mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Install page table
|
||||
*/
|
||||
|
||||
__asm __volatile ("ptesync; mtsdr1 %0; isync"
|
||||
:: "r"((uintptr_t)moea64_pteg_table
|
||||
| (uintptr_t)(flsl(moea64_pteg_mask >> 11))));
|
||||
tlbia();
|
||||
}
|
||||
|
||||
static void
|
||||
moea64_bootstrap_native(mmu_t mmup, vm_offset_t kernelstart,
|
||||
vm_offset_t kernelend)
|
||||
{
|
||||
vm_size_t size;
|
||||
vm_offset_t off;
|
||||
vm_paddr_t pa;
|
||||
register_t msr;
|
||||
|
||||
moea64_early_bootstrap(mmup, kernelstart, kernelend);
|
||||
|
||||
/*
|
||||
* Allocate PTEG table.
|
||||
*/
|
||||
|
||||
size = moea64_pteg_count * sizeof(struct lpteg);
|
||||
CTR2(KTR_PMAP, "moea64_bootstrap: %d PTEGs, %d bytes",
|
||||
moea64_pteg_count, size);
|
||||
|
||||
/*
|
||||
* We now need to allocate memory. This memory, to be allocated,
|
||||
* has to reside in a page table. The page table we are about to
|
||||
* allocate. We don't have BAT. So drop to data real mode for a minute
|
||||
* as a measure of last resort. We do this a couple times.
|
||||
*/
|
||||
|
||||
moea64_pteg_table = (struct lpteg *)moea64_bootstrap_alloc(size, size);
|
||||
DISABLE_TRANS(msr);
|
||||
bzero((void *)moea64_pteg_table, moea64_pteg_count * sizeof(struct lpteg));
|
||||
ENABLE_TRANS(msr);
|
||||
|
||||
CTR1(KTR_PMAP, "moea64_bootstrap: PTEG table at %p", moea64_pteg_table);
|
||||
|
||||
/*
|
||||
* Initialize the TLBIE lock. TLBIE can only be executed by one CPU.
|
||||
*/
|
||||
mtx_init(&tlbie_mutex, "tlbie mutex", NULL, MTX_SPIN);
|
||||
|
||||
moea64_mid_bootstrap(mmup, kernelstart, kernelend);
|
||||
|
||||
/*
|
||||
* Add a mapping for the page table itself if there is no direct map.
|
||||
*/
|
||||
if (!hw_direct_map) {
|
||||
size = moea64_pteg_count * sizeof(struct lpteg);
|
||||
off = (vm_offset_t)(moea64_pteg_table);
|
||||
DISABLE_TRANS(msr);
|
||||
for (pa = off; pa < off + size; pa += PAGE_SIZE)
|
||||
pmap_kenter(pa, pa);
|
||||
ENABLE_TRANS(msr);
|
||||
}
|
||||
|
||||
/* Bring up virtual memory */
|
||||
moea64_late_bootstrap(mmup, kernelstart, kernelend);
|
||||
}
|
||||
|
||||
static void
|
||||
tlbia(void)
|
||||
{
|
||||
vm_offset_t i;
|
||||
#ifndef __powerpc64__
|
||||
register_t msr, scratch;
|
||||
#endif
|
||||
|
||||
TLBSYNC();
|
||||
|
||||
for (i = 0; i < 0xFF000; i += 0x00001000) {
|
||||
#ifdef __powerpc64__
|
||||
__asm __volatile("tlbiel %0" :: "r"(i));
|
||||
#else
|
||||
__asm __volatile("\
|
||||
mfmsr %0; \
|
||||
mr %1, %0; \
|
||||
insrdi %1,%3,1,0; \
|
||||
mtmsrd %1; \
|
||||
isync; \
|
||||
\
|
||||
tlbiel %2; \
|
||||
\
|
||||
mtmsrd %0; \
|
||||
isync;"
|
||||
: "=r"(msr), "=r"(scratch) : "r"(i), "r"(1));
|
||||
#endif
|
||||
}
|
||||
|
||||
EIEIO();
|
||||
TLBSYNC();
|
||||
}
|
||||
|
||||
static uintptr_t
|
||||
moea64_pvo_to_pte_native(mmu_t mmu, const struct pvo_entry *pvo)
|
||||
{
|
||||
struct lpte *pt;
|
||||
int pteidx, ptegidx;
|
||||
uint64_t vsid;
|
||||
|
||||
/* If the PTEG index is not set, then there is no page table entry */
|
||||
if (!PVO_PTEGIDX_ISSET(pvo))
|
||||
return (-1);
|
||||
|
||||
/*
|
||||
* Calculate the ptegidx
|
||||
*/
|
||||
vsid = PVO_VSID(pvo);
|
||||
ptegidx = va_to_pteg(vsid, PVO_VADDR(pvo),
|
||||
pvo->pvo_vaddr & PVO_LARGE);
|
||||
|
||||
/*
|
||||
* We can find the actual pte entry without searching by grabbing
|
||||
* the PTEG index from 3 unused bits in pvo_vaddr and by
|
||||
* noticing the HID bit.
|
||||
*/
|
||||
if (pvo->pvo_pte.lpte.pte_hi & LPTE_HID)
|
||||
ptegidx ^= moea64_pteg_mask;
|
||||
|
||||
pteidx = (ptegidx << 3) | PVO_PTEGIDX_GET(pvo);
|
||||
|
||||
if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) &&
|
||||
!PVO_PTEGIDX_ISSET(pvo)) {
|
||||
panic("moea64_pvo_to_pte: pvo %p has valid pte in pvo but no "
|
||||
"valid pte index", pvo);
|
||||
}
|
||||
|
||||
if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0 &&
|
||||
PVO_PTEGIDX_ISSET(pvo)) {
|
||||
panic("moea64_pvo_to_pte: pvo %p has valid pte index in pvo "
|
||||
"pvo but no valid pte", pvo);
|
||||
}
|
||||
|
||||
pt = &moea64_pteg_table[pteidx >> 3].pt[pteidx & 7];
|
||||
if ((pt->pte_hi ^ (pvo->pvo_pte.lpte.pte_hi & ~LPTE_VALID)) ==
|
||||
LPTE_VALID) {
|
||||
if ((pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) == 0) {
|
||||
panic("moea64_pvo_to_pte: pvo %p has valid pte in "
|
||||
"moea64_pteg_table %p but invalid in pvo", pvo, pt);
|
||||
}
|
||||
|
||||
if (((pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo) &
|
||||
~(LPTE_M|LPTE_CHG|LPTE_REF)) != 0) {
|
||||
panic("moea64_pvo_to_pte: pvo %p pte does not match "
|
||||
"pte %p in moea64_pteg_table difference is %#x",
|
||||
pvo, pt,
|
||||
(uint32_t)(pt->pte_lo ^ pvo->pvo_pte.lpte.pte_lo));
|
||||
}
|
||||
|
||||
return ((uintptr_t)pt);
|
||||
}
|
||||
|
||||
if (pvo->pvo_pte.lpte.pte_hi & LPTE_VALID) {
|
||||
panic("moea64_pvo_to_pte: pvo %p has invalid pte %p in "
|
||||
"moea64_pteg_table but valid in pvo", pvo, pt);
|
||||
}
|
||||
|
||||
return (-1);
|
||||
}
|
||||
|
||||
static __inline int
|
||||
moea64_pte_spillable_ident(u_int ptegidx)
|
||||
{
|
||||
struct lpte *pt;
|
||||
int i, j, k;
|
||||
|
||||
/* Start at a random slot */
|
||||
i = mftb() % 8;
|
||||
k = -1;
|
||||
for (j = 0; j < 8; j++) {
|
||||
pt = &moea64_pteg_table[ptegidx].pt[(i + j) % 8];
|
||||
if (pt->pte_hi & (LPTE_LOCKED | LPTE_WIRED))
|
||||
continue;
|
||||
|
||||
/* This is a candidate, so remember it */
|
||||
k = (i + j) % 8;
|
||||
|
||||
/* Try to get a page that has not been used lately */
|
||||
if (!(pt->pte_lo & LPTE_REF))
|
||||
return (k);
|
||||
}
|
||||
|
||||
return (k);
|
||||
}
|
||||
|
||||
static int
|
||||
moea64_pte_insert_native(mmu_t mmu, u_int ptegidx, struct lpte *pvo_pt)
|
||||
{
|
||||
struct lpte *pt;
|
||||
struct pvo_entry *pvo;
|
||||
u_int pteg_bktidx;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* First try primary hash.
|
||||
*/
|
||||
pteg_bktidx = ptegidx;
|
||||
for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) {
|
||||
if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) {
|
||||
pvo_pt->pte_hi &= ~LPTE_HID;
|
||||
moea64_pte_set_native(pt, pvo_pt);
|
||||
return (i);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Now try secondary hash.
|
||||
*/
|
||||
pteg_bktidx ^= moea64_pteg_mask;
|
||||
for (pt = moea64_pteg_table[pteg_bktidx].pt, i = 0; i < 8; i++, pt++) {
|
||||
if ((pt->pte_hi & (LPTE_VALID | LPTE_LOCKED)) == 0) {
|
||||
pvo_pt->pte_hi |= LPTE_HID;
|
||||
moea64_pte_set_native(pt, pvo_pt);
|
||||
return (i);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Out of luck. Find a PTE to sacrifice.
|
||||
*/
|
||||
pteg_bktidx = ptegidx;
|
||||
i = moea64_pte_spillable_ident(pteg_bktidx);
|
||||
if (i < 0) {
|
||||
pteg_bktidx ^= moea64_pteg_mask;
|
||||
i = moea64_pte_spillable_ident(pteg_bktidx);
|
||||
}
|
||||
|
||||
if (i < 0) {
|
||||
/* No freeable slots in either PTEG? We're hosed. */
|
||||
panic("moea64_pte_insert: overflow");
|
||||
return (-1);
|
||||
}
|
||||
|
||||
if (pteg_bktidx == ptegidx)
|
||||
pvo_pt->pte_hi &= ~LPTE_HID;
|
||||
else
|
||||
pvo_pt->pte_hi |= LPTE_HID;
|
||||
|
||||
/*
|
||||
* Synchronize the sacrifice PTE with its PVO, then mark both
|
||||
* invalid. The PVO will be reused when/if the VM system comes
|
||||
* here after a fault.
|
||||
*/
|
||||
pt = &moea64_pteg_table[pteg_bktidx].pt[i];
|
||||
|
||||
if (pt->pte_hi & LPTE_HID)
|
||||
pteg_bktidx ^= moea64_pteg_mask; /* PTEs indexed by primary */
|
||||
|
||||
LIST_FOREACH(pvo, &moea64_pvo_table[pteg_bktidx], pvo_olink) {
|
||||
if (pvo->pvo_pte.lpte.pte_hi == pt->pte_hi) {
|
||||
KASSERT(pvo->pvo_pte.lpte.pte_hi & LPTE_VALID,
|
||||
("Invalid PVO for valid PTE!"));
|
||||
moea64_pte_unset_native(mmu, (uintptr_t)pt,
|
||||
&pvo->pvo_pte.lpte, pvo->pvo_vpn);
|
||||
PVO_PTEGIDX_CLR(pvo);
|
||||
moea64_pte_overflow++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
KASSERT(pvo->pvo_pte.lpte.pte_hi == pt->pte_hi,
|
||||
("Unable to find PVO for spilled PTE"));
|
||||
|
||||
/*
|
||||
* Set the new PTE.
|
||||
*/
|
||||
moea64_pte_set_native(pt, pvo_pt);
|
||||
|
||||
return (i);
|
||||
}
|
||||
|
||||
@ -121,6 +121,25 @@ struct pvo_entry {
|
||||
};
|
||||
LIST_HEAD(pvo_head, pvo_entry);
|
||||
|
||||
#define PVO_PTEGIDX_MASK 0x007UL /* which PTEG slot */
|
||||
#define PVO_PTEGIDX_VALID 0x008UL /* slot is valid */
|
||||
#define PVO_WIRED 0x010UL /* PVO entry is wired */
|
||||
#define PVO_MANAGED 0x020UL /* PVO entry is managed */
|
||||
#define PVO_EXECUTABLE 0x040UL /* PVO entry is executable */
|
||||
#define PVO_BOOTSTRAP 0x080UL /* PVO entry allocated during
|
||||
bootstrap */
|
||||
#define PVO_FAKE 0x100UL /* fictitious phys page */
|
||||
#define PVO_LARGE 0x200UL /* large page */
|
||||
#define PVO_VADDR(pvo) ((pvo)->pvo_vaddr & ~ADDR_POFF)
|
||||
#define PVO_ISFAKE(pvo) ((pvo)->pvo_vaddr & PVO_FAKE)
|
||||
#define PVO_PTEGIDX_GET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_MASK)
|
||||
#define PVO_PTEGIDX_ISSET(pvo) ((pvo)->pvo_vaddr & PVO_PTEGIDX_VALID)
|
||||
#define PVO_PTEGIDX_CLR(pvo) \
|
||||
((void)((pvo)->pvo_vaddr &= ~(PVO_PTEGIDX_VALID|PVO_PTEGIDX_MASK)))
|
||||
#define PVO_PTEGIDX_SET(pvo, i) \
|
||||
((void)((pvo)->pvo_vaddr |= (i)|PVO_PTEGIDX_VALID))
|
||||
#define PVO_VSID(pvo) ((pvo)->pvo_vpn >> 16)
|
||||
|
||||
struct md_page {
|
||||
u_int64_t mdpg_attrs;
|
||||
vm_memattr_t mdpg_cache_attrs;
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user