Flesh out imx_uart_init() so that we're not relying on u-boot to init
the hardware (meaning uarts other than the console will work).
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044b3e1a2f
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@ -43,10 +43,11 @@ __FBSDID("$FreeBSD$");
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <dev/uart/uart_dev_imx.h>
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#include "uart_if.h"
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#include <arm/freescale/imx/imx_ccmvar.h>
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/*
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* Low-level UART interface.
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*/
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@ -66,6 +67,22 @@ static struct uart_ops uart_imx_uart_ops = {
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.getc = imx_uart_getc,
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};
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#if 0 /* Handy when debugging. */
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static void
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dumpregs(struct uart_bas *bas, const char * msg)
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{
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if (!bootverbose)
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return;
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printf("%s bsh 0x%08lx UCR1 0x%08x UCR2 0x%08x "
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"UCR3 0x%08x UCR4 0x%08x USR1 0x%08x USR2 0x%08x\n",
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msg, bas->bsh,
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GETREG(bas, REG(UCR1)), GETREG(bas, REG(UCR2)),
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GETREG(bas, REG(UCR3)), GETREG(bas, REG(UCR4)),
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GETREG(bas, REG(USR1)), GETREG(bas, REG(USR2)));
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}
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#endif
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static int
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imx_uart_probe(struct uart_bas *bas)
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{
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@ -77,7 +94,59 @@ static void
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imx_uart_init(struct uart_bas *bas, int baudrate, int databits,
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int stopbits, int parity)
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{
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uint32_t baseclk, reg;
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/* Enable the device and the RX/TX channels. */
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SET(bas, REG(UCR1), FLD(UCR1, UARTEN));
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SET(bas, REG(UCR2), FLD(UCR2, RXEN) | FLD(UCR2, TXEN));
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if (databits == 7)
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DIS(bas, UCR2, WS);
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else
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ENA(bas, UCR2, WS);
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if (stopbits == 2)
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ENA(bas, UCR2, STPB);
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else
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DIS(bas, UCR2, STPB);
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switch (parity) {
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case UART_PARITY_ODD:
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DIS(bas, UCR2, PROE);
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ENA(bas, UCR2, PREN);
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break;
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case UART_PARITY_EVEN:
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ENA(bas, UCR2, PROE);
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ENA(bas, UCR2, PREN);
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break;
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case UART_PARITY_MARK:
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case UART_PARITY_SPACE:
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/* FALLTHROUGH: Hardware doesn't support mark/space. */
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case UART_PARITY_NONE:
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default:
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DIS(bas, UCR2, PREN);
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break;
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}
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/*
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* The hardware has an extremely flexible baud clock: it allows setting
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* both the numerator and denominator of the divider, as well as a
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* separate pre-divider. We simplify that problem by assuming a
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* pre-divider and numerator of one because our base clock is so fast we
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* can reach virtually any reasonable speed with a simple divisor. The
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* numerator value actually includes the 16x over-sampling; the register
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* value is the numerator-1, so we have a hard-coded 15. Note that a
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* quirk of the hardware requires that both UBIR and UBMR be set back to
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* back in order for the change to take effect.
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*/
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if (baudrate > 0) {
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baseclk = imx_ccm_uart_hz();
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reg = GETREG(bas, REG(UFCR));
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reg = (reg & ~IMXUART_UFCR_RFDIV_MASK) | IMXUART_UFCR_RFDIV_DIV1;
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SETREG(bas, REG(UFCR), reg);
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SETREG(bas, REG(UBIR), 15);
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SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1);
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}
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}
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static void
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@ -218,6 +287,8 @@ imx_uart_bus_attach(struct uart_softc *sc)
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DIS(bas, UCR3, RI);
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DIS(bas, UCR3, DCD);
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DIS(bas, UCR3, DTRDEN);
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ENA(bas, UCR2, IRTS);
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ENA(bas, UCR3, RXDMUXSEL);
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/* ACK all interrupts */
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SETREG(bas, REG(USR1), 0xffff);
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