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Decode new values for CPUID leaf 2 cache and TLB descriptors, from the

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Intel SDM revision 56.

Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
This commit is contained in:
Konstantin Belousov 2015-10-23 11:43:56 +00:00
parent cd0a26c53f
commit c0db387d25
1 changed files with 12 additions and 0 deletions
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12
sys/x86/x86/identcpu.c
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@ -1883,6 +1883,18 @@ print_INTEL_TLB(u_int data)
case 0x68:
printf("1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size\n");
break;
case 0x6a:
printf("uTLB: 4KByte pages, 8-way set associative, 64 entries\n");
break;
case 0x6b:
printf("DTLB: 4KByte pages, 8-way set associative, 256 entries\n");
break;
case 0x6c:
printf("DTLB: 2M/4M pages, 8-way set associative, 126 entries\n");
break;
case 0x6d:
printf("DTLB: 1 GByte pages, fully associative, 16 entries\n");
break;
case 0x70:
printf("Trace cache: 12K-uops, 8-way set associative\n");
break;