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Add data barriers to the arm64 bus_dmamap_sync function. We need these

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to ensure ordering between the CPU and device. As the CPU and DMA target
may be in different shareability domains they need to be full system
barriers.

Obtained from:	ABT Systems Ltd
Sponsored by:	The FreeBSD Foundation
This commit is contained in:
andrew 2016-05-11 14:59:54 +00:00
parent 97a44a849e
commit c1c72529c8
1 changed files with 14 additions and 1 deletions
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15
sys/arm64/arm64/busdma_bounce.c
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@ -770,8 +770,11 @@ bounce_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map,
struct bounce_page *bpage;
vm_offset_t datavaddr, tempvaddr;
if (map == NULL || (bpage = STAILQ_FIRST(&map->bpages)) == NULL)
if (map == NULL || (bpage = STAILQ_FIRST(&map->bpages)) == NULL) {
/* Wait for any memory access to complete */
dsb(sy);
return;
}
/*
* XXX ARM64TODO:
@ -801,9 +804,19 @@ bounce_bus_dmamap_sync(bus_dma_tag_t dmat, bus_dmamap_t map,
bpage = STAILQ_NEXT(bpage, links);
}
dmat->bounce_zone->total_bounced++;
/*
* Wait for the bcopy to complete before any DMA operations.
*/
dsb(sy);
}
if ((op & BUS_DMASYNC_POSTREAD) != 0) {
/*
* Wait for any DMA operations to complete before the bcopy.
*/
dsb(sy);
while (bpage != NULL) {
tempvaddr = 0;
datavaddr = bpage->datavaddr;