MFC 305695,305696,305699,305702,305703,305713,305715,305827,305852,305906,
305908,306062,306063,306137,306138,306206,306216,306273,306295,306301, 306465,309302: Add support for adapters using the Terminator T6 ASIC. 305695: cxgbe(4): Set up fl_starve_threshold2 accurately for T6. 305696: cxgbe(4): Use correct macro for header length with T6 ASICs. This affects the transmit of the VF driver only. 305699: cxgbe(4): Update the pad_boundary calculation for T6, which has a different range of boundaries. 305702: cxgbe(4): Use smaller min/max bursts for fl descriptors with a T6. 305703: cxgbe(4): Deal with the slightly different SGE_STAT_CFG in T6. 305713: cxgbe(4): Add support for additional port types and link speeds. 305715: cxgbe(4): Catch up with the rename of tlscaps -> cryptocaps. TLS is one of the capabilities of the crypto engine in T6. 305827: cxgbe(4): Use the interface's viid to calculate the PF/VF/VFValid fields to use in tx work requests. 305852: cxgbe(4): Attach to cards with the Terminator 6 ASIC. T6 cards will come up as 't6nex' nexus devices with 'cc' ports hanging off them. The T6 firmware and configuration files will be added as soon as they are released. For now the driver will try to work with whatever firmware and configuration is on the card's flash. 305906: cxgbe/t4_tom: The SMAC entry for a VI is at a different location in the T6. 305908: cxgbe/t4_tom: Update the active/passive open code to support T6. Data path works as-is. 306062: cxgbe(4): Show wcwr_stats for T6 cards. 306063: cxgbe(4): Setup congestion response for T6 rx queues. 306137: cxgbetool: Add T6 support to the SGE context decoder. 306138: Fix typo. 306206: cxgbe(4): Catch up with the different layout of WHOAMI in T6. Note that the code moved below t4_prep_adapter() as part of this change because now it needs a working chip_id(). 306216: cxgbe(4): Fix the output of the "tids" sysctl on T6. 306273: cxgbe(4): Fix netmap with T6, which doesn't encapsulate SGE_EGR_UPDATE message inside a FW_MSG. The base NIC already deals with updates in either form. 306295: cxgbe(4): Support SIOGIFXMEDIA so that ifconfig displays correct media for 25Gbps and 100Gbps ports. This should have been part of r305713, which is when the driver first started reporting extended media types. 306301: cxgbe(4): Use the port's top speed to figure out whether it is "high speed" or not (for the purpose of calculating the number of queues etc.) This does the right thing for 25Gbps and 100Gbps ports. 306465: cxgbe(4): Claim the T6 -DBG card. 309302: cxgbe(4): Include firmware for T6 cards in the driver. Update all firmwares to 1.16.12.0. Sponsored by: Chelsio Communications
This commit is contained in:
John Baldwin
parent
630f89c6db
commit
c1d7a41250
@ -1307,7 +1307,7 @@ t4fw.fwo optional cxgbe \
|
||||
no-implicit-rule \
|
||||
clean "t4fw.fwo"
|
||||
t4fw.fw optional cxgbe \
|
||||
dependency "$S/dev/cxgbe/firmware/t4fw-1.15.37.0.bin.uu" \
|
||||
dependency "$S/dev/cxgbe/firmware/t4fw-1.16.12.0.bin.uu" \
|
||||
compile-with "${NORMAL_FW}" \
|
||||
no-obj no-implicit-rule \
|
||||
clean "t4fw.fw"
|
||||
@ -1331,10 +1331,34 @@ t5fw.fwo optional cxgbe \
|
||||
no-implicit-rule \
|
||||
clean "t5fw.fwo"
|
||||
t5fw.fw optional cxgbe \
|
||||
dependency "$S/dev/cxgbe/firmware/t5fw-1.15.37.0.bin.uu" \
|
||||
dependency "$S/dev/cxgbe/firmware/t5fw-1.16.12.0.bin.uu" \
|
||||
compile-with "${NORMAL_FW}" \
|
||||
no-obj no-implicit-rule \
|
||||
clean "t5fw.fw"
|
||||
t6fw_cfg.c optional cxgbe \
|
||||
compile-with "${AWK} -f $S/tools/fw_stub.awk t6fw_cfg.fw:t6fw_cfg t6fw.fw:t6fw -mt6fw_cfg -c${.TARGET}" \
|
||||
no-implicit-rule before-depend local \
|
||||
clean "t6fw_cfg.c"
|
||||
t6fw_cfg.fwo optional cxgbe \
|
||||
dependency "t6fw_cfg.fw" \
|
||||
compile-with "${NORMAL_FWO}" \
|
||||
no-implicit-rule \
|
||||
clean "t6fw_cfg.fwo"
|
||||
t6fw_cfg.fw optional cxgbe \
|
||||
dependency "$S/dev/cxgbe/firmware/t6fw_cfg.txt" \
|
||||
compile-with "${CP} ${.ALLSRC} ${.TARGET}" \
|
||||
no-obj no-implicit-rule \
|
||||
clean "t6fw_cfg.fw"
|
||||
t6fw.fwo optional cxgbe \
|
||||
dependency "t6fw.fw" \
|
||||
compile-with "${NORMAL_FWO}" \
|
||||
no-implicit-rule \
|
||||
clean "t6fw.fwo"
|
||||
t6fw.fw optional cxgbe \
|
||||
dependency "$S/dev/cxgbe/firmware/t6fw-1.16.12.0.bin.uu" \
|
||||
compile-with "${NORMAL_FW}" \
|
||||
no-obj no-implicit-rule \
|
||||
clean "t6fw.fw"
|
||||
dev/cy/cy.c optional cy
|
||||
dev/cy/cy_isa.c optional cy isa
|
||||
dev/cy/cy_pci.c optional cy pci
|
||||
|
||||
@ -231,6 +231,7 @@ struct vi_info {
|
||||
int if_flags;
|
||||
|
||||
uint16_t *rss, *nm_rss;
|
||||
int smt_idx; /* for convenience */
|
||||
uint16_t viid;
|
||||
int16_t xact_addr_filt;/* index of exact MAC address filter */
|
||||
uint16_t rss_size; /* size of VI's RSS table slice */
|
||||
@ -752,10 +753,20 @@ struct sge {
|
||||
struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
|
||||
};
|
||||
|
||||
struct devnames {
|
||||
const char *nexus_name;
|
||||
const char *ifnet_name;
|
||||
const char *vi_ifnet_name;
|
||||
const char *pf03_drv_name;
|
||||
const char *vf_nexus_name;
|
||||
const char *vf_ifnet_name;
|
||||
};
|
||||
|
||||
struct adapter {
|
||||
SLIST_ENTRY(adapter) link;
|
||||
device_t dev;
|
||||
struct cdev *cdev;
|
||||
const struct devnames *names;
|
||||
|
||||
/* PCIe register resources */
|
||||
int regs_rid;
|
||||
@ -835,7 +846,7 @@ struct adapter {
|
||||
uint16_t niccaps;
|
||||
uint16_t toecaps;
|
||||
uint16_t rdmacaps;
|
||||
uint16_t tlscaps;
|
||||
uint16_t cryptocaps;
|
||||
uint16_t iscsicaps;
|
||||
uint16_t fcoecaps;
|
||||
|
||||
@ -1039,6 +1050,13 @@ is_10G_port(const struct port_info *pi)
|
||||
return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
|
||||
}
|
||||
|
||||
static inline bool
|
||||
is_25G_port(const struct port_info *pi)
|
||||
{
|
||||
|
||||
return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0);
|
||||
}
|
||||
|
||||
static inline bool
|
||||
is_40G_port(const struct port_info *pi)
|
||||
{
|
||||
@ -1046,6 +1064,13 @@ is_40G_port(const struct port_info *pi)
|
||||
return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
|
||||
}
|
||||
|
||||
static inline bool
|
||||
is_100G_port(const struct port_info *pi)
|
||||
{
|
||||
|
||||
return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0);
|
||||
}
|
||||
|
||||
static inline int
|
||||
port_top_speed(const struct port_info *pi)
|
||||
{
|
||||
@ -1054,6 +1079,8 @@ port_top_speed(const struct port_info *pi)
|
||||
return (100);
|
||||
if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
|
||||
return (40);
|
||||
if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
|
||||
return (25);
|
||||
if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
|
||||
return (10);
|
||||
if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
|
||||
@ -1101,6 +1128,7 @@ int t4_os_pci_restore_state(struct adapter *);
|
||||
void t4_os_portmod_changed(const struct adapter *, int);
|
||||
void t4_os_link_changed(struct adapter *, int, int, int);
|
||||
void t4_iterate(void (*)(struct adapter *, void *), void *);
|
||||
void t4_init_devnames(struct adapter *);
|
||||
void t4_add_adapter(struct adapter *);
|
||||
int t4_detach_common(device_t);
|
||||
int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
|
||||
|
||||
@ -578,7 +578,8 @@ int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
|
||||
int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
|
||||
unsigned int flags);
|
||||
int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
|
||||
unsigned int flags, unsigned int defq);
|
||||
unsigned int flags, unsigned int defq, unsigned int skeyidx,
|
||||
unsigned int skey);
|
||||
int t4_read_rss(struct adapter *adapter, u16 *entries);
|
||||
void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
|
||||
unsigned int start_index, unsigned int rw);
|
||||
|
||||
@ -3669,8 +3669,9 @@ void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
|
||||
}
|
||||
|
||||
#define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
|
||||
FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
|
||||
FW_PORT_CAP_SPEED_100G | FW_PORT_CAP_ANEG)
|
||||
FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \
|
||||
FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \
|
||||
FW_PORT_CAP_ANEG)
|
||||
|
||||
/**
|
||||
* t4_link_l1cfg - apply link configuration to MAC/PHY
|
||||
@ -4738,7 +4739,7 @@ int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
|
||||
c.u.manual.mode_pkd =
|
||||
cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
|
||||
} else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
|
||||
c.u.basicvirtual.mode_pkd =
|
||||
c.u.basicvirtual.mode_keymode =
|
||||
cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
|
||||
c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
|
||||
} else
|
||||
@ -4753,11 +4754,14 @@ int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
|
||||
* @viid: the VI id
|
||||
* @flags: RSS flags
|
||||
* @defq: id of the default RSS queue for the VI.
|
||||
* @skeyidx: RSS secret key table index for non-global mode
|
||||
* @skey: RSS vf_scramble key for VI.
|
||||
*
|
||||
* Configures VI-specific RSS properties.
|
||||
*/
|
||||
int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
|
||||
unsigned int flags, unsigned int defq)
|
||||
unsigned int flags, unsigned int defq, unsigned int skeyidx,
|
||||
unsigned int skey)
|
||||
{
|
||||
struct fw_rss_vi_config_cmd c;
|
||||
|
||||
@ -4768,6 +4772,10 @@ int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
|
||||
c.retval_len16 = cpu_to_be32(FW_LEN16(c));
|
||||
c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
|
||||
V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
|
||||
c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32(
|
||||
V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx));
|
||||
c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey);
|
||||
|
||||
return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
|
||||
}
|
||||
|
||||
@ -4886,11 +4894,11 @@ void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
|
||||
if (idx >= 0 && idx < rss_key_addr_cnt) {
|
||||
if (rss_key_addr_cnt > 16)
|
||||
t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
|
||||
V_KEYWRADDRX(idx >> 4) |
|
||||
vrt | V_KEYWRADDRX(idx >> 4) |
|
||||
V_T6_VFWRADDR(idx) | F_KEYWREN);
|
||||
else
|
||||
t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
|
||||
V_KEYWRADDR(idx) | F_KEYWREN);
|
||||
vrt| V_KEYWRADDR(idx) | F_KEYWREN);
|
||||
}
|
||||
}
|
||||
|
||||
@ -5775,6 +5783,13 @@ const char *t4_get_port_type_description(enum fw_port_type port_type)
|
||||
"QSA",
|
||||
"QSFP",
|
||||
"BP40_BA",
|
||||
"KR4_100G",
|
||||
"CR4_QSFP",
|
||||
"CR_QSFP",
|
||||
"CR_SFP28",
|
||||
"SFP28",
|
||||
"KR_SFP28",
|
||||
"CR2_QSFP",
|
||||
};
|
||||
|
||||
if (port_type < ARRAY_SIZE(port_type_description))
|
||||
@ -7462,8 +7477,12 @@ int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
|
||||
speed = 1000;
|
||||
else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
|
||||
speed = 10000;
|
||||
else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
|
||||
speed = 25000;
|
||||
else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
|
||||
speed = 40000;
|
||||
else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
|
||||
speed = 100000;
|
||||
|
||||
for_each_port(adap, i) {
|
||||
pi = adap2pinfo(adap, i);
|
||||
@ -7866,8 +7885,10 @@ int t4_init_sge_params(struct adapter *adapter)
|
||||
sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
|
||||
if (is_t4(adapter))
|
||||
sp->fl_starve_threshold2 = sp->fl_starve_threshold;
|
||||
else
|
||||
else if (is_t5(adapter))
|
||||
sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
|
||||
else
|
||||
sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1;
|
||||
|
||||
/* egress queues: log2 of # of doorbells per BAR2 page */
|
||||
r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
|
||||
@ -7890,7 +7911,13 @@ int t4_init_sge_params(struct adapter *adapter)
|
||||
sp->sge_control = r;
|
||||
sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
|
||||
sp->fl_pktshift = G_PKTSHIFT(r);
|
||||
sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 5);
|
||||
if (chip_id(adapter) <= CHELSIO_T5) {
|
||||
sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
|
||||
X_INGPADBOUNDARY_SHIFT);
|
||||
} else {
|
||||
sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
|
||||
X_T6_INGPADBOUNDARY_SHIFT);
|
||||
}
|
||||
if (is_t4(adapter))
|
||||
sp->pack_boundary = sp->pad_boundary;
|
||||
else {
|
||||
@ -8082,6 +8109,10 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
|
||||
return ret;
|
||||
|
||||
p->vi[0].viid = ret;
|
||||
if (chip_id(adap) <= CHELSIO_T5)
|
||||
p->vi[0].smt_idx = (ret & 0x7f) << 1;
|
||||
else
|
||||
p->vi[0].smt_idx = (ret & 0x7f);
|
||||
p->tx_chan = j;
|
||||
p->rx_chan_map = t4_get_mps_bg_map(adap, j);
|
||||
p->lport = j;
|
||||
|
||||
@ -29,6 +29,7 @@ __FBSDID("$FreeBSD$");
|
||||
|
||||
#include "common.h"
|
||||
#include "t4_regs.h"
|
||||
#include "t4_regs_values.h"
|
||||
|
||||
#undef msleep
|
||||
#define msleep(x) do { \
|
||||
@ -130,9 +131,10 @@ int t4vf_get_sge_params(struct adapter *adapter)
|
||||
sp->fl_starve_threshold = G_EGRTHRESHOLD(vals[5]) * 2 + 1;
|
||||
if (is_t4(adapter))
|
||||
sp->fl_starve_threshold2 = sp->fl_starve_threshold;
|
||||
else if (is_t5(adapter))
|
||||
sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(vals[5]) * 2 + 1;
|
||||
else
|
||||
sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(vals[5]) * 2 +
|
||||
1;
|
||||
sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(vals[5]) * 2 + 1;
|
||||
|
||||
/*
|
||||
* We need the Queues/Page and Host Page Size for our VF.
|
||||
@ -168,7 +170,13 @@ int t4vf_get_sge_params(struct adapter *adapter)
|
||||
*/
|
||||
sp->spg_len = sp->sge_control & F_EGRSTATUSPAGESIZE ? 128 : 64;
|
||||
sp->fl_pktshift = G_PKTSHIFT(sp->sge_control);
|
||||
sp->pad_boundary = 1 << (G_INGPADBOUNDARY(sp->sge_control) + 5);
|
||||
if (chip_id(adapter) <= CHELSIO_T5) {
|
||||
sp->pad_boundary = 1 << (G_INGPADBOUNDARY(sp->sge_control) +
|
||||
X_INGPADBOUNDARY_SHIFT);
|
||||
} else {
|
||||
sp->pad_boundary = 1 << (G_INGPADBOUNDARY(sp->sge_control) +
|
||||
X_T6_INGPADBOUNDARY_SHIFT);
|
||||
}
|
||||
if (is_t4(adapter))
|
||||
sp->pack_boundary = sp->pad_boundary;
|
||||
else {
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
9594
sys/dev/cxgbe/firmware/t4fw-1.16.12.0.bin.uu
Normal file
9594
sys/dev/cxgbe/firmware/t4fw-1.16.12.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
@ -114,6 +114,7 @@ enum fw_wr_opcodes {
|
||||
FW_RI_RECV_WR = 0x17,
|
||||
FW_RI_BIND_MW_WR = 0x18,
|
||||
FW_RI_FR_NSMR_WR = 0x19,
|
||||
FW_RI_FR_NSMR_TPTE_WR = 0x20,
|
||||
FW_RI_INV_LSTAG_WR = 0x1a,
|
||||
FW_RI_SEND_IMMEDIATE_WR = 0x15,
|
||||
FW_RI_ATOMIC_WR = 0x16,
|
||||
@ -135,7 +136,9 @@ enum fw_wr_opcodes {
|
||||
FW_POFCOE_ULPTX_WR = 0x43,
|
||||
FW_ISCSI_TX_DATA_WR = 0x45,
|
||||
FW_PTP_TX_PKT_WR = 0x46,
|
||||
FW_SEC_LOOKASIDE_LPBK_WR= 0x6d,
|
||||
FW_TLSTX_DATA_WR = 0x68,
|
||||
FW_TLS_KEYCTX_TX_WR = 0x69,
|
||||
FW_CRYPTO_LOOKASIDE_WR = 0x6d,
|
||||
FW_COiSCSI_TGT_WR = 0x70,
|
||||
FW_COiSCSI_TGT_CONN_WR = 0x71,
|
||||
FW_COiSCSI_TGT_XMIT_WR = 0x72,
|
||||
@ -913,7 +916,8 @@ enum fw_flowc_mnem {
|
||||
FW_FLOWC_MNEM_DCBPRIO = 12,
|
||||
FW_FLOWC_MNEM_SND_SCALE = 13,
|
||||
FW_FLOWC_MNEM_RCV_SCALE = 14,
|
||||
FW_FLOWC_MNEM_MAX = 15,
|
||||
FW_FLOWC_MNEM_ULP_MODE = 15,
|
||||
FW_FLOWC_MNEM_MAX = 16,
|
||||
};
|
||||
|
||||
struct fw_flowc_mnemval {
|
||||
@ -1336,7 +1340,7 @@ struct fw_ri_cqe {
|
||||
struct fw_ri_scqe {
|
||||
__be32 qpid_n_stat_rxtx_type;
|
||||
__be32 plen;
|
||||
__be32 reserved;
|
||||
__be32 stag;
|
||||
__be32 wrid;
|
||||
} scqe;
|
||||
struct fw_ri_rcqe {
|
||||
@ -1804,6 +1808,18 @@ struct fw_ri_fr_nsmr_wr {
|
||||
#define G_FW_RI_FR_NSMR_WR_DCACPU(x) \
|
||||
(((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
|
||||
|
||||
struct fw_ri_fr_nsmr_tpte_wr {
|
||||
__u8 opcode;
|
||||
__u8 flags;
|
||||
__u16 wrid;
|
||||
__u8 r1[3];
|
||||
__u8 len16;
|
||||
__be32 r2;
|
||||
__be32 stag;
|
||||
struct fw_ri_tpte tpte;
|
||||
__be64 pbl[2];
|
||||
};
|
||||
|
||||
struct fw_ri_inv_lstag_wr {
|
||||
__u8 opcode;
|
||||
__u8 flags;
|
||||
@ -3384,8 +3400,456 @@ struct fw_pi_error {
|
||||
#define G_FW_PI_ERROR_ERR_TYPE(x) \
|
||||
(((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)
|
||||
|
||||
struct fw_tlstx_data_wr {
|
||||
__be32 op_to_immdlen;
|
||||
__be32 flowid_len16;
|
||||
__be32 plen;
|
||||
__be32 lsodisable_to_flags;
|
||||
__be32 ddraddr;
|
||||
__be32 ctxloc_to_exp;
|
||||
__be16 mfs;
|
||||
__be16 adjustedplen_pkd;
|
||||
__be16 expinplenmax_pkd;
|
||||
__u8 pdusinplenmax_pkd;
|
||||
__u8 r9;
|
||||
};
|
||||
|
||||
struct fw_sec_lookaside_lpbk_wr {
|
||||
#define S_FW_TLSTX_DATA_WR_COMPL 21
|
||||
#define M_FW_TLSTX_DATA_WR_COMPL 0x1
|
||||
#define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL)
|
||||
#define G_FW_TLSTX_DATA_WR_COMPL(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL)
|
||||
#define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_IMMDLEN 0
|
||||
#define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff
|
||||
#define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN)
|
||||
#define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_FLOWID 8
|
||||
#define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff
|
||||
#define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID)
|
||||
#define G_FW_TLSTX_DATA_WR_FLOWID(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_LEN16 0
|
||||
#define M_FW_TLSTX_DATA_WR_LEN16 0xff
|
||||
#define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16)
|
||||
#define G_FW_TLSTX_DATA_WR_LEN16(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_LSODISABLE 31
|
||||
#define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1
|
||||
#define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \
|
||||
((x) << S_FW_TLSTX_DATA_WR_LSODISABLE)
|
||||
#define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE)
|
||||
#define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_ALIGNPLD 30
|
||||
#define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1
|
||||
#define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD)
|
||||
#define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD)
|
||||
#define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29
|
||||
#define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1
|
||||
#define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
|
||||
((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
|
||||
#define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \
|
||||
M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
|
||||
#define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_FLAGS 0
|
||||
#define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff
|
||||
#define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS)
|
||||
#define G_FW_TLSTX_DATA_WR_FLAGS(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_CTXLOC 30
|
||||
#define M_FW_TLSTX_DATA_WR_CTXLOC 0x3
|
||||
#define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC)
|
||||
#define G_FW_TLSTX_DATA_WR_CTXLOC(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_IVDSGL 29
|
||||
#define M_FW_TLSTX_DATA_WR_IVDSGL 0x1
|
||||
#define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL)
|
||||
#define G_FW_TLSTX_DATA_WR_IVDSGL(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL)
|
||||
#define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_KEYSIZE 24
|
||||
#define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f
|
||||
#define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE)
|
||||
#define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_NUMIVS 14
|
||||
#define M_FW_TLSTX_DATA_WR_NUMIVS 0xff
|
||||
#define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS)
|
||||
#define G_FW_TLSTX_DATA_WR_NUMIVS(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_EXP 0
|
||||
#define M_FW_TLSTX_DATA_WR_EXP 0x3fff
|
||||
#define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP)
|
||||
#define G_FW_TLSTX_DATA_WR_EXP(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1
|
||||
#define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff
|
||||
#define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
|
||||
((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
|
||||
#define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \
|
||||
M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4
|
||||
#define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff
|
||||
#define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
|
||||
((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX)
|
||||
#define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \
|
||||
M_FW_TLSTX_DATA_WR_EXPINPLENMAX)
|
||||
|
||||
#define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2
|
||||
#define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f
|
||||
#define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
|
||||
((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
|
||||
#define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
|
||||
(((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \
|
||||
M_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
|
||||
|
||||
struct fw_tls_keyctx_tx_wr {
|
||||
__be32 op_to_compl;
|
||||
__be32 flowid_len16;
|
||||
union fw_key_ctx {
|
||||
struct fw_tx_keyctx_hdr {
|
||||
__u8 ctxlen;
|
||||
__u8 r2;
|
||||
__be16 dualck_to_txvalid;
|
||||
__u8 txsalt[4];
|
||||
__be64 r5;
|
||||
} txhdr;
|
||||
struct fw_rx_keyctx_hdr {
|
||||
__u8 flitcnt_hmacctrl;
|
||||
__u8 protover_ciphmode;
|
||||
__u8 authmode_to_rxvalid;
|
||||
__u8 ivpresent_to_rxmk_size;
|
||||
__u8 rxsalt[4];
|
||||
__be64 ivinsert_to_authinsrt;
|
||||
} rxhdr;
|
||||
struct fw_keyctx_clear {
|
||||
__be32 tx_key;
|
||||
__be32 rx_key;
|
||||
} kctx_clr;
|
||||
} u;
|
||||
struct keys {
|
||||
__u8 edkey[32];
|
||||
__u8 ipad[64];
|
||||
__u8 opad[64];
|
||||
} keys;
|
||||
__u8 reneg_to_write_rx;
|
||||
__u8 protocol;
|
||||
__u8 r7[2];
|
||||
__be32 ftid;
|
||||
};
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_OPCODE 24
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_OPCODE 0xff
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_OPCODE(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_OPCODE)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_OPCODE(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_OPCODE) & M_FW_TLS_KEYCTX_TX_WR_OPCODE)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_ATOMIC 23
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_ATOMIC 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_ATOMIC)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_ATOMIC) & M_FW_TLS_KEYCTX_TX_WR_ATOMIC)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_ATOMIC V_FW_TLS_KEYCTX_TX_WR_ATOMIC(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_FLUSH 22
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_FLUSH 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_FLUSH(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLUSH)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_FLUSH(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_FLUSH) & M_FW_TLS_KEYCTX_TX_WR_FLUSH)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_FLUSH V_FW_TLS_KEYCTX_TX_WR_FLUSH(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_COMPL 21
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_COMPL 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_COMPL(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_COMPL)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_COMPL(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_COMPL) & M_FW_TLS_KEYCTX_TX_WR_COMPL)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_COMPL V_FW_TLS_KEYCTX_TX_WR_COMPL(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_FLOWID 8
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_FLOWID 0xfffff
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_FLOWID(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLOWID)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_FLOWID(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_FLOWID) & M_FW_TLS_KEYCTX_TX_WR_FLOWID)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_LEN16 0
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_LEN16 0xff
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_LEN16(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_LEN16)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_LEN16(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_LEN16) & M_FW_TLS_KEYCTX_TX_WR_LEN16)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_DUALCK 12
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_DUALCK 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_DUALCK(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_DUALCK)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_DUALCK(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_DUALCK) & M_FW_TLS_KEYCTX_TX_WR_DUALCK)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_DUALCK V_FW_TLS_KEYCTX_TX_WR_DUALCK(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 11
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT \
|
||||
V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 10
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT \
|
||||
V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 6
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 0xf
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 2
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 0xf
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_TXVALID 0
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_TXVALID 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_TXVALID)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_TXVALID) & M_FW_TLS_KEYCTX_TX_WR_TXVALID)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_TXVALID V_FW_TLS_KEYCTX_TX_WR_TXVALID(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_FLITCNT 3
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_FLITCNT 0x1f
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_FLITCNT)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_FLITCNT) & M_FW_TLS_KEYCTX_TX_WR_FLITCNT)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0x7
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_HMACCTRL)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) & M_FW_TLS_KEYCTX_TX_WR_HMACCTRL)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_PROTOVER 4
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_PROTOVER 0xf
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_PROTOVER)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_PROTOVER) & M_FW_TLS_KEYCTX_TX_WR_PROTOVER)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0xf
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHMODE)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) & M_FW_TLS_KEYCTX_TX_WR_CIPHMODE)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_AUTHMODE 4
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_AUTHMODE 0xf
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHMODE)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) & M_FW_TLS_KEYCTX_TX_WR_AUTHMODE)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 3
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL \
|
||||
V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 1
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 0x3
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_RXVALID 0
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_RXVALID 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_RXVALID)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_RXVALID) & M_FW_TLS_KEYCTX_TX_WR_RXVALID)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_RXVALID V_FW_TLS_KEYCTX_TX_WR_RXVALID(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_IVPRESENT 7
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_IVPRESENT 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_IVPRESENT)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_IVPRESENT)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_IVPRESENT V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 6
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT \
|
||||
V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 3
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 0x7
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0x7
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_IVINSERT 55
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_IVINSERT 0x1ffULL
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_IVINSERT)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_IVINSERT) & M_FW_TLS_KEYCTX_TX_WR_IVINSERT)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 47
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 0xffULL
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 39
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 0xffULL
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 30
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 0x1ffULL
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 23
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 0x7f
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 14
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 0x1ff
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 7
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 0x7f
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0x7f
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_RENEG 4
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_RENEG 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_RENEG(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_RENEG)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_RENEG(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_RENEG) & M_FW_TLS_KEYCTX_TX_WR_RENEG)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_RENEG V_FW_TLS_KEYCTX_TX_WR_RENEG(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_DELETE_TX 3
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_DELETE_TX 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_TX)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_DELETE_TX)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_DELETE_TX V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_DELETE_RX 2
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_DELETE_RX 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_RX)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) & \
|
||||
M_FW_TLS_KEYCTX_TX_WR_DELETE_RX)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_DELETE_RX V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_WRITE_TX 1
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_WRITE_TX 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_TX)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_TX)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_WRITE_TX V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(1U)
|
||||
|
||||
#define S_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0
|
||||
#define M_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0x1
|
||||
#define V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \
|
||||
((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_RX)
|
||||
#define G_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \
|
||||
(((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_RX)
|
||||
#define F_FW_TLS_KEYCTX_TX_WR_WRITE_RX V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(1U)
|
||||
|
||||
struct fw_crypto_lookaside_wr {
|
||||
__be32 op_to_cctx_size;
|
||||
__be32 len16_pkd;
|
||||
__be32 session_id;
|
||||
@ -3395,116 +3859,124 @@ struct fw_sec_lookaside_lpbk_wr {
|
||||
__be64 cookie;
|
||||
};
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE 24
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE 0xff
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_OPCODE)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL 23
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_COMPL 0x1
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_COMPL) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_COMPL)
|
||||
#define F_FW_SEC_LOOKASIDE_LPBK_WR_COMPL V_FW_SEC_LOOKASIDE_LPBK_WR_COMPL(1U)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_COMPL)
|
||||
#define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN 15
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN 0xff
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_IMM_LEN)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC 5
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC 0x3
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_LOC)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE 0
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE 0x1f
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_CCTX_SIZE)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16 0
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_LEN16 0xff
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_LEN16(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_LEN16(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_LEN16) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_LEN16)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_LEN16)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID 29
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID 0x3
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_RX_CHID)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_LCB 27
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_LCB 0x3
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_LCB(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_LCB)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_LCB(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_LCB) & M_FW_SEC_LOOKASIDE_LPBK_WR_LCB)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH 25
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_PHASH 0x3
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_PHASH(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_PHASH(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_PHASH) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_PHASH)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_PHASH)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_IV 23
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_IV 0x3
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_IV(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_IV)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_IV(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_IV) & M_FW_SEC_LOOKASIDE_LPBK_WR_IV)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_IV 23
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH 10
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH 0x3
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_TX_CH)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID 0
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID 0x3ff
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_RX_Q_ID)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE 24
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE 0xff
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_PLD_SIZE)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
|
||||
|
||||
#define S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE 17
|
||||
#define M_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE 0x7f
|
||||
#define V_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE(x) \
|
||||
((x) << S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE)
|
||||
#define G_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE(x) \
|
||||
(((x) >> S_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE) & \
|
||||
M_FW_SEC_LOOKASIDE_LPBK_WR_HASH_SIZE)
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
|
||||
|
||||
#define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17
|
||||
#define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f
|
||||
#define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
|
||||
((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
|
||||
#define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
|
||||
(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \
|
||||
M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
|
||||
|
||||
/******************************************************************************
|
||||
* C O M M A N D s
|
||||
@ -3571,6 +4043,7 @@ enum fw_cmd_opcodes {
|
||||
FW_FCOE_STATS_CMD = 0x37,
|
||||
FW_FCOE_FCF_CMD = 0x38,
|
||||
FW_DCB_IEEE_CMD = 0x3a,
|
||||
FW_DIAG_CMD = 0x3d,
|
||||
FW_PTP_CMD = 0x3e,
|
||||
FW_LASTC2E_CMD = 0x40,
|
||||
FW_ERROR_CMD = 0x80,
|
||||
@ -4095,8 +4568,9 @@ enum fw_caps_config_iscsi {
|
||||
FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100,
|
||||
};
|
||||
|
||||
enum fw_caps_config_tls {
|
||||
FW_CAPS_CONFIG_TLSKEYS = 0x00000001,
|
||||
enum fw_caps_config_crypto {
|
||||
FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
|
||||
FW_CAPS_CONFIG_TLSKEYS = 0x00000002,
|
||||
};
|
||||
|
||||
enum fw_caps_config_fcoe {
|
||||
@ -4128,7 +4602,7 @@ struct fw_caps_config_cmd {
|
||||
__be16 niccaps;
|
||||
__be16 toecaps;
|
||||
__be16 rdmacaps;
|
||||
__be16 tlscaps;
|
||||
__be16 cryptocaps;
|
||||
__be16 iscsicaps;
|
||||
__be16 fcoecaps;
|
||||
__be32 cfcsum;
|
||||
@ -4208,6 +4682,7 @@ enum fw_params_param_dev {
|
||||
FW_PARAMS_PARAM_DEV_RSSINFO = 0x19,
|
||||
FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
|
||||
FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
|
||||
FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
|
||||
};
|
||||
|
||||
/*
|
||||
@ -4294,6 +4769,7 @@ enum fw_params_param_pfvf {
|
||||
FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
|
||||
FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
|
||||
FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
|
||||
FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38,
|
||||
};
|
||||
|
||||
/*
|
||||
@ -6305,7 +6781,7 @@ struct fw_acl_vlan_cmd {
|
||||
enum fw_port_cap {
|
||||
FW_PORT_CAP_SPEED_100M = 0x0001,
|
||||
FW_PORT_CAP_SPEED_1G = 0x0002,
|
||||
FW_PORT_CAP_SPEED_2_5G = 0x0004,
|
||||
FW_PORT_CAP_SPEED_25G = 0x0004,
|
||||
FW_PORT_CAP_SPEED_10G = 0x0008,
|
||||
FW_PORT_CAP_SPEED_40G = 0x0010,
|
||||
FW_PORT_CAP_SPEED_100G = 0x0020,
|
||||
@ -6776,7 +7252,13 @@ enum fw_port_type {
|
||||
FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
|
||||
FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
|
||||
FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
|
||||
|
||||
FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G, Backplane */
|
||||
FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G */
|
||||
FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
|
||||
FW_PORT_TYPE_CR_SFP28 = 19, /* No, 1, 25G - Old vpd */
|
||||
FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G - New vpd */
|
||||
FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G using Backplane */
|
||||
FW_PORT_TYPE_CR2_QSFP = 22, /* No, 2, 50G */
|
||||
FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
|
||||
};
|
||||
|
||||
@ -7477,7 +7959,7 @@ struct fw_rss_glb_config_cmd {
|
||||
__be64 r5;
|
||||
} manual;
|
||||
struct fw_rss_glb_config_basicvirtual {
|
||||
__be32 mode_pkd;
|
||||
__be32 mode_keymode;
|
||||
__be32 synmapen_to_hashtoeplitz;
|
||||
__be64 r8;
|
||||
__be64 r9;
|
||||
@ -7495,6 +7977,19 @@ struct fw_rss_glb_config_cmd {
|
||||
#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
|
||||
#define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1
|
||||
|
||||
#define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26
|
||||
#define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3
|
||||
#define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
|
||||
((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
|
||||
#define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
|
||||
(((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \
|
||||
M_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
|
||||
|
||||
#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0
|
||||
#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1
|
||||
#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2
|
||||
#define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3
|
||||
|
||||
#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
|
||||
#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1
|
||||
#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
|
||||
@ -7594,7 +8089,8 @@ struct fw_rss_vi_config_cmd {
|
||||
struct fw_rss_vi_config_basicvirtual {
|
||||
__be32 r6;
|
||||
__be32 defaultq_to_udpen;
|
||||
__be64 r9;
|
||||
__be32 secretkeyidx_pkd;
|
||||
__be32 secretkeyxor;
|
||||
__be64 r10;
|
||||
} basicvirtual;
|
||||
} u;
|
||||
@ -7661,6 +8157,14 @@ struct fw_rss_vi_config_cmd {
|
||||
(((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
|
||||
#define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
|
||||
|
||||
#define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0
|
||||
#define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf
|
||||
#define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
|
||||
((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
|
||||
#define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
|
||||
(((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \
|
||||
M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
|
||||
|
||||
enum fw_sched_sc {
|
||||
FW_SCHED_SC_CONFIG = 0,
|
||||
FW_SCHED_SC_PARAMS = 1,
|
||||
@ -8565,6 +9069,43 @@ struct fw_debug_cmd {
|
||||
#define G_FW_DEBUG_CMD_TYPE(x) \
|
||||
(((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
|
||||
|
||||
enum fw_diag_cmd_type {
|
||||
FW_DIAG_CMD_TYPE_OFLDIAG = 0,
|
||||
};
|
||||
|
||||
enum fw_diag_cmd_ofldiag_op {
|
||||
FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0,
|
||||
FW_DIAG_CMD_OFLDIAG_TEST_START,
|
||||
FW_DIAG_CMD_OFLDIAG_TEST_STOP,
|
||||
FW_DIAG_CMD_OFLDIAG_TEST_STATUS,
|
||||
};
|
||||
|
||||
enum fw_diag_cmd_ofldiag_status {
|
||||
FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0,
|
||||
FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING,
|
||||
FW_DIAG_CMD_OFLDIAG_STATUS_FAILED,
|
||||
FW_DIAG_CMD_OFLDIAG_STATUS_PASSED,
|
||||
};
|
||||
|
||||
struct fw_diag_cmd {
|
||||
__be32 op_type;
|
||||
__be32 len16_pkd;
|
||||
union fw_diag_test {
|
||||
struct fw_diag_test_ofldiag {
|
||||
__u8 test_op;
|
||||
__u8 r3;
|
||||
__be16 test_status;
|
||||
__be32 duration;
|
||||
} ofldiag;
|
||||
} u;
|
||||
};
|
||||
|
||||
#define S_FW_DIAG_CMD_TYPE 0
|
||||
#define M_FW_DIAG_CMD_TYPE 0xff
|
||||
#define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE)
|
||||
#define G_FW_DIAG_CMD_TYPE(x) \
|
||||
(((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)
|
||||
|
||||
/******************************************************************************
|
||||
* P C I E F W R E G I S T E R
|
||||
**************************************/
|
||||
@ -8778,14 +9319,19 @@ enum fw_hdr_chip {
|
||||
|
||||
enum {
|
||||
T4FW_VERSION_MAJOR = 0x01,
|
||||
T4FW_VERSION_MINOR = 0x05,
|
||||
T4FW_VERSION_MICRO = 0x25,
|
||||
T4FW_VERSION_MINOR = 0x10,
|
||||
T4FW_VERSION_MICRO = 0x0c,
|
||||
T4FW_VERSION_BUILD = 0x00,
|
||||
|
||||
T5FW_VERSION_MAJOR = 0x01,
|
||||
T5FW_VERSION_MINOR = 0x05,
|
||||
T5FW_VERSION_MICRO = 0x25,
|
||||
T5FW_VERSION_MINOR = 0x10,
|
||||
T5FW_VERSION_MICRO = 0x0c,
|
||||
T5FW_VERSION_BUILD = 0x00,
|
||||
|
||||
T6FW_VERSION_MAJOR = 0x01,
|
||||
T6FW_VERSION_MINOR = 0x10,
|
||||
T6FW_VERSION_MICRO = 0x0c,
|
||||
T6FW_VERSION_BUILD = 0x00,
|
||||
};
|
||||
|
||||
enum {
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
10663
sys/dev/cxgbe/firmware/t5fw-1.16.12.0.bin.uu
Normal file
10663
sys/dev/cxgbe/firmware/t5fw-1.16.12.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
@ -467,7 +467,6 @@
|
||||
fcoe_nfcf = 16
|
||||
fcoe_nvnp = 32
|
||||
fcoe_nssn = 1024
|
||||
fcoe_nfcb = 256
|
||||
|
||||
|
||||
# The following function, 1023, is not an actual PCIE function but is used to
|
||||
@ -602,7 +601,7 @@
|
||||
|
||||
[fini]
|
||||
version = 0x1425001c
|
||||
checksum = 0xa4a80156
|
||||
checksum = 0xf9115d76
|
||||
|
||||
# Total resources used by above allocations:
|
||||
# Virtual Interfaces: 104
|
||||
|
||||
8839
sys/dev/cxgbe/firmware/t6fw-1.16.12.0.bin.uu
Normal file
8839
sys/dev/cxgbe/firmware/t6fw-1.16.12.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
583
sys/dev/cxgbe/firmware/t6fw_cfg.txt
Normal file
583
sys/dev/cxgbe/firmware/t6fw_cfg.txt
Normal file
@ -0,0 +1,583 @@
|
||||
# Chelsio T6 Factory Default configuration file.
|
||||
#
|
||||
# Copyright (C) 2014-2016 Chelsio Communications. All rights reserved.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
|
||||
# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
|
||||
# TO ADAPTERS.
|
||||
|
||||
|
||||
# This file provides the default, power-on configuration for 2-port T6-based
|
||||
# adapters shipped from the factory. These defaults are designed to address
|
||||
# the needs of the vast majority of Terminator customers. The basic idea is to
|
||||
# have a default configuration which allows a customer to plug a Terminator
|
||||
# adapter in and have it work regardless of OS, driver or application except in
|
||||
# the most unusual and/or demanding customer applications.
|
||||
#
|
||||
# Many of the Terminator resources which are described by this configuration
|
||||
# are finite. This requires balancing the configuration/operation needs of
|
||||
# device drivers across OSes and a large number of customer application.
|
||||
#
|
||||
# Some of the more important resources to allocate and their constaints are:
|
||||
# 1. Virtual Interfaces: 256.
|
||||
# 2. Ingress Queues with Free Lists: 1024.
|
||||
# 3. Egress Queues: 128K.
|
||||
# 4. MSI-X Vectors: 1088.
|
||||
# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
|
||||
# address matching on Ingress Packets.
|
||||
#
|
||||
# Some of the important OS/Driver resource needs are:
|
||||
# 6. Some OS Drivers will manage all resources through a single Physical
|
||||
# Function (currently PF4 but it could be any Physical Function).
|
||||
# 7. Some OS Drivers will manage different ports and functions (NIC,
|
||||
# storage, etc.) on different Physical Functions. For example, NIC
|
||||
# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
|
||||
#
|
||||
# Some of the customer application needs which need to be accommodated:
|
||||
# 8. Some customers will want to support large CPU count systems with
|
||||
# good scaling. Thus, we'll need to accommodate a number of
|
||||
# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
|
||||
# to be involved per port and per application function. For example,
|
||||
# in the case where all ports and application functions will be
|
||||
# managed via a single Unified PF and we want to accommodate scaling up
|
||||
# to 8 CPUs, we would want:
|
||||
#
|
||||
# 2 ports *
|
||||
# 3 application functions (NIC, FCoE, iSCSI) per port *
|
||||
# 16 Ingress Queue/MSI-X Vectors per application function
|
||||
#
|
||||
# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
|
||||
# (Plus a few for Firmware Event Queues, etc.)
|
||||
#
|
||||
# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
|
||||
# Machines to directly access T6 functionality via SR-IOV Virtual Functions
|
||||
# and "PCI Device Passthrough" -- this is especially true for the NIC
|
||||
# application functionality.
|
||||
#
|
||||
|
||||
|
||||
# Global configuration settings.
|
||||
#
|
||||
[global]
|
||||
rss_glb_config_mode = basicvirtual
|
||||
rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
|
||||
|
||||
# PL_TIMEOUT register
|
||||
pl_timeout_value = 200 # the timeout value in units of us
|
||||
|
||||
# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
|
||||
# Page Size and a 64B L1 Cache Line Size. It programs the
|
||||
# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
|
||||
# If a Master PF Driver finds itself on a machine with different
|
||||
# parameters, then the Master PF Driver is responsible for initializing
|
||||
# these parameters to appropriate values.
|
||||
#
|
||||
# Notes:
|
||||
# 1. The Free List Buffer Sizes below are raw and the firmware will
|
||||
# round them up to the Ingress Padding Boundary.
|
||||
# 2. The SGE Timer Values below are expressed below in microseconds.
|
||||
# The firmware will convert these values to Core Clock Ticks when
|
||||
# it processes the configuration parameters.
|
||||
#
|
||||
reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
|
||||
reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
|
||||
reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
|
||||
reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
|
||||
reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
|
||||
reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
|
||||
reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
|
||||
reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
|
||||
reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
|
||||
reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6
|
||||
reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7
|
||||
reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8
|
||||
reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
|
||||
reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL
|
||||
sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
|
||||
reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
|
||||
|
||||
# enable TP_OUT_CONFIG.IPIDSPLITMODE
|
||||
reg[0x7d04] = 0x00010000/0x00010000
|
||||
|
||||
reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
|
||||
|
||||
#Tick granularities in kbps
|
||||
tsch_ticks = 100000, 10000, 1000, 10
|
||||
|
||||
# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
|
||||
# filter control: compact, fcoemask
|
||||
# server sram : srvrsram
|
||||
# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
|
||||
# protocol, tos, vlan, vnic_id, port, fcoe
|
||||
# valid filterModes are described the Terminator 5 Data Book
|
||||
filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
|
||||
|
||||
# filter tuples enforced in LE active region (equal to or subset of filterMode)
|
||||
filterMask = protocol, fcoe
|
||||
|
||||
# Percentage of dynamic memory (in either the EDRAM or external MEM)
|
||||
# to use for TP RX payload
|
||||
tp_pmrx = 30
|
||||
|
||||
# TP RX payload page size
|
||||
tp_pmrx_pagesize = 64K
|
||||
|
||||
# TP number of RX channels
|
||||
tp_nrxch = 0 # 0 (auto) = 1
|
||||
|
||||
# Percentage of dynamic memory (in either the EDRAM or external MEM)
|
||||
# to use for TP TX payload
|
||||
tp_pmtx = 50
|
||||
|
||||
# TP TX payload page size
|
||||
tp_pmtx_pagesize = 64K
|
||||
|
||||
# TP number of TX channels
|
||||
tp_ntxch = 0 # 0 (auto) = equal number of ports
|
||||
|
||||
# TP OFLD MTUs
|
||||
tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
|
||||
|
||||
# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
|
||||
reg[0x7d04] = 0x00010008/0x00010008
|
||||
|
||||
# TP_GLOBAL_CONFIG
|
||||
reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
|
||||
|
||||
# TP_PC_CONFIG
|
||||
reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
|
||||
|
||||
# TP_PARA_REG0
|
||||
reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
|
||||
|
||||
# LE_DB_CONFIG
|
||||
reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled
|
||||
# LE IPv4 compression disabled
|
||||
# LE_DB_HASH_CONFIG
|
||||
reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,
|
||||
|
||||
# ULP_TX_CONFIG
|
||||
reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err
|
||||
# Enable more error msg for ...
|
||||
# TPT error.
|
||||
|
||||
# ULP_RX_MISC_FEATURE_ENABLE
|
||||
#reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit
|
||||
# Enable offset decrement after ...
|
||||
# PI extraction and before DDP
|
||||
# ulp insert pi source info in DIF
|
||||
# iscsi_eff_offset_en
|
||||
|
||||
#Enable iscsi completion moderation feature
|
||||
reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after
|
||||
# PI extraction and before DDP.
|
||||
# ulp insert pi source info in
|
||||
# DIF.
|
||||
# Enable iscsi hdr cmd mode.
|
||||
# iscsi force cmd mode.
|
||||
# Enable iscsi cmp mode.
|
||||
# MC configuration
|
||||
#mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
|
||||
|
||||
# Some "definitions" to make the rest of this a bit more readable. We support
|
||||
# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
|
||||
# per function per port ...
|
||||
#
|
||||
# NMSIX = 1088 # available MSI-X Vectors
|
||||
# NVI = 256 # available Virtual Interfaces
|
||||
# NMPSTCAM = 336 # MPS TCAM entries
|
||||
#
|
||||
# NPORTS = 2 # ports
|
||||
# NCPUS = 16 # CPUs we want to support scalably
|
||||
# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
|
||||
|
||||
# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
|
||||
# PF" which many OS Drivers will use to manage most or all functions.
|
||||
#
|
||||
# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
|
||||
# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
|
||||
# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
|
||||
# will be specified as the "Ingress Queue Asynchronous Destination Index."
|
||||
# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
|
||||
# than or equal to the number of Ingress Queues ...
|
||||
#
|
||||
# NVI_NIC = 4 # NIC access to NPORTS
|
||||
# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
|
||||
# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
|
||||
# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
|
||||
# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
|
||||
# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_OFLD = 0 # Offload uses NIC function to access ports
|
||||
# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
|
||||
# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
|
||||
# NEQ_OFLD = 16 # Offload Egress Queues (FL)
|
||||
# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)
|
||||
# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_RDMA = 0 # RDMA uses NIC function to access ports
|
||||
# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
|
||||
# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues
|
||||
# NEQ_RDMA = 4 # RDMA Egress Queues (FL)
|
||||
# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)
|
||||
# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NEQ_WD = 128 # Wire Direct TX Queues and FLs
|
||||
# NETHCTRL_WD = 64 # Wire Direct TX Queues
|
||||
# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
|
||||
#
|
||||
# NVI_ISCSI = 4 # ISCSI access to NPORTS
|
||||
# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
|
||||
# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues
|
||||
# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)
|
||||
# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)
|
||||
# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_FCOE = 4 # FCOE access to NPORTS
|
||||
# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
|
||||
# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues
|
||||
# NEQ_FCOE = 66 # FCOE Egress Queues (FL)
|
||||
# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)
|
||||
# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
|
||||
|
||||
# Two extra Ingress Queues per function for Firmware Events and Forwarded
|
||||
# Interrupts, and two extra interrupts per function for Firmware Events (or a
|
||||
# Forwarded Interrupt Queue) and General Interrupts per function.
|
||||
#
|
||||
# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
|
||||
# # Forwarded Interrupts
|
||||
# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
|
||||
# # General Interrupts
|
||||
|
||||
# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
|
||||
# their interrupts forwarded to another set of Forwarded Interrupt Queues.
|
||||
#
|
||||
# NVI_HYPERV = 16 # VMs we want to support
|
||||
# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
|
||||
# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues
|
||||
# NEQ_HYPERV = 32 # VIQs Free Lists
|
||||
# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)
|
||||
# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
|
||||
|
||||
# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
|
||||
# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
|
||||
#
|
||||
# NVI_UNIFIED = 28
|
||||
# NFLIQ_UNIFIED = 106
|
||||
# NETHCTRL_UNIFIED = 32
|
||||
# NEQ_UNIFIED = 124
|
||||
# NMPSTCAM_UNIFIED = 40
|
||||
#
|
||||
# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
|
||||
# that up to 128 to make sure the Unified PF doesn't run out of resources.
|
||||
#
|
||||
# NMSIX_UNIFIED = 128
|
||||
#
|
||||
# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
|
||||
# which is 34 but they're probably safe with 32.
|
||||
#
|
||||
# NMSIX_STORAGE = 32
|
||||
|
||||
# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
|
||||
# associated with it. Thus, the MSI-X Vector allocations we give to the
|
||||
# UnifiedPF aren't inherited by any Virtual Functions. As a result we can
|
||||
# provision many more Virtual Functions than we can if the UnifiedPF were
|
||||
# one of PF0-3.
|
||||
#
|
||||
|
||||
# All of the below PCI-E parameters are actually stored in various *_init.txt
|
||||
# files. We include them below essentially as comments.
|
||||
#
|
||||
# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
|
||||
# ports 0-3.
|
||||
#
|
||||
# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
|
||||
#
|
||||
# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
|
||||
# storage applications across all four possible ports.
|
||||
#
|
||||
# Additionally, since the UnifiedPF isn't one of the per-port Physical
|
||||
# Functions, we give the UnifiedPF and the PF0-3 Physical Functions
|
||||
# different PCI Device IDs which will allow Unified and Per-Port Drivers
|
||||
# to directly select the type of Physical Function to which they wish to be
|
||||
# attached.
|
||||
#
|
||||
# Note that the actual values used for the PCI-E Intelectual Property will be
|
||||
# 1 less than those below since that's the way it "counts" things. For
|
||||
# readability, we use the number we actually mean ...
|
||||
#
|
||||
# PF0_INT = 8 # NCPUS
|
||||
# PF1_INT = 8 # NCPUS
|
||||
# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
|
||||
#
|
||||
# PF4_INT = 128 # NMSIX_UNIFIED
|
||||
# PF5_INT = 32 # NMSIX_STORAGE
|
||||
# PF6_INT = 32 # NMSIX_STORAGE
|
||||
# PF7_INT = 0 # Nothing Assigned
|
||||
# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
|
||||
#
|
||||
# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
|
||||
#
|
||||
# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
|
||||
# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
|
||||
#
|
||||
# NVF = 16
|
||||
|
||||
|
||||
# For those OSes which manage different ports on different PFs, we need
|
||||
# only enough resources to support a single port's NIC application functions
|
||||
# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
|
||||
# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
|
||||
# managed on the "storage PFs" (see below).
|
||||
#
|
||||
[function "0"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x1 # access to only one port
|
||||
|
||||
|
||||
[function "1"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x2 # access to only one port
|
||||
|
||||
[function "2"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x4 # access to only one port
|
||||
|
||||
[function "3"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x8 # access to only one port
|
||||
|
||||
|
||||
# Some OS Drivers manage all application functions for all ports via PF4.
|
||||
# Thus we need to provide a large number of resources here. For Egress
|
||||
# Queues we need to account for both TX Queues as well as Free List Queues
|
||||
# (because the host is responsible for producing Free List Buffers for the
|
||||
# hardware to consume).
|
||||
#
|
||||
[function "4"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 28 # NVI_UNIFIED
|
||||
niqflint = 202 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32)
|
||||
nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD
|
||||
neq = 256 # NEQ_UNIFIED + NEQ_WD
|
||||
nqpcq = 12288
|
||||
nexactf = 40 # NMPSTCAM_UNIFIED
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nethofld = 1024 # number of user mode ethernet flow contexts
|
||||
ncrypto_lookaside = 16 # Number of lookaside flow contexts
|
||||
nclip = 320 # number of clip region entries
|
||||
nfilter = 496 # number of filter region entries
|
||||
nserver = 496 # number of server region entries
|
||||
nhash = 12288 # number of hash region entries
|
||||
nhpfilter = 0 # number of high priority filter region entries
|
||||
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside
|
||||
tp_l2t = 3072
|
||||
tp_ddp = 2
|
||||
tp_ddp_iscsi = 2
|
||||
tp_tls_key = 3
|
||||
tp_stag = 2
|
||||
tp_pbl = 5
|
||||
tp_rq = 7
|
||||
tp_srq = 128
|
||||
|
||||
# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
|
||||
# need to have Virtual Interfaces on each of the four ports with up to NCPUS
|
||||
# "Queue Sets" each.
|
||||
#
|
||||
[function "5"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NPORTS
|
||||
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
|
||||
nethctrl = 32 # NPORTS*NCPUS
|
||||
neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
|
||||
nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nserver = 16
|
||||
nhash = 2048
|
||||
tp_l2t = 1020
|
||||
nclip = 64
|
||||
protocol = iscsi_initiator_fofld
|
||||
tp_ddp_iscsi = 2
|
||||
iscsi_ntask = 2048
|
||||
iscsi_nsess = 2048
|
||||
iscsi_nconn_per_session = 1
|
||||
iscsi_ninitiator_instance = 64
|
||||
|
||||
|
||||
[function "6"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NPORTS
|
||||
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
|
||||
nethctrl = 32 # NPORTS*NCPUS
|
||||
neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
|
||||
nexactf = 32 # NPORTS + adding 28 exact entries for FCoE
|
||||
# which is OK since < MIN(SUM PF0..3, PF4)
|
||||
# and we never load PF0..3 and PF4 concurrently
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nhash = 2048
|
||||
tp_l2t = 4
|
||||
protocol = fcoe_initiator
|
||||
tp_ddp = 2
|
||||
fcoe_nfcf = 16
|
||||
fcoe_nvnp = 32
|
||||
fcoe_nssn = 1024
|
||||
|
||||
|
||||
# The following function, 1023, is not an actual PCIE function but is used to
|
||||
# configure and reserve firmware internal resources that come from the global
|
||||
# resource pool.
|
||||
#
|
||||
[function "1023"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NVI_UNIFIED
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nexactf = 8 # NPORTS + DCBX +
|
||||
nfilter = 16 # number of filter region entries
|
||||
|
||||
|
||||
# For Virtual functions, we only allow NIC functionality and we only allow
|
||||
# access to one port (1 << PF). Note that because of limitations in the
|
||||
# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
|
||||
# and GTS registers, the number of Ingress and Egress Queues must be a power
|
||||
# of 2.
|
||||
#
|
||||
[function "0/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x1 # access to only one port ...
|
||||
|
||||
|
||||
[function "1/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x2 # access to only one port ...
|
||||
|
||||
[function "2/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x1 # access to only one port ...
|
||||
|
||||
|
||||
[function "3/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x2 # access to only one port ...
|
||||
|
||||
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
|
||||
# for packets from the wire as well as the loopback path of the L2 switch. The
|
||||
# folling params control how the buffer memory is distributed and the L2 flow
|
||||
# control settings:
|
||||
#
|
||||
# bg_mem: %-age of mem to use for port/buffer group
|
||||
# lpbk_mem: %-age of port/bg mem to use for loopback
|
||||
# hwm: high watermark; bytes available when starting to send pause
|
||||
# frames (in units of 0.1 MTU)
|
||||
# lwm: low watermark; bytes remaining when sending 'unpause' frame
|
||||
# (in inuits of 0.1 MTU)
|
||||
# dwm: minimum delta between high and low watermark (in units of 100
|
||||
# Bytes)
|
||||
#
|
||||
[port "0"]
|
||||
dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
|
||||
#bg_mem = 25
|
||||
#lpbk_mem = 25
|
||||
hwm = 60
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
dcb_app_tlv[0] = 0x8906, ethertype, 3
|
||||
dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
aec_retry_cnt = 4
|
||||
|
||||
|
||||
[port "1"]
|
||||
dcb = ppp, dcbx
|
||||
#bg_mem = 25
|
||||
#lpbk_mem = 25
|
||||
hwm = 60
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
dcb_app_tlv[0] = 0x8906, ethertype, 3
|
||||
dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
aec_retry_cnt = 4
|
||||
|
||||
|
||||
[fini]
|
||||
version = 0x01000023
|
||||
checksum = 0x683208a2
|
||||
|
||||
# Total resources used by above allocations:
|
||||
# Virtual Interfaces: 104
|
||||
# Ingress Queues/w Free Lists and Interrupts: 526
|
||||
# Egress Queues: 702
|
||||
# MPS TCAM Entries: 336
|
||||
# MSI-X Vectors: 736
|
||||
# Virtual Functions: 64
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
487
sys/dev/cxgbe/firmware/t6fw_cfg_fpga.txt
Normal file
487
sys/dev/cxgbe/firmware/t6fw_cfg_fpga.txt
Normal file
@ -0,0 +1,487 @@
|
||||
# Chelsio T6 Factory Default configuration file.
|
||||
#
|
||||
# Copyright (C) 2014-2015 Chelsio Communications. All rights reserved.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
|
||||
# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
|
||||
# TO ADAPTERS.
|
||||
|
||||
|
||||
# This file provides the default, power-on configuration for 2-port T6-based
|
||||
# adapters shipped from the factory. These defaults are designed to address
|
||||
# the needs of the vast majority of Terminator customers. The basic idea is to
|
||||
# have a default configuration which allows a customer to plug a Terminator
|
||||
# adapter in and have it work regardless of OS, driver or application except in
|
||||
# the most unusual and/or demanding customer applications.
|
||||
#
|
||||
# Many of the Terminator resources which are described by this configuration
|
||||
# are finite. This requires balancing the configuration/operation needs of
|
||||
# device drivers across OSes and a large number of customer application.
|
||||
#
|
||||
# Some of the more important resources to allocate and their constaints are:
|
||||
# 1. Virtual Interfaces: 256.
|
||||
# 2. Ingress Queues with Free Lists: 1024.
|
||||
# 3. Egress Queues: 128K.
|
||||
# 4. MSI-X Vectors: 1088.
|
||||
# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
|
||||
# address matching on Ingress Packets.
|
||||
#
|
||||
# Some of the important OS/Driver resource needs are:
|
||||
# 6. Some OS Drivers will manage all resources through a single Physical
|
||||
# Function (currently PF4 but it could be any Physical Function).
|
||||
# 7. Some OS Drivers will manage different ports and functions (NIC,
|
||||
# storage, etc.) on different Physical Functions. For example, NIC
|
||||
# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
|
||||
#
|
||||
# Some of the customer application needs which need to be accommodated:
|
||||
# 8. Some customers will want to support large CPU count systems with
|
||||
# good scaling. Thus, we'll need to accommodate a number of
|
||||
# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
|
||||
# to be involved per port and per application function. For example,
|
||||
# in the case where all ports and application functions will be
|
||||
# managed via a single Unified PF and we want to accommodate scaling up
|
||||
# to 8 CPUs, we would want:
|
||||
#
|
||||
# 2 ports *
|
||||
# 3 application functions (NIC, FCoE, iSCSI) per port *
|
||||
# 16 Ingress Queue/MSI-X Vectors per application function
|
||||
#
|
||||
# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
|
||||
# (Plus a few for Firmware Event Queues, etc.)
|
||||
#
|
||||
# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
|
||||
# Machines to directly access T6 functionality via SR-IOV Virtual Functions
|
||||
# and "PCI Device Passthrough" -- this is especially true for the NIC
|
||||
# application functionality.
|
||||
#
|
||||
|
||||
|
||||
# Global configuration settings.
|
||||
#
|
||||
[global]
|
||||
rss_glb_config_mode = basicvirtual
|
||||
rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
|
||||
|
||||
# PL_TIMEOUT register
|
||||
pl_timeout_value = 1000 # the timeout value in units of us
|
||||
|
||||
# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
|
||||
# Page Size and a 64B L1 Cache Line Size. It programs the
|
||||
# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
|
||||
# If a Master PF Driver finds itself on a machine with different
|
||||
# parameters, then the Master PF Driver is responsible for initializing
|
||||
# these parameters to appropriate values.
|
||||
#
|
||||
# Notes:
|
||||
# 1. The Free List Buffer Sizes below are raw and the firmware will
|
||||
# round them up to the Ingress Padding Boundary.
|
||||
# 2. The SGE Timer Values below are expressed below in microseconds.
|
||||
# The firmware will convert these values to Core Clock Ticks when
|
||||
# it processes the configuration parameters.
|
||||
#
|
||||
reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
|
||||
reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
|
||||
reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
|
||||
reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
|
||||
reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
|
||||
reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
|
||||
reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
|
||||
reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
|
||||
reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
|
||||
reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6
|
||||
reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7
|
||||
reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8
|
||||
reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
|
||||
reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL
|
||||
sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
|
||||
reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
|
||||
|
||||
#DBQ Timer duration = 1 cclk cycle duration * (sge_dbq_timertick+1) * sge_dbq_timer
|
||||
#SGE DBQ tick value. All timers are multiple of this value
|
||||
# sge_dbq_timertick = 5 #in usecs
|
||||
# sge_dbq_timer = 1, 2, 4, 6, 8, 10, 12, 16
|
||||
# enable TP_OUT_CONFIG.IPIDSPLITMODE
|
||||
reg[0x7d04] = 0x00010000/0x00010000
|
||||
|
||||
reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
|
||||
|
||||
#Tick granularities in kbps
|
||||
tsch_ticks = 1000, 100, 10, 1
|
||||
|
||||
# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
|
||||
# filter control: compact, fcoemask
|
||||
# server sram : srvrsram
|
||||
# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
|
||||
# protocol, tos, vlan, vnic_id, port, fcoe
|
||||
# valid filterModes are described the Terminator 5 Data Book
|
||||
filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
|
||||
|
||||
# filter tuples enforced in LE active region (equal to or subset of filterMode)
|
||||
filterMask = protocol, fcoe
|
||||
|
||||
# Percentage of dynamic memory (in either the EDRAM or external MEM)
|
||||
# to use for TP RX payload
|
||||
tp_pmrx = 30
|
||||
|
||||
# TP RX payload page size
|
||||
tp_pmrx_pagesize = 64K
|
||||
|
||||
# TP number of RX channels
|
||||
tp_nrxch = 0 # 0 (auto) = 1
|
||||
|
||||
# Percentage of dynamic memory (in either the EDRAM or external MEM)
|
||||
# to use for TP TX payload
|
||||
tp_pmtx = 50
|
||||
|
||||
# TP TX payload page size
|
||||
tp_pmtx_pagesize = 64K
|
||||
|
||||
# TP number of TX channels
|
||||
tp_ntxch = 0 # 0 (auto) = equal number of ports
|
||||
|
||||
# TP OFLD MTUs
|
||||
tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
|
||||
|
||||
# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
|
||||
reg[0x7d04] = 0x00010008/0x00010008
|
||||
|
||||
# TP_GLOBAL_CONFIG
|
||||
reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
|
||||
|
||||
# TP_PC_CONFIG
|
||||
reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
|
||||
|
||||
# TP_PARA_REG0
|
||||
reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
|
||||
|
||||
# LE_DB_CONFIG
|
||||
reg[0x19c04] = 0x00400000/0x00440000 # LE Server SRAM Enable,
|
||||
# LE IPv4 compression disabled
|
||||
# LE_DB_HASH_CONFIG
|
||||
reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,
|
||||
|
||||
# ULP_TX_CONFIG
|
||||
reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err
|
||||
# Enable more error msg for ...
|
||||
# TPT error.
|
||||
|
||||
# ULP_RX_MISC_FEATURE_ENABLE
|
||||
reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit
|
||||
# Enable offset decrement after ...
|
||||
# PI extraction and before DDP
|
||||
# ulp insert pi source info in DIF
|
||||
# iscsi_eff_offset_en
|
||||
|
||||
#Enable iscsi completion moderation feature
|
||||
#reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after
|
||||
# PI extraction and before DDP.
|
||||
# ulp insert pi source info in
|
||||
# DIF.
|
||||
# Enable iscsi hdr cmd mode.
|
||||
# iscsi force cmd mode.
|
||||
# Enable iscsi cmp mode.
|
||||
|
||||
# Some "definitions" to make the rest of this a bit more readable. We support
|
||||
# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
|
||||
# per function per port ...
|
||||
#
|
||||
# NMSIX = 1088 # available MSI-X Vectors
|
||||
# NVI = 256 # available Virtual Interfaces
|
||||
# NMPSTCAM = 336 # MPS TCAM entries
|
||||
#
|
||||
# NPORTS = 2 # ports
|
||||
# NCPUS = 16 # CPUs we want to support scalably
|
||||
# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
|
||||
|
||||
# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
|
||||
# PF" which many OS Drivers will use to manage most or all functions.
|
||||
#
|
||||
# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
|
||||
# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
|
||||
# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
|
||||
# will be specified as the "Ingress Queue Asynchronous Destination Index."
|
||||
# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
|
||||
# than or equal to the number of Ingress Queues ...
|
||||
#
|
||||
# NVI_NIC = 4 # NIC access to NPORTS
|
||||
# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
|
||||
# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
|
||||
# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
|
||||
# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
|
||||
# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_OFLD = 0 # Offload uses NIC function to access ports
|
||||
# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
|
||||
# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
|
||||
# NEQ_OFLD = 16 # Offload Egress Queues (FL)
|
||||
# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)
|
||||
# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_RDMA = 0 # RDMA uses NIC function to access ports
|
||||
# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
|
||||
# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues
|
||||
# NEQ_RDMA = 4 # RDMA Egress Queues (FL)
|
||||
# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)
|
||||
# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NEQ_WD = 128 # Wire Direct TX Queues and FLs
|
||||
# NETHCTRL_WD = 64 # Wire Direct TX Queues
|
||||
# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
|
||||
#
|
||||
# NVI_ISCSI = 4 # ISCSI access to NPORTS
|
||||
# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
|
||||
# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues
|
||||
# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)
|
||||
# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)
|
||||
# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_FCOE = 4 # FCOE access to NPORTS
|
||||
# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
|
||||
# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues
|
||||
# NEQ_FCOE = 66 # FCOE Egress Queues (FL)
|
||||
# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)
|
||||
# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
|
||||
|
||||
# Two extra Ingress Queues per function for Firmware Events and Forwarded
|
||||
# Interrupts, and two extra interrupts per function for Firmware Events (or a
|
||||
# Forwarded Interrupt Queue) and General Interrupts per function.
|
||||
#
|
||||
# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
|
||||
# # Forwarded Interrupts
|
||||
# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
|
||||
# # General Interrupts
|
||||
|
||||
# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
|
||||
# their interrupts forwarded to another set of Forwarded Interrupt Queues.
|
||||
#
|
||||
# NVI_HYPERV = 16 # VMs we want to support
|
||||
# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
|
||||
# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues
|
||||
# NEQ_HYPERV = 32 # VIQs Free Lists
|
||||
# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)
|
||||
# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
|
||||
|
||||
# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
|
||||
# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
|
||||
#
|
||||
# NVI_UNIFIED = 28
|
||||
# NFLIQ_UNIFIED = 106
|
||||
# NETHCTRL_UNIFIED = 32
|
||||
# NEQ_UNIFIED = 124
|
||||
# NMPSTCAM_UNIFIED = 40
|
||||
#
|
||||
# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
|
||||
# that up to 128 to make sure the Unified PF doesn't run out of resources.
|
||||
#
|
||||
# NMSIX_UNIFIED = 128
|
||||
#
|
||||
# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
|
||||
# which is 34 but they're probably safe with 32.
|
||||
#
|
||||
# NMSIX_STORAGE = 32
|
||||
|
||||
# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
|
||||
# associated with it. Thus, the MSI-X Vector allocations we give to the
|
||||
# UnifiedPF aren't inherited by any Virtual Functions. As a result we can
|
||||
# provision many more Virtual Functions than we can if the UnifiedPF were
|
||||
# one of PF0-1.
|
||||
#
|
||||
|
||||
# All of the below PCI-E parameters are actually stored in various *_init.txt
|
||||
# files. We include them below essentially as comments.
|
||||
#
|
||||
# For PF0-1 we assign 8 vectors each for NIC Ingress Queues of the associated
|
||||
# ports 0-1.
|
||||
#
|
||||
# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
|
||||
#
|
||||
# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
|
||||
# storage applications across all four possible ports.
|
||||
#
|
||||
# Additionally, since the UnifiedPF isn't one of the per-port Physical
|
||||
# Functions, we give the UnifiedPF and the PF0-1 Physical Functions
|
||||
# different PCI Device IDs which will allow Unified and Per-Port Drivers
|
||||
# to directly select the type of Physical Function to which they wish to be
|
||||
# attached.
|
||||
#
|
||||
# Note that the actual values used for the PCI-E Intelectual Property will be
|
||||
# 1 less than those below since that's the way it "counts" things. For
|
||||
# readability, we use the number we actually mean ...
|
||||
#
|
||||
# PF0_INT = 8 # NCPUS
|
||||
# PF1_INT = 8 # NCPUS
|
||||
# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
|
||||
#
|
||||
# PF4_INT = 128 # NMSIX_UNIFIED
|
||||
# PF5_INT = 32 # NMSIX_STORAGE
|
||||
# PF6_INT = 32 # NMSIX_STORAGE
|
||||
# PF7_INT = 0 # Nothing Assigned
|
||||
# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
|
||||
#
|
||||
# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
|
||||
#
|
||||
# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
|
||||
# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
|
||||
#
|
||||
# NVF = 16
|
||||
|
||||
|
||||
# For those OSes which manage different ports on different PFs, we need
|
||||
# only enough resources to support a single port's NIC application functions
|
||||
# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
|
||||
# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
|
||||
# managed on the "storage PFs" (see below).
|
||||
#
|
||||
|
||||
# Some OS Drivers manage all application functions for all ports via PF4.
|
||||
# Thus we need to provide a large number of resources here. For Egress
|
||||
# Queues we need to account for both TX Queues as well as Free List Queues
|
||||
# (because the host is responsible for producing Free List Buffers for the
|
||||
# hardware to consume).
|
||||
#
|
||||
[function "0"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 28 # NVI_UNIFIED
|
||||
niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD
|
||||
nethctrl = 96 # NETHCTRL_UNIFIED + NETHCTRL_WD
|
||||
neq = 252 # NEQ_UNIFIED + NEQ_WD
|
||||
nexactf = 40 # NMPSTCAM_UNIFIED
|
||||
nrawf = 2
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nethofld = 1024 # number of user mode ethernet flow contexts
|
||||
ncrypto_lookaside = 32
|
||||
nclip = 32 # number of clip region entries
|
||||
nfilter = 48 # number of filter region entries
|
||||
nserver = 48 # number of server region entries
|
||||
nhash = 2048 # number of hash region entries
|
||||
nhpfilter = 0 # number of high priority filter region entries
|
||||
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside
|
||||
tp_l2t = 3072
|
||||
tp_ddp = 2
|
||||
tp_ddp_iscsi = 2
|
||||
tp_tls_key = 3
|
||||
tp_stag = 2
|
||||
tp_pbl = 5
|
||||
tp_rq = 7
|
||||
tp_srq = 128
|
||||
|
||||
# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
|
||||
# need to have Virtual Interfaces on each of the four ports with up to NCPUS
|
||||
# "Queue Sets" each.
|
||||
#
|
||||
[function "1"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NPORTS
|
||||
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
|
||||
nethctrl = 32 # NPORTS*NCPUS
|
||||
neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
|
||||
nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nserver = 16
|
||||
nhash = 2048
|
||||
tp_l2t = 1020
|
||||
protocol = iscsi_initiator_fofld
|
||||
tp_ddp_iscsi = 2
|
||||
iscsi_ntask = 2048
|
||||
iscsi_nsess = 2048
|
||||
iscsi_nconn_per_session = 1
|
||||
iscsi_ninitiator_instance = 64
|
||||
|
||||
|
||||
# The following function, 1023, is not an actual PCIE function but is used to
|
||||
# configure and reserve firmware internal resources that come from the global
|
||||
# resource pool.
|
||||
#
|
||||
[function "1023"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NVI_UNIFIED
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nexactf = 8 # NPORTS + DCBX +
|
||||
nfilter = 16 # number of filter region entries
|
||||
#nhpfilter = 0 # number of high priority filter region entries
|
||||
|
||||
|
||||
# For Virtual functions, we only allow NIC functionality and we only allow
|
||||
# access to one port (1 << PF). Note that because of limitations in the
|
||||
# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
|
||||
# and GTS registers, the number of Ingress and Egress Queues must be a power
|
||||
# of 2.
|
||||
#
|
||||
[function "0/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x1 # access to only one port ...
|
||||
|
||||
|
||||
[function "1/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x2 # access to only one port ...
|
||||
|
||||
|
||||
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
|
||||
# for packets from the wire as well as the loopback path of the L2 switch. The
|
||||
# folling params control how the buffer memory is distributed and the L2 flow
|
||||
# control settings:
|
||||
#
|
||||
# bg_mem: %-age of mem to use for port/buffer group
|
||||
# lpbk_mem: %-age of port/bg mem to use for loopback
|
||||
# hwm: high watermark; bytes available when starting to send pause
|
||||
# frames (in units of 0.1 MTU)
|
||||
# lwm: low watermark; bytes remaining when sending 'unpause' frame
|
||||
# (in inuits of 0.1 MTU)
|
||||
# dwm: minimum delta between high and low watermark (in units of 100
|
||||
# Bytes)
|
||||
#
|
||||
[port "0"]
|
||||
dcb = ppp, dcbx, b2b # configure for DCB PPP and enable DCBX offload
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
dcb_app_tlv[0] = 0x8906, ethertype, 3
|
||||
dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
|
||||
|
||||
[port "1"]
|
||||
dcb = ppp, dcbx, b2b
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
dcb_app_tlv[0] = 0x8906, ethertype, 3
|
||||
dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
|
||||
|
||||
[fini]
|
||||
version = 0x1425001d
|
||||
checksum = 0x5001af51
|
||||
|
||||
# Total resources used by above allocations:
|
||||
# Virtual Interfaces: 104
|
||||
# Ingress Queues/w Free Lists and Interrupts: 526
|
||||
# Egress Queues: 702
|
||||
# MPS TCAM Entries: 336
|
||||
# MSI-X Vectors: 736
|
||||
# Virtual Functions: 64
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
583
sys/dev/cxgbe/firmware/t6fw_cfg_uwire.txt
Normal file
583
sys/dev/cxgbe/firmware/t6fw_cfg_uwire.txt
Normal file
@ -0,0 +1,583 @@
|
||||
# Chelsio T6 Factory Default configuration file.
|
||||
#
|
||||
# Copyright (C) 2014-2016 Chelsio Communications. All rights reserved.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF THIS FILE
|
||||
# WILL RESULT IN A NON-FUNCTIONAL ADAPTER AND MAY RESULT IN PHYSICAL DAMAGE
|
||||
# TO ADAPTERS.
|
||||
|
||||
|
||||
# This file provides the default, power-on configuration for 2-port T6-based
|
||||
# adapters shipped from the factory. These defaults are designed to address
|
||||
# the needs of the vast majority of Terminator customers. The basic idea is to
|
||||
# have a default configuration which allows a customer to plug a Terminator
|
||||
# adapter in and have it work regardless of OS, driver or application except in
|
||||
# the most unusual and/or demanding customer applications.
|
||||
#
|
||||
# Many of the Terminator resources which are described by this configuration
|
||||
# are finite. This requires balancing the configuration/operation needs of
|
||||
# device drivers across OSes and a large number of customer application.
|
||||
#
|
||||
# Some of the more important resources to allocate and their constaints are:
|
||||
# 1. Virtual Interfaces: 256.
|
||||
# 2. Ingress Queues with Free Lists: 1024.
|
||||
# 3. Egress Queues: 128K.
|
||||
# 4. MSI-X Vectors: 1088.
|
||||
# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination
|
||||
# address matching on Ingress Packets.
|
||||
#
|
||||
# Some of the important OS/Driver resource needs are:
|
||||
# 6. Some OS Drivers will manage all resources through a single Physical
|
||||
# Function (currently PF4 but it could be any Physical Function).
|
||||
# 7. Some OS Drivers will manage different ports and functions (NIC,
|
||||
# storage, etc.) on different Physical Functions. For example, NIC
|
||||
# functions for ports 0-1 on PF0-1, FCoE on PF4, iSCSI on PF5, etc.
|
||||
#
|
||||
# Some of the customer application needs which need to be accommodated:
|
||||
# 8. Some customers will want to support large CPU count systems with
|
||||
# good scaling. Thus, we'll need to accommodate a number of
|
||||
# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs
|
||||
# to be involved per port and per application function. For example,
|
||||
# in the case where all ports and application functions will be
|
||||
# managed via a single Unified PF and we want to accommodate scaling up
|
||||
# to 8 CPUs, we would want:
|
||||
#
|
||||
# 2 ports *
|
||||
# 3 application functions (NIC, FCoE, iSCSI) per port *
|
||||
# 16 Ingress Queue/MSI-X Vectors per application function
|
||||
#
|
||||
# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF.
|
||||
# (Plus a few for Firmware Event Queues, etc.)
|
||||
#
|
||||
# 9. Some customers will want to use PCI-E SR-IOV Capability to allow Virtual
|
||||
# Machines to directly access T6 functionality via SR-IOV Virtual Functions
|
||||
# and "PCI Device Passthrough" -- this is especially true for the NIC
|
||||
# application functionality.
|
||||
#
|
||||
|
||||
|
||||
# Global configuration settings.
|
||||
#
|
||||
[global]
|
||||
rss_glb_config_mode = basicvirtual
|
||||
rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp
|
||||
|
||||
# PL_TIMEOUT register
|
||||
pl_timeout_value = 200 # the timeout value in units of us
|
||||
|
||||
# The following Scatter Gather Engine (SGE) settings assume a 4KB Host
|
||||
# Page Size and a 64B L1 Cache Line Size. It programs the
|
||||
# EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2.
|
||||
# If a Master PF Driver finds itself on a machine with different
|
||||
# parameters, then the Master PF Driver is responsible for initializing
|
||||
# these parameters to appropriate values.
|
||||
#
|
||||
# Notes:
|
||||
# 1. The Free List Buffer Sizes below are raw and the firmware will
|
||||
# round them up to the Ingress Padding Boundary.
|
||||
# 2. The SGE Timer Values below are expressed below in microseconds.
|
||||
# The firmware will convert these values to Core Clock Ticks when
|
||||
# it processes the configuration parameters.
|
||||
#
|
||||
reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL
|
||||
reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE
|
||||
reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD
|
||||
reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0
|
||||
reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1
|
||||
reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2
|
||||
reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3
|
||||
reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4
|
||||
reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5
|
||||
reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6
|
||||
reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7
|
||||
reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8
|
||||
reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS
|
||||
reg[0x10a8] = 0x402000/0x402000 # SGE_DOORBELL_CONTROL
|
||||
sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs
|
||||
reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
|
||||
|
||||
# enable TP_OUT_CONFIG.IPIDSPLITMODE
|
||||
reg[0x7d04] = 0x00010000/0x00010000
|
||||
|
||||
reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
|
||||
|
||||
#Tick granularities in kbps
|
||||
tsch_ticks = 100000, 10000, 1000, 10
|
||||
|
||||
# TP_VLAN_PRI_MAP to select filter tuples and enable ServerSram
|
||||
# filter control: compact, fcoemask
|
||||
# server sram : srvrsram
|
||||
# filter tuples : fragmentation, mpshittype, macmatch, ethertype,
|
||||
# protocol, tos, vlan, vnic_id, port, fcoe
|
||||
# valid filterModes are described the Terminator 5 Data Book
|
||||
filterMode = fcoemask, srvrsram, fragmentation, mpshittype, protocol, vlan, port, fcoe
|
||||
|
||||
# filter tuples enforced in LE active region (equal to or subset of filterMode)
|
||||
filterMask = protocol, fcoe
|
||||
|
||||
# Percentage of dynamic memory (in either the EDRAM or external MEM)
|
||||
# to use for TP RX payload
|
||||
tp_pmrx = 30
|
||||
|
||||
# TP RX payload page size
|
||||
tp_pmrx_pagesize = 64K
|
||||
|
||||
# TP number of RX channels
|
||||
tp_nrxch = 0 # 0 (auto) = 1
|
||||
|
||||
# Percentage of dynamic memory (in either the EDRAM or external MEM)
|
||||
# to use for TP TX payload
|
||||
tp_pmtx = 50
|
||||
|
||||
# TP TX payload page size
|
||||
tp_pmtx_pagesize = 64K
|
||||
|
||||
# TP number of TX channels
|
||||
tp_ntxch = 0 # 0 (auto) = equal number of ports
|
||||
|
||||
# TP OFLD MTUs
|
||||
tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600
|
||||
|
||||
# enable TP_OUT_CONFIG.IPIDSPLITMODE and CRXPKTENC
|
||||
reg[0x7d04] = 0x00010008/0x00010008
|
||||
|
||||
# TP_GLOBAL_CONFIG
|
||||
reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
|
||||
|
||||
# TP_PC_CONFIG
|
||||
reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
|
||||
|
||||
# TP_PARA_REG0
|
||||
reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
|
||||
|
||||
# LE_DB_CONFIG
|
||||
reg[0x19c04] = 0x00000000/0x00440000 # LE Server SRAM disabled
|
||||
# LE IPv4 compression disabled
|
||||
# LE_DB_HASH_CONFIG
|
||||
reg[0x19c28] = 0x00800000/0x01f00000 # LE Hash bucket size 8,
|
||||
|
||||
# ULP_TX_CONFIG
|
||||
reg[0x8dc0] = 0x00000104/0x00000104 # Enable ITT on PI err
|
||||
# Enable more error msg for ...
|
||||
# TPT error.
|
||||
|
||||
# ULP_RX_MISC_FEATURE_ENABLE
|
||||
#reg[0x1925c] = 0x01003400/0x01003400 # iscsi tag pi bit
|
||||
# Enable offset decrement after ...
|
||||
# PI extraction and before DDP
|
||||
# ulp insert pi source info in DIF
|
||||
# iscsi_eff_offset_en
|
||||
|
||||
#Enable iscsi completion moderation feature
|
||||
reg[0x1925c] = 0x000041c0/0x000031c0 # Enable offset decrement after
|
||||
# PI extraction and before DDP.
|
||||
# ulp insert pi source info in
|
||||
# DIF.
|
||||
# Enable iscsi hdr cmd mode.
|
||||
# iscsi force cmd mode.
|
||||
# Enable iscsi cmp mode.
|
||||
# MC configuration
|
||||
#mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC
|
||||
|
||||
# Some "definitions" to make the rest of this a bit more readable. We support
|
||||
# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets"
|
||||
# per function per port ...
|
||||
#
|
||||
# NMSIX = 1088 # available MSI-X Vectors
|
||||
# NVI = 256 # available Virtual Interfaces
|
||||
# NMPSTCAM = 336 # MPS TCAM entries
|
||||
#
|
||||
# NPORTS = 2 # ports
|
||||
# NCPUS = 16 # CPUs we want to support scalably
|
||||
# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI)
|
||||
|
||||
# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified
|
||||
# PF" which many OS Drivers will use to manage most or all functions.
|
||||
#
|
||||
# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can
|
||||
# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue
|
||||
# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue
|
||||
# will be specified as the "Ingress Queue Asynchronous Destination Index."
|
||||
# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less
|
||||
# than or equal to the number of Ingress Queues ...
|
||||
#
|
||||
# NVI_NIC = 4 # NIC access to NPORTS
|
||||
# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists
|
||||
# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues
|
||||
# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX)
|
||||
# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4)
|
||||
# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_OFLD = 0 # Offload uses NIC function to access ports
|
||||
# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists
|
||||
# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues
|
||||
# NEQ_OFLD = 16 # Offload Egress Queues (FL)
|
||||
# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's)
|
||||
# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_RDMA = 0 # RDMA uses NIC function to access ports
|
||||
# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists
|
||||
# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues
|
||||
# NEQ_RDMA = 4 # RDMA Egress Queues (FL)
|
||||
# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's)
|
||||
# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NEQ_WD = 128 # Wire Direct TX Queues and FLs
|
||||
# NETHCTRL_WD = 64 # Wire Direct TX Queues
|
||||
# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists
|
||||
#
|
||||
# NVI_ISCSI = 4 # ISCSI access to NPORTS
|
||||
# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists
|
||||
# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues
|
||||
# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL)
|
||||
# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS)
|
||||
# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ)
|
||||
#
|
||||
# NVI_FCOE = 4 # FCOE access to NPORTS
|
||||
# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists
|
||||
# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues
|
||||
# NEQ_FCOE = 66 # FCOE Egress Queues (FL)
|
||||
# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS)
|
||||
# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ)
|
||||
|
||||
# Two extra Ingress Queues per function for Firmware Events and Forwarded
|
||||
# Interrupts, and two extra interrupts per function for Firmware Events (or a
|
||||
# Forwarded Interrupt Queue) and General Interrupts per function.
|
||||
#
|
||||
# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and
|
||||
# # Forwarded Interrupts
|
||||
# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and
|
||||
# # General Interrupts
|
||||
|
||||
# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have
|
||||
# their interrupts forwarded to another set of Forwarded Interrupt Queues.
|
||||
#
|
||||
# NVI_HYPERV = 16 # VMs we want to support
|
||||
# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM
|
||||
# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues
|
||||
# NEQ_HYPERV = 32 # VIQs Free Lists
|
||||
# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV)
|
||||
# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues
|
||||
|
||||
# Adding all of the above Unified PF resource needs together: (NIC + OFLD +
|
||||
# RDMA + ISCSI + FCOE + EXTRA + HYPERV)
|
||||
#
|
||||
# NVI_UNIFIED = 28
|
||||
# NFLIQ_UNIFIED = 106
|
||||
# NETHCTRL_UNIFIED = 32
|
||||
# NEQ_UNIFIED = 124
|
||||
# NMPSTCAM_UNIFIED = 40
|
||||
#
|
||||
# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round
|
||||
# that up to 128 to make sure the Unified PF doesn't run out of resources.
|
||||
#
|
||||
# NMSIX_UNIFIED = 128
|
||||
#
|
||||
# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors
|
||||
# which is 34 but they're probably safe with 32.
|
||||
#
|
||||
# NMSIX_STORAGE = 32
|
||||
|
||||
# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions
|
||||
# associated with it. Thus, the MSI-X Vector allocations we give to the
|
||||
# UnifiedPF aren't inherited by any Virtual Functions. As a result we can
|
||||
# provision many more Virtual Functions than we can if the UnifiedPF were
|
||||
# one of PF0-3.
|
||||
#
|
||||
|
||||
# All of the below PCI-E parameters are actually stored in various *_init.txt
|
||||
# files. We include them below essentially as comments.
|
||||
#
|
||||
# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated
|
||||
# ports 0-3.
|
||||
#
|
||||
# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above.
|
||||
#
|
||||
# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI
|
||||
# storage applications across all four possible ports.
|
||||
#
|
||||
# Additionally, since the UnifiedPF isn't one of the per-port Physical
|
||||
# Functions, we give the UnifiedPF and the PF0-3 Physical Functions
|
||||
# different PCI Device IDs which will allow Unified and Per-Port Drivers
|
||||
# to directly select the type of Physical Function to which they wish to be
|
||||
# attached.
|
||||
#
|
||||
# Note that the actual values used for the PCI-E Intelectual Property will be
|
||||
# 1 less than those below since that's the way it "counts" things. For
|
||||
# readability, we use the number we actually mean ...
|
||||
#
|
||||
# PF0_INT = 8 # NCPUS
|
||||
# PF1_INT = 8 # NCPUS
|
||||
# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT
|
||||
#
|
||||
# PF4_INT = 128 # NMSIX_UNIFIED
|
||||
# PF5_INT = 32 # NMSIX_STORAGE
|
||||
# PF6_INT = 32 # NMSIX_STORAGE
|
||||
# PF7_INT = 0 # Nothing Assigned
|
||||
# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT
|
||||
#
|
||||
# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT
|
||||
#
|
||||
# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries)
|
||||
# but we'll lower that to 16 to make our total 64 and a nice power of 2 ...
|
||||
#
|
||||
# NVF = 16
|
||||
|
||||
|
||||
# For those OSes which manage different ports on different PFs, we need
|
||||
# only enough resources to support a single port's NIC application functions
|
||||
# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue
|
||||
# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be
|
||||
# managed on the "storage PFs" (see below).
|
||||
#
|
||||
[function "0"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x1 # access to only one port
|
||||
|
||||
|
||||
[function "1"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x2 # access to only one port
|
||||
|
||||
[function "2"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x4 # access to only one port
|
||||
|
||||
[function "3"]
|
||||
nvf = 16 # NVF on this function
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 8 # NCPUS "Queue Sets"
|
||||
nethctrl = 8 # NCPUS "Queue Sets"
|
||||
neq = 16 # niqflint + nethctrl Egress Queues
|
||||
nexactf = 8 # number of exact MPSTCAM MAC filters
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x8 # access to only one port
|
||||
|
||||
|
||||
# Some OS Drivers manage all application functions for all ports via PF4.
|
||||
# Thus we need to provide a large number of resources here. For Egress
|
||||
# Queues we need to account for both TX Queues as well as Free List Queues
|
||||
# (because the host is responsible for producing Free List Buffers for the
|
||||
# hardware to consume).
|
||||
#
|
||||
[function "4"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 28 # NVI_UNIFIED
|
||||
niqflint = 202 # NFLIQ_UNIFIED + NLFIQ_WD + NFLIQ_CRYPTO (32)
|
||||
nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD
|
||||
neq = 256 # NEQ_UNIFIED + NEQ_WD
|
||||
nqpcq = 12288
|
||||
nexactf = 40 # NMPSTCAM_UNIFIED
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nethofld = 1024 # number of user mode ethernet flow contexts
|
||||
ncrypto_lookaside = 16 # Number of lookaside flow contexts
|
||||
nclip = 320 # number of clip region entries
|
||||
nfilter = 496 # number of filter region entries
|
||||
nserver = 496 # number of server region entries
|
||||
nhash = 12288 # number of hash region entries
|
||||
nhpfilter = 0 # number of high priority filter region entries
|
||||
protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif, tlskeys, crypto_lookaside
|
||||
tp_l2t = 3072
|
||||
tp_ddp = 2
|
||||
tp_ddp_iscsi = 2
|
||||
tp_tls_key = 3
|
||||
tp_stag = 2
|
||||
tp_pbl = 5
|
||||
tp_rq = 7
|
||||
tp_srq = 128
|
||||
|
||||
# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may
|
||||
# need to have Virtual Interfaces on each of the four ports with up to NCPUS
|
||||
# "Queue Sets" each.
|
||||
#
|
||||
[function "5"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NPORTS
|
||||
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
|
||||
nethctrl = 32 # NPORTS*NCPUS
|
||||
neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX)
|
||||
nexactf = 16 # (NPORTS *(no of snmc grp + 1 hw mac) + 1 anmc grp)) rounded to 16.
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nserver = 16
|
||||
nhash = 2048
|
||||
tp_l2t = 1020
|
||||
nclip = 64
|
||||
protocol = iscsi_initiator_fofld
|
||||
tp_ddp_iscsi = 2
|
||||
iscsi_ntask = 2048
|
||||
iscsi_nsess = 2048
|
||||
iscsi_nconn_per_session = 1
|
||||
iscsi_ninitiator_instance = 64
|
||||
|
||||
|
||||
[function "6"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NPORTS
|
||||
niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA
|
||||
nethctrl = 32 # NPORTS*NCPUS
|
||||
neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA)
|
||||
nexactf = 32 # NPORTS + adding 28 exact entries for FCoE
|
||||
# which is OK since < MIN(SUM PF0..3, PF4)
|
||||
# and we never load PF0..3 and PF4 concurrently
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nhash = 2048
|
||||
tp_l2t = 4
|
||||
protocol = fcoe_initiator
|
||||
tp_ddp = 2
|
||||
fcoe_nfcf = 16
|
||||
fcoe_nvnp = 32
|
||||
fcoe_nssn = 1024
|
||||
|
||||
|
||||
# The following function, 1023, is not an actual PCIE function but is used to
|
||||
# configure and reserve firmware internal resources that come from the global
|
||||
# resource pool.
|
||||
#
|
||||
[function "1023"]
|
||||
wx_caps = all # write/execute permissions for all commands
|
||||
r_caps = all # read permissions for all commands
|
||||
nvi = 4 # NVI_UNIFIED
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nexactf = 8 # NPORTS + DCBX +
|
||||
nfilter = 16 # number of filter region entries
|
||||
|
||||
|
||||
# For Virtual functions, we only allow NIC functionality and we only allow
|
||||
# access to one port (1 << PF). Note that because of limitations in the
|
||||
# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL
|
||||
# and GTS registers, the number of Ingress and Egress Queues must be a power
|
||||
# of 2.
|
||||
#
|
||||
[function "0/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x1 # access to only one port ...
|
||||
|
||||
|
||||
[function "1/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x2 # access to only one port ...
|
||||
|
||||
[function "2/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x1 # access to only one port ...
|
||||
|
||||
|
||||
[function "3/*"] # NVF
|
||||
wx_caps = 0x82 # DMAQ | VF
|
||||
r_caps = 0x86 # DMAQ | VF | PORT
|
||||
nvi = 1 # 1 port
|
||||
niqflint = 4 # 2 "Queue Sets" + NXIQ
|
||||
nethctrl = 2 # 2 "Queue Sets"
|
||||
neq = 4 # 2 "Queue Sets" * 2
|
||||
nexactf = 4
|
||||
cmask = all # access to all channels
|
||||
pmask = 0x2 # access to only one port ...
|
||||
|
||||
# MPS features a 196608 bytes ingress buffer that is used for ingress buffering
|
||||
# for packets from the wire as well as the loopback path of the L2 switch. The
|
||||
# folling params control how the buffer memory is distributed and the L2 flow
|
||||
# control settings:
|
||||
#
|
||||
# bg_mem: %-age of mem to use for port/buffer group
|
||||
# lpbk_mem: %-age of port/bg mem to use for loopback
|
||||
# hwm: high watermark; bytes available when starting to send pause
|
||||
# frames (in units of 0.1 MTU)
|
||||
# lwm: low watermark; bytes remaining when sending 'unpause' frame
|
||||
# (in inuits of 0.1 MTU)
|
||||
# dwm: minimum delta between high and low watermark (in units of 100
|
||||
# Bytes)
|
||||
#
|
||||
[port "0"]
|
||||
dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
|
||||
#bg_mem = 25
|
||||
#lpbk_mem = 25
|
||||
hwm = 60
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
dcb_app_tlv[0] = 0x8906, ethertype, 3
|
||||
dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
aec_retry_cnt = 4
|
||||
|
||||
|
||||
[port "1"]
|
||||
dcb = ppp, dcbx
|
||||
#bg_mem = 25
|
||||
#lpbk_mem = 25
|
||||
hwm = 60
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
dcb_app_tlv[0] = 0x8906, ethertype, 3
|
||||
dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
aec_retry_cnt = 4
|
||||
|
||||
|
||||
[fini]
|
||||
version = 0x01000023
|
||||
checksum = 0x683208a2
|
||||
|
||||
# Total resources used by above allocations:
|
||||
# Virtual Interfaces: 104
|
||||
# Ingress Queues/w Free Lists and Interrupts: 526
|
||||
# Egress Queues: 702
|
||||
# MPS TCAM Entries: 336
|
||||
# MSI-X Vectors: 736
|
||||
# Virtual Functions: 64
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
44
sys/dev/cxgbe/if_cc.c
Normal file
44
sys/dev/cxgbe/if_cc.c
Normal file
@ -0,0 +1,44 @@
|
||||
/*-
|
||||
* Copyright (c) 2016 Chelsio Communications, Inc.
|
||||
* All rights reserved.
|
||||
* Written by: Navdeep Parhar <np@FreeBSD.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
|
||||
static int
|
||||
mod_event(module_t mod, int cmd, void *arg)
|
||||
{
|
||||
|
||||
return (0);
|
||||
}
|
||||
static moduledata_t if_cc_mod = {"if_cc", mod_event};
|
||||
DECLARE_MODULE(if_cc, if_cc_mod, SI_SUB_EXEC, SI_ORDER_ANY);
|
||||
MODULE_VERSION(if_cc, 1);
|
||||
MODULE_DEPEND(if_cc, cc, 1, 1, 1);
|
||||
44
sys/dev/cxgbe/if_ccv.c
Normal file
44
sys/dev/cxgbe/if_ccv.c
Normal file
@ -0,0 +1,44 @@
|
||||
/*-
|
||||
* Copyright (c) 2016 Chelsio Communications, Inc.
|
||||
* All rights reserved.
|
||||
* Written by: Navdeep Parhar <np@FreeBSD.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
|
||||
static int
|
||||
mod_event(module_t mod, int cmd, void *arg)
|
||||
{
|
||||
|
||||
return (0);
|
||||
}
|
||||
static moduledata_t if_ccv_mod = {"if_ccv", mod_event};
|
||||
DECLARE_MODULE(if_ccv, if_ccv_mod, SI_SUB_EXEC, SI_ORDER_ANY);
|
||||
MODULE_VERSION(if_ccv, 1);
|
||||
MODULE_DEPEND(if_ccv, ccv, 1, 1, 1);
|
||||
@ -90,6 +90,12 @@ struct {
|
||||
{0x500f, "Chelsio Amsterdam"},
|
||||
{0x5013, "Chelsio T580-CHR"},
|
||||
#endif
|
||||
}, t6iov_pciids[] = {
|
||||
{0x6001, "Chelsio T6225-CR"}, /* 2 x 10/25G */
|
||||
{0x6002, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
|
||||
{0x6007, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
|
||||
{0x6008, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
|
||||
{0x600d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
|
||||
};
|
||||
|
||||
static int t4iov_attach_child(device_t dev);
|
||||
@ -128,6 +134,23 @@ t5iov_probe(device_t dev)
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
static int
|
||||
t6iov_probe(device_t dev)
|
||||
{
|
||||
uint16_t d;
|
||||
size_t i;
|
||||
|
||||
d = pci_get_device(dev);
|
||||
for (i = 0; i < nitems(t6iov_pciids); i++) {
|
||||
if (d == t6iov_pciids[i].device) {
|
||||
device_set_desc(dev, t6iov_pciids[i].desc);
|
||||
device_quiet(dev);
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
}
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
static int
|
||||
t4iov_attach(device_t dev)
|
||||
{
|
||||
@ -288,10 +311,36 @@ static driver_t t5iov_driver = {
|
||||
sizeof(struct t4iov_softc)
|
||||
};
|
||||
|
||||
static devclass_t t4iov_devclass, t5iov_devclass;
|
||||
static device_method_t t6iov_methods[] = {
|
||||
DEVMETHOD(device_probe, t6iov_probe),
|
||||
DEVMETHOD(device_attach, t4iov_attach),
|
||||
DEVMETHOD(device_detach, t4iov_detach),
|
||||
|
||||
#ifdef PCI_IOV
|
||||
DEVMETHOD(pci_iov_init, t4iov_iov_init),
|
||||
DEVMETHOD(pci_iov_uninit, t4iov_iov_uninit),
|
||||
DEVMETHOD(pci_iov_add_vf, t4iov_add_vf),
|
||||
#endif
|
||||
|
||||
DEVMETHOD(t4_attach_child, t4iov_attach_child),
|
||||
DEVMETHOD(t4_detach_child, t4iov_detach_child),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t t6iov_driver = {
|
||||
"t6iov",
|
||||
t6iov_methods,
|
||||
sizeof(struct t4iov_softc)
|
||||
};
|
||||
|
||||
static devclass_t t4iov_devclass, t5iov_devclass, t6iov_devclass;
|
||||
|
||||
DRIVER_MODULE(t4iov, pci, t4iov_driver, t4iov_devclass, 0, 0);
|
||||
MODULE_VERSION(t4iov, 1);
|
||||
|
||||
DRIVER_MODULE(t5iov, pci, t5iov_driver, t5iov_devclass, 0, 0);
|
||||
MODULE_VERSION(t5iov, 1);
|
||||
|
||||
DRIVER_MODULE(t6iov, pci, t6iov_driver, t6iov_devclass, 0, 0);
|
||||
MODULE_VERSION(t6iov, 1);
|
||||
|
||||
@ -174,6 +174,39 @@ static driver_t vcxl_driver = {
|
||||
sizeof(struct vi_info)
|
||||
};
|
||||
|
||||
/* T6 bus driver interface */
|
||||
static int t6_probe(device_t);
|
||||
static device_method_t t6_methods[] = {
|
||||
DEVMETHOD(device_probe, t6_probe),
|
||||
DEVMETHOD(device_attach, t4_attach),
|
||||
DEVMETHOD(device_detach, t4_detach),
|
||||
|
||||
DEVMETHOD(t4_is_main_ready, t4_ready),
|
||||
DEVMETHOD(t4_read_port_device, t4_read_port_device),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
static driver_t t6_driver = {
|
||||
"t6nex",
|
||||
t6_methods,
|
||||
sizeof(struct adapter)
|
||||
};
|
||||
|
||||
|
||||
/* T6 port (cc) interface */
|
||||
static driver_t cc_driver = {
|
||||
"cc",
|
||||
cxgbe_methods,
|
||||
sizeof(struct port_info)
|
||||
};
|
||||
|
||||
/* T6 VI (vcc) interface */
|
||||
static driver_t vcc_driver = {
|
||||
"vcc",
|
||||
vcxgbe_methods,
|
||||
sizeof(struct vi_info)
|
||||
};
|
||||
|
||||
/* ifnet + media interface */
|
||||
static void cxgbe_init(void *);
|
||||
static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
|
||||
@ -355,8 +388,8 @@ TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
|
||||
static int t4_rdmacaps_allowed = -1;
|
||||
TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
|
||||
|
||||
static int t4_tlscaps_allowed = 0;
|
||||
TUNABLE_INT("hw.cxgbe.tlscaps_allowed", &t4_tlscaps_allowed);
|
||||
static int t4_cryptocaps_allowed = 0;
|
||||
TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed);
|
||||
|
||||
static int t4_iscsicaps_allowed = -1;
|
||||
TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
|
||||
@ -567,6 +600,14 @@ struct {
|
||||
{0x540f, "Chelsio Amsterdam"},
|
||||
{0x5413, "Chelsio T580-CHR"},
|
||||
#endif
|
||||
}, t6_pciids[] = {
|
||||
{0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
|
||||
{0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
|
||||
{0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
|
||||
{0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
|
||||
{0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
|
||||
{0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
|
||||
{0x6410, "Chelsio T62100-DBG"}, /* 2 x 40/50/100G, debug */
|
||||
};
|
||||
|
||||
#ifdef TCP_OFFLOAD
|
||||
@ -629,6 +670,26 @@ t5_probe(device_t dev)
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
static int
|
||||
t6_probe(device_t dev)
|
||||
{
|
||||
int i;
|
||||
uint16_t v = pci_get_vendor(dev);
|
||||
uint16_t d = pci_get_device(dev);
|
||||
|
||||
if (v != PCI_VENDOR_ID_CHELSIO)
|
||||
return (ENXIO);
|
||||
|
||||
for (i = 0; i < nitems(t6_pciids); i++) {
|
||||
if (d == t6_pciids[i].device) {
|
||||
device_set_desc(dev, t6_pciids[i].desc);
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
}
|
||||
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
static void
|
||||
t5_attribute_workaround(device_t dev)
|
||||
{
|
||||
@ -656,6 +717,45 @@ t5_attribute_workaround(device_t dev)
|
||||
device_get_nameunit(root_port));
|
||||
}
|
||||
|
||||
static const struct devnames devnames[] = {
|
||||
{
|
||||
.nexus_name = "t4nex",
|
||||
.ifnet_name = "cxgbe",
|
||||
.vi_ifnet_name = "vcxgbe",
|
||||
.pf03_drv_name = "t4iov",
|
||||
.vf_nexus_name = "t4vf",
|
||||
.vf_ifnet_name = "cxgbev"
|
||||
}, {
|
||||
.nexus_name = "t5nex",
|
||||
.ifnet_name = "cxl",
|
||||
.vi_ifnet_name = "vcxl",
|
||||
.pf03_drv_name = "t5iov",
|
||||
.vf_nexus_name = "t5vf",
|
||||
.vf_ifnet_name = "cxlv"
|
||||
}, {
|
||||
.nexus_name = "t6nex",
|
||||
.ifnet_name = "cc",
|
||||
.vi_ifnet_name = "vcc",
|
||||
.pf03_drv_name = "t6iov",
|
||||
.vf_nexus_name = "t6vf",
|
||||
.vf_ifnet_name = "ccv"
|
||||
}
|
||||
};
|
||||
|
||||
void
|
||||
t4_init_devnames(struct adapter *sc)
|
||||
{
|
||||
int id;
|
||||
|
||||
id = chip_id(sc);
|
||||
if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
|
||||
sc->names = &devnames[id - CHELSIO_T4];
|
||||
else {
|
||||
device_printf(sc->dev, "chip id %d is not supported.\n", id);
|
||||
sc->names = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
t4_attach(device_t dev)
|
||||
{
|
||||
@ -713,15 +813,6 @@ t4_attach(device_t dev)
|
||||
if (rc != 0)
|
||||
goto done; /* error message displayed already */
|
||||
|
||||
/*
|
||||
* This is the real PF# to which we're attaching. Works from within PCI
|
||||
* passthrough environments too, where pci_get_function() could return a
|
||||
* different PF# depending on the passthrough configuration. We need to
|
||||
* use the real PF# in all our communication with the firmware.
|
||||
*/
|
||||
sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI));
|
||||
sc->mbox = sc->pf;
|
||||
|
||||
memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
|
||||
|
||||
/* Prepare the adapter for operation. */
|
||||
@ -733,6 +824,22 @@ t4_attach(device_t dev)
|
||||
goto done;
|
||||
}
|
||||
|
||||
/*
|
||||
* This is the real PF# to which we're attaching. Works from within PCI
|
||||
* passthrough environments too, where pci_get_function() could return a
|
||||
* different PF# depending on the passthrough configuration. We need to
|
||||
* use the real PF# in all our communication with the firmware.
|
||||
*/
|
||||
j = t4_read_reg(sc, A_PL_WHOAMI);
|
||||
sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
|
||||
sc->mbox = sc->pf;
|
||||
|
||||
t4_init_devnames(sc);
|
||||
if (sc->names == NULL) {
|
||||
rc = ENOTSUP;
|
||||
goto done; /* error message displayed already */
|
||||
}
|
||||
|
||||
/*
|
||||
* Do this really early, with the memory windows set up even before the
|
||||
* character device. The userland tool's register i/o and mem read
|
||||
@ -864,7 +971,7 @@ t4_attach(device_t dev)
|
||||
pi->tc = malloc(sizeof(struct tx_sched_class) *
|
||||
sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
|
||||
|
||||
if (is_10G_port(pi) || is_40G_port(pi)) {
|
||||
if (port_top_speed(pi) >= 10) {
|
||||
n10g++;
|
||||
} else {
|
||||
n1g++;
|
||||
@ -872,7 +979,7 @@ t4_attach(device_t dev)
|
||||
|
||||
pi->linkdnrc = -1;
|
||||
|
||||
pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1);
|
||||
pi->dev = device_add_child(dev, sc->names->ifnet_name, -1);
|
||||
if (pi->dev == NULL) {
|
||||
device_printf(dev,
|
||||
"failed to add device for port %d.\n", i);
|
||||
@ -980,7 +1087,7 @@ t4_attach(device_t dev)
|
||||
|
||||
vi->first_rxq = rqidx;
|
||||
vi->first_txq = tqidx;
|
||||
if (is_10G_port(pi) || is_40G_port(pi)) {
|
||||
if (port_top_speed(pi) >= 10) {
|
||||
vi->tmr_idx = t4_tmr_idx_10g;
|
||||
vi->pktc_idx = t4_pktc_idx_10g;
|
||||
vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
|
||||
@ -1004,7 +1111,7 @@ t4_attach(device_t dev)
|
||||
#ifdef TCP_OFFLOAD
|
||||
vi->first_ofld_rxq = ofld_rqidx;
|
||||
vi->first_ofld_txq = ofld_tqidx;
|
||||
if (is_10G_port(pi) || is_40G_port(pi)) {
|
||||
if (port_top_speed(pi) >= 10) {
|
||||
vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
|
||||
vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
|
||||
iaq.nofldrxq_vi;
|
||||
@ -1355,6 +1462,7 @@ static int
|
||||
cxgbe_attach(device_t dev)
|
||||
{
|
||||
struct port_info *pi = device_get_softc(dev);
|
||||
struct adapter *sc = pi->adapter;
|
||||
struct vi_info *vi;
|
||||
int i, rc;
|
||||
|
||||
@ -1367,8 +1475,7 @@ cxgbe_attach(device_t dev)
|
||||
for_each_vi(pi, i, vi) {
|
||||
if (i == 0)
|
||||
continue;
|
||||
vi->dev = device_add_child(dev, is_t4(pi->adapter) ?
|
||||
"vcxgbe" : "vcxl", -1);
|
||||
vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
|
||||
if (vi->dev == NULL) {
|
||||
device_printf(dev, "failed to add VI %d\n", i);
|
||||
continue;
|
||||
@ -1631,6 +1738,7 @@ fail:
|
||||
|
||||
case SIOCSIFMEDIA:
|
||||
case SIOCGIFMEDIA:
|
||||
case SIOCGIFXMEDIA:
|
||||
ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
|
||||
break;
|
||||
|
||||
@ -1925,6 +2033,10 @@ vcxgbe_attach(device_t dev)
|
||||
return (-rc);
|
||||
}
|
||||
vi->viid = rc;
|
||||
if (chip_id(sc) <= CHELSIO_T5)
|
||||
vi->smt_idx = (rc & 0x7f) << 1;
|
||||
else
|
||||
vi->smt_idx = (rc & 0x7f);
|
||||
|
||||
param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
|
||||
V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
|
||||
@ -2027,11 +2139,11 @@ t4_map_bar_2(struct adapter *sc)
|
||||
}
|
||||
sc->udbs_base = rman_get_virtual(sc->udbs_res);
|
||||
|
||||
if (is_t5(sc)) {
|
||||
if (chip_id(sc) >= CHELSIO_T5) {
|
||||
setbit(&sc->doorbells, DOORBELL_UDB);
|
||||
#if defined(__i386__) || defined(__amd64__)
|
||||
if (t5_write_combine) {
|
||||
int rc;
|
||||
int rc, mode;
|
||||
|
||||
/*
|
||||
* Enable write combining on BAR2. This is the
|
||||
@ -2054,8 +2166,9 @@ t4_map_bar_2(struct adapter *sc)
|
||||
rc);
|
||||
}
|
||||
|
||||
mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
|
||||
t4_write_reg(sc, A_SGE_STAT_CFG,
|
||||
V_STATSOURCE_T5(7) | V_STATMODE(0));
|
||||
V_STATSOURCE_T5(7) | mode);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@ -2685,6 +2798,22 @@ struct fw_info {
|
||||
.intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
|
||||
.intfver_fcoe = FW_INTFVER(T5, FCOE),
|
||||
},
|
||||
}, {
|
||||
.chip = CHELSIO_T6,
|
||||
.kld_name = "t6fw_cfg",
|
||||
.fw_mod_name = "t6fw",
|
||||
.fw_hdr = {
|
||||
.chip = FW_HDR_CHIP_T6,
|
||||
.fw_ver = htobe32_const(FW_VERSION(T6)),
|
||||
.intfver_nic = FW_INTFVER(T6, NIC),
|
||||
.intfver_vnic = FW_INTFVER(T6, VNIC),
|
||||
.intfver_ofld = FW_INTFVER(T6, OFLD),
|
||||
.intfver_ri = FW_INTFVER(T6, RI),
|
||||
.intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
|
||||
.intfver_iscsi = FW_INTFVER(T6, ISCSI),
|
||||
.intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
|
||||
.intfver_fcoe = FW_INTFVER(T6, FCOE),
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
@ -3113,7 +3242,7 @@ use_config_on_flash:
|
||||
LIMIT_CAPS(niccaps);
|
||||
LIMIT_CAPS(toecaps);
|
||||
LIMIT_CAPS(rdmacaps);
|
||||
LIMIT_CAPS(tlscaps);
|
||||
LIMIT_CAPS(cryptocaps);
|
||||
LIMIT_CAPS(iscsicaps);
|
||||
LIMIT_CAPS(fcoecaps);
|
||||
#undef LIMIT_CAPS
|
||||
@ -3250,7 +3379,7 @@ get_params__post_init(struct adapter *sc)
|
||||
READ_CAPS(niccaps);
|
||||
READ_CAPS(toecaps);
|
||||
READ_CAPS(rdmacaps);
|
||||
READ_CAPS(tlscaps);
|
||||
READ_CAPS(cryptocaps);
|
||||
READ_CAPS(iscsicaps);
|
||||
READ_CAPS(fcoecaps);
|
||||
|
||||
@ -3459,6 +3588,39 @@ build_medialist(struct port_info *pi, struct ifmedia *media)
|
||||
}
|
||||
break;
|
||||
|
||||
case FW_PORT_TYPE_CR_QSFP:
|
||||
case FW_PORT_TYPE_CR_SFP28:
|
||||
case FW_PORT_TYPE_SFP28:
|
||||
case FW_PORT_TYPE_KR_SFP28:
|
||||
switch (pi->mod_type) {
|
||||
|
||||
case FW_PORT_MOD_TYPE_SR:
|
||||
ifmedia_add(media, m | IFM_25G_SR, 0, NULL);
|
||||
ifmedia_set(media, m | IFM_25G_SR);
|
||||
break;
|
||||
|
||||
case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
|
||||
case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
|
||||
ifmedia_add(media, m | IFM_25G_CR, 0, NULL);
|
||||
ifmedia_set(media, m | IFM_25G_CR);
|
||||
break;
|
||||
|
||||
case FW_PORT_MOD_TYPE_NONE:
|
||||
m &= ~IFM_FDX;
|
||||
ifmedia_add(media, m | IFM_NONE, 0, NULL);
|
||||
ifmedia_set(media, m | IFM_NONE);
|
||||
break;
|
||||
|
||||
default:
|
||||
device_printf(pi->dev,
|
||||
"unknown port_type (%d), mod_type (%d)\n",
|
||||
pi->port_type, pi->mod_type);
|
||||
ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
|
||||
ifmedia_set(media, m | IFM_UNKNOWN);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case FW_PORT_TYPE_QSFP:
|
||||
switch (pi->mod_type) {
|
||||
|
||||
@ -3494,6 +3656,42 @@ build_medialist(struct port_info *pi, struct ifmedia *media)
|
||||
}
|
||||
break;
|
||||
|
||||
case FW_PORT_TYPE_KR4_100G:
|
||||
case FW_PORT_TYPE_CR4_QSFP:
|
||||
switch (pi->mod_type) {
|
||||
|
||||
case FW_PORT_MOD_TYPE_LR:
|
||||
ifmedia_add(media, m | IFM_100G_LR4, 0, NULL);
|
||||
ifmedia_set(media, m | IFM_100G_LR4);
|
||||
break;
|
||||
|
||||
case FW_PORT_MOD_TYPE_SR:
|
||||
ifmedia_add(media, m | IFM_100G_SR4, 0, NULL);
|
||||
ifmedia_set(media, m | IFM_100G_SR4);
|
||||
break;
|
||||
|
||||
case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
|
||||
case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
|
||||
ifmedia_add(media, m | IFM_100G_CR4, 0, NULL);
|
||||
ifmedia_set(media, m | IFM_100G_CR4);
|
||||
break;
|
||||
|
||||
case FW_PORT_MOD_TYPE_NONE:
|
||||
m &= ~IFM_FDX;
|
||||
ifmedia_add(media, m | IFM_NONE, 0, NULL);
|
||||
ifmedia_set(media, m | IFM_NONE);
|
||||
break;
|
||||
|
||||
default:
|
||||
device_printf(pi->dev,
|
||||
"unknown port_type (%d), mod_type (%d)\n",
|
||||
pi->port_type, pi->mod_type);
|
||||
ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
|
||||
ifmedia_set(media, m | IFM_UNKNOWN);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
device_printf(pi->dev,
|
||||
"unknown port_type (%d), mod_type (%d)\n", pi->port_type,
|
||||
@ -4234,7 +4432,7 @@ vi_full_init(struct vi_info *vi)
|
||||
F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
|
||||
F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
|
||||
#endif
|
||||
rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0]);
|
||||
rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0);
|
||||
if (rc != 0) {
|
||||
if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
|
||||
goto done;
|
||||
@ -4590,7 +4788,7 @@ static char *caps_decoder[] = {
|
||||
"\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
|
||||
"\007T10DIF"
|
||||
"\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
|
||||
"\20\00KEYS", /* 7: TLS */
|
||||
"\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
|
||||
"\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
|
||||
"\004PO_INITIATOR\005PO_TARGET",
|
||||
};
|
||||
@ -4698,7 +4896,7 @@ t4_sysctls(struct adapter *sc)
|
||||
SYSCTL_CAP(toecaps, 4, "TCP offload");
|
||||
SYSCTL_CAP(rdmacaps, 5, "RDMA");
|
||||
SYSCTL_CAP(iscsicaps, 6, "iSCSI");
|
||||
SYSCTL_CAP(tlscaps, 7, "TLS");
|
||||
SYSCTL_CAP(cryptocaps, 7, "crypto");
|
||||
SYSCTL_CAP(fcoecaps, 8, "FCoE");
|
||||
#undef SYSCTL_CAP
|
||||
|
||||
@ -4874,7 +5072,7 @@ t4_sysctls(struct adapter *sc)
|
||||
CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
|
||||
sysctl_ulprx_la, "A", "ULPRX logic analyzer");
|
||||
|
||||
if (is_t5(sc)) {
|
||||
if (chip_id(sc) >= CHELSIO_T5) {
|
||||
SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
|
||||
CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
|
||||
sysctl_wcwr_stats, "A", "write combined work requests");
|
||||
@ -7018,7 +7216,12 @@ sysctl_tids(SYSCTL_HANDLER_ARGS)
|
||||
|
||||
if (t->ntids) {
|
||||
if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
|
||||
uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
|
||||
uint32_t b;
|
||||
|
||||
if (chip_id(sc) <= CHELSIO_T5)
|
||||
b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
|
||||
else
|
||||
b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
|
||||
|
||||
if (b) {
|
||||
sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
|
||||
@ -7473,6 +7676,8 @@ sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
|
||||
struct sbuf *sb;
|
||||
int rc, v;
|
||||
|
||||
MPASS(chip_id(sc) >= CHELSIO_T5);
|
||||
|
||||
rc = sysctl_wire_old_buffer(req, 0);
|
||||
if (rc != 0)
|
||||
return (rc);
|
||||
@ -7483,14 +7688,19 @@ sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
|
||||
|
||||
v = t4_read_reg(sc, A_SGE_STAT_CFG);
|
||||
if (G_STATSOURCE_T5(v) == 7) {
|
||||
if (G_STATMODE(v) == 0) {
|
||||
int mode;
|
||||
|
||||
mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
|
||||
if (mode == 0) {
|
||||
sbuf_printf(sb, "total %d, incomplete %d",
|
||||
t4_read_reg(sc, A_SGE_STAT_TOTAL),
|
||||
t4_read_reg(sc, A_SGE_STAT_MATCH));
|
||||
} else if (G_STATMODE(v) == 1) {
|
||||
} else if (mode == 1) {
|
||||
sbuf_printf(sb, "total %d, data overflow %d",
|
||||
t4_read_reg(sc, A_SGE_STAT_TOTAL),
|
||||
t4_read_reg(sc, A_SGE_STAT_MATCH));
|
||||
} else {
|
||||
sbuf_printf(sb, "unknown mode %d", mode);
|
||||
}
|
||||
}
|
||||
rc = sbuf_finish(sb);
|
||||
@ -9556,9 +9766,9 @@ done_unload:
|
||||
return (rc);
|
||||
}
|
||||
|
||||
static devclass_t t4_devclass, t5_devclass;
|
||||
static devclass_t cxgbe_devclass, cxl_devclass;
|
||||
static devclass_t vcxgbe_devclass, vcxl_devclass;
|
||||
static devclass_t t4_devclass, t5_devclass, t6_devclass;
|
||||
static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
|
||||
static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
|
||||
|
||||
DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
|
||||
MODULE_VERSION(t4nex, 1);
|
||||
@ -9567,7 +9777,6 @@ MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
|
||||
MODULE_DEPEND(t4nex, netmap, 1, 1, 1);
|
||||
#endif /* DEV_NETMAP */
|
||||
|
||||
|
||||
DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
|
||||
MODULE_VERSION(t5nex, 1);
|
||||
MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
|
||||
@ -9575,14 +9784,27 @@ MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
|
||||
MODULE_DEPEND(t5nex, netmap, 1, 1, 1);
|
||||
#endif /* DEV_NETMAP */
|
||||
|
||||
DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
|
||||
MODULE_VERSION(t6nex, 1);
|
||||
MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
|
||||
#ifdef DEV_NETMAP
|
||||
MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
|
||||
#endif /* DEV_NETMAP */
|
||||
|
||||
DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
|
||||
MODULE_VERSION(cxgbe, 1);
|
||||
|
||||
DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
|
||||
MODULE_VERSION(cxl, 1);
|
||||
|
||||
DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
|
||||
MODULE_VERSION(cc, 1);
|
||||
|
||||
DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
|
||||
MODULE_VERSION(vcxgbe, 1);
|
||||
|
||||
DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
|
||||
MODULE_VERSION(vcxl, 1);
|
||||
|
||||
DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
|
||||
MODULE_VERSION(vcc, 1);
|
||||
|
||||
@ -139,8 +139,10 @@ alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
|
||||
(fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
|
||||
(black_hole == 2 ? F_FW_IQ_CMD_FL0PACKEN : 0));
|
||||
c.fl0dcaen_to_fl0cidxfthresh =
|
||||
htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) |
|
||||
V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
|
||||
htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
|
||||
X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
|
||||
V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
|
||||
X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
|
||||
c.fl0size = htobe16(na->num_rx_desc / 8 + sp->spg_len / EQ_ESIZE);
|
||||
c.fl0addr = htobe64(nm_rxq->fl_ba);
|
||||
|
||||
@ -176,7 +178,7 @@ alloc_nm_rxq_hwq(struct vi_info *vi, struct sge_nm_rxq *nm_rxq, int cong)
|
||||
nm_rxq->fl_db_val = V_QID(nm_rxq->fl_cntxt_id) |
|
||||
sc->chip_params->sge_fl_db;
|
||||
|
||||
if (is_t5(sc) && cong >= 0) {
|
||||
if (chip_id(sc) >= CHELSIO_T5 && cong >= 0) {
|
||||
uint32_t param, val;
|
||||
|
||||
param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
|
||||
@ -881,19 +883,23 @@ cxgbe_nm_detach(struct vi_info *vi)
|
||||
netmap_detach(vi->ifp);
|
||||
}
|
||||
|
||||
static void
|
||||
handle_nm_fw6_msg(struct adapter *sc, struct ifnet *ifp,
|
||||
const struct cpl_fw6_msg *cpl)
|
||||
static inline const void *
|
||||
unwrap_nm_fw6_msg(const struct cpl_fw6_msg *cpl)
|
||||
{
|
||||
|
||||
MPASS(cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL);
|
||||
|
||||
/* data[0] is RSS header */
|
||||
return (&cpl->data[1]);
|
||||
}
|
||||
|
||||
static void
|
||||
handle_nm_sge_egr_update(struct adapter *sc, struct ifnet *ifp,
|
||||
const struct cpl_sge_egr_update *egr)
|
||||
{
|
||||
const struct cpl_sge_egr_update *egr;
|
||||
uint32_t oq;
|
||||
struct sge_nm_txq *nm_txq;
|
||||
|
||||
if (cpl->type != FW_TYPE_RSSCPL && cpl->type != FW6_TYPE_RSSCPL)
|
||||
panic("%s: FW_TYPE 0x%x on nm_rxq.", __func__, cpl->type);
|
||||
|
||||
/* data[0] is RSS header */
|
||||
egr = (const void *)&cpl->data[1];
|
||||
oq = be32toh(egr->opcode_qid);
|
||||
MPASS(G_CPL_OPCODE(oq) == CPL_SGE_EGR_UPDATE);
|
||||
nm_txq = (void *)sc->sge.eqmap[G_EGR_QID(oq) - sc->sge.eq_start];
|
||||
@ -912,6 +918,7 @@ t4_nm_intr(void *arg)
|
||||
struct netmap_kring *kring = &na->rx_rings[nm_rxq->nid];
|
||||
struct netmap_ring *ring = kring->ring;
|
||||
struct iq_desc *d = &nm_rxq->iq_desc[nm_rxq->iq_cidx];
|
||||
const void *cpl;
|
||||
uint32_t lq;
|
||||
u_int n = 0, work = 0;
|
||||
uint8_t opcode;
|
||||
@ -924,6 +931,7 @@ t4_nm_intr(void *arg)
|
||||
|
||||
lq = be32toh(d->rsp.pldbuflen_qid);
|
||||
opcode = d->rss.opcode;
|
||||
cpl = &d->cpl[0];
|
||||
|
||||
switch (G_RSPD_TYPE(d->rsp.u.type_gen)) {
|
||||
case X_RSPD_TYPE_FLBUF:
|
||||
@ -940,8 +948,10 @@ t4_nm_intr(void *arg)
|
||||
switch (opcode) {
|
||||
case CPL_FW4_MSG:
|
||||
case CPL_FW6_MSG:
|
||||
handle_nm_fw6_msg(sc, ifp,
|
||||
(const void *)&d->cpl[0]);
|
||||
cpl = unwrap_nm_fw6_msg(cpl);
|
||||
/* fall through */
|
||||
case CPL_SGE_EGR_UPDATE:
|
||||
handle_nm_sge_egr_update(sc, ifp, cpl);
|
||||
break;
|
||||
case CPL_RX_PKT:
|
||||
ring->slot[fl_cidx].len = G_RSPD_LEN(lq) -
|
||||
|
||||
@ -229,8 +229,8 @@ static inline u_int txpkts0_len16(u_int);
|
||||
static inline u_int txpkts1_len16(void);
|
||||
static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
|
||||
struct mbuf *, u_int);
|
||||
static u_int write_txpkt_vm_wr(struct sge_txq *, struct fw_eth_tx_pkt_vm_wr *,
|
||||
struct mbuf *, u_int);
|
||||
static u_int write_txpkt_vm_wr(struct adapter *, struct sge_txq *,
|
||||
struct fw_eth_tx_pkt_vm_wr *, struct mbuf *, u_int);
|
||||
static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
|
||||
static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
|
||||
static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
|
||||
@ -433,16 +433,20 @@ static inline void
|
||||
setup_pad_and_pack_boundaries(struct adapter *sc)
|
||||
{
|
||||
uint32_t v, m;
|
||||
int pad, pack;
|
||||
int pad, pack, pad_shift;
|
||||
|
||||
pad_shift = chip_id(sc) > CHELSIO_T5 ? X_T6_INGPADBOUNDARY_SHIFT :
|
||||
X_INGPADBOUNDARY_SHIFT;
|
||||
pad = fl_pad;
|
||||
if (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad)) {
|
||||
if (fl_pad < (1 << pad_shift) ||
|
||||
fl_pad > (1 << (pad_shift + M_INGPADBOUNDARY)) ||
|
||||
!powerof2(fl_pad)) {
|
||||
/*
|
||||
* If there is any chance that we might use buffer packing and
|
||||
* the chip is a T4, then pick 64 as the pad/pack boundary. Set
|
||||
* it to 32 in all other cases.
|
||||
* it to the minimum allowed in all other cases.
|
||||
*/
|
||||
pad = is_t4(sc) && buffer_packing ? 64 : 32;
|
||||
pad = is_t4(sc) && buffer_packing ? 64 : 1 << pad_shift;
|
||||
|
||||
/*
|
||||
* For fl_pad = 0 we'll still write a reasonable value to the
|
||||
@ -456,7 +460,7 @@ setup_pad_and_pack_boundaries(struct adapter *sc)
|
||||
}
|
||||
}
|
||||
m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
|
||||
v = V_INGPADBOUNDARY(ilog2(pad) - 5);
|
||||
v = V_INGPADBOUNDARY(ilog2(pad) - pad_shift);
|
||||
t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
|
||||
|
||||
if (is_t4(sc)) {
|
||||
@ -2452,7 +2456,8 @@ eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
|
||||
total++;
|
||||
remaining--;
|
||||
ETHER_BPF_MTAP(ifp, m0);
|
||||
n = write_txpkt_vm_wr(txq, (void *)wr, m0, available);
|
||||
n = write_txpkt_vm_wr(sc, txq, (void *)wr, m0,
|
||||
available);
|
||||
} else if (remaining > 1 &&
|
||||
try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
|
||||
|
||||
@ -2720,8 +2725,10 @@ alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
|
||||
F_FW_IQ_CMD_FL0CONGEN);
|
||||
}
|
||||
c.fl0dcaen_to_fl0cidxfthresh =
|
||||
htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) |
|
||||
V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
|
||||
htobe16(V_FW_IQ_CMD_FL0FBMIN(chip_id(sc) <= CHELSIO_T5 ?
|
||||
X_FETCHBURSTMIN_128B : X_FETCHBURSTMIN_64B) |
|
||||
V_FW_IQ_CMD_FL0FBMAX(chip_id(sc) <= CHELSIO_T5 ?
|
||||
X_FETCHBURSTMAX_512B : X_FETCHBURSTMAX_256B));
|
||||
c.fl0size = htobe16(fl->qsize);
|
||||
c.fl0addr = htobe64(fl->ba);
|
||||
}
|
||||
@ -2784,7 +2791,7 @@ alloc_iq_fl(struct vi_info *vi, struct sge_iq *iq, struct sge_fl *fl,
|
||||
FL_UNLOCK(fl);
|
||||
}
|
||||
|
||||
if (is_t5(sc) && !(sc->flags & IS_VF) && cong >= 0) {
|
||||
if (chip_id(sc) >= CHELSIO_T5 && !(sc->flags & IS_VF) && cong >= 0) {
|
||||
uint32_t param, val;
|
||||
|
||||
param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
|
||||
@ -3238,8 +3245,9 @@ alloc_nm_txq(struct vi_info *vi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
|
||||
nm_txq->nid = idx;
|
||||
nm_txq->iqidx = iqidx;
|
||||
nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
|
||||
V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) |
|
||||
V_TXPKT_VF(vi->viid));
|
||||
V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
|
||||
V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
|
||||
V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
|
||||
|
||||
snprintf(name, sizeof(name), "%d", idx);
|
||||
oid = SYSCTL_ADD_NODE(&vi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
|
||||
@ -3607,8 +3615,10 @@ alloc_txq(struct vi_info *vi, struct sge_txq *txq, int idx,
|
||||
V_TXPKT_INTF(pi->tx_chan));
|
||||
else
|
||||
txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
|
||||
V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_VF_VLD(1) |
|
||||
V_TXPKT_VF(vi->viid));
|
||||
V_TXPKT_INTF(pi->tx_chan) |
|
||||
V_TXPKT_PF(G_FW_VIID_PFN(vi->viid)) |
|
||||
V_TXPKT_VF(G_FW_VIID_VIN(vi->viid)) |
|
||||
V_TXPKT_VF_VLD(G_FW_VIID_VIVLD(vi->viid)));
|
||||
txq->tc_idx = -1;
|
||||
txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
|
||||
M_ZERO | M_WAITOK);
|
||||
@ -4033,8 +4043,8 @@ imm_payload(u_int ndesc)
|
||||
* The return value is the # of hardware descriptors used.
|
||||
*/
|
||||
static u_int
|
||||
write_txpkt_vm_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_vm_wr *wr,
|
||||
struct mbuf *m0, u_int available)
|
||||
write_txpkt_vm_wr(struct adapter *sc, struct sge_txq *txq,
|
||||
struct fw_eth_tx_pkt_vm_wr *wr, struct mbuf *m0, u_int available)
|
||||
{
|
||||
struct sge_eq *eq = &txq->eq;
|
||||
struct tx_sdesc *txsd;
|
||||
@ -4150,9 +4160,13 @@ write_txpkt_vm_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_vm_wr *wr,
|
||||
("%s: mbuf %p needs checksum offload but missing header lengths",
|
||||
__func__, m0));
|
||||
|
||||
/* XXX: T6 */
|
||||
ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
|
||||
ETHER_HDR_LEN);
|
||||
if (chip_id(sc) <= CHELSIO_T5) {
|
||||
ctrl1 |= V_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
|
||||
ETHER_HDR_LEN);
|
||||
} else {
|
||||
ctrl1 |= V_T6_TXPKT_ETHHDR_LEN(m0->m_pkthdr.l2hlen -
|
||||
ETHER_HDR_LEN);
|
||||
}
|
||||
ctrl1 |= V_TXPKT_IPHDR_LEN(m0->m_pkthdr.l3hlen);
|
||||
ctrl1 |= V_TXPKT_CSUM_TYPE(csum_type);
|
||||
} else
|
||||
|
||||
@ -124,7 +124,8 @@ t4_cloner_match(struct if_clone *ifc, const char *name)
|
||||
{
|
||||
|
||||
if (strncmp(name, "t4nex", 5) != 0 &&
|
||||
strncmp(name, "t5nex", 5) != 0)
|
||||
strncmp(name, "t5nex", 5) != 0 &&
|
||||
strncmp(name, "t6nex", 5) != 0)
|
||||
return (0);
|
||||
if (name[5] < '0' || name[5] > '9')
|
||||
return (0);
|
||||
@ -471,6 +472,7 @@ tracer_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
|
||||
break;
|
||||
case SIOCSIFMEDIA:
|
||||
case SIOCGIFMEDIA:
|
||||
case SIOCGIFXMEDIA:
|
||||
sx_xlock(&t4_trace_lock);
|
||||
sc = ifp->if_softc;
|
||||
if (sc == NULL)
|
||||
|
||||
@ -111,6 +111,12 @@ struct {
|
||||
{0x580f, "Chelsio Amsterdam VF"},
|
||||
{0x5813, "Chelsio T580-CHR VF"},
|
||||
#endif
|
||||
}, t6vf_pciids[] = {
|
||||
{0x6801, "Chelsio T6225-CR VF"}, /* 2 x 10/25G */
|
||||
{0x6802, "Chelsio T6225-SO-CR VF"}, /* 2 x 10/25G, nomem */
|
||||
{0x6807, "Chelsio T62100-LP-CR VF"}, /* 2 x 40/50/100G */
|
||||
{0x6808, "Chelsio T62100-SO-CR VF"}, /* 2 x 40/50/100G, nomem */
|
||||
{0x680d, "Chelsio T62100-CR VF"}, /* 2 x 40/50/100G */
|
||||
};
|
||||
|
||||
static d_ioctl_t t4vf_ioctl;
|
||||
@ -153,6 +159,22 @@ t5vf_probe(device_t dev)
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
static int
|
||||
t6vf_probe(device_t dev)
|
||||
{
|
||||
uint16_t d;
|
||||
size_t i;
|
||||
|
||||
d = pci_get_device(dev);
|
||||
for (i = 0; i < nitems(t6vf_pciids); i++) {
|
||||
if (d == t6vf_pciids[i].device) {
|
||||
device_set_desc(dev, t6vf_pciids[i].desc);
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
}
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
#define FW_PARAM_DEV(param) \
|
||||
(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
|
||||
V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
|
||||
@ -498,6 +520,12 @@ t4vf_attach(device_t dev)
|
||||
if (rc != 0)
|
||||
goto done;
|
||||
|
||||
t4_init_devnames(sc);
|
||||
if (sc->names == NULL) {
|
||||
rc = ENOTSUP;
|
||||
goto done; /* error message displayed already */
|
||||
}
|
||||
|
||||
/*
|
||||
* Leave the 'pf' and 'mbox' values as zero. This ensures
|
||||
* that various firmware messages do not set the fields which
|
||||
@ -634,7 +662,7 @@ t4vf_attach(device_t dev)
|
||||
pi->tc = malloc(sizeof(struct tx_sched_class) *
|
||||
sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
|
||||
|
||||
if (is_10G_port(pi) || is_40G_port(pi)) {
|
||||
if (port_top_speed(pi) >= 10) {
|
||||
n10g++;
|
||||
} else {
|
||||
n1g++;
|
||||
@ -642,8 +670,7 @@ t4vf_attach(device_t dev)
|
||||
|
||||
pi->linkdnrc = -1;
|
||||
|
||||
pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbev" : "cxlv",
|
||||
-1);
|
||||
pi->dev = device_add_child(dev, sc->names->vf_ifnet_name, -1);
|
||||
if (pi->dev == NULL) {
|
||||
device_printf(dev,
|
||||
"failed to add device for port %d.\n", i);
|
||||
@ -702,7 +729,7 @@ t4vf_attach(device_t dev)
|
||||
|
||||
vi->first_rxq = rqidx;
|
||||
vi->first_txq = tqidx;
|
||||
if (is_10G_port(pi) || is_40G_port(pi)) {
|
||||
if (port_top_speed(pi) >= 10) {
|
||||
vi->tmr_idx = t4_tmr_idx_10g;
|
||||
vi->pktc_idx = t4_pktc_idx_10g;
|
||||
vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
|
||||
@ -920,6 +947,20 @@ static driver_t t5vf_driver = {
|
||||
sizeof(struct adapter)
|
||||
};
|
||||
|
||||
static device_method_t t6vf_methods[] = {
|
||||
DEVMETHOD(device_probe, t6vf_probe),
|
||||
DEVMETHOD(device_attach, t4vf_attach),
|
||||
DEVMETHOD(device_detach, t4_detach_common),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t t6vf_driver = {
|
||||
"t6vf",
|
||||
t6vf_methods,
|
||||
sizeof(struct adapter)
|
||||
};
|
||||
|
||||
static driver_t cxgbev_driver = {
|
||||
"cxgbev",
|
||||
cxgbe_methods,
|
||||
@ -932,8 +973,14 @@ static driver_t cxlv_driver = {
|
||||
sizeof(struct port_info)
|
||||
};
|
||||
|
||||
static devclass_t t4vf_devclass, t5vf_devclass;
|
||||
static devclass_t cxgbev_devclass, cxlv_devclass;
|
||||
static driver_t ccv_driver = {
|
||||
"ccv",
|
||||
cxgbe_methods,
|
||||
sizeof(struct port_info)
|
||||
};
|
||||
|
||||
static devclass_t t4vf_devclass, t5vf_devclass, t6vf_devclass;
|
||||
static devclass_t cxgbev_devclass, cxlv_devclass, ccv_devclass;
|
||||
|
||||
DRIVER_MODULE(t4vf, pci, t4vf_driver, t4vf_devclass, 0, 0);
|
||||
MODULE_VERSION(t4vf, 1);
|
||||
@ -943,8 +990,15 @@ DRIVER_MODULE(t5vf, pci, t5vf_driver, t5vf_devclass, 0, 0);
|
||||
MODULE_VERSION(t5vf, 1);
|
||||
MODULE_DEPEND(t5vf, t5nex, 1, 1, 1);
|
||||
|
||||
DRIVER_MODULE(t6vf, pci, t6vf_driver, t6vf_devclass, 0, 0);
|
||||
MODULE_VERSION(t6vf, 1);
|
||||
MODULE_DEPEND(t6vf, t6nex, 1, 1, 1);
|
||||
|
||||
DRIVER_MODULE(cxgbev, t4vf, cxgbev_driver, cxgbev_devclass, 0, 0);
|
||||
MODULE_VERSION(cxgbev, 1);
|
||||
|
||||
DRIVER_MODULE(cxlv, t5vf, cxlv_driver, cxlv_devclass, 0, 0);
|
||||
MODULE_VERSION(cxlv, 1);
|
||||
|
||||
DRIVER_MODULE(ccv, t6vf, ccv_driver, ccv_devclass, 0, 0);
|
||||
MODULE_VERSION(ccv, 1);
|
||||
|
||||
@ -277,19 +277,26 @@ t4_init_connect_cpl_handlers(void)
|
||||
static inline int
|
||||
act_open_cpl_size(struct adapter *sc, int isipv6)
|
||||
{
|
||||
static const int sz_t4[] = {
|
||||
sizeof (struct cpl_act_open_req),
|
||||
sizeof (struct cpl_act_open_req6)
|
||||
};
|
||||
static const int sz_t5[] = {
|
||||
sizeof (struct cpl_t5_act_open_req),
|
||||
sizeof (struct cpl_t5_act_open_req6)
|
||||
int idx;
|
||||
static const int sz_table[3][2] = {
|
||||
{
|
||||
sizeof (struct cpl_act_open_req),
|
||||
sizeof (struct cpl_act_open_req6)
|
||||
},
|
||||
{
|
||||
sizeof (struct cpl_t5_act_open_req),
|
||||
sizeof (struct cpl_t5_act_open_req6)
|
||||
},
|
||||
{
|
||||
sizeof (struct cpl_t6_act_open_req),
|
||||
sizeof (struct cpl_t6_act_open_req6)
|
||||
},
|
||||
};
|
||||
|
||||
if (is_t4(sc))
|
||||
return (sz_t4[!!isipv6]);
|
||||
else
|
||||
return (sz_t5[!!isipv6]);
|
||||
MPASS(chip_id(sc) >= CHELSIO_T4);
|
||||
idx = min(chip_id(sc) - CHELSIO_T4, 2);
|
||||
|
||||
return (sz_table[idx][!!isipv6]);
|
||||
}
|
||||
|
||||
/*
|
||||
@ -373,28 +380,32 @@ t4_connect(struct toedev *tod, struct socket *so, struct rtentry *rt,
|
||||
|
||||
if (isipv6) {
|
||||
struct cpl_act_open_req6 *cpl = wrtod(wr);
|
||||
struct cpl_t5_act_open_req6 *cpl5 = (void *)cpl;
|
||||
struct cpl_t6_act_open_req6 *cpl6 = (void *)cpl;
|
||||
|
||||
if ((inp->inp_vflag & INP_IPV6) == 0) {
|
||||
/* XXX think about this a bit more */
|
||||
log(LOG_ERR,
|
||||
"%s: time to think about AF_INET6 + vflag 0x%x.\n",
|
||||
__func__, inp->inp_vflag);
|
||||
if ((inp->inp_vflag & INP_IPV6) == 0)
|
||||
DONT_OFFLOAD_ACTIVE_OPEN(ENOTSUP);
|
||||
}
|
||||
|
||||
toep->ce = hold_lip(td, &inp->in6p_laddr);
|
||||
if (toep->ce == NULL)
|
||||
DONT_OFFLOAD_ACTIVE_OPEN(ENOENT);
|
||||
|
||||
if (is_t4(sc)) {
|
||||
switch (chip_id(sc)) {
|
||||
case CHELSIO_T4:
|
||||
INIT_TP_WR(cpl, 0);
|
||||
cpl->params = select_ntuple(vi, toep->l2te);
|
||||
} else {
|
||||
struct cpl_t5_act_open_req6 *c5 = (void *)cpl;
|
||||
|
||||
INIT_TP_WR(c5, 0);
|
||||
c5->iss = htobe32(tp->iss);
|
||||
c5->params = select_ntuple(vi, toep->l2te);
|
||||
break;
|
||||
case CHELSIO_T5:
|
||||
INIT_TP_WR(cpl5, 0);
|
||||
cpl5->iss = htobe32(tp->iss);
|
||||
cpl5->params = select_ntuple(vi, toep->l2te);
|
||||
break;
|
||||
case CHELSIO_T6:
|
||||
default:
|
||||
INIT_TP_WR(cpl6, 0);
|
||||
cpl6->iss = htobe32(tp->iss);
|
||||
cpl6->params = select_ntuple(vi, toep->l2te);
|
||||
break;
|
||||
}
|
||||
OPCODE_TID(cpl) = htobe32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
|
||||
qid_atid));
|
||||
@ -409,16 +420,25 @@ t4_connect(struct toedev *tod, struct socket *so, struct rtentry *rt,
|
||||
cpl->opt2 = calc_opt2a(so, toep);
|
||||
} else {
|
||||
struct cpl_act_open_req *cpl = wrtod(wr);
|
||||
struct cpl_t5_act_open_req *cpl5 = (void *)cpl;
|
||||
struct cpl_t6_act_open_req *cpl6 = (void *)cpl;
|
||||
|
||||
if (is_t4(sc)) {
|
||||
switch (chip_id(sc)) {
|
||||
case CHELSIO_T4:
|
||||
INIT_TP_WR(cpl, 0);
|
||||
cpl->params = select_ntuple(vi, toep->l2te);
|
||||
} else {
|
||||
struct cpl_t5_act_open_req *c5 = (void *)cpl;
|
||||
|
||||
INIT_TP_WR(c5, 0);
|
||||
c5->iss = htobe32(tp->iss);
|
||||
c5->params = select_ntuple(vi, toep->l2te);
|
||||
break;
|
||||
case CHELSIO_T5:
|
||||
INIT_TP_WR(cpl5, 0);
|
||||
cpl5->iss = htobe32(tp->iss);
|
||||
cpl5->params = select_ntuple(vi, toep->l2te);
|
||||
break;
|
||||
case CHELSIO_T6:
|
||||
default:
|
||||
INIT_TP_WR(cpl6, 0);
|
||||
cpl6->iss = htobe32(tp->iss);
|
||||
cpl6->params = select_ntuple(vi, toep->l2te);
|
||||
break;
|
||||
}
|
||||
OPCODE_TID(cpl) = htobe32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
|
||||
qid_atid));
|
||||
|
||||
@ -694,7 +694,7 @@ t4_syncache_respond(struct toedev *tod, void *arg, struct mbuf *m)
|
||||
synqe->iss = be32toh(th->th_seq);
|
||||
synqe->ts = to.to_tsval;
|
||||
|
||||
if (is_t5(sc)) {
|
||||
if (chip_id(sc) >= CHELSIO_T5) {
|
||||
struct cpl_t5_pass_accept_rpl *rpl5 = wrtod(wr);
|
||||
|
||||
rpl5->iss = th->th_seq;
|
||||
@ -1053,8 +1053,8 @@ calc_opt2p(struct adapter *sc, struct port_info *pi, int rxqid,
|
||||
}
|
||||
|
||||
static void
|
||||
pass_accept_req_to_protohdrs(const struct mbuf *m, struct in_conninfo *inc,
|
||||
struct tcphdr *th)
|
||||
pass_accept_req_to_protohdrs(struct adapter *sc, const struct mbuf *m,
|
||||
struct in_conninfo *inc, struct tcphdr *th)
|
||||
{
|
||||
const struct cpl_pass_accept_req *cpl = mtod(m, const void *);
|
||||
const struct ether_header *eh;
|
||||
@ -1063,8 +1063,13 @@ pass_accept_req_to_protohdrs(const struct mbuf *m, struct in_conninfo *inc,
|
||||
const struct tcphdr *tcp;
|
||||
|
||||
eh = (const void *)(cpl + 1);
|
||||
l3hdr = ((uintptr_t)eh + G_ETH_HDR_LEN(hlen));
|
||||
tcp = (const void *)(l3hdr + G_IP_HDR_LEN(hlen));
|
||||
if (chip_id(sc) >= CHELSIO_T6) {
|
||||
l3hdr = ((uintptr_t)eh + G_T6_ETH_HDR_LEN(hlen));
|
||||
tcp = (const void *)(l3hdr + G_T6_IP_HDR_LEN(hlen));
|
||||
} else {
|
||||
l3hdr = ((uintptr_t)eh + G_ETH_HDR_LEN(hlen));
|
||||
tcp = (const void *)(l3hdr + G_IP_HDR_LEN(hlen));
|
||||
}
|
||||
|
||||
if (inc) {
|
||||
bzero(inc, sizeof(*inc));
|
||||
@ -1188,7 +1193,7 @@ do_pass_accept_req(struct sge_iq *iq, const struct rss_header *rss,
|
||||
CTR4(KTR_CXGBE, "%s: stid %u, tid %u, lctx %p", __func__, stid, tid,
|
||||
lctx);
|
||||
|
||||
pass_accept_req_to_protohdrs(m, &inc, &th);
|
||||
pass_accept_req_to_protohdrs(sc, m, &inc, &th);
|
||||
t4opt_to_tcpopt(&cpl->tcpopt, &to);
|
||||
|
||||
pi = sc->port[G_SYN_INTF(be16toh(cpl->l2info))];
|
||||
@ -1427,14 +1432,14 @@ reject:
|
||||
}
|
||||
|
||||
static void
|
||||
synqe_to_protohdrs(struct synq_entry *synqe,
|
||||
synqe_to_protohdrs(struct adapter *sc, struct synq_entry *synqe,
|
||||
const struct cpl_pass_establish *cpl, struct in_conninfo *inc,
|
||||
struct tcphdr *th, struct tcpopt *to)
|
||||
{
|
||||
uint16_t tcp_opt = be16toh(cpl->tcp_opt);
|
||||
|
||||
/* start off with the original SYN */
|
||||
pass_accept_req_to_protohdrs(synqe->syn, inc, th);
|
||||
pass_accept_req_to_protohdrs(sc, synqe->syn, inc, th);
|
||||
|
||||
/* modify parts to make it look like the ACK to our SYN|ACK */
|
||||
th->th_flags = TH_ACK;
|
||||
@ -1536,7 +1541,7 @@ reset:
|
||||
KASSERT(so != NULL, ("%s: socket is NULL", __func__));
|
||||
|
||||
/* Come up with something that syncache_expand should be ok with. */
|
||||
synqe_to_protohdrs(synqe, cpl, &inc, &th, &to);
|
||||
synqe_to_protohdrs(sc, synqe, cpl, &inc, &th, &to);
|
||||
|
||||
/*
|
||||
* No more need for anything in the mbuf that carried the
|
||||
|
||||
@ -538,7 +538,6 @@ select_rcv_wscale(void)
|
||||
}
|
||||
|
||||
extern int always_keepalive;
|
||||
#define VIID_SMACIDX(v) (((unsigned int)(v) & 0x7f) << 1)
|
||||
|
||||
/*
|
||||
* socket so could be a listening socket too.
|
||||
@ -569,7 +568,7 @@ calc_opt0(struct socket *so, struct vi_info *vi, struct l2t_entry *e,
|
||||
opt0 |= V_L2T_IDX(e->idx);
|
||||
|
||||
if (vi != NULL) {
|
||||
opt0 |= V_SMAC_SEL(VIID_SMACIDX(vi->viid));
|
||||
opt0 |= V_SMAC_SEL(vi->smt_idx);
|
||||
opt0 |= V_TX_CHAN(vi->pi->tx_chan);
|
||||
}
|
||||
|
||||
|
||||
@ -7,10 +7,13 @@ SYSDIR?=${.CURDIR}/../..
|
||||
|
||||
SUBDIR= if_cxgbe
|
||||
SUBDIR+= if_cxl
|
||||
SUBDIR+= if_cc
|
||||
SUBDIR+= if_cxgbev
|
||||
SUBDIR+= if_cxlv
|
||||
SUBDIR+= if_ccv
|
||||
SUBDIR+= t4_firmware
|
||||
SUBDIR+= t5_firmware
|
||||
SUBDIR+= t6_firmware
|
||||
SUBDIR+= ${_tom}
|
||||
SUBDIR+= ${_iw_cxgbe}
|
||||
SUBDIR+= ${_cxgbei}
|
||||
|
||||
11
sys/modules/cxgbe/if_cc/Makefile
Normal file
11
sys/modules/cxgbe/if_cc/Makefile
Normal file
@ -0,0 +1,11 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
CXGBE= ${.CURDIR}/../../../dev/cxgbe
|
||||
.PATH: ${CXGBE}
|
||||
|
||||
KMOD= if_cc
|
||||
SRCS= if_cc.c
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
11
sys/modules/cxgbe/if_ccv/Makefile
Normal file
11
sys/modules/cxgbe/if_ccv/Makefile
Normal file
@ -0,0 +1,11 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
CXGBE= ${.CURDIR}/../../../dev/cxgbe
|
||||
.PATH: ${CXGBE}
|
||||
|
||||
KMOD= if_ccv
|
||||
SRCS= if_ccv.c
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T4FW_VER= 1.15.37.0
|
||||
T4FW_VER= 1.16.12.0
|
||||
FIRMWS+= t4fw.fw:t4fw:${T4FW_VER}
|
||||
CLEANFILES+= t4fw.fw
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T5FW_VER= 1.15.37.0
|
||||
T5FW_VER= 1.16.12.0
|
||||
FIRMWS+= t5fw.fw:t5fw:${T5FW_VER}
|
||||
CLEANFILES+= t5fw.fw
|
||||
|
||||
|
||||
27
sys/modules/cxgbe/t6_firmware/Makefile
Normal file
27
sys/modules/cxgbe/t6_firmware/Makefile
Normal file
@ -0,0 +1,27 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
T6FW= ${.CURDIR}/../../../dev/cxgbe/firmware
|
||||
.PATH: ${T6FW}
|
||||
|
||||
KMOD= t6fw_cfg
|
||||
FIRMWS= ${KMOD}.txt:${KMOD}:1.0.0.0
|
||||
|
||||
# You can have additional configuration files in the ${T6FW} directory.
|
||||
# t6fw_cfg_<name>.txt
|
||||
CFG_FILES != cd ${T6FW} && echo ${KMOD}_*.txt
|
||||
.for F in ${CFG_FILES}
|
||||
.if exists(${F})
|
||||
FIRMWS+= ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T6FW_VER= 1.16.12.0
|
||||
FIRMWS+= t6fw.fw:t6fw:${T6FW_VER}
|
||||
CLEANFILES+= t6fw.fw
|
||||
|
||||
t6fw.fw: t6fw-${T6FW_VER}.bin.uu
|
||||
uudecode -o ${.TARGET} ${.ALLSRC}
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
@ -1360,7 +1360,7 @@ show_struct(const uint32_t *words, int nwords, const struct field_desc *fd)
|
||||
#define FIELD1(name, start) FIELD(name, start, start)
|
||||
|
||||
static void
|
||||
show_t5_ctxt(const struct t4_sge_context *p)
|
||||
show_t5t6_ctxt(const struct t4_sge_context *p, int vers)
|
||||
{
|
||||
static struct field_desc egress_t5[] = {
|
||||
FIELD("DCA_ST:", 181, 191),
|
||||
@ -1400,6 +1400,44 @@ show_t5_ctxt(const struct t4_sge_context *p)
|
||||
FIELD1("CachePriority:", 0),
|
||||
{ NULL }
|
||||
};
|
||||
static struct field_desc egress_t6[] = {
|
||||
FIELD("DCA_ST:", 181, 191),
|
||||
FIELD1("StatusPgNS:", 180),
|
||||
FIELD1("StatusPgRO:", 179),
|
||||
FIELD1("FetchNS:", 178),
|
||||
FIELD1("FetchRO:", 177),
|
||||
FIELD1("Valid:", 176),
|
||||
FIELD1("ReschedulePending_1:", 175),
|
||||
FIELD1("PCIeDataChannel:", 174),
|
||||
FIELD1("StatusPgTPHintEn:", 173),
|
||||
FIELD("StatusPgTPHint:", 171, 172),
|
||||
FIELD1("FetchTPHintEn:", 170),
|
||||
FIELD("FetchTPHint:", 168, 169),
|
||||
FIELD1("FCThreshOverride:", 167),
|
||||
{ "WRLength:", 162, 166, 9, 0, 1 },
|
||||
FIELD1("WRLengthKnown:", 161),
|
||||
FIELD1("ReschedulePending:", 160),
|
||||
FIELD("TimerIx:", 157, 159),
|
||||
FIELD1("FetchBurstMin:", 156),
|
||||
FIELD1("FLMPacking:", 155),
|
||||
FIELD("FetchBurstMax:", 153, 154),
|
||||
FIELD("uPToken:", 133, 152),
|
||||
FIELD1("uPTokenEn:", 132),
|
||||
FIELD1("UserModeIO:", 131),
|
||||
FIELD("uPFLCredits:", 123, 130),
|
||||
FIELD1("uPFLCreditEn:", 122),
|
||||
FIELD("FID:", 111, 121),
|
||||
FIELD("HostFCMode:", 109, 110),
|
||||
FIELD1("HostFCOwner:", 108),
|
||||
{ "CIDXFlushThresh:", 105, 107, 0, 0, 1 },
|
||||
FIELD("CIDX:", 89, 104),
|
||||
FIELD("PIDX:", 73, 88),
|
||||
{ "BaseAddress:", 18, 72, 9, 1 },
|
||||
FIELD("QueueSize:", 2, 17),
|
||||
FIELD1("QueueType:", 1),
|
||||
FIELD1("FetchSizeMode:", 0),
|
||||
{ NULL }
|
||||
};
|
||||
static struct field_desc fl_t5[] = {
|
||||
FIELD("DCA_ST:", 181, 191),
|
||||
FIELD1("StatusPgNS:", 180),
|
||||
@ -1470,6 +1508,42 @@ show_t5_ctxt(const struct t4_sge_context *p)
|
||||
FIELD1("CachePriority:", 0),
|
||||
{ NULL }
|
||||
};
|
||||
static struct field_desc ingress_t6[] = {
|
||||
FIELD1("SP_NS:", 158),
|
||||
FIELD1("SP_RO:", 157),
|
||||
FIELD1("SP_TPHintEn:", 156),
|
||||
FIELD("SP_TPHint:", 154, 155),
|
||||
FIELD("DCA_ST:", 143, 153),
|
||||
FIELD1("ISCSICoalescing:", 142),
|
||||
FIELD1("Queue_Valid:", 141),
|
||||
FIELD1("TimerPending:", 140),
|
||||
FIELD1("DropRSS:", 139),
|
||||
FIELD("PCIeChannel:", 137, 138),
|
||||
FIELD1("SEInterruptArmed:", 136),
|
||||
FIELD1("CongestionMgtEnable:", 135),
|
||||
FIELD1("NoSnoop:", 134),
|
||||
FIELD1("RelaxedOrdering:", 133),
|
||||
FIELD1("GTSmode:", 132),
|
||||
FIELD1("TPHintEn:", 131),
|
||||
FIELD("TPHint:", 129, 130),
|
||||
FIELD1("UpdateScheduling:", 128),
|
||||
FIELD("UpdateDelivery:", 126, 127),
|
||||
FIELD1("InterruptSent:", 125),
|
||||
FIELD("InterruptIDX:", 114, 124),
|
||||
FIELD1("InterruptDestination:", 113),
|
||||
FIELD1("InterruptArmed:", 112),
|
||||
FIELD("RxIntCounter:", 106, 111),
|
||||
FIELD("RxIntCounterThreshold:", 104, 105),
|
||||
FIELD1("Generation:", 103),
|
||||
{ "BaseAddress:", 48, 102, 9, 1 },
|
||||
FIELD("PIDX:", 32, 47),
|
||||
FIELD("CIDX:", 16, 31),
|
||||
{ "QueueSize:", 4, 15, 4, 0 },
|
||||
{ "QueueEntrySize:", 2, 3, 4, 0, 1 },
|
||||
FIELD1("QueueEntryOverride:", 1),
|
||||
FIELD1("CachePriority:", 0),
|
||||
{ NULL }
|
||||
};
|
||||
static struct field_desc flm_t5[] = {
|
||||
FIELD1("Valid:", 89),
|
||||
FIELD("SplitLenMode:", 87, 88),
|
||||
@ -1489,6 +1563,28 @@ show_t5_ctxt(const struct t4_sge_context *p)
|
||||
FIELD("PIDX:", 0, 7),
|
||||
{ NULL }
|
||||
};
|
||||
static struct field_desc flm_t6[] = {
|
||||
FIELD1("Valid:", 89),
|
||||
FIELD("SplitLenMode:", 87, 88),
|
||||
FIELD1("TPHintEn:", 86),
|
||||
FIELD("TPHint:", 84, 85),
|
||||
FIELD1("NoSnoop:", 83),
|
||||
FIELD1("RelaxedOrdering:", 82),
|
||||
FIELD("DCA_ST:", 71, 81),
|
||||
FIELD("EQid:", 54, 70),
|
||||
FIELD("SplitEn:", 52, 53),
|
||||
FIELD1("PadEn:", 51),
|
||||
FIELD1("PackEn:", 50),
|
||||
FIELD1("Cache_Lock :", 49),
|
||||
FIELD1("CongDrop:", 48),
|
||||
FIELD1("Inflight:", 47),
|
||||
FIELD1("CongEn:", 46),
|
||||
FIELD1("CongMode:", 45),
|
||||
FIELD("PackOffset:", 20, 39),
|
||||
FIELD("CIDX:", 8, 15),
|
||||
FIELD("PIDX:", 0, 7),
|
||||
{ NULL }
|
||||
};
|
||||
static struct field_desc conm_t5[] = {
|
||||
FIELD1("CngMPSEnable:", 21),
|
||||
FIELD("CngTPMode:", 19, 20),
|
||||
@ -1499,12 +1595,17 @@ show_t5_ctxt(const struct t4_sge_context *p)
|
||||
{ NULL }
|
||||
};
|
||||
|
||||
if (p->mem_id == SGE_CONTEXT_EGRESS)
|
||||
show_struct(p->data, 6, (p->data[0] & 2) ? fl_t5 : egress_t5);
|
||||
else if (p->mem_id == SGE_CONTEXT_FLM)
|
||||
show_struct(p->data, 3, flm_t5);
|
||||
if (p->mem_id == SGE_CONTEXT_EGRESS) {
|
||||
if (p->data[0] & 2)
|
||||
show_struct(p->data, 6, fl_t5);
|
||||
else if (vers == 5)
|
||||
show_struct(p->data, 6, egress_t5);
|
||||
else
|
||||
show_struct(p->data, 6, egress_t6);
|
||||
} else if (p->mem_id == SGE_CONTEXT_FLM)
|
||||
show_struct(p->data, 3, vers == 5 ? flm_t5 : flm_t6);
|
||||
else if (p->mem_id == SGE_CONTEXT_INGRESS)
|
||||
show_struct(p->data, 5, ingress_t5);
|
||||
show_struct(p->data, 5, vers == 5 ? ingress_t5 : ingress_t6);
|
||||
else if (p->mem_id == SGE_CONTEXT_CNM)
|
||||
show_struct(p->data, 1, conm_t5);
|
||||
}
|
||||
@ -1689,7 +1790,7 @@ get_sge_context(int argc, const char *argv[])
|
||||
if (chip_id == 4)
|
||||
show_t4_ctxt(&cntxt);
|
||||
else
|
||||
show_t5_ctxt(&cntxt);
|
||||
show_t5t6_ctxt(&cntxt, chip_id);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user