parent
fd589c2e36
commit
c211f23b90
@ -733,8 +733,8 @@
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#define ISP1080_ISP_PARAMETER(c) \
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(((c)[18]) | ((c)[19] << 8))
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#define ISP1080_FAST_POST ISPBSMX(c, 20, 0, 0x01)
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#define ISP1080_REPORT_LVD_TRANSITION ISPBSMX(c, 20, 1, 0x01)
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#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01)
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#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01)
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#define ISP1080_BUS1_OFF 112
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@ -793,6 +793,80 @@
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#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \
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ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01)
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#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE
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#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE
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#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD
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#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT
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#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE
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#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE
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#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER
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#define ISP12160_FAST_POST ISP1080_FAST_POST
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#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION
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#define ISP12160_NVRAM_INITIATOR_ID \
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ISP1080_NVRAM_INITIATOR_ID
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#define ISP12160_NVRAM_BUS_RESET_DELAY \
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ISP1080_NVRAM_BUS_RESET_DELAY
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#define ISP12160_NVRAM_BUS_RETRY_COUNT \
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ISP1080_NVRAM_BUS_RETRY_COUNT
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#define ISP12160_NVRAM_BUS_RETRY_DELAY \
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ISP1080_NVRAM_BUS_RETRY_DELAY
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#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \
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ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME
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#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \
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ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION
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#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \
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ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION
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#define ISP12160_NVRAM_SELECTION_TIMEOUT \
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ISP1080_NVRAM_SELECTION_TIMEOUT
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#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \
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ISP1080_NVRAM_MAX_QUEUE_DEPTH
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#define ISP12160_BUS0_OFF 24
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#define ISP12160_BUS1_OFF 136
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#define ISP12160_NVRAM_TARGOFF(b) \
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(((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16)
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#define ISP12160_NVRAM_TARGSIZE 6
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#define _IxT16(tgt, tidx, b) \
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(ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx))
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#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \
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ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01)
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#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \
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ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01)
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#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \
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ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01)
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#define ISP12160_NVRAM_TGT_TQING(c, t, b) \
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ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01)
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#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \
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ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01)
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#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \
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ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01)
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#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \
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ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01)
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#define ISP12160_NVRAM_TGT_DISC(c, t, b) \
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ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01)
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#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
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ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff)
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#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
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ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff)
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#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
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ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f)
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#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
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ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01)
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#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \
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ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f)
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#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \
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ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03)
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#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \
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ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01)
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/*
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* Qlogic 2XXX NVRAM is an array of 256 bytes.
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*
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