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Teach the re(4) driver about the CFG2 register, which tells us whether

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we're on a 32-bit/64-bit bus or not. Use this to decide if we should
set the PCI dual-address cycle enable bit in the C+ command register.
(Enabling DAC on a 32-bit bus seems to do bad things.)

Also, initialize the C+ command register early in the re_init() routine.
The documentation says this register should be configured first.
This commit is contained in:
Bill Paul 2003-09-13 23:51:35 +00:00
parent d7b645262d
commit c2c6548b3a
2 changed files with 29 additions and 8 deletions
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21
sys/dev/re/if_re.c
View File

@ -2075,6 +2075,19 @@ re_init(xsc)
*/
re_stop(sc);
/*
* Enable C+ RX and TX mode, as well as VLAN stripping and
* RX checksum offload. Only enable dual-address cycle if
* we're on a 64-bit bus. We must configure the C+ register
* before all others.
*/
CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
(CSR_READ_1(sc, RL_CFG2) & RL_BUSWIDTH_64BITS ?
RL_CPLUSCMD_PCI_DAC : 0)|RL_CPLUSCMD_VLANSTRIP|
(ifp->if_capenable & IFCAP_RXCSUM ?
RL_CPLUSCMD_RXCSUM_ENB : 0));
/*
* Init our MAC address. Even though the chipset
* documentation doesn't mention it, we need to enter "Config
@ -2167,14 +2180,8 @@ re_init(xsc)
CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
#endif
/*
* If this is a C+ capable chip, enable C+ RX and TX mode,
* and load the addresses of the RX and TX lists into the chip.
* Load the addresses of the RX and TX lists into the chip.
*/
CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
RL_CPLUSCMD_VLANSTRIP|
(ifp->if_capenable & IFCAP_RXCSUM ?
RL_CPLUSCMD_RXCSUM_ENB : 0));
CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));

16
sys/pci/if_rlreg.h
View File

@ -76,7 +76,7 @@
#define RL_EECMD 0x0050 /* EEPROM command register */
#define RL_CFG0 0x0051 /* config register #0 */
#define RL_CFG1 0x0052 /* config register #1 */
/* 0053-0057 reserved */
/* 0053-0057 reserved */
#define RL_MEDIASTAT 0x0058 /* media status register (8139) */
/* 0059-005A reserved */
#define RL_MII 0x005A /* 8129 chip only */
@ -110,6 +110,7 @@
#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
#define RL_CFG2 0x0053
#define RL_TIMERINT 0x0054 /* interrupt on timer expire */
#define RL_TXSTART 0x00D9 /* 8 bits */
#define RL_CPLUS_CMD 0x00E0 /* 16 bits */
@ -354,6 +355,19 @@
#define RL_TXSTART_START 0x40 /* start normal queue transmit */
#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
/*
* Config 2 register, 8139C+/8169/8169S/8110S only
*/
#define RL_CFG2_BUSFREQ 0x07
#define RL_CFG2_BUSWIDTH 0x08
#define RL_CFG2_AUXPWRSTS 0x10
#define RL_BUSFREQ_33MHZ 0x00
#define RL_BUSFREQ_66MHZ 0x01
#define RL_BUSWIDTH_32BITS 0x00
#define RL_BUSWIDTH_64BITS 0x08
/* C+ mode command register */
#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */